Few Arm reference design Fixed Virtual Platforms (FVPs) support Virtio-P9
device as part of the RoS subsystem. The Virtio-P9 device implements a
subset of the Plan 9 file protocol over a virtio transport that enables
accessing a shared directory on the host's filesystem from a running
FVP platform.
Some of the Arm reference design FVP platforms support the Virtio-p9
device as part of the RoS subsystem. Add an entry for this device in
the SSDT acpi table.
The device entry is listed in a new SSDT file as only some of the
reference design FVP platforms support it and so this file is included
in
Enable the virtio-p9 device that is present as part of the RoS
peripherals on RD-N2 platform variants. This will allow filesystem
sharing between the Host PC and target platform.
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 8 ++--
Platform/ARM/SgiP
Enable Address Translation Service (ATS) support for the PCI root
complex listed in the iort table. Enabling ATS mode also enables
PRI support.
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/AR
Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work with PCIe devices.
ATS allows PCIe devices to cache translation in th
Add the generic SMMUv3 type node in the iort table and
setup the rid->stream-id->device-id mapping accordingly.
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 58 ++--
1 file changed, 54 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/A
Hi Sami,
On 3/1/21 8:08 PM, Sami Mujawar via Groups.Io wrote:
Hi Vivek,
Can you include the description you included in the cover letter in the commit
message for this patch, please?
Sure, I will update the commit message.
On Mon, Feb 15, 2021 at 01:00 PM, Vivek Kumar Gautam wrote
Enable Address Translation Service (ATS) support for the PCI root
complex listed in the iort table.
ATS allows PCIe devices to request an address translation before
starting the dma transaction, so that devices can cache these
translations in their private cache that is called as Address
Translatio
Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work with PCIe devices.
ATS allows PCIe devices to request translation fro
Arm's SMMU-v3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe
bus. SMMU-v3 also supports Address Translation Service (ATS) and
Page Request Interface (PRI) to work with PCIe devices.
The overall system topology looks as below:
On 3/5/21 6:44 PM, Vivek Kumar Gautam via groups.io wrote:
Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work
-Original Message-
From: Vivek Kumar Gautam
Sent: 05 March 2021 01:21 PM
To: devel@edk2.groups.io
Cc: ardb+tianoc...@kernel.org; l...@nuviainc.com; Sami Mujawar
Subject: Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm
SGI/RD platforms
On 3/5/21 6:44 PM, Vivek Kumar Gautam
Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
I/O virtualization blocks that allow connecting PCIe root bus or non-PCIe
(non-discoverable) devices to the system. Each of the I/O virtualization
blocks consists of an Arm SMMUv3 compliant MMU-700 controller to handle
addres
The SMMUv3 node in IORT table requires interrupt vector information
of 4 programmable interrupts - Event, PRI, Global error, and Sync.
In addition to these interrupt vectors, DeviceID information is
required to support MSI interrupts using GIC ITS block. Add the
PCD entries for SMMUv3 base address,
Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
devices to the system. For platforms that connect non-discoverable (non-
PCI) devices to IO virtualization block, add a SSDT table to describe
such devi
From: Shriram K
The IO virtualization block on reference design platforms allow
connecting non-discoverable devices such as PL011 UART. On platforms
that support this, initialize the UART controller connected to the
IO virtualization block.
Signed-off-by: Shriram K
Signed-off-by: Vivek Gautam
Add preprocessor macros for ITS, SMMUv3 and DMA named component nodes
of IORT table that can be used to describe the IO topology connected
to the IO Virtualization block. An IO virtualization block could be
used to connect PCIe root bus or non-PCIe devices.
For a non-PCIe IO-Virtualization block,
Arm reference design RD-N2-Cfg1 platform has multiple I/O virtualization
blocks that allow connecting PCIe root bus or non-PCIe devices to the
system. Each of the I/O virtualization blocks (IoVirtBlk) consists of
an Arm SMMUv3 compliant MMU-700 controller to handle address translation
and a GIC-700
Arm reference design RD-N2 platform has multiple I/O virtualization
blocks that allow connecting PCIe root bus or non-PCIe devices to
the system. Each of the I/O virtualization blocks (IoVirtBlk)
consists of an Arm SMMUv3 compliant MMU-700 controller to handle
address translations and a GIC-700 Int
Include the FdtLib path to fix a build issue coming on Arm/SgiPkg with
PlatformStandaloneMm2.
Fixes the build breakage introduced by 9ad168c9e0:
StandaloneMmPkg: Include libfdt in the StMM
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 1 +
1 file changed, 1 inserti
Hi Sami,
On 4/26/23 21:47, Sami Mujawar wrote:
Hi Vivek,
Thank you for this patch.
I have some minor feedback that I will address before merging.
Reviewed-by: Sami Mujawar
Thank you for the review of this patch and other patches in the series.
Please find my comments inline below.
Re
Arm reference design Fixed Virtual Platforms (FVPs) such as the RD-N2
platform variants have multiple IO virtualization blocks that allow
connecting PCIe root bus or non-PCIe SoC peripherals to the system.
Each of these IO virtualization blocks consists of an Arm SMMUv3, a
GIC-ITS and a NCI (networ
Some of the Arm reference design FVP platforms support the Virtio-p9
device as part of the RoS subsystem. Add an entry for this device in
the SSDT acpi table.
The device entry is listed in a new SSDT file as only some of the
reference design FVP platforms support it and so this file is included
in
Enable the virtio-p9 device that is present as part of the RoS
peripherals on RD-N2 platform variants. This will allow filesystem
sharing between the Host PC and target platform.
Signed-off-by: Vivek Gautam
Reviewed-by: Pierre Gondois
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf |
Arm reference design platforms have multiple IO virtualization blocks
that allow connecting PCIe root bus or non-PCIe SoC peripherals to the
system. Each of these IO virtualization blocks consists of an instance
of SMMUv3, a GIC-ITS and a NCI (network chip interconnect) to support
traffic flow and
From: Shriram K
The IO virtualization block on reference design platforms allow
connecting SoC expansion devices such as PL011 UART. On platforms
that support this, initialize the UART controller connected to the
IO virtualization block.
Signed-off-by: Shriram K
Signed-off-by: Vivek Gautam
---
For all the RD-N2 platform variants, include the SSDT ACPI table that
describes the devices present in SoC expansion block that is connected
to the IO virtualization block.
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 5 +
Platform/ARM/SgiPkg/AcpiTa
Hi Pierre,
On 3/30/23 15:16, Pierre Gondois wrote:
Hello Vivek,
Thanks for the new version,
Reviewed-by: Pierre Gondois:
Thanks a lot for your review.
Best regards
Vivek
[snip]
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View/Reply Online (#1021
This reverts commit eb3950b842d3f335671600fdfa9b58c482886c79.
This commit referenced the change (9ad168c9e0 StandaloneMmPkg:
Include libfdt in the StMM) in edk2 as the dependency to add FdtLib
instance. However, as this change is not yet upstreamed, it was
incorrect to introduce this dependency an
Hi Sami,
On 1/11/23 16:03, Sami Mujawar wrote:
Hi Vivek,
Thank you for this fix.
Reviewed-by: Sami Mujawar
Thanks for the review and apologies again for the mixup.
Best regards
Vivek
Regards,
Sami Mujawar
On 11/01/2023, 10:13, "Vivek Gautam" wrote:
This reverts commit eb3950b
inline.
Regards,
Pierre
On 2/14/22 13:13, Vivek Kumar Gautam via groups.io wrote:
Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have
multiple
IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
devices to the system. For platforms that connect non-discoverable
Arm reference design Fixed Virtual Platforms (FVPs) such as the RD-N2
platform variants have multiple IO virtualization blocks that allow
connecting PCIe root bus or non-PCIe SoC peripherals to the system.
Each of these IO virtualization blocks consists of an Arm SMMUv3, a
GIC-ITS and a NCI (networ
Some of the Arm reference design FVP platforms support the Virtio-p9
device as part of the RoS subsystem. Add an entry for this device in
the SSDT acpi table.
The device entry is listed in a new SSDT file as only some of the
reference design FVP platforms support it and so this file is included
in
Enable the virtio-p9 device that is present as part of the RoS
peripherals on RD-N2 platform variants. This will allow filesystem
sharing between the Host PC and target platform.
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 8 ++--
Platform/ARM/SgiP
Arm reference design platforms have multiple IO virtualization blocks
that allow connecting PCIe root bus or non-PCIe SoC peripherals to the
system. Each of these IO virtualization blocks consists of an instance
of SMMUv3, a GIC-ITS and a NCI (network chip interconnect) to support
traffic flow and
From: Shriram K
The IO virtualization block on reference design platforms allow
connecting SoC expansion devices such as PL011 UART. On platforms
that support this, initialize the UART controller connected to the
IO virtualization block.
Signed-off-by: Shriram K
Signed-off-by: Vivek Gautam
---
For all the RD-N2 platform variants, include the SSDT ACPI table that
describes the devices present in SoC expansion block that is connected
to the IO virtualization block.
Signed-off-by: Vivek Gautam
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 7 +++
Platform/ARM/SgiPkg/Acpi
Hi Pierre,
On 2/3/23 21:25, PierreGondois via groups.io wrote:
Hello Vivek,
Thanks for your review. Please find my responses inline below.
On 1/27/23 10:23, Vivek Gautam wrote:
From: Shriram K
The IO virtualization block on reference design platforms allow
connecting SoC expansion device
Hi Pierre,
On 2/3/23 21:28, Pierre Gondois wrote:
Hello Vivek,
On 1/27/23 10:23, Vivek Gautam wrote:
Arm reference design Fixed Virtual Platforms (FVPs) such as the RD-N2
platform variants have multiple IO virtualization blocks that allow
connecting PCIe root bus or non-PCIe SoC peripherals t
Hi Pierre
On 2/3/23 21:26, Pierre Gondois wrote:
Hello Vivek,
Thanks for review the changes, please find my responses inline below.
On 1/27/23 10:23, Vivek Gautam wrote:
Arm reference design platforms have multiple IO virtualization blocks
that allow connecting PCIe root bus or non-PCIe So
Hi Pierre,
On 2/7/23 14:20, Pierre Gondois wrote:
Hello Vivek,
Thanks for the answers,
On 2/7/23 07:59, Vivek Kumar Gautam wrote:
Hi Pierre
On 2/3/23 21:26, Pierre Gondois wrote:
Hello Vivek,
Thanks for review the changes, please find my responses inline below.
On 1/27/23 10:23, Vivek
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