Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work with PCIe devices.
ATS allows PCIe devices to cache translation in their private
caches called as Address Translation Cache (ATC).
The ITS block present in the system accepts the downstream traffic
from SMMUv3 and provides the right interrupt translation for LPIs.
Thus, the overall topology looks like below -
--------------- ------------ ------------
| PCIe device |---->| SMMUv3 |---->| ITS |
| (RequesterID) | | (StreamID) | | (DeviceID) |
--------------- ------------ ------------
Vivek Gautam (2):
Platform/Sgi: Add smmu node in the iort acpi table
Platform/Sgi: Enable ATS mode over PCI root complex
Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 60 ++++++++++++++++++--
1 file changed, 55 insertions(+), 5 deletions(-)
--
2.17.1
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