> ASM_PFX(FspInfoHeaderRelativeOff):
>
> DD0x12345678 ; This value must be patched by the build
> script
>
> - and rax, 0x
>
> + mov eax, eax ; equal to and rax, 0x
Based on the discussion, we know "mov eax, eax" clears upper 32bit
Combine the 'if' condition branch for non-present and leaf Parent
Entry in PageTableLibMapInLevel. Most steps of these two condition
are the same. This commit doesn't change any functionality.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/Li
Add code to compare ParentPagingEntry Attribute&Mask and input
Attribute&Mask to decide if new next level page table is needed
in non-present ParentPagingEntry condition. This can help avoid
unneccessary page table creation.
For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3
From: Zhiguang Liu
Last commit changed the CpuPageTableLib API PageTableMap, unit
test code should also be modified.
Cc: Eric Dong
Reviewed-by: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Zhiguang Liu
---
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 38
In function CreatePageTable(), Add code to initialize MapMask to
0. Missing the initialization doesn't cause functionality issue
but looks confusing.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 1 +
From: Zhiguang Liu
The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit
field PageTableBaseAddress is from bit 12 to bit 52. This means if the
compiler treats the 64bits value as two UINT32 value, the field
PageTableBaseAddress spans two UINT32 value. That's why when building in
N
Modify RandomTest to check if parameter IsModified of
PageTableMap() correctlly indicates whether input page table
is modified or not.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Zhiguang Liu
---
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTes
Add OUTPUT IsModified parameter in PageTableMap() to indicate
if page table has been modified. With this parameter, caller
can know if need to call FlushTlb when the page table is in CR3.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/Include
Enable non-1:1 mapping in random test. In previous test, non-1:1
test will fail due to the non-1:1 mapping issue in CpuPageTableLib
and invalid Input Mask when creating new page table or mapping
not-present range. Now these issue have been fixed.
Signed-off-by: Dun Tan
Cc: Eric Dong
Reviewed-by:
Modify RandomTest to check invalid input. When creating new page
table or updating exsiting page table:
1.If set [LinearAddress, LinearAddress+Length] to non-preset, all
other attributes should not be provided.
2.If [LinearAddress, LinearAddress+Length] contain non-present range,
the Returnstat
Add an input parameter to control the probability of returning
true. Change RandomBoolean() in RandomTest from 50% chance
returning true to returning true with the percentage of input
Probability.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPk
Add manual test case to check input Mask and Attribute. The check
steps are:
1.Create Page table to cover [0, 2G]. All fields of MapMask should
be set.
2.Update Page table to set [2G - 8K,2G] from present to non-present.
All fields of MapMask except present should not be set.
3.Still set [2G -
For different usage, check if the combination for Mask and
Attr is valid when creating or updating page table.
1.For non-present range
1.1Mask.Present is 0 but some other attributes is provided.
This case is invalid.
1.2Mask.Present is 1 and Attr.Present is 0. In this case,all
other
When splitting leaf parent entry to smaller granularity, create
child page table before modifing parent entry. In previous code
logic, when splitting a leaf parent entry, parent entry will
point to a null 4k memory before child page table is created in
this 4k memory. When the page table to be modi
Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle.
This function is used to set non-leaf entry attributes so it should
make sure that the PageSize bit of the entry should be 0.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/L
In previous code logic, when splitting a leaf parent entry to
smaller granularity child page table, if the parent entry
Attribute&Mask(without PageTableBaseAddress field) is equal to the
input attribute&mask(without PageTableBaseAddress field), the split
process won't happen. This may lead to failu
Move some local variable initialization to the beginning of the
function. Also delete duplicated calculation for RegionLength.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 20
Add check for input Length in PageTableMap (). Return
RETURN_SUCCESS when input Length is 0.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++--
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap
Remove unneeded 'if' condition in CpuPageTableLib code.
The deleted code is in the code branch for present non-leaf parent
entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present
== 0) is always FALSE.
Signed-off-by: Dun Tan
Cc: Eric Dong
Reviewed-by: Ray Ni
Cc: Rahul Kumar
Cc: Gerd
In the V3 patch set:
1.Modify the V2 patch set based on Ray's comments
2.Remove the patch to enable PAE paging. Will do this in future patches
3.Add patches to combine code branch for non-present and leaf ParentEntry
Dun Tan (16):
UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition
Uefi
Reviewed-by: Nickle Wang
Regards,
Nickle
-Original Message-
From: abner.ch...@amd.com
Sent: Thursday, March 9, 2023 11:41 PM
To: devel@edk2.groups.io
Cc: Nickle Wang ; Igor Kulchytskyy
Subject: [PATCH 2/3] RedfishPkg: Update Redfish DSC
External email: Use caution opening links or at
Please find my comment inline below, thanks!
Regards,
Nickle
-Original Message-
From: abner.ch...@amd.com
Sent: Thursday, March 9, 2023 11:41 PM
To: devel@edk2.groups.io
Cc: Nickle Wang ; Igor Kulchytskyy
Subject: [PATCH 1/3] RedfishPkg/Library: Redfish BMC USBNIC Host Interface
Exter
[AMD Official Use Only - General]
Reviewed-by: Abner Chang
> -Original Message-
> From: Simon Wang
> Sent: Tuesday, March 14, 2023 7:39 PM
> To: devel@edk2.groups.io
> Cc: Nickle Wang ; Chang, Abner
> ; Igor Kulchytskyy ; Nick
> Ramirez
> Subject: [edk2-staging][PATCH] edk2-staging/Red
*Reminder: Tools, CI, Code base construction meeting series*
*When:*
Monday, March 20, 2023
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles
*Where:*
https://github.com/tianocore/edk2/discussions/2614
View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=1753770 )
*Description:*
TianoC
The fixes since 0.9.4 are
Andreas Schwab (1):
sbsigntool: add support for RISC-V 64-bit PE/COFF images
Daniel Axtens (1):
sbvarsign: do not include PKCS#7 attributes
James Bottomley (1):
Add support for openssl-3
Jeremi Piotrowski (1):
Fix openssl-3.0 issue i
On 3/13/2023 10:17 AM, Ard Biesheuvel wrote:
Currently, we rely on the memory type for loading images being
executable by default, and only restrict the permissions if the policy
says so, and the image sections are suitably aligned. This requires that
the various 'code' memory types are executabl
On 3/13/2023 10:16 AM, Ard Biesheuvel wrote:
One nitpick below.
To permit the platform to adopt a stricter policy when it comes to
memory protections, and map all memory XP by default, add the necessary
handling to the DXE IPL PEIM to ensure that the DXE core code section is
mapped executable be
[AMD Official Use Only - General]
Hi Abner,
Thanks for reviewing the code, I had addressed the review comments in
V2 version.
- Abdul
-Original Message-
From: Abdul Lateef Attar
Sent: 17 March 2023 11:59
To: devel@edk2.groups.io
Cc: Attar, AbdulLateef (Abdul Lateef) ; Ard
Bieshe
Hi Ard,
For the patchset:
Reviewed- and Tested-by: Oliver Smith-Denny
Thanks for sending this out! I tested with some integrations to Project
Mu on both a virtual and physical platform.
Oliver
On 3/13/2023 10:16 AM, Ard Biesheuvel wrote:
Link: https://bugzilla.tianocore.org/show_bug.cgi?i
Yes, you are right. Tested on the H/W, It clears the upper 32bits. đ
From: devel@edk2.groups.io On Behalf Of Marvin Häuser
Sent: Sunday, March 19, 2023 3:07 PM
To: S, Ashraf Ali
Cc: devel@edk2.groups.io; Chiu, Chasel ; Desimone,
Nathaniel L ; Zeng, Star
Subject: Re: [edk2-devel] [PATCH v2] Int
Yes - it does. Most (if not all?) operations on 32-bit registers zero-extend
the corresponding 64-bit register. This is an AMD64 / Intel 64 design to combat
partial register stall. Please consult the SDM (or at least try it out).
What I didnât realize is that âmov eax, eaxâ apparently defeats re
Hi.,
Nope, it will not clear the upper 32bit right.
From: Marvin Häuser
Sent: Sunday, March 19, 2023 3:38 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.
Hi Ashraf,
âmov eax, eaxâ does clear the high 32 Bits of rax.
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