Yes - it does. Most (if not all?) operations on 32-bit registers zero-extend the corresponding 64-bit register. This is an AMD64 / Intel 64 design to combat partial register stall. Please consult the SDM (or at least try it out).
What I didn’t realize is that “mov eax, eax” apparently defeats register renaming optimisations: https://stackoverflow.com/a/45660140 Best regards, Marvin > On 19. Mar 2023, at 10:07, S, Ashraf Ali <ashraf.al...@intel.com> wrote: > > Hi., > > Nope, it will not clear the upper 32bit right. > > > From: Marvin Häuser <mhaeu...@posteo.de> > Sent: Sunday, March 19, 2023 3:38 AM > To: S, Ashraf Ali <ashraf.al...@intel.com>; devel@edk2.groups.io > Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build > warnings. > > Hi Ashraf, > > ”mov eax, eax” does clear the high 32 Bits of rax. > > Best regards, > Marvin -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101368): https://edk2.groups.io/g/devel/message/101368 Mute This Topic: https://groups.io/mt/97678369/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
