Since this set started, edk2-platforms has migrated to the new
Maintainers.txt format - adjust the entry accordingly. As part
of this, squash Platform and Silicon portions into a single
section entry.
Also, flip Graeme Gregory from M: to R:, since he does not have
repository write access.
Signed-o
The SbsaQemu platform port has been in flight for a long time now,
so to facilitate getting it merged, here is a set of proposed layout
changes and minor tweaks that I would prefer to have included.
I also propose changing the commit message as follows:
---
SbsaQemu: add port for SbsaQemu platform
Platform/Qemu is empty, apart from the SbsaQemu dirctory, which holds
SbsaQemu.dsc and SbsaQemu.fdf. Silicon/Qemu held Drivers, Library and
a file called SbsaQemuPkg.dec. Move them all into a subdirectory called
SbsaQemu, and drop the Pkg but from the .dec name.
Signed-off-by: Leif Lindholm
---
For some reason, SbsaQemu.dec holds a spurious LibraryClasses
declaration for ArmPlatformLib - nuke it.
Signed-off-by: Leif Lindholm
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
b/Silicon/Qemu/SbsaQemu/SbsaQemu.d
“Maybe you entirely missed my message that I posted in response to
version 2 of this specific patch (i.e. you may have fully missed the
message I link at the top). That could be the case because I mentioned
"OvmfXen.dsc" under the v2 blurb as well.”
Yup. That’s the one. Saw this request, but not t
On 5/22/20 10:05 PM, Laszlo Ersek via groups.io wrote:
On 05/22/20 22:01, Laszlo Ersek wrote:
On 05/22/20 12:12, Ard Biesheuvel wrote:
GCC 10 enabled a feature by default that was introduced in GCC 9,
which results in atomic operations to be emitted as function calls
to intrinsics provided by a
Hi,
On 05/22/20 00:43, Michael Kubacki wrote:
> From: Bret Barkelew
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=2522
>
> Cc: Laszlo Ersek
> Cc: Ard Biesheuvel
> Cc: Leif Lindholm
> Cc: Bret Barkelew
> Signed-off-by: Michael Kubacki
> ---
> ArmVirtPkg/ArmVirt.dsc.inc | 7 +++
>
Hello Michael / Bret,
I don't understand the (lack of) updates in this patch:
On 05/22/20 00:43, Michael Kubacki wrote:
> From: Bret Barkelew
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=2522
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Biesheuvel
> Cc: Bret Barkelew
> Signed-o
On 5/22/20 9:50 AM, Laszlo Ersek via groups.io wrote:
On 05/22/20 16:48, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.c
On 5/22/20 9:19 AM, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7Cfc8d0918a2474d08139808d7fe5b2a93%7C3dd8961fe4884e
On 5/22/20 9:14 AM, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7Cfdd2325c2e5341d8ae5408d7fe5a75f5%7C3dd8961fe4884e
Hello,
(+Ard)
this patch does not apply (with "master" being at 74f90d38c446).
Because:
On 05/22/20 00:43, Michael Kubacki wrote:
> diff --git
> a/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
> b/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
> in
On 05/22/20 22:01, Laszlo Ersek wrote:
> On 05/22/20 12:12, Ard Biesheuvel wrote:
>> GCC 10 enabled a feature by default that was introduced in GCC 9,
>> which results in atomic operations to be emitted as function calls
>> to intrinsics provided by a runtime library.
>>
>> Atomics are hardly used
On 05/22/20 12:12, Ard Biesheuvel wrote:
> GCC 10 enabled a feature by default that was introduced in GCC 9,
> which results in atomic operations to be emitted as function calls
> to intrinsics provided by a runtime library.
>
> Atomics are hardly used in EDK2, which runs on a single CPU anyway,
>
This is v2 with Maciej Rabeda's feedback.
Python http.server seems to FIN after the first HEAD request to size
the loaded file is completed and ACKed. What happens next is interesting.
On low latency connections, the GET request to download may get sent
after the server sends the FIN but before th
Thank you. I made the updates and will now send v2.
A
From: devel@edk2.groups.io on behalf of Maciej Rabeda
via groups.io
Sent: Tuesday, May 19, 2020 7:02 AM
To: Andrei Warkentin ; devel@edk2.groups.io
Cc: jiaxin...@intel.com ; siyuan...@intel.com
Subject: R
On 5/22/20 5:31 AM, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7C95b407c13bd44ad1b89608d7fe3b450a%7C3dd8961fe4884e
On 05/22/20 15:27, Ard Biesheuvel wrote:
> On 5/22/20 12:54 PM, Leif Lindholm wrote:
>> On Thu, May 21, 2020 at 22:22:58 +0200, Laszlo Ersek wrote:
>>> On 05/21/20 16:16, Leif Lindholm wrote:
>>>
OK, then I would vote *for* merging the patch regardless. We know how
long some toolchain ver
On 5/22/20 8:57 PM, Laszlo Ersek via groups.io wrote:
On 05/22/20 10:40, Ard Biesheuvel wrote:
The way the BDS handles the short-form USB device path of the console
keyboard relies on USB host controllers to be locatable via their PCI
metadata, which implies that these controllers already have a
On 5/22/20 5:27 AM, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7C34f8c61055564e148e1408d7fe3ab37f%7C3dd8961fe4884e
On 05/22/20 10:40, Ard Biesheuvel wrote:
> The way the BDS handles the short-form USB device path of the console
> keyboard relies on USB host controllers to be locatable via their PCI
> metadata, which implies that these controllers already have a PCI I/O
> protocol installed on their handle.
>
>
On 05/22/20 07:48, Bret Barkelew wrote:
> In Mu we have a similar problem of keeping track of what features/bugs
> have already been upstreamed and when can they be dropped during an
> upstream integration, so that's the more personal interest I have in
> such automation.
Proposal:
- Whenever up
On 5/22/20 6:48 PM, Laszlo Ersek wrote:
On 05/22/20 18:46, Laszlo Ersek wrote:
the spec led me to believe
Well, if I had read a few more pages from the spec... It's totally my
fault! :) sorry, it's Friday! :)
No worries, thanks for taking the time to dig into this.
I had already noticed
On 05/22/20 18:46, Laszlo Ersek wrote:
> the spec led me to believe
Well, if I had read a few more pages from the spec... It's totally my
fault! :) sorry, it's Friday! :)
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On 05/22/20 18:36, Laszlo Ersek wrote:
> On 05/21/20 23:58, Ard Biesheuvel wrote:
>
>> ConnectController() does not work for these handles - that will result
>> in the created PciIo protocol to be connected immediately as well (the
>> non-recursive bit about ConnectController() appears to refer to
On 05/21/20 23:58, Ard Biesheuvel wrote:
> ConnectController() does not work for these handles - that will result
> in the created PciIo protocol to be connected immediately as well (the
> non-recursive bit about ConnectController() appears to refer to
> connecting newly created handles by bus dri
We’d like to ask that this patch be considered for the stable tag:
[PATCH v1 1/1] UnitTestFrameworkPkg/UnitTestResultReportLib: Use AsciiStrnCpyS()
https://bugzilla.tianocore.org/show_bug.cgi?id=2721
The patch was reviewed prior to the hard freeze date, and is a small change
that affects new(ish)
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a DR7 read or write intercept generates a #VC exception.
> The #VC handler must provide special support to the guest for this. On
> a DR7 write, the #VC handler must cache the val
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a MWAIT/MWAITX intercept generates a #VC exception.
> VMGEXIT must be used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a MONITOR/MONITORX intercept generates a #VC exception.
> VMGEXIT must be used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc:
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a RDTSCP intercept generates a #VC exception. VMGEXIT must be
> used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Bieshe
On 05/22/20 16:48, Laszlo Ersek wrote:
> On 05/19/20 23:50, Lendacky, Thomas wrote:
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>
>> Under SEV-ES, a VMMCALL intercept generates a #VC exception. VMGEXIT must
>> be used to allow the hypervisor to handle this intercept.
>>
>> Cc: Jorda
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a VMMCALL intercept generates a #VC exception. VMGEXIT must
> be used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Biesh
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a INVD intercept generates a #VC exception. VMGEXIT must be
> used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Biesheuv
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a RDPMC intercept generates a #VC exception. VMGEXIT must be
> used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Biesheu
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a RDTSC intercept generates a #VC exception. VMGEXIT must be
> used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Biesheu
On 05/22/20 16:14, Laszlo Ersek wrote:
> INT64 Displacement;
> Displacement *= (1 << Ext->Sib.Scale);
> (10c) Multiplying a negative INT64 by 1, 2, 4, or 8 is well-defined
> (assuming again that the initial Displacement value is small enough,
> which depends on the original instruction).
>
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a WBINVD intercept generates a #VC exception. VMGEXIT must be
> used to allow the hypervisor to handle this intercept.
>
> Cc: Jordan Justen
> Cc: Laszlo Ersek
> Cc: Ard Bieshe
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a NPF intercept for an NPT entry with a reserved bit set
> generates a #VC exception. This condition is assumed to be an MMIO access.
> VMGEXIT must be used to allow the hypervisor
On 5/22/20 5:05 AM, Laszlo Ersek wrote:
On 05/21/20 19:25, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7C6eeb665fe
On 5/21/20 12:25 PM, Laszlo Ersek wrote:
On 05/19/20 23:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2198&data=02%7C01%7Cthomas.lendacky%40amd.com%7Ccba3f15d7c694d95e8e908d7fdabffd6%7C3dd8961fe4884
On 5/22/20 12:54 PM, Leif Lindholm wrote:
On Thu, May 21, 2020 at 22:22:58 +0200, Laszlo Ersek wrote:
On 05/21/20 16:16, Leif Lindholm wrote:
OK, then I would vote *for* merging the patch regardless. We know how
long some toolchain versions can stick around simply because they were
mentioned i
On Fri, May 22, 2020 at 14:42:34 +0200, Ard Biesheuvel wrote:
> > > > > ---
> > > > > The GCC support for this pragma has already been pulled into the 10.2
> > > > > release branch. I think we should consider adding this to the stable
> > > > > tag, so that the issue can easily be resolved by upgra
From: Radoslaw Biernacki
Linaro LDCG group is coordinating work for adding SBSA compliant
virtual platform for QEMU. This patch adds initial support for this
platform with nondiscoverable AHCI, VGA and single DRAM window over
32bit address space.
We are using FDF to compose EFI flash images with
On 5/22/20 2:14 PM, Leif Lindholm wrote:
On Fri, May 22, 2020 at 14:05:02 +0200, Ard Biesheuvel wrote:
On 5/22/20 1:41 PM, Leif Lindholm wrote:
On Fri, May 22, 2020 at 12:12:02 +0200, Ard Biesheuvel wrote:
GCC 10 enabled a feature by default that was introduced in GCC 9,
which results in atomi
On Fri, May 22, 2020 at 14:06:16 +0200, Ard Biesheuvel wrote:
> On 5/22/20 2:03 PM, Leif Lindholm wrote:
> > On Fri, May 22, 2020 at 10:40:06 +0200, Ard Biesheuvel wrote:
> > > The way the BDS handles the short-form USB device path of the console
> > > keyboard relies on USB host controllers to be
On Fri, May 22, 2020 at 14:05:02 +0200, Ard Biesheuvel wrote:
> On 5/22/20 1:41 PM, Leif Lindholm wrote:
> > On Fri, May 22, 2020 at 12:12:02 +0200, Ard Biesheuvel wrote:
> > > GCC 10 enabled a feature by default that was introduced in GCC 9,
> > > which results in atomic operations to be emitted a
On 5/22/20 2:03 PM, Leif Lindholm wrote:
On Fri, May 22, 2020 at 10:40:06 +0200, Ard Biesheuvel wrote:
The way the BDS handles the short-form USB device path of the console
keyboard relies on USB host controllers to be locatable via their PCI
metadata, which implies that these controllers alread
On 5/22/20 1:41 PM, Leif Lindholm wrote:
On Fri, May 22, 2020 at 12:12:02 +0200, Ard Biesheuvel wrote:
GCC 10 enabled a feature by default that was introduced in GCC 9,
which results in atomic operations to be emitted as function calls
to intrinsics provided by a runtime library.
Atomics are ha
On Fri, May 22, 2020 at 10:40:06 +0200, Ard Biesheuvel wrote:
> The way the BDS handles the short-form USB device path of the console
> keyboard relies on USB host controllers to be locatable via their PCI
> metadata, which implies that these controllers already have a PCI I/O
> protocol installed
Hello Bob and Liming,
What do you think about the patch? Do you think it goes in the right direction?
Regards,
Pierre
-Original Message-
From: devel@edk2.groups.io On Behalf Of PierreGondois
via groups.io
Sent: Monday, May 18, 2020 3:32 PM
To: Pierre Gondois ; devel@edk2.groups.io
Cc: b
On Fri, May 22, 2020 at 12:12:02 +0200, Ard Biesheuvel wrote:
> GCC 10 enabled a feature by default that was introduced in GCC 9,
> which results in atomic operations to be emitted as function calls
> to intrinsics provided by a runtime library.
>
> Atomics are hardly used in EDK2, which runs on a
On Fri, May 22, 2020 at 11:46:07 +0200, Ard Biesheuvel wrote:
> On 5/22/20 1:02 AM, Wasim Khan wrote:
> > From: Wasim Khan
> >
> > Add PCIe Support for NXP Layerscape SoC which supports
> > different PCIe controllers.
> > Use generic PCIe drivers and wire up PciHostBridgeLib,
> > PciSegmentLib an
On Thu, May 21, 2020 at 22:22:58 +0200, Laszlo Ersek wrote:
> On 05/21/20 16:16, Leif Lindholm wrote:
>
> > OK, then I would vote *for* merging the patch regardless. We know how
> > long some toolchain versions can stick around simply because they were
> > mentioned in some blog post somewhere tha
From: Wasim Khan
NXP SoC has multiple PCIe RCs and there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for different RCs for IO access.
Signed-off-by: Wasim Khan
---
Silicon/NXP/Drivers
From: Wasim Khan
Define PCIe related PCDs for LS1043A.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 8
1 file changed, 8 insertions(+)
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 67
From: Wasim Khan
Dump ATU windows for PCIe LsGen4 controller if PcdPciDebug
is enabled.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 +
.../Library/PciHostBridgeLib/PciHostBridgeLib.c| 34 ++
2 files
From: Wasim Khan
Add PCIe related PCDs.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
Silicon/NXP/NxpQoriqLs.dec | 9 +
1 file changed, 9 insertions(+)
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 0722f59ef4f6..bafdfd9f4298 100644
--- a/Sili
From: Wasim Khan
Add PCIe Support for NXP Layerscape SoC which supports
different PCIe controllers.
Use generic PCIe drivers and wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe driver for controller
specific implementation.
Wasim Khan (16):
Silicon/NXP/NxpQoriqLs.dec: Add PCIe related
From: Wasim Khan
PCIe Layerscape Gen4 controller is not ECAM complaint and have
different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For config transactio
From: Wasim Khan
PCIe Layerscape controller can be enabled for ECAM style
configuration access using CFG SHIFT Feature.
Check for PcdPciCfgShiftEnable to decide the configuration access
scheme to be used with PCIe LS controller.
Signed-off-by: Wasim Khan
---
Silicon/NXP/Library/PciSegmentLib/
From: Wasim Khan
Setup PCIe LayerscapeGen4 controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Check for PcdPciLsGen4Ctrl to enable LsGen4 PCIe
controller.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
Silicon/NXP/NxpQoriqLs.dec | 1 +
.../Librar
From: Wasim Khan
When PCIe Layerscape Gen4 controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split completions
and FC update DLLP,the controller does not give priority to ACK
transmission. This r
From: Wasim Khan
With PCIe LsGen4 controller, clearing the Bus Master Enable bit in
Command register blocks all outbound transactions to be sent out
in RC mode.
According to PCI Express base specification, the Command register’s
Bus Master Enable bit of a PCI Express RC controller can only
contr
From: Wasim Khan
Enable generic PCIe drivers and Wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe.
Signed-off-by: Wasim Khan
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 +
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 7 +++
2 files changed, 16 insertions(+)
diff
From: Wasim Khan
We have different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs with PCIe LS controller.
Add PciSegmentLib for PCIe LS controller.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For config
From: Wasim Khan
PCIe layerscape controller supports CFG Shift feature. It can be
enabled by setting BIT[28] of iATU Control 2 Register.
Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in
PCIe controller.
if enable, PCIe layerscape controller shifts BDF from bits[27:12] to
bits[31:16] an
From: Wasim Khan
Implement PciHostBridgeLib that exposes the PCIe root complexes to
the generic PCI host bridge driver.
Setup PCIe Layerscape Controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib/Pc
From: Wasim Khan
Dump ATU windows for PCIe Layerscape controller if PcdPciDebug
is enabled.
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.c| 42 ++
1 file changed, 42 insertions(+)
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostB
From: Wasim Khan
Increase fv image size to pass debug build.
Signed-off-by: Wasim Khan
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
b/Platform/NXP/LS1043aRdbPkg/LS1043a
From: Wasim Khan
Enable NetworkPkg for LS1043aRdb Platform.
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Wasim Khan
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 11 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 5 +
2 files changed, 16 insertions(+)
diff --git a/P
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must
> be used to allow the hypervisor to handle this intercept.
>
> Add support to construct the required GHCB values to
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be
> used to allow the hypervisor to handle this intercept.
>
> Add support to construct the required GHCB values to sup
On 05/19/20 23:50, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>
> Add support to the #VC exception handler to handle string IO. This
> requires expanding the IO instruction parsing to recognize string based
> IO instructions as well as preparing an un-encrypt
GCC 10 enabled a feature by default that was introduced in GCC 9,
which results in atomic operations to be emitted as function calls
to intrinsics provided by a runtime library.
Atomics are hardly used in EDK2, which runs on a single CPU anyway,
and any benefit that would result from reusing libra
On 05/21/20 19:25, Laszlo Ersek wrote:
> On 05/19/20 23:50, Lendacky, Thomas wrote:
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
>>
>> Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT
>> must be used to allow the hypervisor to handle this intercept.
>>
>> Add sup
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Add PCIe Support for NXP Layerscape SoC which supports
different PCIe controllers.
Use generic PCIe drivers and wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe driver for controller
specific implementation.
Thanks. This is looki
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Increase fv image size to pass debug build.
Signed-off-by: Wasim Khan
Acked-by: Ard Biesheuvel
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Platform/N
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Enable NetworkPkg for LS1043aRdb Platform.
Signed-off-by: Meenakshi Aggarwal
Drop the signoff please. If Meenakshi wrote the patch, make them the
author not the submitter.
Signed-off-by: Wasim Khan
---
Platform/NXP/LS1043aRdbPkg/
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
NXP SoC has multiple PCIe RCs and there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for different RCs for IO access.
Signed-off-
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
With PCIe LsGen4 controller, clearing the Bus Master Enable bit in
Command register blocks all outbound transactions to be sent out
in RC mode.
According to PCI Express base specification, the Command register’s
Bus Master Enable bit of a
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
PCIe Layerscape Gen4 controller is not ECAM complaint and have
compliant
different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs.
For config transactions for Bus0:
- Config transaction address =
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
PCIe Layerscape controller can be enabled for ECAM style
configuration access using CFG SHIFT Feature.
Check for PcdPciCfgShiftEnable to decide the configuration access
scheme to be used with PCIe LS controller.
Signed-off-by: Wasim Khan
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Dump ATU windows for PCIe LsGen4 controller if PcdPciDebug
is enabled.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 +
.../Library/PciHostBridgeLib/PciHostBridgeLib
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Dump ATU windows for PCIe Layerscape controller if PcdPciDebug
is enabled.
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.c| 42 ++
1 file changed, 42 insertions(+)
diff --git a/Sil
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
We have different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs with PCIe LS controller.
Add PciSegmentLib for PCIe LS controller.
For config transactions for Bus0:
- Config transaction address = PCI
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Setup PCIe LayerscapeGen4 controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Check for PcdPciLsGen4Ctrl to enable LsGen4 PCIe
controller.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
How much overlap is there between
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
PCIe layerscape controller supports CFG Shift feature. It can be
enabled by setting BIT[28] of iATU Control 2 Register.
Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in
PCIe controller.
if enable, PCIe layerscape controller shift
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Implement PciHostBridgeLib that exposes the PCIe root complexes to
the generic PCI host bridge driver.
Setup PCIe Layerscape Controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Kh
On 5/22/20 1:02 AM, Wasim Khan wrote:
From: Wasim Khan
Add PCIe related PCDs.
Signed-off-by: Vabhav Sharma
Please drop this signoff. This is not the correct way to acknowledge
(co-)authorship.
Signed-off-by: Wasim Khan
---
Silicon/NXP/NxpQoriqLs.dec | 9 +
1 file changed, 9
The way the BDS handles the short-form USB device path of the console
keyboard relies on USB host controllers to be locatable via their PCI
metadata, which implies that these controllers already have a PCI I/O
protocol installed on their handle.
This is not the case for non-discoverable USB host c
On 5/21/20 10:22 PM, Laszlo Ersek wrote:
On 05/21/20 16:16, Leif Lindholm wrote:
OK, then I would vote *for* merging the patch regardless. We know how
long some toolchain versions can stick around simply because they were
mentioned in some blog post somewhere that ended up high in search
rankin
Hi, all
Today, we enter into Hard Feature Freeze phase until edk2-stable202005 tag is
created at 2020-05-29. In this phase, there is no feature to be pushed. The
critical bug fix is still allowed.
If the patch is sent after Hard Feature Freeze, and plans to catch this
stable tag, please add
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