[PATCH] D79877: [clang][SveEmitter] SVE builtins for `svusdot` and `svsudot` ACLE.

fpetrogalli created this revision. fpetrogalli added reviewers: sdesmalen, efriedma, david-arm. Herald added subscribers: cfe-commits, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. fpetrogalli added a parent revision: D79639: [SveEmitter] Builtins for SV

[PATCH] D79639: [SveEmitter] Builtins for SVE matrix multiply `mmla`.

fpetrogalli updated this revision to Diff 264074. fpetrogalli marked 2 inline comments as done. fpetrogalli added a comment. Thank you for the review @sdesmalen! Francesco Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79639/new/ https://reviews.ll

[PATCH] D79639: [SveEmitter] Builtins for SVE matrix multiply `mmla`.

fpetrogalli added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c:17 + // CHECK: ret %[[RET]] + return SVE_ACLE_FUNC(svmmla, _s32, , )(x, y, z); +} sdesmalen wrote: > nit: please remove the whitespace between the commas (

[PATCH] D79877: [clang][SveEmitter] SVE builtins for `svusdot` and `svsudot` ACLE.

fpetrogalli marked 2 inline comments as done. fpetrogalli added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:1249 +def SVSUDOT_S: SInst<"svsudot[_s32]","ddqb", "i", MergeNone, "aarch64_sve_usdot", [ReverseUSDOT]>; +def SVSUDOT_N_S : SInst<"svs

[PATCH] D79639: [SveEmitter] Builtins for SVE matrix multiply `mmla`.

This revision was automatically updated to reflect the committed changes. Closed by commit rGe2cc12e41282: [SveEmitter] Builtins for SVE matrix multiply `mmla`. (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79639/new/ http

[PATCH] D79877: [clang][SveEmitter] SVE builtins for `svusdot` and `svsudot` ACLE.

fpetrogalli updated this revision to Diff 264735. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. Fix formatting of code in test. NFC Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79877/new/ https://reviews.llvm.org/D7987

[PATCH] D79877: [clang][SveEmitter] SVE builtins for `svusdot` and `svsudot` ACLE.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:1249 +def SVSUDOT_S: SInst<"svsudot[_s32]","ddqb", "i", MergeNone, "aarch64_sve_usdot", [ReverseUSDOT]>; +def SVSUDOT_N_S : SInst<"svs

[PATCH] D79877: [clang][SveEmitter] SVE builtins for `svusdot` and `svsudot` ACLE.

This revision was automatically updated to reflect the committed changes. Closed by commit rGb593bfd4d8e3: [clang][SveEmitter] SVE builtins for `svusdot` and `svsudot` ACLE. (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D798

[PATCH] D85977: [release][docs] Update contributions to LLVM 11 for SVE.

fpetrogalli added a comment. I merged it in the release branch as https://github.com/llvm/llvm-project/commit/7e6bf0bfe6de9e0d0e58764a66f93210f296bbfa Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D85977/new/ https://reviews.llvm.org/D85977 __

[PATCH] D86065: [SVE] Make ElementCount members private

fpetrogalli added inline comments. Comment at: llvm/include/llvm/Support/TypeSize.h:56 + friend bool operator>(const ElementCount &LHS, const ElementCount &RHS) { +assert(LHS.Scalable == RHS.Scalable && paulwalker-arm wrote: > david-arm wrote: > > ctetreau

[PATCH] D86065: [SVE] Make ElementCount members private

fpetrogalli added a comment. In D86065#2235434 , @david-arm wrote: > Hi @fpetrogalli, if you don't mind I think I'll stick with Paul's idea for > ogt because this matches the IR neatly, i.e. "fcmp ogt". Also, for me > personally it's much simpler and mor

[PATCH] D90956: [clang][SVE] Additional macros implied by `-msve-vector-bits=`.

fpetrogalli created this revision. fpetrogalli added reviewers: peterwaller-arm, paulwalker-arm, efriedma, c-rhodes. Herald added subscribers: cfe-commits, psnobl, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. fpetrogalli requested review of this revisi

[PATCH] D90956: [clang][SVE] Additional macros implied by `-msve-vector-bits=`.

fpetrogalli updated this revision to Diff 303805. fpetrogalli added a comment. NFC: update tests to use `%clang_cc1` instead of `%clang` to prevent errors for missing includes: https://reviews.llvm.org/B77907 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llv

[PATCH] D90956: [clang][SVE] Additional macros implied by `-msve-vector-bits=`.

fpetrogalli updated this revision to Diff 303908. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. I removed the enablement of __ARM_FEATURE_SVE_PREDICATE_OPERATORS as the codegen is incorrect. I have extended testing of the codegen for __ARM_FEATURE_SVE_VECTOR_OPERATOR

[PATCH] D90956: [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`.

fpetrogalli updated this revision to Diff 303911. fpetrogalli edited the summary of this revision. fpetrogalli added a comment. In the last update I removed the tests for `__ARM_FEATURE_SVE_PREDICATE_OPERATORS`but forgot to remove the code that generates and tests the macro. Repository: rG L

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

fpetrogalli added a comment. Hi @joechrisellis - thank you for this patch! I have left a couple of comments. Francesco Comment at: clang/lib/AST/ASTContext.cpp:8563-8566 +if (const auto *BT = FirstType->getAs()) { + if (const auto *VT = SecondType->getAs()) { +

[PATCH] D90956: [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`.

fpetrogalli updated this revision to Diff 304473. fpetrogalli added a comment. I have added more test coverage for the codegen of the examples mentioned in section 3.7.3.3 of the SVE ACLE. The tests are generic to work for `-msve-vector-bits=128|...|2048`. Repository: rG LLVM Github Monorepo

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

fpetrogalli accepted this revision. fpetrogalli added a comment. This revision is now accepted and ready to land. Thank you @joechrisellis - LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91067/new/ https://reviews.llvm.org/D91067 __

[PATCH] D90956: [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`.

fpetrogalli added a comment. @rengolin - thank you for looking into this. The patch has changed quite a bit since you approved it (faulty codegen for one of the macros, which I have removed from this patch). You might want to re-look at it. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

fpetrogalli added inline comments. Comment at: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp:1 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestandi

[PATCH] D91333: [clang][SveEmitter] Fix enum declarations. [NFCI]

fpetrogalli created this revision. fpetrogalli added reviewers: peterwaller-arm, paulwalker-arm, joechrisellis, efriedma. Herald added subscribers: cfe-commits, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. fpetrogalli requested review of this revision.

[PATCH] D91333: [clang][SveEmitter] Fix enum declarations. [NFCI]

fpetrogalli updated this revision to Diff 304941. fpetrogalli added a comment. Improve comment in test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91333/new/ https://reviews.llvm.org/D91333 Files: clang/test/Sema/aarch64-sve-enums.c clang/u

[PATCH] D91333: [clang][SveEmitter] Fix enum declarations. [NFCI]

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG02bdbdc76021: [clang][SveEmitter] Fix enum declarations. [NFCI] (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D91642: [AArch64][SVE] Add tests for VLST -> VLAT lax conversions

fpetrogalli accepted this revision. fpetrogalli added a comment. This revision is now accepted and ready to land. HI @joechrisellis - thank you. This LGTM. Please make sure to specify a link to the original patch on phabricator in the commit message before submitting. Repository: rG LLVM Gi

[PATCH] D91696: [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors

fpetrogalli accepted this revision. fpetrogalli added a comment. This revision is now accepted and ready to land. This LGTM. May I ask to extend the commit message to add a reference to the paragraph in section "3.7.3.3", item 2 on page 23 of the specs version 00bet6? Repository: rG LLVM Gith

[PATCH] D91806: [SVE] Remove warnings from release notes example on SVE ACLE.

fpetrogalli created this revision. fpetrogalli added reviewers: peterwaller-arm, efriedma, paulwalker-arm, joechrisellis, sdesmalen. Herald added subscribers: llvm-commits, cfe-commits, dexonsmith, lxfind, psnobl, hiraditya, tschuett. Herald added projects: clang, LLVM. fpetrogalli requested revi

[PATCH] D91806: [SVE] Remove warnings from release notes example on SVE ACLE.

fpetrogalli updated this revision to Diff 306626. fpetrogalli added a comment. I updated the RUN lines of the `.ll` test to prevent the failure at https://reviews.llvm.org/harbormaster/unit/view/196899/. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org

[PATCH] D91806: [SVE] Remove warnings from release notes example on SVE ACLE.

fpetrogalli added a comment. FYI: I am trying to figure out this failure that does not appear on my machine: https://reviews.llvm.org/harbormaster/unit/view/196974/ Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91806/new/ https://reviews.llvm.org/

[PATCH] D91806: [SVE] Remove warnings from release notes example on SVE ACLE.

fpetrogalli updated this revision to Diff 306643. fpetrogalli added a comment. This last change is trying to remove the failure at https://reviews.llvm.org/harbormaster/unit/view/196974/ I haven’t been able to reproduce such failure on my dev machine, so I just changed the RUN lines in the test

[PATCH] D91806: [SVE] Remove warnings from release notes example on SVE ACLE.

fpetrogalli updated this revision to Diff 306684. fpetrogalli added a comment. I have removed the C test, as the LL test is enough to test the changes I have done in `Local.cpp`. I can confirm that with this patch, the release note ton'r raise any warnings when compiling with debug info: fra

[PATCH] D88154: Initial support for vectorization using Libmvec (GLIBC vector math library).

fpetrogalli added inline comments. Comment at: llvm/include/llvm/Analysis/TargetLibraryInfo.h:91 Accelerate, // Use Accelerate framework. +LIBMVEC,// GLIBC Vector Math library. MASSV, // IBM MASS vector library. Can we call this LIBMVEC-X86

[PATCH] D88154: Initial support for vectorization using Libmvec (GLIBC vector math library).

fpetrogalli added inline comments. Comment at: llvm/include/llvm/Analysis/TargetLibraryInfo.h:91 Accelerate, // Use Accelerate framework. +LIBMVEC,// GLIBC Vector Math library. MASSV, // IBM MASS vector library. nemanjai wrote: > fpetrogall

[PATCH] D88154: Initial support for vectorization using Libmvec (GLIBC vector math library).

fpetrogalli added a comment. Hi, Thank you for modifying the implementation to facilitate the extension to other targets. Please add `libmvec`-specific tests is `clang/Driver/fveclib.c`, and simplify the loop-vectorize tests. Other than that, I only have minor comments. Francesco

[PATCH] D88154: Initial support for vectorization using Libmvec (GLIBC vector math library).

fpetrogalli added a comment. LGTM from the perspective of making sure that this solution can be extended to any of the architectures that `libmvec` supports. Thank you. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D88154/new/ https://reviews.llvm.org/D88154 __

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli marked an inline comment as done. fpetrogalli added a comment. Thank you for the review @sdesmalen 1. I have replied to the comment about `auto` with my reason for removing it. 2. I removed the C test, as the LL file is enough. 3. The third comment requires more investigation, I'll ge

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli updated this revision to Diff 306715. fpetrogalli edited the summary of this revision. fpetrogalli added a comment. I have added assertions around before `TypeSize` comparisons where it made sense to do so, but not in the lambda used in the `sort` invocation. Repository: rG LLVM G

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/lib/Transforms/Coroutines/CoroFrame.cpp:589 sort(FrameData.Allocas, [&](const auto &Iter1, const auto &Iter2) { -return GetAllocaSize(Iter1) > GetAllocaSize(Iter2); +retur

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli updated this revision to Diff 307306. fpetrogalli added a comment. Rebase on top of D92020 . NFC. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91806/new/ https://reviews.llvm.org/D91806 Files: llvm/i

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli updated this revision to Diff 307329. fpetrogalli added a comment. Add comment to `DbgVariableIntrinsic::getFragmentSizeInBits()`. NFC Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91806/new/ https://reviews.llvm.org/D91806 Files: ll

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli added a comment. Hi @sdesmalen I have extracted D92020 to implement only the change of interface for `AllocaInst::getAllocationSizeInBits`. I wanted to extract also the interface change in `DbgVariableIntrinsic::getFragmentSizeInBits()` but such ch

[PATCH] D90956: [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGe592dde6889b: [clang][SVE] Activate macro `__ARM_FEATURE_SVE_VECTOR_OPERATORS`. (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CH

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

fpetrogalli updated this revision to Diff 308078. fpetrogalli added a comment. Reverted `getFragmentSizeInBits` to return an integral type and not `TypeSize`, because scalable variables cannot be part of structs/arrays - hence they cannot be pointed by fragments. Repository: rG LLVM Github M

[PATCH] D88233: [clang][aarch64] Address various fixed-length SVE vector operations

fpetrogalli added a comment. Hi @c-rhodes, Peter asked me to take a look at this. LGTM, I only have minor stuff. In the commit message: > Arm C Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1]. It seems that a reference to [1] is missing: https://developer.arm.com/docu

[PATCH] D88233: [clang][aarch64] Address various fixed-length SVE vector operations

fpetrogalli accepted this revision. fpetrogalli added a comment. This revision is now accepted and ready to land. LGTM, thank you! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D88233/new/ https://reviews.llvm.org/D88233 ___ cfe-commits mailin

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484283. fpetrogalli added a comment. Herald added a subscriber: pengfei. This update is not based anymore on D137516 , but uses the refactoring of `TargetParser` as part of `LLVMSupport` into the new component `LLVMTarge

[PATCH] D137516: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli abandoned this revision. fpetrogalli added a comment. Replaced by D137838 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137516/new/ https://reviews.llvm.org/D137516 ___

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. Hi - gentle ping on reviewing this Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) lenary wrote: > craig.topper wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) craig.topper wrote: > fpetrogalli wrote: > > lenary wrote: > > > crai

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484380. fpetrogalli marked 8 inline comments as done. fpetrogalli added a comment. 1. I have split the RISCV bits of the target parser out of TargetParser.cpp so that none of the non-RISCV components need to include the folder with the autogenerated .inc

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484391. fpetrogalli added a comment. @pcwang-thead, I addressed some of your comments. The value of `EnumFeatures` is now computed dynamicaly from the `Features` field of the `Processor` class. As for generating `MArch` out of the `Features` field, @crai

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) lenary wrote: > fpetrog

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a subscriber: aprantl. fpetrogalli added inline comments. Comment at: llvm/include/llvm/module.modulemap:420 textual header "Support/CSKYTargetParser.def" -textual header "Support/RISCVTargetParser.def" textual header "Support/TargetOpcodes.def" --

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484561. fpetrogalli added a comment. There is no need to use `target_include_directories(LLVMRISCVDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)` for components that are not related to the RISC-V target. Thank you @lenary for the suggestion! Repositor

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484563. fpetrogalli added a comment. NFC - I just restored an empty line to prevent modifying a file that is not being touched by the patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https:

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484564. fpetrogalli added a comment. Same NFC - restore an empty line change... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Targets/R

[PATCH] D137838: [Support] Move TargetParsers to new component

fpetrogalli added a comment. In D137838#4010987 , @dblaikie wrote: > This has introduced a circular dependency due to the forwarding header > (forwarding header depends on new lib, new lib depends on support, where the > forwarding header is). Generally

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484649. fpetrogalli marked 5 inline comments as done. fpetrogalli added a comment. I submitted some of the cleanup suggested by @barannikov88 - thank you! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:15 +#include "llvm/TableGen/Record.h" +#include +namespace llvm { barannikov88 wrote: > [[ > https://llvm.org/docs/CodingStandards.html#include-iostream-is-forbidden |

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/lib/TargetParser/CMakeLists.txt:29 +# LLVMTargetParser. See https://stackoverflow.com/a/25681179 +target_include_directories(LLVMTargetParser PUBLIC $) barannikov88

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:52 + for (auto &Def : Map) { +const auto &Record = Def.second; +if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC")) --

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484654. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. ops - this was wrong: /Users/fpetrogalli/projects/cpu-defs/upstream/llvm-project/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:38:17: error: variable 'Record' with type

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484655. fpetrogalli added a comment. Restore the following... -const auto *Record = Def.second; +const auto &Record = Def.second; ... to prevent this error: /<...>/llvm-project/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:38:17: error: v

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484658. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. Remove `RISCVTargetParser.def` from the module map. Follow the guidelines on using namespace llvm

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4009328 , @jrtc27 wrote: > Hm, this means that llvm/lib/Target/$TARGET/$TARGET.td needs to remain > working (or at least mostly working, things like ISel patterns can fail to > type check) in order for Clang to bu

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484664. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. Remove all `auto` types in the emitter. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:52 + for (auto &Def : Map) { +const auto &Record = Def.second; +if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC")) barannikov88 wrote: > fpetrogalli wrote

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484795. fpetrogalli added a comment. I added some fixes to make it work when building with modules (`-DLLVM_ENABLE_MODULES=On`). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.ll

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4012449 , @pcwang-thead wrote: > In D137517#4012307 , @craig.topper > wrote: > >> In D137517#4012298 , @pcwang-thead >> wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 485852. fpetrogalli added a comment. NFC - just an update on top of current `main`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Targe

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 485858. fpetrogalli added a comment. Fix pre-merge check at https://buildkite.com/llvm-project/premerge-checks/builds/128468#0185724f-5ade-4603-99ce-f417efb546e8 (missing header inclusion): C:\ws\w3\llvm-project\premerge-checks\llvm\include\llvm/Targ

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. @craig.topper @lenary @barannikov88 @pcwang-thead - New Year's gentle ping :) Thank you, Francesco Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 __

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 486222. fpetrogalli added a comment. I have addressed last round of review from @craig.topper and @pcwang-thead: 1. Renamed the RISCV-specific classes for the ProcessorModel. 2. Swapped `tunef` with `f` in `RISCVTuneProcessorModel`. 3. Fixed comment. 4. A

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 486223. fpetrogalli added a comment. [NFC] Restore empty line before end of namespace. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Ta

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. Gentle ping! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 487962. fpetrogalli added a comment. Formatting changes in RISCV.td (NFC). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Targets/RISCV.

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

This revision was automatically updated to reflect the committed changes. Closed by commit rGcf7a8305a2b4: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen. (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. After submitting this, I had to revert it because of failures like https://lab.llvm.org/buildbot/#/builders/225/builds/12367/steps/5/logs/stdio Repository: rG LLVM Github Mono

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4042758 , @fpetrogalli wrote: > After submitting this, I had to revert it > > because of failures like > https://lab.llvm.or

[PATCH] D137515: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli created this revision. Herald added subscribers: kosarev, foad, frasercrmck, kerbowa, luismarques, apazos, sameer.abuasal, pengfei, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, a

[PATCH] D137515: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli abandoned this revision. fpetrogalli added a comment. Abandoning because I accidentally squashed the two commits together when using Arcanist. I'll follow up with two new revisions. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137515/n

[PATCH] D137516: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli created this revision. Herald added subscribers: kosarev, foad, frasercrmck, kerbowa, luismarques, apazos, sameer.abuasal, pengfei, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, a

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli created this revision. Herald added subscribers: kosarev, sunshaoce, VincentWu, foad, vkmr, frasercrmck, evandro, kerbowa, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiv

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 473532. fpetrogalli added a comment. I updated the text of the header of the file `RISCVTargetDefEmitter.cpp`. NFC. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517

[PATCH] D137516: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli added a comment. RFC at https://discourse.llvm.org/t/targetparser-auto-generation-of-riscv-cpu-definitions/66419 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137516/new/ https://reviews.llvm.org/D137516 __

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. RFC at RFC at https://discourse.llvm.org/t/targetparser-auto-generation-of-riscv-cpu-definitions/66419 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 ___

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 473545. fpetrogalli added a comment. I have made the dependency on `RISCVTargetSupportTableGen` explicit in the `RISCVCodeGen` target. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://revi

[PATCH] D137516: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli added a comment. @arsenm @frasercrmck @lenary - thank you for the feedback 1. The library could host anything that needs to be auto-generated with tablegen. If we add `MVT`s, the name `TargetSupport` becomes obsolete. 2. Therefore we could use a name like `AutoGenSupport` (or similar

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:509 -def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; -def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +class RISCVProcessorModelPROC { + string Enum = enum; --

[PATCH] D137516: [TargetSupport] Move TargetParser API in a separate LLVM component.

fpetrogalli added a comment. In D137516#3912842 , @lenary wrote: > In D137516#3912751 , @fpetrogalli > wrote: > >> @arsenm @frasercrmck @lenary - thank you for the feedback >> >> 1. The library could host anythin

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 473738. fpetrogalli added a comment. When looping through the records in tablegen, I have added an extra (necessary) condition to make sure that the records we are processing are also derived from the class `ProcessorModel`. Repository: rG LLVM Gith

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/lib/TargetSupport/CMakeLists.txt:2 + +set(LLVM_TARGET_DEFINITIONS ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/RISCV.td) + tmatheson wrote: > Here `RISCVTargetSupportTableGen` depends on files in `lib/Target/RISCV`, >

[PATCH] D137838: [RFC][Support] Move TargetParsers to new component

fpetrogalli added a comment. Hi @lenary - thank you for working on this! The patch is reasonable to me. I agree on the suggestion of using forwarding headers or the first iteration of the change, it will make it easier to review. I'll adapt the auto-get patch at D137517

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 474817. fpetrogalli added a comment. I have applied the chaged suggested by @jrtc27: 1. The classes `RISCVProcessorModelPROC` and `RISCVProcessorModelTUNE_PROC` now are derived from `ProcessorModel`; 2. The `Enum` field is removed from both classes. What

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. I intend to base this patch on D137838 once it goes through the major refactoring of bridging the header files. For the sake of simplicity, for now I'll keep it on top of D137516 . Repository:

[PATCH] D137838: [RFC][Support] Move TargetParsers to new component

fpetrogalli added a comment. @lenary - thank you for the update! I have added a bunch of miso comments, a bit repetitive... by the time I realised they were repetitive it was faster to get to the bottom of it than removing them! In D137838#3931295 , @l

[PATCH] D142976: [clang][CGCall] Remove header file not used. [NFCI]

fpetrogalli created this revision. Herald added a project: All. fpetrogalli requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D142976 Files: clang/lib/CodeGen/CGCall.cpp Ind

[PATCH] D142976: [clang][CGCall] Remove header file not used. [NFCI]

fpetrogalli accepted this revision. fpetrogalli added a comment. This revision is now accepted and ready to land. Self approving a non-controversial trivial change. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142976/new/ https://reviews.llvm.org/

[PATCH] D142976: [clang][CGCall] Remove header file not used. [NFCI]

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG20f3ebd25885: [clang][CGCall] Remove header file not used. [NFCI] (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/include/llvm/TargetParser/CMakeLists.txt:3 +tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/) +add_public_tablegen_target(RISCVT

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added a comment. In D137517#4045299 , @jrtc27 wrote: > In D137517#4042875 , @fpetrogalli > wrote: > >> In D137517#4042758

<    1   2   3   >