fpetrogalli added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCV.td:509
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROC<string enum, string enum_features, string
default_march> {
+ string Enum = enum;
----------------
pcwang-thead wrote:
> Can `EnumFeatures/DefaultMarch` string be inferred from ProcessorModel's
> SubtargetFeature if not specified and `Enum` just be the uppercase of the
> name of ProcessorModel? The implementation could be more complicated but I
> think it's worthy.
> Can `EnumFeatures/DefaultMarch` string be inferred from ProcessorModel's
> SubtargetFeature if not specified
Sorry, I don't see how. `SubtargetFeature` is used in the fields `Features` and
`TuneFeatures`. I don't see the logic to extract this information from them.
> and `Enum` just be the uppercase of the name of ProcessorModel? The
> implementation could be more complicated but I think it's worthy.
My preference would be to keep the Enum explicit as it would help using those
enums in the code. Also, sometimes the enum cannot be derived from the Name
(see for example `"sifive-7-series"` vs `"SIFIVE_7"`).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137517/new/
https://reviews.llvm.org/D137517
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