[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

ppenzin wrote: If we are all good, can someone merge this? I don't have write access. https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

ppenzin wrote: Are there still open questions for the sync call? https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

ppenzin wrote: We would take `ascalon-d8`, but `tt-ascalon-d8` is just as good. https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/ppenzin updated https://github.com/llvm/llvm-project/pull/115100 >From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001 From: Petr Penzin Date: Tue, 5 Nov 2024 13:11:48 -0600 Subject: [PATCH 1/4] [RISCV] Add TT-Ascalon-d8 processor Ascalon is an out-of-order

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -104,6 +104,62 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s // MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalo

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/ppenzin updated https://github.com/llvm/llvm-project/pull/115100 >From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001 From: Petr Penzin Date: Tue, 5 Nov 2024 13:11:48 -0600 Subject: [PATCH 1/3] [RISCV] Add TT-Ascalon-d8 processor Ascalon is an out-of-order

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

https://github.com/ppenzin updated https://github.com/llvm/llvm-project/pull/115100 >From 246f1374b31ac11041deffe2f4afc35ee93cc66f Mon Sep 17 00:00:00 2001 From: Petr Penzin Date: Tue, 5 Nov 2024 13:11:48 -0600 Subject: [PATCH 1/2] [RISCV] Add TT-Ascalon-d8 processor Ascalon is an out-of-order

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

ppenzin wrote: > Hi @ppenzin! Is this core used in many-cores products like wormhole? This is separate from AI accelerator cores. https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.ll

[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVP