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LGTM
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@@ -7429,6 +7429,11 @@ class Sema final : public SemaBase {
/// the perspective of SVE bitcasts.
bool isValidSveBitcast(QualType srcType, QualType destType);
+ /// Check for bitcast beween a regular vector type and builtin Neon vector
jthackray wrote:
ty
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@@ -1045,6 +1045,9 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support for SVE2.1 and SME2.1 using the Arm C Language Extensions (ACLE) is
jthackray wrote:
Done.
https://github.com/llvm/llvm-project/pull/122705
_
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/122705
>From 4206edb54ccad4012970ec1b14748f81ccf5b01c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Mon, 13 Jan 2025 13:23:20 +
Subject: [PATCH 1/2] [NFC][AArch64] Add relnote saying SVE2.1 and SME2.1 no
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/122705
None
>From 4206edb54ccad4012970ec1b14748f81ccf5b01c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Mon, 13 Jan 2025 13:23:20 +
Subject: [PATCH] [NFC][AArch64] Add relnote saying SVE2.1 and SME2.1
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/121802
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>From 519bcca2359ee9c89b12bac6e58eb955c79cd7bc Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 20 Dec 2024 14:50:37 +
Subject: [PATCH 1/2] [AArch64] Enable FEAT_SVE2p1 by default for Armv9.4-A
jthackray wrote:
> Actually this is being added as a mandatory dependency of 9.4, should it not
> be added as one of the default features instead?
Good point. I'll amend.
https://github.com/llvm/llvm-project/pull/120753
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LGTM. Merry Christmas :)
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>From e235c1175aee293be30d3fc478d83c9b130e3452 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 13 Dec 2024 20:07:37 +
Subject: [PATCH 1/2] [AArch64] Add intrinsics for SME FP8 FVDOT, FVDOTB and
https://github.com/jthackray closed
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@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --filter-out "// kill:" --version 4
+; RUN: llc -force-streaming < %s | FileCheck %s
+target triple = "aarch64-linux"
+
+define void @test_fvdot16_1x2_indexed(i32 %slice.0,
+
@@ -5882,3 +5882,14 @@ multiclass sme2_fp8_fdot_index_za32_vg1x4;
}
+
+multiclass sme2_fp8_fdotv_index_za32_vg1x4 {
+ def NAME : sme2_fp8_multi_vec_array_vg4_index,
+SMEPseudo2Instr {
+let Uses=[FPMR, FPCR];
jthack
@@ -5882,3 +5882,14 @@ multiclass sme2_fp8_fdot_index_za32_vg1x4;
}
+
+multiclass sme2_fp8_fdotv_index_za32_vg1x4 {
+ def NAME : sme2_fp8_multi_vec_array_vg4_index,
+SMEPseudo2Instr {
+let Uses=[FPMR, FPCR];
+ }
+
+ def _PSEUDO :
@@ -748,11 +748,16 @@ let SMETargetGuard = "sme2" in {
let SMETargetGuard = "sme-f8f32" in {
def SVDOT_LANE_FP8_ZA32_VG1x2 : Inst<"svdot_lane_za32[_mf8]_vg1x2_fpm",
"vm2di>", "m", MergeNone, "aarch64_sme_fp8_fdot_lane_za32_vg1x2", [IsStreaming,
IsInOutZA, SetsFPMR, IsOverloa
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/119922
>From e235c1175aee293be30d3fc478d83c9b130e3452 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 13 Dec 2024 20:07:37 +
Subject: [PATCH 1/2] [AArch64] Add intrinsics for SME FP8 FVDOT, FVDOTB and
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/119922
Add support for the following SME 8 bit floating-point dot-product intrinsics:
```
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svvdot_lane_za16[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
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LGTM
https://github.com/llvm/llvm-project/pull/119568
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@@ -827,11 +827,21 @@ let SMETargetGuard = "sme-lutv2" in {
let SMETargetGuard = "sme-f8f32" in {
def SVMOPA_FP8_ZA32 : Inst<"svmopa_za32[_mf8]_m_fpm", "viPPdd>", "m",
MergeNone, "aarch64_sme_fp8_fmopa_za32",
[IsStreaming, IsInOutZA, SetsFPMR,
I
@@ -827,11 +827,21 @@ let SMETargetGuard = "sme-lutv2" in {
let SMETargetGuard = "sme-f8f32" in {
def SVMOPA_FP8_ZA32 : Inst<"svmopa_za32[_mf8]_m_fpm", "viPPdd>", "m",
MergeNone, "aarch64_sme_fp8_fmopa_za32",
[IsStreaming, IsInOutZA, SetsFPMR,
I
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/119845
Add support for the following SME 8 bit floating-point dot-product intrinsics:
* svdot_single_za16_mf8_vg1x2_fpm(uint32_t slice, svmfloat8x2_t f8x2,
svmfloat8_t f8, fpm_t fpm);
* svdot_single_za16_mf8_vg1x4_f
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>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/8] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/118581
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>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/7] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
@@ -986,8 +986,8 @@ def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00,
0b00, "luti4">;
let Predicates = [HasSMEF8F16] in {
defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fvdot",
0b11, 0b110, ZZ_b_mul_r, ZPR4b8>;
-defm FDOT_VG2_M2ZZI_BtoH : sme2p1
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/118492
>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/6] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
@@ -219,6 +219,37 @@ class SME2_Tile_Movaz_Pat(name # _PSEUDO) $tile, $base, $offset)>;
+
+// FP8 SME FDOT instructions
+
+// Selection DAG patterns - map to first level of pseudo-instructions
(xxx_PSEUDO)
+class SME2_FP8_FMLA_FDOT_Index_VG1x2_Pat
+ : Pat<(intrinsic (i32 (tile
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@@ -0,0 +1,114 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: aarch64-registered-target
+#include
+
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2
-target-feature +sme-f8f16 -
@@ -0,0 +1,114 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: aarch64-registered-target
+#include
+
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2
-target-feature +sme-f8f16 -
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme
-target-feature +sme2 -verify -emit-llvm -o - %s
+
+// REQUIRES: aarch64-registered-target
+
+#include
+
+void test_features(uint32_t slice, svmfloat8_t f8, svmfloat8x2_t f8x2,
+
@@ -986,8 +986,8 @@ def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00,
0b00, "luti4">;
let Predicates = [HasSMEF8F16] in {
defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fvdot",
0b11, 0b110, ZZ_b_mul_r, ZPR4b8>;
-defm FDOT_VG2_M2ZZI_BtoH : sme2p1
@@ -219,6 +219,37 @@ class SME2_Tile_Movaz_Pat(name # _PSEUDO) $tile, $base, $offset)>;
+
+// FP8 SME FDOT instructions
+
+// Selection DAG patterns - map to first level of pseudo-instructions
(xxx_PSEUDO)
+class SME2_FP8_FMLA_FDOT_Index_VG1x2_Pat
+ : Pat<(intrinsic (i32 (tile
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/118492
>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/5] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/118811
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@@ -740,6 +740,11 @@ let SMETargetGuard = "sme2" in {
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+// FDOT
jthackray wrote:
> We would also want feature and immediate range tests
Now added.
https://github.com/llvm/llvm-project/pull/118492
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>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/4] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/118492
>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/3] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
@@ -740,6 +740,11 @@ let SMETargetGuard = "sme2" in {
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+// FDOT
jthackray wrote:
> [Immediate argument
> tests](https://github.com/llvm/llvm-project/blob/e804d5f7cc459b9310122ed5405bba5c4d6a2350/clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_imm.c)
Thanks. Looks like this is in #118549 which hasn't been merged yet (/me starts
reviewing your change ;)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/118492
>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/3] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
@@ -0,0 +1,57 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: aarch64-registered-target
+#include
+
+// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme
-target-feature +sme2 -target
@@ -5737,3 +5768,113 @@ multiclass sme2_fmop4a_fp8_fp16_2way {
// Multiple vectors
def _M2Z2Z_BtoH : sme2_fp8_fp16_quarter_tile_outer_product<0b1, 0b1,
mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>;
}
+
+// FP8 SME FDOT instructions
+
+// Selection DAG patterns - map to first le
@@ -740,6 +740,11 @@ let SMETargetGuard = "sme2" in {
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+// FDOT
+let
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/118492
>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/3] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/118126
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LGTM
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LGTM
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>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH 1/2] [AArch64] Add intrinsics for SME FP8 FDOT LANE
instru
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/118492
None
>From 609cf3fbdb28c155f4b8c787c1e2cb791c8a292f Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 29 Nov 2024 11:27:03 +
Subject: [PATCH] [AArch64] Add intrinsics for SME FP8 FDOT LANE instr
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/116959
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https://github.com/jthackray commented:
You could also create an ARM/ directory, and move arm-* files into that too
(186 files)
https://github.com/llvm/llvm-project/pull/115818
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https://github.com/jthackray approved this pull request.
Fine by me; I guess anyone with a PR in-flight will need to rebase.
https://github.com/llvm/llvm-project/pull/115818
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https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/115296
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https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/114804
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https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/113580
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https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/112747
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https://github.com/jthackray closed
https://github.com/llvm/llvm-project/pull/113496
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https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/113496
>From f56eb26dbeb683777a7db97b43ebaea19a88e5b8 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Sat, 19 Oct 2024 00:20:20 +0100
Subject: [PATCH] [AArch64] Add support for Armv9.6-A FEAT_PoPS architecture
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/113496
Add support for the following Armv9.6-A architecture extensions:
* FEAT_PoPS - Point of Physical Storage
as documented here:
https://developer.arm.com/documentation/109697/2024_09/Feature-description
https://github.com/jthackray approved this pull request.
Looks like a good improvement.
https://github.com/llvm/llvm-project/pull/113281
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@@ -68,19 +68,13 @@ struct ExtensionInfo {
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
struct FMVInfo {
- StringRef Name; // The target_version/target_clones spelling.
- CPUFeatures Bit;// Index of the bit in the FMV feature bitset.
- StringRef Features;
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/112341
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@@ -1331,7 +1331,10 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SVE_F16F32MM, AArch64::AEK_SVE_AES2,
AArch64::AEK_SSVE_AES, AArch64::AEK_F8F32MM,
AArch64::AEK_F8F16MM, AArch64::AEK_LSFE,
- AArch64::AEK_FPRCVT, AArch64
@@ -533,11 +638,158 @@ bool
AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
return true;
}
+// Check if a type is a Pure Scalable Type as defined by AAPCS64. Return the
+// number of data vectors and the number of predicate vectors in the types,
into
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/112747
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@@ -533,11 +638,158 @@ bool
AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
return true;
}
+// Check if a type is a Pure Scalable Type as defined by AAPCS64. Return the
+// number of data vectors and the number of predicate vectors in the types,
into
@@ -423,6 +510,19 @@ ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType
RetTy,
// Homogeneous Floating-point Aggregates (HFAs) are returned directly.
return ABIArgInfo::getDirect();
+ // In AAPCS return values of a Pure Scalable type are treated is a first
named
https://github.com/jthackray approved this pull request.
https://github.com/llvm/llvm-project/pull/112687
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@@ -0,0 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+pcdphint %s | FileCheck
%s
jthackray wrote:
I think these tests should also check the instructions are rejecte
@@ -0,0 +1,14 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+occmo
-mattr=+mte < %s | FileCheck %s
jthackray wrote:
I think these tests should also check in
jthackray wrote:
> It might be worth splitting each feature into its own commit rather than one
> big commit, it makes the review easier. Currently it's difficult to determine
> which section belongs to which feature.
Hmm, yeah possible.
https://github.com/llvm/llvm-project/pull/112341
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https://github.com/jthackray approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/112341
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@@ -799,6 +802,24 @@ bool CFI_Parser::parseFDEInstructions(A &addressSpace,
}
break;
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+ case DW_CFA_AARCH64_negate_ra_state_with_pc: {
+int64_t value =
+results->savedRegisters[UNW_AARCH64_RA_SIGN_
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