================
@@ -3064,6 +3064,76 @@ let TargetPrefix = "aarch64" in {
def int_aarch64_sme_usmopa_wide : SME_OuterProduct_Intrinsic;
def int_aarch64_sme_usmops_wide : SME_OuterProduct_Intrinsic;
+ class SME_OuterProduct_QuaterTile_Single
+ : DefaultAttrsIntrinsic<[],
+ [llvm_i32_ty,
+ llvm_anyvector_ty,
+ LLVMMatchType<0>], [ImmArg<ArgIndex<0>>]>;
+
+ def int_aarch64_sme_mop4a_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_mop4s_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_mop4a_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_mop4s_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_smop4a_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_smop4s_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_smop4a_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_smop4s_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_umop4a_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_umop4s_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_umop4a_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_umop4s_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_sumop4a_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_sumop4s_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_sumop4a_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_sumop4s_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_usmop4a_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_usmop4s_wide_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_usmop4a_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_usmop4s_1x1 : SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_smop4a_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_smop4s_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_umop4a_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_umop4s_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_sumop4a_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_sumop4s_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_usmop4a_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+ def int_aarch64_sme_usmop4s_za64_wide_1x1 :
SME_OuterProduct_QuaterTile_Single;
+
+ class SME_OuterProduct_QuaterTile_Multi
----------------
jthackray wrote:
```suggestion
class SME_OuterProduct_QuaterTile_Single_Multi
```
Then we can create `SME_OuterProduct_QuaterTile_Multi_Single` and
`SME_OuterProduct_QuaterTile_Multi_Multi`
https://github.com/llvm/llvm-project/pull/128854
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