Paul
I endorse your point regarding Lattice's gouging. Support for anything prior
to the XO parts now costs a significant premium. Their XO2 parts are the most
useful to this community - free tools and 0.5 mm pitch, e.g. 100p & 144p - not
dense but usefully large, 3v3 IO and agricultural asse
> On 09/22/2023 6:26 PM CDT Mike Katz via cctalk wrote:
>
>
> I plan on controlling the gate array with an RP2040 dual core cortex M0
> running at 133 MHz and 8 PIO processors.
>
Hi Mike,
Since you are planning to use a micro anyway, and it doesn't appear you will
need a great deal of exte
> On Sep 22, 2023, at 3:59 PM, Martin Bishop via cctalk
> wrote:
>
> 100% disagree, Verilog and SV are bad tools - very easy to do a bad job with
> - penknife grade.
>
> Verilog however is very c like in that it is untyped and prone to all the
> consequent tar pits; see above.
>
> VHDL is
Martin,
Thank you for all of your suggestions.
I am a software guy who has dabbled in hardware since I built my first
Heathkit in 1972. I have designed simple 6809 single boards in my past
professional life but the Omnibus is several orders of magnitude more
complicated than a 6809.
Just r
Mike
An M0 will require an FPGA below it to interact with the OmniBus
A BeagleBone, using the PRUs - which are ~microcoded, would be in with more of
a chance
Industrial grade SoCs / FPGAs should have no difficulty
Martin
-Original Message-
From: Mike Katz via cctalk [mailto:cctalk@cla
I have no plans to emulate the CPU. This is intended to be a board to
help debug programs and possibly some hardware issues.
On 9/22/2023 6:06 PM, Martin Bishop via cctalk wrote:
Chuck,
Your point is wholly valid, although the core will run more at 1 GHz than 200
MHz.
The UniBone http://ret
I plan on controlling the gate array with an RP2040 dual core cortex M0
running at 133 MHz and 8 PIO processors.
However, the Data Break (DMA) timings on the Omnibus are in the 100nS
range. The bus runs 6 different timing signals plus manipulating all of
the other signals to implement Data Br
Chuck,
Your point is wholly valid, although the core will run more at 1 GHz than 200
MHz.
The UniBone http://retrocmp.com/projects/unibone is a UniBus board capable of
monitoring the unibus and of emulating CPU / rotating rust / memory / ... With
the bulk of the logic in c on an Arm Processor
On 9/22/2023 4:45 PM, ben via cctalk wrote:
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8).
Stupid question, I know, but someone has to ask it.
Is there some overwhelming reason that the FPGA and associated logic
couldn't be subsumed into an inexpensive 32-bit MCU running at, oh, 200
MHz? I can't believe that a PDP8 is all that fast...
--Chuck
My plan is to have both a serial port for connection to a PC/Terminal
and an I2C output to a multi line display.
Thanks for the suggestion.
On 9/22/2023 4:45 PM, ben via cctalk wrote:
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
Martin,
The debug board will need to have the following
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8). Single Cycle
DMA requires some interestin
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8). Single Cycle
DMA requires some interesting signaling, including putting the
priority on the da
On 2023-09-22 12:34 p.m., emanuel stiebler via cctalk wrote:
On 2023-09-22 12:04, Mike Katz via cctalk wrote:
I'm working on the design for an Omnibus (PDP-8/E) debug board and I
am not very good at circuit design. I know there are programs that
will compile something that looks like C into Ve
Mike
The level you are working at, inspecting busses, is not really where C like
tools are targeted - however ...
I shall infer that an 8/E debug board has the functionality of a bus monitor /
logic analyser front end.
The recent discussion <> covered
a lot of similar ground : worth reviewing
100% disagree, Verilog and SV are bad tools - very easy to do a bad job with -
penknife grade.
Verilog however is very c like in that it is untyped and prone to all the
consequent tar pits; see above.
VHDL is a good tool which is typed and like the Algol family of languages
precludes many foll
Oh, and Verilog all the way. I just can't with VHDL.
😆
--
Anders Nelson
www.andersknelson.com
On Fri, Sep 22, 2023 at 3:24 PM Anders Nelson
wrote:
> Maybe these can help?:
>
>
> https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware,
> pair with
> https://www.olimex.com/
Maybe these can help?:
https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware,
pair with
https://www.olimex.com/Products/FPGA/iCE40/iCE40-DIO/open-source-hardware
https://www.crowdsupply.com/1bitsquared/icebreaker-fpga
I've personally used the iCE40 and iCE5LP in my larger
On 9/22/23 11:34, emanuel stiebler via cctalk wrote:
> There are still some 84pin chips out there(Altera & Xilinx). Sometimes
> they are pulls, or some 5V tolerant xilinx xc95l
I still have a few 84 pin PLCC XC95108 5V CPLDs Originally, I did a
tape controller design with one before Xilinx d
On 2023-09-22 12:04, Mike Katz via cctalk wrote:
I'm working on the design for an Omnibus (PDP-8/E) debug board and I am
not very good at circuit design. I know there are programs that will
compile something that looks like C into Verilog/VHDL/Abel/Etc for use
on some kind of large (more than
> On Sep 22, 2023, at 12:04 PM, Mike Katz via cctalk
> wrote:
>
> I'm working on the design for an Omnibus (PDP-8/E) debug board and I am not
> very good at circuit design. I know there are programs that will compile
> something that looks like C into Verilog/VHDL/Abel/Etc for use on some
FPGA's tend to be ALL 3.3 volts or less today. Cmos 22v10's are nice
chips to program that is still working at 5 volts. FPGA's also have
high learning curve to catch the bugs and gotya's.
I got tl866 ii + programer and it works great under windows, with wincupl.
You will likely learn a lot by watching this series:
https://www.youtube.com/watch?v=xmCrbUk1evc (we're up to Episode 17, be
warned!).
Or, to dream about hiring a pro: https://www.youtube.com/watch?v=BNdZowgySnE
http://ghservices.com/gregh/fairligh/
- Kurt
-Original Message-
From: Eth
I'm working on the design for an Omnibus (PDP-8/E) debug board and I am
not very good at circuit design. I know there are programs that will
compile something that looks like C into Verilog/VHDL/Abel/Etc for use
on some kind of large (more than 64 pins) programmable logic device.
Can any of y
That's why I said broken!
A boy can dream!
- Ethan
They are a fairly high demand item when they come up for sale, and are very
expensive.
Sellam
On 9/22/23 01:57, Peter Coghlan via cctalk wrote:
>
> It looks like a disk FST tweaked for writing to tape to me. Using the FST
> layout in LY24-5221-2 referenced by Dennis earlier, I think maybe it might
> be interpreted something like below. Apologies if I've mixed anything up
> here.
Thank y
They are a fairly high demand item when they come up for sale, and are very
expensive.
Sellam
On Fri, Sep 22, 2023, 9:02 AM Ethan O'Toole via cctalk <
cctalk@classiccmp.org> wrote:
> Anyone have any leads in USA on a Fairlight CMI or similar that needs
> repair? S-100 based sampler from the 80s.
Anyone have any leads in USA on a Fairlight CMI or similar that needs
repair? S-100 based sampler from the 80s. Would be fun to restore one.
- Ethan
>
> Thanks for the information so far, folks.
>
> Now this boils down to interpreting the final CMS record for each file.
> I'm not clear on how to interpret them, however. For example,
>
>> Block 10, 87 bytes:
>> 00 02 c3 d4 e2 d5 01 76 00 01 c1 f1 01 75 00 00 c6 |.CMSNA1F|
>> 00
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