On Mon, Jun 20, 2016 at 10:07 PM, ben wrote:
> Do you use Static or Dynamic ram with the FPGA's?
I've done both.
You indicated that you wanted 5V I/O. AFAIK, there haven't been any
new FPGAs made in many years that have even 5V-tolerant I/O, let alone
actual 5V I/O. Some really old FPGAs may st
On 6/20/2016 9:43 PM, Eric Smith wrote:
On Mon, Jun 20, 2016 at 9:34 PM, ben wrote:
My other pet-peave is that every thing is point and click wizard for any
useful modules. Need a rom module or adder module, point and click no
portable code.
I predominantly use Xilinx, and I don't use much po
Are you going for the 6600 CPU with PPU or just the CPU itself?
The 6400 CPU, on the other hand was one of the initial proof of concept
targets when Neil Lincoln at (then) ADL and later ETA was playing with
his "box of Chiclets" IC concept. To the best of my knowledge, a 6600
was not attempted.
On Mon, Jun 20, 2016 at 9:34 PM, ben wrote:
> My other pet-peave is that every thing is point and click wizard for any
> useful modules. Need a rom module or adder module, point and click no
> portable code.
I predominantly use Xilinx, and I don't use much point-and-click at
all. I do all my HDL
On 6/20/2016 9:00 PM, Toby Thain wrote:
Altera Cyclone has 9 bit byte lanes, so getting 36 bit memory is no
problem.
Internal memory only.
My other pet-peave is that every thing is point and click wizard for any
useful modules. Need a rom module or adder module, point and click no
portable c
On Mon, Jun 20, 2016 at 2:56 PM, Swift Griggs wrote:
> On Mon, 20 Jun 2016, Paul Koning wrote:
>> a and b will both equal 1 at the end. But in the VHDL code:
>> a <= 1;
>> b <= a;
>
> Whoa. That makes total sense, though. In the real world, I'm guessing the
> "less than" just reflects
All, I messed around with VHDL last year. I found this a great book
to learn VHDL best practices:
http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf
The book is free but you can also buy a printed copy at
http://freerangefactory.org/
I started with GHDL: https://www.fpgarelated
On 2016-06-20 5:12 PM, ben wrote:
On 6/20/2016 2:41 PM, Toby Thain wrote:
This is frankly amazing. Thankyou for the details. Maybe one day I'll be
able to volunteer some help. (Actually if there's anything I can do now,
as an electronics noob but beginning student of digital logic & FPGA,
let
* On Mon, Jun 20, 2016 at 04:19:56PM -0400, Paul Koning
wrote:
>
> I haven't looked for open source Verilog simulators.
I've used Icarus Verilog ('iverilog') in the past. It's pretty bare
bones, but you can feed the output into gnuplot and make reasonable
diagrams from it.
> paul
-Seth
> On Jun 20, 2016, at 5:12 PM, ben wrote:
>
> On 6/20/2016 2:41 PM, Toby Thain wrote:
>
>>
>> This is frankly amazing. Thankyou for the details. Maybe one day I'll be
>> able to volunteer some help. (Actually if there's anything I can do now,
>> as an electronics noob but beginning student of
I have a printer - just finished putting a Rostock V2 together a week or so
ago - and an 87xm (and 86b, fwiw) and some modules, but no PRM-85. If fit
against a standard module board is sufficient, I can do an iteration or
two. I haven't quite finished calibration, but it is printing sufficiently
On 06/20/2016 03:19 PM, Paul Koning wrote:
On Jun 20, 2016, at 4:17 PM, Paul Koning wrote:
On Jun 20, 2016, at 3:35 PM, Swift Griggs wrote:
In my recent studies of electronics (I'm a noob for all practical
purposes) I keep seeing folks refer to Verilog almost as a verb. I read
about it in W
On 15 June 2016 at 20:39, Swift Griggs wrote:
> Hmm. I think you'd fly right through it, Liam. You are a smart guy, I
> doubt you'd have any significant problems these days. Still, it's a
> console-based install.
FWIW, I've tried again this evening. Not on bare metal -- on the
latest VirtualBox.
On Mon, 20 Jun 2016, Cameron Kaiser wrote:
> In short: no.
Thanks, Cameron. At least now I know.
> In long: NetBoot requires a G4 or a late G3, and that would imply pretty
> much only 8.6 and up.
Hmm, that's what I'd seen so far and was lead to believe.
> You *can* netboot a *IIgs* from an Ap
I'm interested as well.
Dave
On Monday, June 20, 2016 2:16 PM, "alexmcwhir...@triadic.us"
wrote:
On 2016-06-20 11:34, Pete Plank wrote:
>> On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:
>>
>> I read in this list that there are more people interested in such a
>> case.
>
> Due to the news about the MacOS name change, it's becoming quite hard to
> Google for older MacOS stuff. Was it ever possible to netboot MacOS 8.1 or
> earlier? I have A/UX 3 running nicely on a Quadra 700, now, but now I want
> to dual boot it with MacOS, but I don't have a CDROM. Taking out
On Mon, 20 Jun 2016, Eric Christopherson wrote:
> For learning, I really recommend this Coursera MOOC:
> https://www.coursera.org/learn/build-a-computer/home/welcome
Hmm, I had to sign up with them, but I did it. I wanted to see this
simulator. It's a very "slick" course with lots of way-cool to
On 6/20/2016 2:41 PM, Toby Thain wrote:
This is frankly amazing. Thankyou for the details. Maybe one day I'll be
able to volunteer some help. (Actually if there's anything I can do now,
as an electronics noob but beginning student of digital logic & FPGA,
let me know offlist.)
How about a REA
On 6/20/2016 2:36 PM, Swift Griggs wrote:
So far, it's been great. I'm just finishing up some of the analog stuff on
that same site, and I've greedily skipped ahead a bit to digital. However,
I'm just now getting to TTLs and gates. I have to actually write out
examples or test things physically
> On Jun 20, 2016, at 1:56 PM, Swift Griggs wrote:
>
> On Mon, 20 Jun 2016, Paul Koning wrote:
>> used to how C or similar languages work. For example, in this C code:
>> a = 1;
>> b = a;
>> a and b will both equal 1 at the end. But in the VHDL code:
>> a <= 1;
>> b <= a;
>
On Mon, Jun 20, 2016, Ian Finder wrote:
> The hardest part of the process is distilling the functional specification
> of the part you are trying to replace. This is the heart of the topic. Some
> ways this can be done:
> > If adequate documentation exists, use it.
> > Observe the part's behavior i
On 6/20/2016 2:24 PM, Ian Finder wrote:
I find most of the open source HDL simulators kind of suck. I think you can
still get ModelSim Web edition for free from altera.
I think you get 1 month free ... then $$$.
I like the CRASH and BURN testing for FPGA's.
What I want is 5 volt I/O FPGA wi
On Mon, 20 Jun 2016, Paul Koning wrote:
> used to how C or similar languages work. For example, in this C code:
> a = 1;
> b = a;
> a and b will both equal 1 at the end. But in the VHDL code:
> a <= 1;
> b <= a;
Whoa. That makes total sense, though. In the real world, I'm
Most of the FPGA companies provide (free) tools that allow you to write in
verilog/VHDL and then simulate and observe the outputs (you can even “drill
down” and see internal signals as well.
It’s fairly easy to write a little bit of code (there are lots of examples on
the
web) and try it out on t
On Mon, 20 Jun 2016, Ian Finder wrote:
> Some PALs, PLAs, and GALs will yield the fuse map if you try and read them
> with a programmer. This makes your job really easy. Take the fuse map and
> compare to the original data sheet. Cool beans.
That sounds like magic. I'm reading about what "fuse map
Paul wrote:
>>> I'm thinking I'll stop trying OCR and simply type the wire lists
instead; that's likely to be faster in the long run.
If you need someone to help, I'd be happy to transcribe some shit while
watching TV if you send me the docs and desired schema. I'm no stranger to
this sort of proc
On 2016-06-20 4:35 PM, Paul Koning wrote:
On Jun 20, 2016, at 4:22 PM, Toby Thain wrote:
On 2016-06-20 4:17 PM, Paul Koning wrote:
...A hardware model can
be used to replicate what old hardware did; for example, I have a
partial CDC 6600 model that shows how it boots, and that model include
On Mon, 20 Jun 2016, Ian Finder wrote:
> The hardest part of the process is distilling the functional
> specification of the part you are trying to replace. This is the heart
> of the topic.
Hmm, okay so that's pretty much what I expected. They start with what that
particular chip or ROM etc..
> On Jun 20, 2016, at 4:22 PM, Toby Thain wrote:
>
> On 2016-06-20 4:17 PM, Paul Koning wrote:
>> ...A hardware model can
> be used to replicate what old hardware did; for example, I have a
> partial CDC 6600 model that shows how it boots, and that model includes
> propagation delays on some sig
I find most of the open source HDL simulators kind of suck. I think you can
still get ModelSim Web edition for free from altera.
This will do mixed language designs of Verilog, VHDL and schematic, and
works rather nicely.
Remember, each module is just a set of input and output signals, so the
lan
On 2016-06-20 4:17 PM, Paul Koning wrote:
...A hardware model can
be used to replicate what old hardware did; for example, I have a
partial CDC 6600 model that shows how it boots, and that model includes
propagation delays on some signals (which are critical to correct
operation in certain spots
> On Jun 20, 2016, at 4:17 PM, Paul Koning wrote:
>
>
>> On Jun 20, 2016, at 3:35 PM, Swift Griggs wrote:
>>
>> In my recent studies of electronics (I'm a noob for all practical
>> purposes) I keep seeing folks refer to Verilog almost as a verb. I read
>> about it in Wikipedia and it sounds
To expand on my response-
Some PALs, PLAs, and GALs will yield the fuse map if you try and read them
with a programmer. This makes your job really easy. Take the fuse map and
compare to the original data sheet. Cool beans.
Some have the security bits set- in this case you would use a home-made
tes
> On Jun 20, 2016, at 3:35 PM, Swift Griggs wrote:
>
> In my recent studies of electronics (I'm a noob for all practical
> purposes) I keep seeing folks refer to Verilog almost as a verb. I read
> about it in Wikipedia and it sounds pretty interesting. It's basically
> described as a coding s
The hardest part of the process is distilling the functional specification
of the part you are trying to replace. This is the heart of the topic. Some
ways this can be done:
> If adequate documentation exists, use it.
> Observe the part's behavior in-system
> Build a test bench to observe behavior
What you can do (and I’ve seen it done) is define verilog modules that
provide the functions of the IC and use that in their designs. I’ve seen
at least two interesting classic computer recreations using this approach
(re-implemenation of the CADR lisp machine in verilog and an IBM 360/30
in veril
On 2016-06-20 3:35 PM, Swift Griggs wrote:
In my recent studies of electronics (I'm a noob for all practical
purposes) I keep seeing folks refer to Verilog almost as a verb. I read
about it in Wikipedia and it sounds pretty interesting. It's basically
described as a coding scheme for electronics
In my recent studies of electronics (I'm a noob for all practical
purposes) I keep seeing folks refer to Verilog almost as a verb. I read
about it in Wikipedia and it sounds pretty interesting. It's basically
described as a coding scheme for electronics, similar to programming but
with extras
On Mon, 20 Jun 2016, Jay West wrote:
> This has drifted too far off topic.
Not to mention that it could go on for freakin' years. It's a "wedge
issue" as they'd say in politics. I'm done. FYI. It's my last systemd
related post to the list (or probably any list) for me. The PoS has
already t
On 2016-06-20 11:34, Pete Plank wrote:
On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:
I read in this list that there are more people interested in such a
case.
I don’t have a 3D printer either, but I’m on board for one when
they’re ready to go - my PRM-85 is still in its anti-stat
This has drifted too far off topic.
J
> -Oorspronkelijk bericht-
> Van: cctalk [mailto:cctalk-boun...@classiccmp.org] Namens Jay West
> Verzonden: maandag 20 juni 2016 19:41
> Aan: 'General Discussion: On-Topic and Off-Topic Posts'
> Onderwerp: RE: HP Series-80 computers - PRM-85 board case? ... maybe!
>
> I'll chime in as a
Due to the news about the MacOS name change, it's becoming quite hard to
Google for older MacOS stuff. Was it ever possible to netboot MacOS 8.1 or
earlier? I have A/UX 3 running nicely on a Quadra 700, now, but now I want
to dual boot it with MacOS, but I don't have a CDROM. Taking out the dri
On Sat, 18 Jun 2016, Stefan Skoglund (lokal anv?ndare) wrote:
> What i don't like about systemd is: the fud about how easy it is to
> write systemd unit files vs old shell script init.d/ditos .
In most simple cases, their argument is that it's easier to write a unit
file because you don't need t
Ian wrote...
Changing thread title and invoking filter.
Thanks, duly noted.
J
Changing thread title and invoking filter.
Thanks,
- Ian
On Mon, Jun 20, 2016 at 10:50 AM, Swift Griggs
wrote:
> > And yet, now that significant chunks of the Linux underpinnings are
> > being combined into one purpose-written close-knit chunk, designed by a
> > single team, the same sort of p
> And yet, now that significant chunks of the Linux underpinnings are
> being combined into one purpose-written close-knit chunk, designed by a
> single team, the same sort of people that praise *BSD for its conceptual
> unity are harshly damning the thing bringing comparable unity to Linux.
>
I'll chime in as a 3rd person wanting a case for my PRM-85, and I know for sure
two other listmembers (who are not the two who mentioned it just now) who will
definitely want one.
So probably 5 takers.
Anyone with a 3d printer want to make one for us?
J
> From: Paul Birkel
>> I will upload the content to the CHW (and add the DB9 pinouts, too).
> Yes, please.
OK, done; see:
http://gunkies.org/wiki/DEC_asynchronous_serial_line_pinout
and it references the new:
http://gunkies.org/wiki/EIA_RS-232_serial_line_interface
I'd be gra
http://www.righto.com/2016/06/y-combinators-xerox-alto-restoring.html
https://news.ycombinator.com/item?id=11929396
http://ed-thelen.org/RestoreAlto/index.html
On 6/20/16 8:51 AM, Al Kossow wrote:
> I post just went up on Saturday. It's nice that both CHM and LCM folks
> are helping with this.
>
I post just went up on Saturday. It's nice that both CHM and LCM folks
are helping with this.
On 6/20/16 8:41 AM, Liam Proven wrote:
> http://www.righto.com/2016/06/y-combinators-xerox-alto-restoring.html
>
> Found via:
>
> http://www.osnews.com/story/29261/Xerox_Alto_restoring_the_legendary_19
http://www.righto.com/2016/06/y-combinators-xerox-alto-restoring.html
Found via:
http://www.osnews.com/story/29261/Xerox_Alto_restoring_the_legendary_1970s_GUI_computer
There are 2 videos up so far, with disassemblies that may interest CCmpers.
Some people from the list are involved, including
> On Jun 20, 2016, at 6:20 AM, martin.heppe...@dlr.de wrote:
>
> I read in this list that there are more people interested in such a case.
I don’t have a 3D printer either, but I’m on board for one when they’re ready
to go - my PRM-85 is still in its anti-static bag.
Pete
Marlin, why not try to find a hackerspace in your area, they usually
have 3D printers and willing to help.
---
- Original Message -
From:
To:
Sent: Monday, June 20, 2016 10:20 AM
Subject: HP Series-80 computers - PRM-85 board case? ... maybe!
Hi,
I own PRM-85 boards for m
Hi,
I own PRM-85 boards for my HP-85 and 86 machines. While they are very useful
extension modules for these computers, they lack a proper case. I hate to
destroy a working interface or memory module just for the case.
I read in this list that there are more people interested in such a case.
So
Can read it online:
https://catalog.hathitrust.org/Record/000476266
On Thu, Jun 16, 2016 at 9:28 PM, Brian Walenz wrote:
> Is there an electronic copy of this floating around? My (ex-library) copy
> is missing all of chapter 11, "What is there to calculate?. (And the last
> page of the previo
On Mon, Jun 20, 2016 at 07:12:35AM -0400, Noel Chiappa wrote:
[...]
> Although how a monitor is supposed to tell whether a signal is interlaced, or
> non-interlaced, is not clear - there's certainly no pin on the VGA connector
> which says so! :-)
It's encoded in the sync signal. The timings are t
> I'm puzzled as to how one could drive both interlaced and
> non-interlaced monitors off the same video signal - wouldn't the
> interlaced one need a video signal which has 'odd lines, then a
> vertical retrace, then even lines, then a vertical retrace'?
So to sort of answer my ow
I have a friend looking for 2 DEC VRC21-KA monitors in Europe.
I have one here, but will pack it only as a last resort.
If you have one of two you want to sell or trade, please let me know off
list. Also where you are located.
Thanks, Paul
Am 17.06.16 um 17:36 schrieb Noel Chiappa:
> The first couple of LCD's I plugged in,
[...]
> Finally I found one that _did_ give me the numbers,
> and it said the retrace was 35.6 Khz / 44 Hz.
[...]
> So I finally found an old CRT monitor that worked - but now I have another
> problem! It reports
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