Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-11-02 Thread adr
Hello, I'm going nuts trying to find out why h5 is unstable... but that's another story. The case is that studying the code it seems to me that it would be more consistent to add H3_CLK_PLL_CPUX to sun8i_h3_gates[] and use sxiccmu_ccu_enable (or even SXICLR4(sc, sun8i_h3_gates[idx].reg, (1U << sun

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-26 Thread adr
> > reg |= H3_CPUX_CLK_SRC_SEL_OSC24M; > > SXIWRITE4(sc, H3_CPUX_AXI_CFG_REG, reg); > > + /* Must wait at least 8 cycles of the current clock. */ > > + delay(1); > > > > error = sxiccmu_h3_set_frequency(sc, H3_CLK_PLL_CPUX, freq); > > > >

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-26 Thread Mark Kettenis
> Date: Wed, 26 Aug 2020 21:54:30 + > From: a...@sdf.org > > > > reg |= H3_CPUX_CLK_SRC_SEL_OSC24M; > > > SXIWRITE4(sc, H3_CPUX_AXI_CFG_REG, reg); > > > + /* Must wait at least 8 cycles of the current clock. */ > > > + delay(1); > > > > > > error

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-25 Thread Mark Kettenis
> Date: Tue, 25 Aug 2020 18:36:03 +0900 > From: SASANO Takayoshi > > Hi, > > I thought to avoid false-LOCKed situation but I didn't consider > about false-unLOCKed. So same as adr says, it is the best solution > to wait simply with delay(PLL_STABLE_TIME_REG1 usec). No need to refer > LOCK flag.

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-25 Thread SASANO Takayoshi
Hi, I thought to avoid false-LOCKed situation but I didn't consider about false-unLOCKed. So same as adr says, it is the best solution to wait simply with delay(PLL_STABLE_TIME_REG1 usec). No need to refer LOCK flag. Here is renewed diff. I also tested on Banana Pi BPI-P2 (Allwinner H2+). This di

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-18 Thread adr
Hi, > I thought LOCK flag is set regardless PLL is locked or not, simply > time passed... but your comment tells the flag reflects PLL status > but unstable. And you are right!, that's what happens with these documents... The PLL_CPUX_CTRL_REG description says that the lock bit "indicates that t

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-08-17 Thread SASANO Takayoshi
Hello, sorry for late reply. > It seems that the PLL is not been stabilized although LOCK is read as > set. You can check it by putting a delay in sxiccmu_h3_set_frequency > after H3_PLL_CPUX_LOCK is tested, delay(200) is sufficient, the machine > will boot ok. My OrangePi PC took 257usec to LOCK

Re: Allwinner H3/H5: PLL1 (CPU_PLL) setting

2020-07-10 Thread adr
> Hi, > > Previously I found OpenBSD-6.6, 6.7 and -current did not work on > my Orange Pi PC (Allwinner H3). > > For these days I was looking for what caused this problem, and > finally I found the M field of H3_PLL_CPUX_CTRL_REG (@0x01c2) > made thing worse. > > This, M value should be 2. I

Re: Allwinner H3: other UART ports (not console UART0) support

2020-03-23 Thread Mark Kettenis
> Date: Mon, 23 Mar 2020 22:51:05 +0900 > From: SASANO Takayoshi > > On Allwinner H3, currently we can use UART0 for debug/console port. > To use UART1-3 port, we have to make proper device tree blob > and fix kernel code like this. > > - com_fdt.c needs to add reset signal de-assert code > - sc

Re: Allwinner 10

2013-09-09 Thread Janne Johansson
Sending a box or three to the arm devs could actually work. 2013/9/9 Patrick Wildt > Hi, > > a port to the Cubieboard(s) is in progress, which includes Allwinner A10 > and A20. > > Not sure though if and how many changes will be needed for your box. > > \Patrick > > Am 07.09.2013 um 14:38 schri

Re: Allwinner 10

2013-09-08 Thread Patrick Wildt
Hi, a port to the Cubieboard(s) is in progress, which includes Allwinner A10 and A20. Not sure though if and how many changes will be needed for your box. \Patrick Am 07.09.2013 um 14:38 schrieb Felipe Mesquita de Oliveira : > Hi, > > I'm new in this list, and would like to know if is there

Re: Allwinner 10

2013-09-08 Thread Warner Losh
On Sep 7, 2013, at 6:38 AM, Felipe Mesquita de Oliveira wrote: > Hi, > > I'm new in this list, and would like to know if is there any work in > progress porting to allwinner A10 chipset. > > I've made some search, and found a FreeBSD port (looks not that active): > https://github.com/tsgan/allwi

Re: Allwinner

2013-07-16 Thread Artturi Alm
tralalaaa im so happy! during weekend i almost gave up, did already order pandaboard and beaglebone black to just get the project forward i bought the cubie for.. oh well i can find a use for them too. now is time to allow ehci1 to attach again and see if i can make this crash with usb-wifi. so

Re: Allwinner

2013-07-12 Thread Artturi Alm
On 07/12/13 00:33, Marek Vasut wrote: Dear Artturi Alm, [...] Checking the linux code, they really seem to use their own thing, not gic. That sucks. Best regards, Marek Vasut Sucks or not, it's not the problem, interrupts now work as supposed to, as far as i can tell. After sending out t

Re: Allwinner

2013-07-11 Thread Marek Vasut
Dear Artturi Alm, > On 07/11/13 03:25, Marek Vasut wrote: > > Dear Artturi Alm, > > > >> [...] > > > > Does it not use standard ARM GIC ? > > > > [...] > > > > Best regards, > > Marek Vasut > > Hi, > > While I know about the credibility issues with wikipedia, there > Cortex-A8 is only one wi

Re: Allwinner

2013-07-11 Thread Artturi Alm
On 07/11/13 03:25, Marek Vasut wrote: Dear Artturi Alm, [...] Does it not use standard ARM GIC ? [...] Best regards, Marek Vasut Hi, While I know about the credibility issues with wikipedia, there Cortex-A8 is only one without it listed in features from ARMv7-A cores. On top of that, fw

Re: Allwinner

2013-07-10 Thread Marek Vasut
Dear Artturi Alm, > On 07/02/13 19:28, minux wrote: > > On Mon, Jul 1, 2013 at 7:20 PM, Artturi Alm wrote: > >> So, i found out that the docs i have don't include > >> sd/mmc controller register definitions etc., only the overview. > >> which lead me to fix ehci and now it might boot, but > >> i

Re: Allwinner

2013-07-05 Thread Artturi Alm
On 07/02/13 19:28, minux wrote: On Mon, Jul 1, 2013 at 7:20 PM, Artturi Alm wrote: So, i found out that the docs i have don't include sd/mmc controller register definitions etc., only the overview. which lead me to fix ehci and now it might boot, but i cant figure out how to cross-build releas

Re: Allwinner

2013-07-02 Thread minux
On Mon, Jul 1, 2013 at 7:20 PM, Artturi Alm wrote: > So, i found out that the docs i have don't include > sd/mmc controller register definitions etc., only the overview. > which lead me to fix ehci and now it might boot, but > i cant figure out how to cross-build release, if it's even > the cross

Re: Allwinner

2013-07-01 Thread Artturi Alm
So, i found out that the docs i have don't include sd/mmc controller register definitions etc., only the overview. which lead me to fix ehci and now it might boot, but i cant figure out how to cross-build release, if it's even supported, and if not, what else can i do? in short: i dont know how to

Re: Allwinner

2013-06-30 Thread Artturi Alm
2013/6/26 Artturi Alm : > Yeah, now intc is attaching, and possibly even working :) > i think i'll find out soon after timer attaches so initclocks wouldnt panic. they weren't... interesting stuff anyway, while very frustrating w/my (missing) knowledge, after banging my head into walls for a few d

Re: Allwinner

2013-06-26 Thread Artturi Alm
2013/6/25 Tobias Ulmer : > On Tue, Jun 25, 2013 at 04:45:43AM +0300, Artturi Alm wrote: >> Hi, >> >> So i found the answers myself, should of have started porting >> instead of writing the mail back in friday already, given how easy >> it was to find the answers, sorry for being lazy.. >> >> anyway

Re: Allwinner

2013-06-24 Thread Tobias Ulmer
On Tue, Jun 25, 2013 at 04:45:43AM +0300, Artturi Alm wrote: > Hi, > > So i found the answers myself, should of have started porting > instead of writing the mail back in friday already, given how easy > it was to find the answers, sorry for being lazy.. > > anyway, i already got dmesg w/com0 att