Hi, > I thought LOCK flag is set regardless PLL is locked or not, simply > time passed... but your comment tells the flag reflects PLL status > but unstable.
And you are right!, that's what happens with these documents... The PLL_CPUX_CTRL_REG description says that the lock bit "indicates that the PLL has been stable", but then in the PLL_STABLE_TIME_REG1 description you learn that there is only a wait. This is what I think, PLL_CPUX_CTRL_REG lock bit is there so you can poll this bit instead of just waiting, for example to do other things in the polling loop. But in sxiccmu.c there is no reason to do the polling, nothing is done inside the loop, so you can just let the delay alone. And if some h3 board has problems, you can always write a bigger value to PLL_STABLE_TIME_REG1, it is R/W. Regards, adr.
