This DC patchset brings improvements in multiple areas. In summary, we have:
* Fix ARGB16161616 pixel format;
* Fix pixel clock in 10/12-bpc;
* Add reserved dc_log_type;
* Fix some variables widths in dc;
* Add chip version GC_11_0_3_A0 to DCN32 family;
* Fix light up bug with dcn314 with 8K@30;
From: Ethan Wellenreiter
[WHY]
Limiting vscsdp_for_colorimetry for YCbCr420/BT2020 resulted in red/green
point failures in HDR10 DTN tests. The re-implementation of ARGB16161616
was to fix this however it did not actually fix this issue but a side effect of
the
issue.
[HOW]
Change ARGB16161616
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(
From: Ilya Bakoulin
[Why]
Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned
between different HDMI lanes when using YCbCr420 10-bit pixel format.
BIOS functions for transmitter/encoder control take pixel clock in kHz
increments, whereas the function for setting the pixel clock
From: Aric Cyr
This version brings along following fixes:
-Fix edp panel missing event
-Set ARGB16161616 pixel format to 26
-Fix dcn32 interger issue
-Clear optc underflow bit after ODM clock off
-Fix issue with stereo3D
-Fix DML2 lightup issue
-Correct DTBCLK for dcn314
-Revert for a regression
From: Ian Chen
Reviewed-by: Anthony Koo
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/include/logger_types.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h
b/drivers/gpu/drm/amd/display
From: Daniel Miess
[Why]
Need a way to retain default clock table to aid
the investigation into why 8k@30 display not
lighting up on dcn314
[How]
Use flag to prevent execution of bw_params helper
function and function for updating bw_bounding_box
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: J
From: Tom Chung
[Why]
Pipes for MPO primary and overlay will be power down and power up during
plug/unplug external monitor while MPO video playback.
But the pipes were the same after plug/unplug and should not need to be
power down and power up or it will make page flip interrupt disabled and
ca
From: Samson Tam
[Why & How]
Add GC_11_0_3_A0 as a chip revision to the DCN32 family
Reviewed-by: Rodrigo Siqueira
Acked-by: Brian Chang
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/driv
From: Alvin Lee
[Description]
For SubVP scaling cases, we must include the scaling
info as part of the cmd. This is required when converting
OTG line to HUBP line for the MALL_START_LINE programming.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/display/
From: Alvin Lee
[Description]
Use pitch when calculating size to cache in MALL
Reviewed-by: Samson Tam
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
From: Charlene Liu
[why]
this is to ensure that driver will not reprogram hvm_prefetch_req again if
it is done.
Reviewed-by: Martin Leung
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 8 +++-
1 file changed, 7 insertions(+), 1
From: Nicholas Kazlauskas
[Why & How]
Depending on how the clock table is constructed from PMFW we can run
into issues where we don't think we have enough bandwidth available
due to FCLK too low - eg. when the FCLK table contains invalid entries
or a single entry.
We should always pick up the ma
From: Alvin Lee
[Description]
Don't set DSC bit for phantom pipes, not
required since phantom pipe don't have
any actual output
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 +
1 file changed, 1 insertion(+)
This DC patchset brings improvements in multiple areas. In summary, we have:
* Remove redundant check in atomic_check.
* Add log clock table for SMU.
* Add SubVP scaling.
* Add interface to track PHY state.
* Free phantom plane after removing from the context.
* Add k1/k2 driver for virtual signal
From: Aric Cyr
This verion brings along following fixes:
-Add scaling factor for SubVP
-Modify stop_dbg_mode return value
-Add gfx_off members and document
-Add GFXOFF function for vangogh
-Add GFXOFF stats to debug
-Fix codestyle problems
-Fix overflow on MIN_I64
-Fix Unneeded semicolon
-Fix com
From: Derek Lai
[Why]
RV2 do not change pipe split policy in the
minimal pipe split transition state.
This will unblock mode support on some
parts that limit to DPM0 for power reason.
[How]
Do not change pipe split policy in the
minimal pipe split transition state to
allow 4k multi display confi
From: Samson Tam
[Why]
odm 2:1 policy is splitting the pipes in 4k144.
then in subvp code, we merge the pipes. but since the
configuration is unsupported, we keep the pipes split
[How]
for unsupported subvp configuration, redo the dml and
pipe split calls
Reviewed-by: Alvin Lee
Reviewed-by:
From: Robin Chen
[Why]
The DAL driver may transmit the wrong cursor position to PSRSU
DMUB driver when there are multiple planes.
[How]
Currently the driver apply the HW cursor on the top plane. So we
should only transmit the cursor position on the top plane to
PSRSU DMUB driver.
Reviewed-by: A
From: Aurabindo Pillai
[Why&How]
When using IGT, kms_bw multi display tests trigger an assert since
we ignore virtual signal type. k1/k2 dividers should be correctly
programmed if VSYNC needs to be correct. Add the appropriate condition
to the if arm to fix this.
Reviewed-by: Rodrigo Siqueira
A
From: Aurabindo Pillai
DC was using compile time initialization of register addresses using
SR_* macros and their variants. These have been converted to use runtime
initialization.
The REG_STRUCT macro is a definition that is added to SR_* macros.
During initialization, this must be defined befo
From: Ilya Bakoulin
[Why]
Retrying on receiving a NACK can result in long overall EDID read times
in some cases.
[How]
Retry only on DEFER and return immediately on NACK.
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.
From: Aurabindo Pillai
DC was using compile time initialization of register addresses using
SR_* macros and their variants. These have been converted to use runtime
initialization.
The REG_STRUCT macro is a definition that is added to SR_* macros.
During initialization, this must be defined befo
From: Taimur Hassan
[Why]
Sometimes pixel clock needs to remain active after transmitter disable.
[How]
Use update_phy_state to track PHY state after stream
enable/disable and program pixel clock as needed.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
driver
From: Roman Li
[Why]
We have 2 back-to-back checks for skipping connectors.
Logically one of them will do the job.
[How]
Remove redundant check.
Reviewed-by: Hersen Wu >
Acked-by: Brian Chang
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
1 file change
From: Alvin Lee
[Description]
Uncomment scaling cmd assignment since
FW headers are now promoted.
Reviewed-by: Martin Leung
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a
From: Leo Chen
[Why & How]
Adding log for clock table from SMU helps with the debugging process.
Implemented using DC_LOG_SMU to output log.
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 46 ++
.../
From: Chaitanya Dhere
[Why]
Recent backport from opensource broke the Nightly tool build
that tests DC and DML for bugs and regressions. This was
because the backport had a header inclusion that was not
consistent with the AMD style of including headers was allowed
to be merged back in DML code t
From: Saaem Rizvi
[WHY]
Reprogramming the stream despite no changes in ODM combine mode.
Reprogramming the stream would cause intermittent black screen on
display which could only be recovered through enable/disable sequence.
[HOW]
Fixed bug where we detected a change in ODM combine mode despite
From: Alvin Lee
[Description]
Refcount is incremented on allocation and
when adding to the context. Therefore we must
release the phantom plane and stream after
removing from the context.
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn3
This DC patchset brings improvements in multiple areas. In summary, we have:
* Correct cursor position on horizontal mirror;
* Fix black flash when switching from ODM2to1 to ODMBypass;
* Fix plane and stream check;
* Fix viewport after pipe merge;
* Correct plane for CAB cursor;
* Fix comment to c
From: Taimur Hassan
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../
From: George Shen
[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.
Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-t
From: Lewis Huang
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito
Acked-by: B
From: Duncan Ma
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acke
From: Alvin Lee
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/d
From: Charlene Liu
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h| 9 ++---
.../amd/display/
From: Wang Fudong
[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.
[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display
From: Alvin Lee
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-
From: "Chen, Leo"
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
di
From: Michael Strauss
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen
Acked-by: Brian Chang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5
This DC patchset brings improvements in multiple areas. In summary, we have:
* Correct cursor position on horizontal mirror;
* Fix black flash when switching from ODM2to1 to ODMBypass;
* Fix plane and stream check;
* Fix viewport after pipe merge;
* Correct plane for CAB cursor;
* Fix comment to c
From: Alvin Lee
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/d
From: Taimur Hassan
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../
From: George Shen
[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.
Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-t
From: Lewis Huang
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito
Acked-by: B
From: Duncan Ma
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acke
From: Charlene Liu
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h| 9 ++---
.../amd/display/
From: Wang Fudong
[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.
[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display
From: Alvin Lee
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-
From: Gabe Teeger
[Why]
On edp with psr1, we do not provide updates
of the cursor position regularly to firmware
like with PSR2. To send updates regularly,
the flag enable_sw_cntl_psr has to equal 1,
but cursor update should be provided
regularly to FW regardless of that flag.
[How]
Ensure that
From: "Chen, Leo"
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
di
From: Michael Strauss
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen
Acked-by: Brian Chang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON, such as
when using MST or during resolution change. This is expected, so allow HW
programming to continue.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/g
From: Gabe Teeger
[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.
[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the
From: "Leo (Hanghong) Ma"
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this displ
From: "Leo (Hanghong) Ma"
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Leo (Hanghong) Ma
From: Alvin Lee
[Description]
For SubVP scaling case we have to combine
the plane scaling and stream scaling.
Use UCLK dummy p-state WM for FCLK WM set C
[Description]
For DCN32/321 program dummy UCLK P-state watermark into FCLK
watermark set C register.
Reviewed-by: Jun Lei
Reviewed-by: Neve
From: Ian Chen
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |
From: Leo Chen
[Why & How]
Number of encoder is set to 4 but only 3 instances are created.
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/a
From: Aurabindo Pillai
For calculating cursor size allocation, surface size was used, resulting
in over allocation
Reviewed-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
1 f
From: Aurabindo Pillai
[Why&How]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.
Prevent entering SS if we are on the edge case and cursor caching is not
From: Charlene Liu
[why]
fw version check was for release branch.
for staging, it has a chance to enter wrong code path.
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 3 +++
.../gpu/drm/amd/di
From: Aurabindo Pillai
[Why&How]
When calculating allocation for cursor size, get the real cursor through
the HUBP instead of using the maximum cursor size for more optimal
allocation
Reviewed-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
From: Iswara Nagulendran
[HOW&WHY]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.
* SWDEV-342936 - dc: DSC bringup for SAG 1.5
[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.
[HOW]
From: Aurabindo Pillai
[Why & How]
This reverts commit 9dd9c085ae3b since it
causes a SubVP related regression: "Switching between windowed video and
fullscreen can intermittently cause black screen"
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/
From: Ian Chen
Reviewed-by: Dennis Chan
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 43d250918fd0..3f64b
From: Anthony Koo
- Fix comment to indicate correct visual confirm option
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/displ
From: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9cde9465f5ce..75dbc66
From: Aurabindo Pillai
[Why&How]
plane and stream variables used for cursor size allocation calculation
were stale from previous iteration. Redo the iteration to find the
correct cursor plane for the calculation.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
From: Ethan Wellenreiter
[Why]
Pipes get merged in preparation for SubVP but if they don't get used, and
are in ODM or some other multi pipe config, it would calculate the
voltage level with a viewport of just one pipe from when they were split
resulting in too low of a voltage level.
[How]
Made
From: Vladimir Stempen
[Why]
On secondary display hotplug we switch primary
stream from ODM2to1 to ODMBypass mode. Current
logic will trigger disabling front end for this
stream.
[How]
We need to check if prev_odm_pipe is equal to NULL
in order to disable dangling planes in this scenario.
Revie
From: Ethan Wellenreiter
[WHY]
Function wasn't returning false when it had a no stream
[HOW]
Made it return false when it had no stream.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Ethan Wellenreiter
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
1
From: Martin Tsai
[Why]
Incorrect cursor position will induce system hang on pipe split.
[How]
1.Handle horizontal mirror on rotation,
2.Correct cursor set on piep split.
Reviewed-by: Ariel Bernstein
Acked-by: Brian Chang
Signed-off-by: Martin Tsai
---
.../gpu/drm/amd/display/dc/dcn10/dcn10
From: Camille Cho
[Why & How]
Add configuration 2 for ABM 2.3/2.4 to suit customer preferences, which
is to lower the brightness curves in 80%-100% range compared to the
existing default config 0.
Reviewed-by: Josip Pavic
Acked-by: Brian Chang
Signed-off-by: Camille Cho
---
.../gpu/drm/amd/d
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
*Add configuration 2 for ABM 2.3/2.4.
*Add margin for HUBP for SubVp + DRR.
*Fix no display after resume from WB/CB.
*Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
*Lower watermarks fo
From: "Lee, Alvin"
[Description]
- Add margin for HUBP "jitter" for SubVp + DRR case
- Also do a min transition even if MPO is added on a
non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR)
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/disp
From: Tsung-hua Lin
[why]
First MST sideband message returns AUX_RET_ERROR_HPD_DISCON
on certain intel platform. Aux transaction considered failure
if HPD unexpected pulled low. The actual aux transaction success
in such case, hence do not return error.
[how]
Not returning error when AUX_RET_ERR
From: Alvin Lee
[Description]
- For SubVP, we cannot support HW cursor if it's
greater than 64 x 64 x 4 bytes in size
- However, on certain config changes (i.e. pixel format)
we can exit SubVP (then change to HW cursor) then re-enter
SubVP without changing back to SW cursor because there is
From: Nicholas Kazlauskas
[Why]
Even if we block Z9 based on crossover threshold it's possible to
allow for Z8.
[How]
There's support for this on DCN314, so update the support types to
include a z8 only and z8_z10 only state.
Update the decide_zstate_support function to allow for specifying
the
From: Nicholas Kazlauskas
[Why & How]
Update from HW, need to lower watermarks for enter/enter+exit latency.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 d
From: Dillon Varone
[WHY?]
Prefetch is not budgetting time for dummy pstate when using subvp and low uclk.
[HOW?]
Override fclk change latency to use dummy pstate latency when calculating
prefetch schedule for subvp configs with low uclk.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-
From: Dillon Varone
[Description]
New values for soc bounding box and dummy pstate.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 6 +++---
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 8 --
From: Dillon Varone
[WHY?]
Some configurations are constructed with very marginal DET buffers relative to
the worst possible time required to fetch a swath.
[HOW?]
Add a check to see that the DET buffer allocated for each pipe can hide the
latency for all pipes to fetch at least one swath.
Revi
From: Rodrigo Siqueira
When some of the IGT tests are executed in DCN31, it is possible to see
multiple occurrences of this warning:
WARNING: CPU: 9 PID: 3482 at
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dcn30/dcn30_dpp.c:154
dpp3_program_post_csc+0x196/0x220 [amdgpu]
[..]
PU: 9 PID: 3482 Co
From: Mustapha Ghaddar
[WHY]
To implement BW Allocation as per USB4 spec chapter 10.7
[HOW]
Implement the DP-Tx portion of the logic to interact with DPIA
Reviewed-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Mustapha Ghaddar
---
drivers/gpu/drm/amd/display/dc/
From: Alvin Lee
[Description]
- When attempting to enter MALL SS when a PSR panel
is connected, we have to check that the PSR panel
has already entered PSR because the vsync interrupt
call is per display index (can be called for the
non-PSR panel first)
- Also don't override link settings
From: Alvin Lee
[Description]
- If we fail validation, we should retain the phantom
stream/planes
- Full updates assume that phantom pipes will be fully
removed, but if validation fails we keep the phantom
pipes
- Therefore we have to retain the plane/stream if validation
fails (since the
From: Dillon Varone
[WHY?]
MALL allocation size depends on the viewport height, not the addressable
vertical lines, which will not match when scaling.
[HOW?]
Base MALL allocation size calculations off viewport height.
Reviewed-by: Alvin Lee
Reviewed-by: Martin Leung
Acked-by: Brian Chang
Sig
From: Ilya Bakoulin
[Why]
Brief corruption is observed on hotplug/unplug with certain display
configurations when VSR is enabled.
[How]
Work around the issue by avoiding 2to1 ODM when stream plane_count is 0.
Reviewed-by: Dillon Varone
Acked-by: Brian Chang
Signed-off-by: Ilya Bakoulin
---
From: Tsung-hua Lin
[why]
First MST sideband message returns AUX_RET_ERROR_HPD_DISCON
on certain intel platform. Aux transaction considered failure
if HPD unexpected pulled low. The actual aux transaction success
in such case, hence do not return error.
[how]
Not returning error when AUX_RET_ERR
From: Alvin Lee
[Description]
- Add debug option for increasing number of phantom lines
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/dcn32/dc
From: Taimur Hassan
[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.
[How]
Set valid divider values for virtual and FRL/DP2 cases.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/dr
From: David Galiffi
[Why]
Underflow is observed when cursor is still enabled when the cursor
rectangle is outside the bounds of it's surface viewport.
[How]
Update parameters used to determine when cursor should be disabled.
Reviewed-by: Martin Leung
Acked-by: Brian Chang
Signed-off-by: David
From: Dillon Varone
[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.
[HOW?]
Use num_memclk_level from num_entries_per_clk
From: Alvin Lee
[Description]
Revert change since enabling SubVP on 8K60 single cable
results in corruption
Reviewed-by: Nevenko Stupar
Reviewed-by: Martin Leung
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +-
1 file
From: Aric Cyr
Signed-off-by: Aric Cyr
This version brings along following fixes:
-Add configuration 2 for ABM 2.3/2.4.
-Add margin for HUBP for SubVp + DRR.
-Fix no display after resume from WB/CB.
-Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
-Lower watermarks
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