From: "Leo (Hanghong) Ma" <hanghong...@amd.com>
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo <anthony....@amd.com>
Reviewed-by: Aric Cyr <aric....@amd.com>
Acked-by: Brian Chang <brian.ch...@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 31 +++++++++++++
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 44 +++++++++++++++++++
7 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index eef38d2e4753..a53863bddee0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1184,6 +1184,7 @@ struct dc_plane_state {
/* private to dc_surface.c */
enum dc_irq_source irq_source;
struct kref refcount;
+ struct tg_color visual_confirm_color;
};
struct dc_plane_info {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index cd7225d98b3d..61dfe5358d1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -387,6 +387,37 @@ void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
}
}
+void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx
*pipe_ctx)
+{
+ union dmub_rb_cmd cmd = { 0 };
+ enum dmub_status status;
+ unsigned int panel_inst = 0;
+
+ dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
+
+ memset(&cmd, 0, sizeof(cmd));
+
+ // Prepare fw command
+ cmd.visual_confirm_color.header.type =
DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
+ cmd.visual_confirm_color.header.sub_type = 0;
+ cmd.visual_confirm_color.header.ret_status = 1;
+ cmd.visual_confirm_color.header.payload_bytes = sizeof(struct
dmub_cmd_visual_confirm_color_data);
+
cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst
= panel_inst;
+
+ // Send command to fw
+ status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd);
+
+ ASSERT(status == DMUB_STATUS_OK);
+
+ // If command was processed, copy feature caps to dmub srv
+ if (status == DMUB_STATUS_OK &&
+ cmd.visual_confirm_color.header.ret_status == 0) {
+ memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
+ &cmd.visual_confirm_color.visual_confirm_color_data,
+ sizeof(struct dmub_visual_confirm_color));
+ }
+}
+
#ifdef CONFIG_DRM_AMD_DC_DCN
/**
*
***********************************************************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 159782cd6659..9f5b47b9a83d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -78,6 +78,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc,
uint32_t tg_inst);
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct
dc_state *context);
void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
+void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx
*pipe_ctx);
void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union
dmub_inbox0_data_register data);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2118ad3e37d0..d3f6a2609c8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2539,8 +2539,10 @@ void dcn10_update_visual_confirm_color(struct dc *dc,
struct pipe_ctx *pipe_ctx,
color_space_to_black_color(
dc, pipe_ctx->stream->output_color_space,
color);
- if (mpc->funcs->set_bg_color)
+ if (mpc->funcs->set_bg_color) {
+ memcpy(&pipe_ctx->plane_state->visual_confirm_color, color,
sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+ }
}
void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4b4368456477..6271caca4d9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2468,8 +2468,10 @@ void dcn20_update_visual_confirm_color(struct dc *dc,
struct pipe_ctx *pipe_ctx,
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
get_subvp_visual_confirm_color(dc, pipe_ctx, color);
- if (mpc->funcs->set_bg_color)
+ if (mpc->funcs->set_bg_color) {
+ memcpy(&pipe_ctx->plane_state->visual_confirm_color, color,
sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+ }
}
void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 840460ad0bf8..fdaa6f4fdde1 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -442,6 +442,7 @@ struct dmub_srv {
/* Feature capabilities reported by fw */
struct dmub_feature_caps feature_caps;
+ struct dmub_visual_confirm_color visual_confirm_color;
};
/**
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 829410a883a1..1184bef22673 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -246,6 +246,16 @@ struct dmub_feature_caps {
uint8_t reserved[6];
};
+struct dmub_visual_confirm_color {
+ /**
+ * Maximum 10 bits color value
+ */
+ uint16_t color_r_cr;
+ uint16_t color_g_y;
+ uint16_t color_b_cb;
+ uint16_t panel_inst;
+};
+
#if defined(__cplusplus)
}
#endif
@@ -644,6 +654,10 @@ enum dmub_cmd_type {
* Command type used to query FW feature caps.
*/
DMUB_CMD__QUERY_FEATURE_CAPS = 6,
+ /**
+ * Command type used to get visual confirm color.
+ */
+ DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
/**
* Command type used for all PSR commands.
*/
@@ -2778,6 +2792,31 @@ struct dmub_rb_cmd_query_feature_caps {
struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
};
+/**
+ * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR
command.
+ */
+struct dmub_cmd_visual_confirm_color_data {
+ /**
+ * DMUB feature capabilities.
+ * After DMUB init, driver will query FW capabilities prior to enabling
certain features.
+ */
+struct dmub_visual_confirm_color visual_confirm_color;
+};
+
+/**
+ * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+struct dmub_rb_cmd_get_visual_confirm_color {
+ /**
+ * Command header.
+ */
+ struct dmub_cmd_header header;
+ /**
+ * Data passed from driver to FW in a
DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+ struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
+};
+
struct dmub_optc_state {
uint32_t v_total_max;
uint32_t v_total_min;
@@ -3150,6 +3189,11 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
*/
struct dmub_rb_cmd_query_feature_caps query_feature_caps;
+
+ /**
+ * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+ struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
struct dmub_rb_cmd_drr_update drr_update;
struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
--
2.25.1
