[PATCH] drm/amd/display: reset the workload type when using MALL

Reset the workload type when using MALL. When there is no activity on the screen, dal requestes dmcub to use MALL. However, gfx ring is not empty at the same time. Currrently the workload type is set to 3D fullscreen when gfx ring has jobs. No activity on the screen and the gfx ring empty state can

Re: [PATCH] drm/amd: Keep display off while going into S4

On Thu, Mar 6, 2025 at 1:51 PM Mario Limonciello wrote: > > When userspace invokes S4 the flow is: > > 1) amdgpu_pmops_prepare() > 2) amdgpu_pmops_freeze() > 3) Create hibernation image > 4) amdgpu_pmops_thaw() > 5) Write out image to disk > 6) Turn off system > > Then on resume amdgpu_pmops_resto

Re: [PATCH RFC v3 4/7] drm/display: dp-aux-dev: use new DCPD access helpers

I thought we had agreed that drm_dp_aux_dev.c was one of the few places where we wanted to keep using the old functions here? On Fri, 2025-03-07 at 06:34 +0200, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > Switch drm_dp_aux_dev.c to use new set of DPCD read / write helpers. > > Acked-by

Re: [PATCH v4] drm/amdgpu: Fix the race condition for draining retry fault

On 3/6/2025 7:27 PM, Deng, Emily wrote: [AMD Official Use Only - AMD Internal Distribution Only] *From:*Chen, Xiaogang *Sent:* Friday, March 7, 2025 1:01 AM *To:* Deng, Emily ; amd-gfx@lists.freedesktop.org *Subject:* Re: [PATCH v4] drm/amdgpu: Fix the race condition for draining retry faul

[PATCH 1/2] drm/amd/pm: Add debug bit for smu pool allocation

In certain cases, it's desirable to avoid PMFW log transactions to system memory. Add a mask bit to decide whether to allocate smu pool in device memory or system memory. Signed-off-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 + drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h

RE: [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size

[AMD Official Use Only - AMD Internal Distribution Only] The series is: Reviewed-by: Ruijing Dong -Original Message- From: amd-gfx On Behalf Of David Rosca Sent: Friday, February 28, 2025 10:10 AM To: Alex Deucher Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/4] drm/amdgpu:

Re: [PATCH] drm/amd: Keep display off while going into S4

On 2025-03-06 13:51, Mario Limonciello wrote: > When userspace invokes S4 the flow is: > > 1) amdgpu_pmops_prepare() > 2) amdgpu_pmops_freeze() > 3) Create hibernation image > 4) amdgpu_pmops_thaw() > 5) Write out image to disk > 6) Turn off system > > Then on resume amdgpu_pmops_restore() is

Re: [PATCH] drm/amdgpu/vcn: fix idle work handler for VCN 2.5

Ping? This fixes a regression on VCN 2.5. Thanks, Alex On Thu, Mar 6, 2025 at 10:05 AM Alex Deucher wrote: > > Ping? > > Thanks, > > Alex > > On Wed, Mar 5, 2025 at 2:42 PM Alex Deucher wrote: > > > > VCN 2.5 uses the PG callback to enable VCN DPM which is > > a global state. As such, we nee

[PATCH 10/11] drm/amdgpu/sdma6: add support for disable_kq

When the parameter is set, disable user submissions to kernel queues. Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdm

[PATCH] drm/amdgpu: deprecate guilty handling

The guilty handling tried to establish a second way of signaling problems with the GPU back to userspace. This caused quite a bunch of issue we had to work around, especially lifetime issues with the drm_sched_entity. Just drop the handling altogether and use the dma_fence based approach instead.

[PATCH] drm/amd/display: allow 256B DCC max compressed block sizes on gfx12

The hw supports it. Signed-off-by: Marek Olšák --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) From 02f89c11dca69c6555f8bad75c84b50126c53554 Mon Sep 17 00:00:00 2

Re: [PATCH] drm/amd/display: allow 256B DCC max compressed block sizes on gfx12

Acked-by: Alex Deucher On Fri, Mar 7, 2025 at 10:01 AM Marek Olšák wrote: > > The hw supports it. > > Signed-off-by: Marek Olšák > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- > 2 files changed, 3 inser

[PATCH 06/11] drm/amdgpu/mes: make more vmids available when disable_kq=1

If we don't have kernel queues, the vmids can be used by the MES for user queues. Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- 3 files cha

[PATCH V3 00/11] Add disable kernel queue support

To better evaluate user queues, add a module parameter to disable kernel queues. With this set kernel queues are disabled and only user queues are available. This frees up hardware resources for use in user queues which would otherwise be used by kernel queues and provides a way to validate user

[PATCH 09/11] drm/amdgpu/sdma: add flag for tracking disable_kq

For SDMA, we still need kernel queues for paging so they need to be initialized, but we no not want to accept submissions from userspace when disable_kq is set. Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 + 1 file changed, 1 insertion(

[PATCH 01/11] drm/amdgpu: add parameter to disable kernel queues

On chips that support user queues, setting this option will disable kernel queues to be used to validate user queues without kernel queues. Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 ++

[PATCH 05/11] drm/amdgpu/mes: update hqd masks when disable_kq is set

Make all resources available to user queues. Suggested-by: Sunil Khatri Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers

[PATCH 08/11] drm/amdgpu/gfx12: add support for disable_kq

Plumb in support for disabling kernel queues. v2: use ring counts per Felix' suggestion Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 96 -- 1 file changed, 58 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

[PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq

Plumb in support for disabling kernel queues in GFX11. We have to bring up a GFX queue briefly in order to initialize the clear state. After that we can disable it. v2: use ring counts per Felix' suggestion Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 99 ++

[PATCH 02/11] drm/amdgpu: add ring flag for no user submissions

This would be set by IPs which only accept submissions from the kernel, not userspace, such as when kernel queues are disabled. Don't expose the rings to userspace and reject any submissions in the CS IOCTL. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 driv

Re: [PATCH] drm/amd/display: reset the workload type when using MALL

On 2025-03-07 09:48, Alex Deucher wrote: > On Thu, Mar 6, 2025 at 10:45 PM Kenneth Feng wrote: >> >> Reset the workload type when using MALL. >> When there is no activity on the screen, dal requestes dmcub >> to use MALL. However, gfx ring is not empty at the same time. >> Currrently the worklo

Re: [PATCH RFC v3 0/7] drm/display: dp: add new DPCD access functions

On Fri, Mar 07, 2025 at 06:34:42AM +0200, Dmitry Baryshkov wrote: > Existing DPCD access functions return an error code or the number of > bytes being read / write in case of partial access. However a lot of > drivers either (incorrectly) ignore partial access or mishandle error > codes. In other c

[PATCH 11/11] drm/amdgpu/sdma7: add support for disable_kq

When the parameter is set, disable user submissions to kernel queues. Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdm

Re: [PATCH v3] drm/amd: Fail initialization earlier when DC is disabled

On Thu, Mar 6, 2025 at 3:51 PM Mario Limonciello wrote: > > Modern APU and dGPU require DC support to be able to light up the > display. If DC support has been disabled either by kernel config > or by kernel command line the screen will visibly freeze when the > driver finishes early init. > > As

Re: [PATCH] drm/amd: Keep display off while going into S4

Hi, Thank you Mario for finding and fixing! On 3/6/25 11:51 PM, Mario Limonciello wrote: > When userspace invokes S4 the flow is: > > 1) amdgpu_pmops_prepare() > 2) amdgpu_pmops_freeze() > 3) Create hibernation image > 4) amdgpu_pmops_thaw() > 5) Write out image to disk > 6) Turn off system > >

Re: [PATCH] drm/amd/display: reset the workload type when using MALL

On Thu, Mar 6, 2025 at 10:45 PM Kenneth Feng wrote: > > Reset the workload type when using MALL. > When there is no activity on the screen, dal requestes dmcub > to use MALL. However, gfx ring is not empty at the same time. > Currrently the workload type is set to 3D fullscreen when gfx > ring has

[PATCH 6/8] drm/amdgpu: stop reserving VMIDs to enforce isolation

That was quite troublesome for gang submit. Completely drop this approach and enforce the isolation separately. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 9 + drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 11

[PATCH 2/8] drm/amdgpu: use GFP_NOWAIT for memory allocations

In the critical submission path memory allocations can't wait for reclaim since that can potentially wait for submissions to finish. Finally clean that up and mark most memory allocations in the critical path with GFP_NOWAIT. The only exception left is the dma_fence_array() used when no VMID is av

[PATCH 8/8] drm/amdgpu: add cleaner shader trace point

Note when the cleaner shader is executed. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 15 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/

[PATCH 1/8] drm/amdgpu: grab an additional reference on the gang fence v2

We keep the gang submission fence around in adev, make sure that it stays alive. v2: fix memory leak on retry Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/am

[PATCH 3/8] drm/amdgpu: overwrite signaled fence in amdgpu_sync

This allows using amdgpu_sync even without peeking into the fences for a long time. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gp

[PATCH 4/8] drm/amdgpu: rework how isolation is enforced v2

Limiting the number of available VMIDs to enforce isolation causes some issues with gang submit and applying certain HW workarounds which require multiple VMIDs to work correctly. So instead start to track all submissions to the relevant engines in a per partition data structure and use the dma_fe

[PATCH 7/8] drm/amdgpu: add isolation trace point

Note when we switch from one isolation owner to another. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 17 + 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_devi

[PATCH 5/8] drm/amdgpu: rework how the cleaner shader is emitted v3

Instead of emitting the cleaner shader for every job which has the enforce_isolation flag set only emit it for the first submission from every client. v2: add missing NULL check v3: fix another NULL pointer deref Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 27 +++

RE: [PATCH] drm/amdgpu: format old RAS eeprom data into V3 version

[AMD Official Use Only - AMD Internal Distribution Only] > -Original Message- > From: Yang, Stanley > Sent: Friday, March 7, 2025 3:36 PM > To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org > Cc: Zhou1, Tao > Subject: RE: [PATCH] drm/amdgpu: format old RAS eeprom data into V3 version > > [A

Re: [PATCH] drm/amdgpu: Allow buffers that don't fit GTT into VRAM

Am 06.03.25 um 18:01 schrieb Natalie Vock: > When userspace requests buffers to be placed into GTT | VRAM, it is > requesting the buffer to be placed into either of these domains. If the > buffer fits into VRAM but does not fit into GTT, then let the buffer > reside in VRAM instead of failing alloc

[PATCH] drm/amdgpu: Allow buffers that don't fit GTT into VRAM

When userspace requests buffers to be placed into GTT | VRAM, it is requesting the buffer to be placed into either of these domains. If the buffer fits into VRAM but does not fit into GTT, then let the buffer reside in VRAM instead of failing allocation entirely. Reported-by: Ivan Avdeev <1...@pro

[PATCH v2] drm/amd/amdkfd: Evict all queues even HWS remove queue failed

[Why] If reset is detected and kfd need to evict working queues, HWS moving queue will be failed. Then remaining queues are not evicted and in active state. After reset done, kfd uses HWS to termination remaining activated queues but HWS is resetted. So remove queue will be failed again. [How]

RE: [PATCH] drm/amdgpu: format old RAS eeprom data into V3 version

[AMD Official Use Only - AMD Internal Distribution Only] > -Original Message- > From: Zhou1, Tao > Sent: Friday, March 7, 2025 4:41 PM > To: Yang, Stanley ; amd-gfx@lists.freedesktop.org > Subject: RE: [PATCH] drm/amdgpu: format old RAS eeprom data into V3 version > > [AMD Official Use On

Re: [PATCH] drm/amd/amdkfd: Evict all queues even HWS remove queue failed

[AMD Official Use Only - AMD Internal Distribution Only] Hi Felix, Thanks. Patch v2 is submitted. It should make sure error returned even if remove_queue_mes is success. Could you pleas help to review it again? Thanks. Best regard, Yifan Zha From: Kuehl

[PATCH RFC v3 1/7] drm/display: dp: implement new access helpers

From: Dmitry Baryshkov Existing DPCD access functions return an error code or the number of bytes being read / write in case of partial access. However a lot of drivers either (incorrectly) ignore partial access or mishandle error codes. In other cases this results in a boilerplate code which com

[PATCH RFC v3 6/7] drm/display: dp-mst-topology: use new DCPD access helpers

From: Dmitry Baryshkov Switch drm_dp_mst_topology.c to use new set of DPCD read / write helpers. Reviewed-by: Lyude Paul Acked-by: Jani Nikula Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 105 +- 1 file changed, 51 insertions(+),

RE: [PATCH] drm/amdgpu: format old RAS eeprom data into V3 version

[AMD Official Use Only - AMD Internal Distribution Only] > -Original Message- > From: amd-gfx On Behalf Of Tao Zhou > Sent: Friday, March 7, 2025 2:47 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhou1, Tao > Subject: [PATCH] drm/amdgpu: format old RAS eeprom data into V3 version > > Cle

[PATCH] drm/amdgpu: add UAPI for workload profile to ctx interface

Allow a rendering context to set a workload profile. This allows an application to select a workload profile to match its intended use case. Each rendering context can set a profile and internally the SMU firmware will select the highest priority profile among those that are active. When the con

[PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq

Plumb in support for disabling kernel queues in GFX11. We have to bring up a GFX queue briefly in order to initialize the clear state. After that we can disable it. v2: use ring counts per Felix' suggestion Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 99 ++

Re: [PATCH RFC v3 1/7] drm/display: dp: implement new access helpers

A few tiny nitpicks below, but with those addressed: Reviewed-by: Lyude Paul On Fri, 2025-03-07 at 06:34 +0200, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > Existing DPCD access functions return an error code or the number of > bytes being read / write in case of partial access. Howeve

Re: [PATCH RFC v3 2/7] drm/display: dp: change drm_dp_dpcd_read_link_status() return value

Reviewed-by: Lyude Paul On Fri, 2025-03-07 at 06:34 +0200, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > drm_dp_dpcd_read_link_status() follows the "return error code or number > of bytes read" protocol, with the code returning less bytes than > requested in case of some errors. However

[PATCH 04/11] drm/amdgpu/mes: centralize gfx_hqd mask management

Move it to amdgpu_mes to align with the compute and sdma hqd masks. No functional change. v2: rebase on new changes Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 22 ++ drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 +++- drivers/gpu/drm

Re: [PATCH] drm/amdgpu/vcn: fix idle work handler for VCN 2.5

[AMD Official Use Only - AMD Internal Distribution Only] V4 is Reviewed-by: Boyuan Zhang From: amd-gfx on behalf of Alex Deucher Sent: March 7, 2025 10:22 AM To: Deucher, Alexander Cc: amd-gfx@lists.freedesktop.org Subject: Re:

Re: [PATCH v2] drm/amd/amdkfd: Evict all queues even HWS remove queue failed

On 2025-03-07 03:53, Yifan Zha wrote: [Why] If reset is detected and kfd need to evict working queues, HWS moving queue will be failed. Then remaining queues are not evicted and in active state. After reset done, kfd uses HWS to termination remaining activated queues but HWS is resetted. So

[pull] amdgpu, amdkfd, radeon, UAPI drm-next-6.15

Hi Dave, Simona, More updates for 6.15. The following changes since commit 7d83c129a8d7df23334d4a35bca9090a26b0a118: drm/amdgpu: Fix parameter annotation in vcn_v5_0_0_is_idle (2025-02-27 16:50:05 -0500) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.gi

Re: [PATCH RFC v3 4/7] drm/display: dp-aux-dev: use new DCPD access helpers

On Fri, Mar 07, 2025 at 05:53:38PM -0500, Lyude Paul wrote: > I thought we had agreed that drm_dp_aux_dev.c was one of the few places where > we wanted to keep using the old functions here? Hmm, I thought I dropped it. > > On Fri, 2025-03-07 at 06:34 +0200, Dmitry Baryshkov wrote: > > From: Dmit

[PATCH 04/11] drm/amdgpu/mes: centralize gfx_hqd mask management

Move it to amdgpu_mes to align with the compute and sdma hqd masks. No functional change. v2: rebase on new changes Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 22 ++ drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 +++- drivers/gpu/drm