Plumb in support for disabling kernel queues.

v2: use ring counts per Felix' suggestion

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 96 ++++++++++++++++----------
 1 file changed, 58 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 34cf187e72d9f..23ee4651cbffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1421,11 +1421,13 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
                break;
        }
 
-       /* recalculate compute rings to use based on hardware configuration */
-       num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
-                            adev->gfx.mec.num_queue_per_pipe) / 2;
-       adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
-                                         num_compute_rings);
+       if (adev->gfx.num_compute_rings) {
+               /* recalculate compute rings to use based on hardware 
configuration */
+               num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
+                                    adev->gfx.mec.num_queue_per_pipe) / 2;
+               adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
+                                                 num_compute_rings);
+       }
 
        /* EOP Event */
        r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
@@ -1471,37 +1473,41 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
                return r;
        }
 
-       /* set up the gfx ring */
-       for (i = 0; i < adev->gfx.me.num_me; i++) {
-               for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
-                       for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
-                               if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, 
j))
-                                       continue;
-
-                               r = gfx_v12_0_gfx_ring_init(adev, ring_id,
-                                                           i, k, j);
-                               if (r)
-                                       return r;
-                               ring_id++;
+       if (adev->gfx.num_gfx_rings) {
+               /* set up the gfx ring */
+               for (i = 0; i < adev->gfx.me.num_me; i++) {
+                       for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
+                               for (k = 0; k < adev->gfx.me.num_pipe_per_me; 
k++) {
+                                       if 
(!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
+                                               continue;
+
+                                       r = gfx_v12_0_gfx_ring_init(adev, 
ring_id,
+                                                                   i, k, j);
+                                       if (r)
+                                               return r;
+                                       ring_id++;
+                               }
                        }
                }
        }
 
-       ring_id = 0;
-       /* set up the compute queues - allocate horizontally across pipes */
-       for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
-               for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
-                       for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
-                               if (!amdgpu_gfx_is_mec_queue_enabled(adev,
-                                                               0, i, k, j))
-                                       continue;
+       if (adev->gfx.num_compute_rings) {
+               ring_id = 0;
+               /* set up the compute queues - allocate horizontally across 
pipes */
+               for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
+                       for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
+                               for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 
k++) {
+                                       if 
(!amdgpu_gfx_is_mec_queue_enabled(adev,
+                                                                            0, 
i, k, j))
+                                               continue;
 
-                               r = gfx_v12_0_compute_ring_init(adev, ring_id,
-                                                               i, k, j);
-                               if (r)
-                                       return r;
+                                       r = gfx_v12_0_compute_ring_init(adev, 
ring_id,
+                                                                       i, k, 
j);
+                                       if (r)
+                                               return r;
 
-                               ring_id++;
+                                       ring_id++;
+                               }
                        }
                }
        }
@@ -3495,12 +3501,18 @@ static int gfx_v12_0_cp_resume(struct amdgpu_device 
*adev)
        if (r)
                return r;
 
-       if (!amdgpu_async_gfx_ring) {
-               r = gfx_v12_0_cp_gfx_resume(adev);
-               if (r)
-                       return r;
+       if (adev->gfx.num_gfx_rings) {
+               if (!amdgpu_async_gfx_ring) {
+                       r = gfx_v12_0_cp_gfx_resume(adev);
+                       if (r)
+                               return r;
+               } else {
+                       r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
+                       if (r)
+                               return r;
+               }
        } else {
-               r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
+               r = gfx_v12_0_cp_gfx_start(adev);
                if (r)
                        return r;
        }
@@ -3809,11 +3821,19 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block 
*ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
 
+       if (amdgpu_disable_kq == 1)
+               adev->gfx.disable_kq = true;
+
        adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
 
-       adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
-       adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
-                                         AMDGPU_MAX_COMPUTE_RINGS);
+       if (adev->gfx.disable_kq) {
+               adev->gfx.num_gfx_rings = 0;
+               adev->gfx.num_compute_rings = 0;
+       } else {
+               adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
+               adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+                                                 AMDGPU_MAX_COMPUTE_RINGS);
+       }
 
        gfx_v12_0_set_kiq_pm4_funcs(adev);
        gfx_v12_0_set_ring_funcs(adev);
-- 
2.48.1

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