Check return value and conduct null pointer handling to avoid null pointer
dereference.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
i
Hi,
On Wed, Jun 19, 2024 at 09:53:12AM GMT, Alex Deucher wrote:
> On Wed, Jun 19, 2024 at 9:50 AM Alex Deucher wrote:
> >
> > On Tue, Jun 18, 2024 at 7:53 PM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Tue, Jun 18, 2024 at 3:00 PM Alex Deucher
> > > wrote:
> > > >
> > > > On Tue, Jun 1
Fix the unchecked return value warning by warning reported by
Coverity, so add error handling.
Signed-off-by: Bob Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/a
[AMD Official Use Only - AMD Internal Distribution Only]
Ping for this.
Thanks,
Jane
-Original Message-
From: Jane Jian
Sent: Thursday, June 20, 2024 12:32 AM
To: Lazar, Lijo
Cc: amd-gfx@lists.freedesktop.org; Jian, Jane
Subject: [PATCH] drm/amdgpu: part I - normalize registers as loca
Am 20.06.24 um 02:30 schrieb Yunxiang Li:
Before, every time fdinfo is queried we try to lock all the BOs in the
VM and calculate memory usage from scratch. This works okay if the
fdinfo is rarely read and the VMs don't have a ton of BOs. If either of
these conditions is not true, we get a massiv
On 6/19/2024 10:01 PM, Jane Jian wrote:
> [WHY]
> sriov has the higher bit violation when flushing tlb
>
> [HOW]
> normalize the registers to keep lower 16-bit(dword aligned) to aviod higher
> bit violation
> RLCG will mask xcd out and always assume it's accessing its own xcd
>
> [TODO]
> lat
On Wed, Jun 19, 2024 at 9:32 PM Kenneth Feng wrote:
>
> This reverts commit 63400bcf5cb23b6a9b674eb3f2d733d826860065.
> Revert this due to a final solution in amdgu vcn:
> commit eef47ed5f703377781ce89eae4b9140325049873
> Author: Sonny Jiang
> Date: Tue Jun 18 11:11:11 2024 -0400
>
> drm/amdgpu
On Thu, Jun 20, 2024 at 3:10 AM Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Jun 19, 2024 at 09:53:12AM GMT, Alex Deucher wrote:
> > On Wed, Jun 19, 2024 at 9:50 AM Alex Deucher wrote:
> > >
> > > On Tue, Jun 18, 2024 at 7:53 PM Doug Anderson
> > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > On Tue,
Le 19/06/2024 à 11:26, Christian König a écrit :
Am 18.06.24 um 17:23 schrieb Pierre-Eric Pelloux-Prayer:
Waking up a device can take multiple seconds, so if it's not
going to be used we might as well not resume it.
The safest default behavior for all ioctls is to resume the GPU,
so this cha
Both versions are fine by me, so I'll update the code to match whatever
you agree on.
Pierre-Eric
Le 19/06/2024 à 20:44, Marek Olšák a écrit :
The INFO ioctl was designed to allow increasing the sizes of all info
structures. GB_ADDR_CONFIG isn't that special to justify a separate
query.
Marek
On Thu, Jun 20, 2024 at 3:02 AM Min, Frank wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> From: Frank Min
>
> Access ltr through pci cfg space instead of mmio while programing aspm on
> gfx12
>
> Signed-off-by: Frank Min
Acked-by: Alex Deucher
> ---
> drivers/gpu/dr
Am 20.06.24 um 15:06 schrieb Pierre-Eric Pelloux-Prayer:
Le 19/06/2024 à 11:26, Christian König a écrit :
Am 18.06.24 um 17:23 schrieb Pierre-Eric Pelloux-Prayer:
Waking up a device can take multiple seconds, so if it's not
going to be used we might as well not resume it.
The safest default be
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
[TODO]
later will add the normalization in sriovw/rreg after fixing bugs
Clearing the IH_RB_W/RPTR during interrupts disable is not clearing
the RB_OVERFLOW bit.
Adding workaround to clear the wptr when enabling interrupts in case
RB_OVERFLOW bit is set.
Signed-off-by: Danijel Slivka
---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 6 ++
1 file changed, 6 insertions(+)
[AMD Official Use Only - AMD Internal Distribution Only]
From: Frank Min
update gfxhub client id for gfx12
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
[AMD Official Use Only - AMD Internal Distribution Only]
Series is:
Reviewed-by: Sonny Jiang
From: Alex Deucher
Sent: Thursday, June 20, 2024 8:48 AM
To: Feng, Kenneth
Cc: amd-gfx@lists.freedesktop.org ; Jiang, Sonny
Subject: Re: [PATCH 2/2] Revert "drm/amd/am
[Public]
> > + dma_resv_lock(bo->tbo.base.resv, NULL);
>
> Why do you grab the BO lock to update the stats? That doesn't seem to make
> any sense.
>
> > + update_stats = !(bo->flags & AMDGPU_GEM_WAS_EXPORTED);
> > + if (update_stats)
> > + amdgpu_bo_add_memory(bo, &stats);
> > +
On Thu, Jun 20, 2024 at 10:32 AM Min, Frank wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> From: Frank Min
Acked-by: Alex Deucher
>
> update gfxhub client id for gfx12
>
> Signed-off-by: Frank Min
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c | 22 +++
Am 20.06.24 um 16:30 schrieb Li, Yunxiang (Teddy):
[Public]
+ dma_resv_lock(bo->tbo.base.resv, NULL);
Why do you grab the BO lock to update the stats? That doesn't seem to make
any sense.
+ update_stats = !(bo->flags & AMDGPU_GEM_WAS_EXPORTED);
+ if (update_stats)
+ amdgpu_bo
Convert amdgpu to use ttm_bo_vmap() instead of ttm_bo_kmap(). The
latter is deprecated. Passing ttm_bo_vmap()'s locking validation
requires to remove the implicit unmap from the BO release path.
Smoke-tested with an Radeon RX 460.
There's similar patchset for xe at [1], which requires additional
Replace each call to ttm_bo_kmap() with a call to ttm_bo_vmap().
Same for ttm_bo_kunmap() and ttm_bo_vunmap(). There's now one less
driver depending on the deprecated ttm_bo_kmap().
Also allows for dropping struct ttm_bo_kmap_obj in favor of struct
iosys_map, which is the preferred representation
Prepares for using ttm_bo_vmap() and ttm_bo_vunmap() in amdgpu. Both
require the caller to hold the GEM reservation lock, which is not the
case while releasing a buffer object. Hence, push a possible call to
unmap out from the buffer-object release code. Warn if a buffer object
with mapped pages is
On Thu, Jun 20, 2024 at 3:47 AM Bob Zhou wrote:
>
> Fix the unchecked return value warning by warning reported by
> Coverity, so add error handling.
>
> Signed-off-by: Bob Zhou
Looks like there are a few other places in the driver where
amdgpu_ring_alloc() is not checked. Can you fix those up t
Applied. Thanks!
Alex
On Thu, Jun 20, 2024 at 4:49 AM Dan Carpenter wrote:
>
> This code works, but it's not aligned correctly. Add a couple missing
> tabs.
>
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++--
> 1 file changed, 2 inse
Applied. Thanks!
Alex
On Thu, Jun 20, 2024 at 5:07 AM Jiapeng Chong
wrote:
>
> No functional modification involved.
>
> ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:3171:2-3:
> Unneeded semicolon.
> ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_
Applied. Thanks!
Alex
On Thu, Jun 20, 2024 at 5:07 AM Dan Carpenter wrote:
>
> We recently added locking to add_queue_mes() but this error path was
> overlooked. Add an unlock to the error path.
>
> Fixes: 1802b042a343 ("drm/amdgpu/kfd: remove is_hws_hang and is_resetting")
> Signed-off-by: Da
I think the "break;" there is to silence the compilation warning - it is
ugly but needed.
David
On 2024-06-20 11:38, Alex Deucher wrote:
Applied. Thanks!
Alex
On Thu, Jun 20, 2024 at 5:07 AM Jiapeng Chong
wrote:
No functional modification involved.
./drivers/gpu/drm/amd/display/dc/dml2/d
Am 20.06.24 um 16:44 schrieb Thomas Zimmermann:
Prepares for using ttm_bo_vmap() and ttm_bo_vunmap() in amdgpu. Both
require the caller to hold the GEM reservation lock, which is not the
case while releasing a buffer object. Hence, push a possible call to
unmap out from the buffer-object release
Am 20.06.24 um 15:55 schrieb Danijel Slivka:
Clearing the IH_RB_W/RPTR during interrupts disable is not clearing
the RB_OVERFLOW bit.
Adding workaround to clear the wptr when enabling interrupts in case
RB_OVERFLOW bit is set.
Signed-off-by: Danijel Slivka
---
drivers/gpu/drm/amd/amdgpu/ih_v6
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Enable DCC on DCN401
* Fix cursor issues
* Misc Coverity fixes
Cc: Daniel Wheeler
Alex Hung (12):
drm/amd/display: Remove redundant checks for pipe_ctx->stream
drm/amd/display: Run DC_LOG_DC after checking
From: Nicholas Susanto
[WHY]
On hotpluggin a 4k144 HDMI FRL setup, display fails FRL link training
and falls back to TMDS which is caused by driver not ungating HPO before
doing FRL link training.
[HOW]
Enable debug flag to disable HPO power gate in DCN35
Reviewed-by: Nicholas Kazlauskas
Revie
From: Relja Vojvodic
[WHY]
Function was used to check the number of FEs connected to the current BE.
This was then used to determine if the symclk could be disabled, if all
FEs were disconnected. However, the function would skip over the primary
FE and return 0 when the primary FE was still conne
From: Ivan Lipski
[WHY]
Coverity analysis flagged these files as containing DEADCODE, i. e.
redundant or unreachabale. In these files, variable 'mode_422' is
always the same file (0 or false), so any code logic with it is
redundant.
[HOW]
Removed 'mode_422' variable and all code with it from
'di
From: Ivan Lipski
[WHY]
Coverity analysis flagged this code as DEADCODE because
the condition '(!need_recovery)' is never true.
The variable 'need_recovery' is initialized as 'true',
is not assigned to 'false' anywhere before the
conditional statement.
Since the variable is only used for the co
From: Nevenko Stupar
[WHY & HOW]
Current code for cursor positions does not work properly
with different ODM options and HW rotations like ODM
2to1, 3to1 and 4to1, and has different issues depending on
angle of HW rotations.
[HOW]
Fixed these issues so to work properly when ODM is used with HW r
From: Michael Strauss
[WHY]
New register field added in DP2.1 SCR, needed for auxless ALPM
[HOW]
Echo value read from 0xF0007 back to sink
Reviewed-by: Wenjing Liu
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../
[WHAT & HOW]
The null checks for pipe_ctx->stream and pipe_ctx->stream_res.tg
are redundant as they were already dereferenced previously, as
reported by Coverity; therefore the null checks are removed.
This fixes 6 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by
[WHAT]
The DC_LOG_DC should be run after link->link_enc is checked, not before.
This fixes 1 REVERSE_INULL issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/link/link_factory.c | 6 +++---
1 file changed,
From: Nevenko Stupar
[WHY & HOW]
Fix the cursor size between ODM slices.
Reviewed-by: Sridevi Arvindekar
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Nevenko Stupar
---
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 14 +
[WHAT & HOW]
surf_linear_128_l/c are used in CalculateBytePerPixelAndBlockSizes
before they are assigned, so initializing them before passing them into
the function.
This fixes 2 UNINIT issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
[WHAT & HOW]
clk_mgr_helper_get_active_display_cnt returns display count and itself
alone has no use.
This fixes 1 CHECKED_RETURN issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk
[WHAT & HOW]
BIOS_CMD_TABLE_REVISION and link_transmitter_control can return error
codes and errors should be reported.
This fixes 3 CHECKED_RETURN issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/bios/c
[WHAT & HOW]
dm_dmub_hw_init and drm_dp_mst_topology_mgr_set_mst can return error
codes and errors should be reported.
This fixes 2 CHECKED_RETURN issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/
[WHAT & HOW]
Check mod_hdcp_execute_and_set() return values in authenticated_dp.
This fixes 3 CHECKED_RETURN issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
.../amd/display/modules/hdcp/hdcp1_execution.c| 15 +--
1 fi
From: Joan Lee
[WHY & HOW]
Driver side adding replay general cmd interface.
Replay general command will config at most two uint_32 parameters,
with a replay general command subtype to set relative configurations.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Joan Lee
---
From: Aurabindo Pillai
[WHAT & HOW]
On DCN401, the cursor composition to the plane happens after scaler.
So the cursor isn't stretched with the rest of the surface. Temporarily
disable hardware cursor in case when hardware rotation is enabled
such that userspace falls back to software cursor.
Re
From: "Leo (Hanghong) Ma"
[WHY && HOW]
Some DP EDID CTS tests fail due to HPO disable, and we should keep it
enable on DCN4 dGPU.
Reviewed-by: Wenjing Liu
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/
From: TungYu Lu
[WHY]
Tiled displays showed not aligned on 8K60hz when system resumed
from S3/S4.
[HOW]
Do dc_trigger_sync to re-sync pipes to ensure OTG become synced.
Reviewed-by: Alvin Lee
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by
From: George Shen
[WHY]
In check_mode_supported, we should validate that the required clocks
can be successfully mapped to DPM levels.
This ensures we only apply dynamic ODM optimizations to modes that
are supported without dynamic ODM optimizations to begin with.
[HOW]
Call dpmm to check that
From: Sung-huai Wang
[WHY]
Underflow occurs on some platforms when urgent BW is close to
the maximum in DPM0.
[HOW]
It does not occur at DPM1, so as a workaround restrict the maximum
amount and increase the lowest state index for clock states until
we're out of DPM0.
Adds DML2 config options to
From: Dillon Varone
[WHY & HOW]
Currently the force only works for a single display, make it so it can
be forced per stream.
Reviewed-by: Alvin Lee
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/dis
From: Daniel Sa
[WHY]
Some monitors are forced to a lower resolution and refresh rate after
system restarts.
[HOW]
Some monitors may give invalid LTTPR information when queried such as
indicating they have one DP lane instead of 4. If given an invalid DPCD
version, skip over getting lttpr link r
[WHAT]
1. is_pwrseq0 needs to check link before accessing link->link_index.
2. context is checked before accessing its bw_ctx.dml2
3. clk_mgr_base->bw_params is checked before clk_table.num_entries_per_cl
This fixes 4 REVERSE_INULL issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked
From: Alvin Lee
[WHAT & HOW]
According to register specifications, the CURSOR_DST_X_OFFSET
is relative to the start of the data viewport, not RECOUT space.
In this case we must transform the cursor coordinates passed to
hubp401_cursor_set_position into viewport space to program this
register. Thi
From: Duncan Ma
[WHY]
When system exits idle state followed by enabling the display,
DSC memory may still be forced in a deep sleep or shutdown state.
Intermittent DSC corruption is seen when display is visible.
[HOW]
When DSC is enabled, reset dsc memory to force and disable status.
Reviewed-
From: Alvin Lee
[WHAT & HOW]
We must wait for ODM double buffer updates to complete
before exiting the pipe update sequence or we may reduce
DISPCLK and hit some transient underflow (pixel rate is
reduced before the pipes have ODM enabled).
Reviewed-by: Samson Tam
Cc: Mario Limonciello
Cc: Ale
From: Nevenko Stupar
[WHY & HOW]
Adjust hot spot positions between ODM slices when cursor
magnification is used.
Reviewed-by: Sridevi Arvindekar
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Nevenko Stupar
---
.../gpu/drm/amd/display/d
From: Ryan Seto
[WHY]
Added HW cursor visual confirm
[HOW]
Added visual confirm logic when programming cursor positions.
HW is programmed on cursor updates since cursor can change without flips.
Reviewed-by: Alvin Lee
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by
From: Wenjing Liu
[WHY]
mod_hdcp_execute_and_set returns (*status == MOD_HDCP_STATUS_SUCCESS).
When it return 0, it is guaranteed that status == MOD_HDCP_STATUS_SUCCESS
will be evaluated as false. Since now we are using goto out already, all 3
if (status == MOD_HDCP_STATUS_SUCCESS) clauses are gu
From: Ryan Seto
[WHY]
DSC was waiting for the wrong field to disconnect cleanly.
[HOW]
Changed field the DSC disconnect was waiting on.
Reviewed-by: Wenjing Liu
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung
Signed-off-by: Ryan Seto
---
drivers/gpu/d
From: Relja Vojvodic
[WHY]
Enabling NL SDR blending caused the 1D LUTs to be set/populated in two
different functions. This caused flickering as the LUT was set differently
by the two functions, one of which should only have been modifying the 1D
LUT if 3D LUT was enabled.
[HOW]
Added check to o
From: Roman Li
[WHY]
Hotplug is not detected in headless (no eDP) mode on dcn35x.
With no display dcn35x goes to IPS2 powersaving state where HPD interrupt
is not handled.
[HOW]
Use idle worker thread for periodic detection of HPD in headless mode.
Reviewed-by: Aurabindo Pillai
Cc: Mario Limon
[WHAT & HOW]
Check cm3_helper_translate_curve_to_hw_format runs successfully so the
regamma_params is valid and can be used.
Also revmoed two result assignments.
This fixes 2 CHECKED_RETURN UNUSED_VALUE issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by:
[WHAT & HOW]
Function return values must be checked before data can be used
in subsequent functions.
This fixes 4 CHECKED_RETURN issues reported by Coverity.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
[WHAT & HOW]
advanced_pstate_switching was initialized to false and never assigned to
another value; as a result !advanced_pstate_switching is always true and
should be removed.
This fixes 2 DEADCODE issues reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: A
[WHAT & HOW]
The same display null check was a few lines above.
This fixes 1 DEADCODE issue reported by Coverity.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 3 ---
1 file changed, 3 deletions(-)
diff --
From: Aurabindo Pillai
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
.../include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 110 ++
1 file changed, 110 insertions(+)
diff --
From: Aurabindo Pillai
[WHAT]
Add registers and entry points to enable DCC on DCN4x
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 11 +
drivers/gpu/
From: Aric Cyr
This version brings along the following:
- Enable DCC on DCN401
- Add reg definitions for DCN401 DCC
- Remove duplicate null check
- Remove always true condition
- Validate function returns
- Ensure curve to hw translation succeed
- Use periodic detection for ipx/headless
- Fix 1D
On Thu, Jun 20, 2024 at 10:12 AM Danijel Slivka wrote:
>
> Clearing the IH_RB_W/RPTR during interrupts disable is not clearing
> the RB_OVERFLOW bit.
> Adding workaround to clear the wptr when enabling interrupts in case
> RB_OVERFLOW bit is set.
>
> Signed-off-by: Danijel Slivka
> ---
> drivers
On Thu, Jun 20, 2024 at 12:07 PM David Wu wrote:
>
> I think the "break;" there is to silence the compilation warning - it is
> ugly but needed.
Which break? It looks fine to me.
Alex
>
> David
>
> On 2024-06-20 11:38, Alex Deucher wrote:
> > Applied. Thanks!
> >
> > Alex
> >
> > On Thu, Jun
see inline, please
David
On 2024-06-20 12:50, Alex Deucher wrote:
On Thu, Jun 20, 2024 at 12:07 PM David Wu wrote:
I think the "break;" there is to silence the compilation warning - it is
ugly but needed.
Which break? It looks fine to me.
example here - code is fine but the compiler will com
On Thu, Jun 20, 2024 at 1:18 PM David Wu wrote:
>
> see inline, please
> David
>
> On 2024-06-20 12:50, Alex Deucher wrote:
> > On Thu, Jun 20, 2024 at 12:07 PM David Wu wrote:
> >> I think the "break;" there is to silence the compilation warning - it is
> >> ugly but needed.
> > Which break? It
Add support for SMDA to the KIQ map/unmap functions.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 85 +-
drivers/gpu/drm/amd/amdgpu/nvd.h | 2 +
2 files changed, 73 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/
On 2024-06-20 13:21, Alex Deucher wrote:
On Thu, Jun 20, 2024 at 1:18 PM David Wu wrote:
see inline, please
David
On 2024-06-20 12:50, Alex Deucher wrote:
On Thu, Jun 20, 2024 at 12:07 PM David Wu wrote:
I think the "break;" there is to silence the compilation warning - it is
ugly but nee
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Alex,
Thanks for your review, I will push other patch to fix those issues.
Regards,
Bob
-Original Message-
From: Alex Deucher
Sent: 2024年6月20日 22:59
To: Zhou, Bob
Cc: amd-gfx@lists.freedesktop.org; Huang, Tim ; Zhang,
Jesse(
fault_status is read only register. fault_cntl
is not accessible from guest environment.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 8 +---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 8 +---
3 files change
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Tao Zhou
> -Original Message-
> From: amd-gfx On Behalf Of Hawking
> Zhang
> Sent: Friday, June 21, 2024 11:30 AM
> To: amd-gfx@lists.freedesktop.org; Zhou1, Tao
> Cc: Zhang, Hawking
> Subject: [PATCH] drm/amdgpu: F
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
[TODO]
later will add the normalization in sriovw/rreg after fixing bugs
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in situations like if drivers would like to do address alignment
for specific requirements.
- Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this
flag to disab
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Min, Frank
Sent: Thursday, June 20, 2024 14:52
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Hawking
; Koenig, Christian ; Gao,
Likun
Subj
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Min, Frank
Sent: Tuesday, June 18, 2024 21:07
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Gao, Likun ;
Deucher, Alexander ; Koenig, Christian
Subje
[AMD Official Use Only - AMD Internal Distribution Only]
Shall we make pre_de_queried_count to be local variable? Others look good to me
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Thursday, June 20, 2024 13:40
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Thursday, June 20, 2024 13:40
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Li,
Candice ; Wang, Yang(Kevin) ; Yang,
St
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Thursday, June 20, 2024 13:40
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Li,
Candice ; Wang, Yang(Kevin) ; Yang,
St
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chai, Thomas
Sent: Thursday, June 20, 2024 13:40
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Li,
Candice ; Wang, Yang(Kevin) ; Yang,
St
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