From: Nicholas Susanto <nicholas.susa...@amd.com>
[WHY]
On hotpluggin a 4k144 HDMI FRL setup, display fails FRL link training
and falls back to TMDS which is caused by driver not ungating HPO before
doing FRL link training.
[HOW]
Enable debug flag to disable HPO power gate in DCN35
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Reviewed-by: Charlene Liu <charlene....@amd.com>
Acked-by: Alex Hung <alex.h...@amd.com>
Signed-off-by: Nicholas Susanto <nicholas.susa...@amd.com>
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 0094ef223c5d..67ab8c1962ff 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -721,7 +721,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dpp_power_gate = true,
.disable_hubp_power_gate = true,
.disable_optc_power_gate = true, /*should the same as above two*/
- .disable_hpo_power_gate = false, /*dmubfw force domain25 on*/
+ .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
.disable_clock_gate = false,
.disable_dsc_power_gate = true,
.vsr_support = true,
--
2.34.1
