From: Daniel Sa <daniel...@amd.com>
[WHY]
Some monitors are forced to a lower resolution and refresh rate after
system restarts.
[HOW]
Some monitors may give invalid LTTPR information when queried such as
indicating they have one DP lane instead of 4. If given an invalid DPCD
version, skip over getting lttpr link rate and lane counts.
Reviewed-by: Wenjing Liu <wenjing....@amd.com>
Cc: Mario Limonciello <mario.limoncie...@amd.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
Acked-by: Alex Hung <alex.h...@amd.com>
Signed-off-by: Daniel Sa <daniel...@amd.com>
---
.../dc/link/protocols/link_dp_capability.c | 21 ++++++++++---------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index f1cac74dd7f7..46bb7a855bc2 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -409,9 +409,6 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct
dc_link *link)
case LINK_RATE_HIGH3:
lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
break;
- default:
- // Assume all LTTPRs support up to HBR3 to improve misbehaving
sink interop
- lttpr_max_link_rate = LINK_RATE_HIGH3;
}
if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
@@ -2137,15 +2134,19 @@ struct dc_link_settings dp_get_max_link_cap(struct
dc_link *link)
* notes: repeaters do not snoop in the DPRX Capabilities addresses
(3.6.3).
*/
if (dp_is_lttpr_present(link)) {
- if (link->dpcd_caps.lttpr_caps.max_lane_count <
max_link_cap.lane_count)
- max_link_cap.lane_count =
link->dpcd_caps.lttpr_caps.max_lane_count;
- lttpr_max_link_rate = get_lttpr_max_link_rate(link);
- if (lttpr_max_link_rate < max_link_cap.link_rate)
- max_link_cap.link_rate = lttpr_max_link_rate;
+ /* Some LTTPR devices do not report valid DPCD revisions, if
so, do not take it's link cap into consideration. */
+ if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) {
+ if (link->dpcd_caps.lttpr_caps.max_lane_count <
max_link_cap.lane_count)
+ max_link_cap.lane_count =
link->dpcd_caps.lttpr_caps.max_lane_count;
+ lttpr_max_link_rate = get_lttpr_max_link_rate(link);
- if
(!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
- is_uhbr13_5_supported = false;
+ if (lttpr_max_link_rate < max_link_cap.link_rate)
+ max_link_cap.link_rate = lttpr_max_link_rate;
+
+ if
(!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
+ is_uhbr13_5_supported = false;
+ }
DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane
count %d max_link rate %d \n",
__func__,
--
2.34.1
