[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, January 22, 2025 11:45
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad ; Wang,
Yang(Kevin)
Aldebaran doesn't support querying MM activity percentage. Keep the
field as 0xFFs to mark it as unsupported.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/
On 1/22/2025 8:28 AM, Mario Limonciello wrote:
> On 1/20/2025 23:45, Lazar, Lijo wrote:
>>
>>
>> On 1/13/2025 9:10 AM, Jiang Liu wrote:
>>> When GPU suspend is aborted, do the same for dGPU as APU to reset
>>> soc15 asic. Otherwise it may cause following errors:
>>> [ 547.229463] amdgpu 0001:81
On 1/20/2025 23:45, Lazar, Lijo wrote:
On 1/13/2025 9:10 AM, Jiang Liu wrote:
When GPU suspend is aborted, do the same for dGPU as APU to reset
soc15 asic. Otherwise it may cause following errors:
[ 547.229463] amdgpu 0001:81:00.0: [drm:amdgpu_ring_test_helper [amdgpu]]
*ERROR* ring kiq_0.2.
On 1/20/25 14:00, Laurent Pinchart wrote:
On Fri, Jan 10, 2025 at 01:23:40PM -0800, James Jones wrote:
On 12/19/24 10:03, Simona Vetter wrote:
On Thu, Dec 19, 2024 at 09:02:27AM +, Daniel Stone wrote:
On Wed, 18 Dec 2024 at 10:32, Brian Starkey wrote:
On Wed, Dec 18, 2024 at 11:24:58AM +
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Alex, thank you for the review, it was very helpful.
Submitted a different approach:
[PATCH 3/3] drm/amdgpu: Set lower queue retry timeout for gfx9 family
Thank you,
Elena
From: Alex Deucher
Sent: De
From: George Shen
[Why]
DP spec updated to have the CR AUX RD interval match the EQ AUX RD
interval interpretation of DPCD Eh/0220Eh for 8b/10b non-LTTPR mode
and LTTPR transparent mode cases.
[How]
Update interpretation of DPCD Eh/0220Eh for CR AUX RD interval
during 8b/10b link trainin
From: Charlene Liu
[why]
currently dml2 is using a hard coded 16 to convert memclk to dram_speed_mts.
for apu, this depends on wck_ratio.
change to pass the already calculated dram_speed_mts from fpu to dml2.
Reviewed-by: Natanel Roizenman
Signed-off-by: Charlene Liu
Signed-off-by: Zaeem Moha
From: Dillon Varone
[WHY&HOW]
IP_REQUEST_CNTL should only be toggled off when it was originally, never
unconditionally.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Zaeem Mohamed
---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 14 +---
.../amd/display/dc/hwss/dc
From: Peichen Huang
[WHY]
We would like to have new dio encoder assigning flow.
Which should be aligned with hpo assigning and have
simple logic and data representation.
[HOW}
1. A new config option to enable/disable the new code.
2. Encoder-link mapping is in res_ctx and assigned encoder.
is ac
From: Aric Cyr
Signed-off-by: Aric Cyr
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 06d9cf0a7edc..559446dcd431 100644
---
From: Alex Hung
[WHAT & HOW]
GET_IMAGE can return null, and checking firmware_info32 before
dereferencing it is necessary.
This fixes 1 NULL_RETURNS issue reported by Coverity.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/
From: Sung Lee
[WHY]
In some situations, dc->res_pool may be null.
[HOW]
Check if pointer is null before dereference.
Reviewed-by: Joshua Aberback
Signed-off-by: Sung Lee
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +---
1 file changed, 5 insertions(+),
From: Wayne Lin
Fix NULL_RETURNS error caught by Coverity.
=> firmware_info32 might be NULL. Check it before dereference.
Fixes: 352f9a9451ec ("drm/amd/display/dc: add support for oem i2c in
atom_firmware_info_v3_1")
Reviewed-by: Wayne Lin
Signed-off-by: Wayne Lin
Signed-off-by: Zaeem Mohame
From: loanchen
[Why]
the offset address of mmCLK5_spll_field_8 was incorrect for dcn35
which causes SSC not to be enabled.
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Signed-off-by: Lo-An Chen
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mg
From: Hansen Dsouza
[Why]
Spread on DPREFCLK by 0.3 percent can have a negative effect on sink
when PHY SSC is also spread by 0.3 percent
[How]
Add boot option for DMU to lower PHY SSC
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Hansen Dsouza
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/
From: Tom Chung
[Why]
PSR-SU may cause some glitching randomly on some OLED panel.
[How]
Disable the PSR-SU for certain PSR-SU OLED panel.
Reviewed-by: Sun peng Li
Signed-off-by: Tom Chung
Signed-off-by: Zaeem Mohamed
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 20 ++
From: Austin Zheng
[Why]
1) The current calculations for OTO prefetch bandwidth do not consider the
number of DPP pipes in use.
As a result, OTO prefetch bandwidth may be larger than the vactive bandwidth if
multiple DPP pipes are used.
OTO prefetch bandwidth should never exceed the vactive ban
From: Zhikai Zhai
[Why]
The double buffer cursor registers is updated by the cursor
vupdate event. There is a gap between vupdate and cursor data
fetch if cursor fetch data reletive to cursor position.
Cursor corruption will happen if we update the cursor surface
in this gap.
[How]
Modify the cu
From: Tom Chung
[Why & How]
The initial setting for psr_version is not correct while
create a virtual link.
The default psr_version should be DC_PSR_VERSION_UNSUPPORTED.
Reviewed-by: Roman Li
Signed-off-by: Tom Chung
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/core/dc.c
This DC patchset brings improvements in multiple areas. In summary, we have:
- Fixes on psr_version, dcn35 register address, DCPG OP control sequences
- Imporvements to CR AUX RD interval interpretation, dio link encoder
- Disable PSR-SU on some OLED panels
Cc: Daniel Wheeler
Alex Hung (1)
On Mon, Jan 20, 2025 at 1:41 PM Simona Vetter
wrote:
> On Mon, Jan 20, 2025 at 08:58:20AM +0100, Thomas Zimmermann wrote:
> > Hi
> >
> >
> > Am 18.01.25 um 03:37 schrieb Marek Olšák:
> > [...]
> > >
> > > 3) Implementing DRM_FORMAT_MOD_LINEAR as having 256B pitch and offset
> > > alignment. This
On 1/21/25 10:32, Harry Wentland wrote:
On 2025-01-21 08:57, Mario Limonciello wrote:
From: Mario Limonciello
The number of active surfaces is initialized to the number
of active planes. If the number of planes aren't initialized
properly then the last plane can end up not getting initia
On 2025-01-21 08:57, Mario Limonciello wrote:
> From: Mario Limonciello
>
> The number of active surfaces is initialized to the number
> of active planes. If the number of planes aren't initialized
> properly then the last plane can end up not getting initialized
> which can be a divide by ze
On 2025-01-20 14:49, Mario Limonciello wrote:
> From: Mario Limonciello
>
> mark_seamless_boot_stream() can be called multiple times to run
> the more expensive checks in dc_validate_boot_timing().
>
> Refactor the function so that if those have already passed once
> the function isn't called ag
On Tue, Jan 21, 2025 at 12:47 AM Lijo Lazar wrote:
>
> Fix the initialization and usage of SMU v13.0.6 capability values. Use
> caps_set/clear functions to set/clear capability.
>
> Also, fix SET_UCLK_MAX capability on APUs, it is supported on APUs.
>
> Signed-off-by: Lijo Lazar
> Reviewed-by: Al
From: Mario Limonciello
The indentation for some lines in DML2 code is off and checkpatch
reported it while fixing another issue.
```
WARNING: suspect code indent for conditional statements (24, 40)
46: FILE: drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c:6416:
+ f
Hi Dmitry,
On Tue, Jan 7, 2025 at 12:31 PM Dmitry Baryshkov
wrote:
> On Sat, 14 Dec 2024 15:37:04 +0200, Dmitry Baryshkov wrote:
> > While working on the generic mode_valid() implementation for the HDMI
> > Connector framework I noticed that unlike other DRM objects
> > drm_connector accepts non-
From: Mario Limonciello
Iterators of `num_active_planes` start at zero but since the loops
have a condition of `<= num_active_planes - 1`. This will mean that
the last plane isn't checked.
Adjust the condition to go all the way to `num_acftive_planes`.
Fixes: 7966f319c66d9 ("drm/amd/display: In
From: Mario Limonciello
The number of active surfaces is initialized to the number
of active planes. If the number of planes aren't initialized
properly then the last plane can end up not getting initialized
which can be a divide by zero error.
Reported-and-tested-by: Luke Jones
Closes: https:
From: Mario Limonciello
Many people have reported a series of issues that lead to divide
by zero errors in DML2 code on DCN 3.5.
This divide by zero error is caused by accessing outside of the bound
of what is initialized on an array for the number of planes.
The first patch in the series fixes
From: Mario Limonciello
Iterators of `NumberOfActiveSurfaces` start at zero but since the loops
have a condition of `<= NumberOfActiveSurfaces - 1`. This will mean that
the last surface isn't checked.
Adjust the condition to go all the way to `NumberOfActiveSurfaces`.
Signed-off-by: Mario Limon
On 20/01/2025 17:17, Danilo Krummrich wrote:
On Mon, Jan 20, 2025 at 04:52:39PM +, Tvrtko Ursulin wrote:
The code assumes queue node is the first element in struct
drm_sched_job.
I'd add that this assumption lies in doing the NULL check after the
container_of(). Without saying that, it m
On 20/01/2025 18:49, Christian König wrote:
Am 20.01.25 um 18:13 schrieb Danilo Krummrich:
On Mon, Jan 20, 2025 at 04:52:37PM +, Tvrtko Ursulin wrote:
Idea is to add a helper for popping jobs from the entity with the goal
of making amdgpu use it in the next patch. That way amdgpu will dec
Hi Dmitry,
CC sfr
On Tue, Jan 21, 2025 at 11:44 AM Dmitry Baryshkov
wrote:
> On Tue, 21 Jan 2025 at 11:13, Geert Uytterhoeven wrote:
> > On Tue, Jan 7, 2025 at 12:31 PM Dmitry Baryshkov
> > wrote:
> > > On Sat, 14 Dec 2024 15:37:04 +0200, Dmitry Baryshkov wrote:
> > > > While working on the ge
On Tue, Jan 21, 2025 at 12:10:25PM +0100, Geert Uytterhoeven wrote:
> Hi Dmitry,
>
> CC sfr
>
> On Tue, Jan 21, 2025 at 11:44 AM Dmitry Baryshkov
> wrote:
> > On Tue, 21 Jan 2025 at 11:13, Geert Uytterhoeven
> > wrote:
> > > On Tue, Jan 7, 2025 at 12:31 PM Dmitry Baryshkov
> > > wrote:
> > >
Am 21.01.25 um 07:50 schrieb Lin.Cao:
use job && job->vm to check ib has vmid and use job && job->vmid to
check if switch buffer should be emitted
Signed-off-by: Lin.Cao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/driv
On Tue, 21 Jan 2025 at 11:13, Geert Uytterhoeven wrote:
>
> Hi Dmitry,
>
> On Tue, Jan 7, 2025 at 12:31 PM Dmitry Baryshkov
> wrote:
> > On Sat, 14 Dec 2024 15:37:04 +0200, Dmitry Baryshkov wrote:
> > > While working on the generic mode_valid() implementation for the HDMI
> > > Connector framewor
On 1/20/2025 9:19 AM, Yifan Zha wrote:
> [Why]
> Under SRIOV VF, driver send a VF unsupportted smu message causing
> a failure.
>
> [How]
> Update smu_v13_0_0 message mapping table based on PMFW.
>
Does this hold good for 1VF case also?
Thanks,
Lijo
> Signed-off-by: Yifan Zha
> ---
> driv
At one point I thought I wanted to add a member to struct drm_sched_job. As I
noticed there is a hole in the struct, I went to re-order some members to get
rid of it (the hole), at which point I was greeted by a subtle bug cause by the
frequent pattern of:
job = to_drm_sched_job(spsc_queue_peek|p
Dependency tracking via xarray uses xa_limit_32b so there is not need for
the struct member to be unsigned long.
At the same time re-order some struct members and take u32 credits outside
of the pointer sandwich and avoid a hole.
Pahole report before:
/* size: 160, cachelines: 3, members:
Amdgpu is the only driver which peeks into scheduler internals in this way
so lets make it use the previously added helper. This allows removing the
local copy of the to_drm_sched_job macro.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp St
The code assumes queue node is the first element in struct
drm_sched_job. Since this is not documented it can be very fragile so lets
just remove the internal helper and explicitly check for "nothing
dequeued", before converting the node to a sched job.
Signed-off-by: Tvrtko Ursulin
Cc: Christian
Idea is to add a helper for popping jobs from the entity with the goal
of making amdgpu use it in the next patch. That way amdgpu will decouple
itself a tiny bit more from scheduler implementation details.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
On Tue, Jan 21, 2025 at 12:50 AM Deucher, Alexander
wrote:
>
> [Public]
>
> > -Original Message-
> > From: amd-gfx On Behalf Of Pavel
> > Nikulin
> > Sent: Sunday, January 19, 2025 2:29 PM
> > To: Alex Deucher
> > Cc: amd-gfx@lists.freedesktop.org
> > Subject: Re: drm/amdgpu: AMDGPU unus
Hi,
I experimented with using this in KWin, and
https://invent.kde.org/plasma/kwin/-/merge_requests/7027/diffs?commit_id=6da40f1b9e2bc94615a436de4778880cee16f940
makes it fall back to a software renderer when a rebind is required to
recover the GPU.
Making it also survive the rebind properly is mo
> +It is the responsibility of the consumer to make sure that the device or
> +its resources are not in use by any process before attempting recovery.
I'm not convinced this is actually doable in practice, outside of
killing all apps that aren't the one trying to recover the GPU.
Is this just about
Hi,
On Mo, 2025-01-20 at 08:58 +0100, Thomas Zimmermann wrote:
> Hi
>
>
> Am 18.01.25 um 03:37 schrieb Marek Olšák:
> [...]
> >
> > 3) Implementing DRM_FORMAT_MOD_LINEAR as having 256B pitch and offset
> > alignment. This is what we do today. Even if Intel and some AMD chips
> > can do 64B or
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