From: Martin Tsai
[Why]
Incorrect cursor position will induce system hang on pipe split.
[How]
1.Handle horizontal mirror on rotation,
2.Correct cursor set on piep split.
Reviewed-by: Ariel Bernstein
Acked-by: Brian Chang
Signed-off-by: Martin Tsai
---
.../gpu/drm/amd/display/dc/dcn10/dcn10
From: Ethan Wellenreiter
[WHY]
Function wasn't returning false when it had a no stream
[HOW]
Made it return false when it had no stream.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Ethan Wellenreiter
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
1
From: Vladimir Stempen
[Why]
On secondary display hotplug we switch primary
stream from ODM2to1 to ODMBypass mode. Current
logic will trigger disabling front end for this
stream.
[How]
We need to check if prev_odm_pipe is equal to NULL
in order to disable dangling planes in this scenario.
Revie
From: Ethan Wellenreiter
[Why]
Pipes get merged in preparation for SubVP but if they don't get used, and
are in ODM or some other multi pipe config, it would calculate the
voltage level with a viewport of just one pipe from when they were split
resulting in too low of a voltage level.
[How]
Made
From: Aurabindo Pillai
[Why&How]
plane and stream variables used for cursor size allocation calculation
were stale from previous iteration. Redo the iteration to find the
correct cursor plane for the calculation.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
From: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9cde9465f5ce..75dbc66
From: Anthony Koo
- Fix comment to indicate correct visual confirm option
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/displ
From: Ian Chen
Reviewed-by: Dennis Chan
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 43d250918fd0..3f64b
From: Aurabindo Pillai
[Why & How]
This reverts commit 9dd9c085ae3b since it
causes a SubVP related regression: "Switching between windowed video and
fullscreen can intermittently cause black screen"
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/
From: Iswara Nagulendran
[HOW&WHY]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.
* SWDEV-342936 - dc: DSC bringup for SAG 1.5
[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.
[HOW]
From: Aurabindo Pillai
[Why&How]
When calculating allocation for cursor size, get the real cursor through
the HUBP instead of using the maximum cursor size for more optimal
allocation
Reviewed-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
From: Charlene Liu
[why]
fw version check was for release branch.
for staging, it has a chance to enter wrong code path.
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 3 +++
.../gpu/drm/amd/di
From: Aurabindo Pillai
[Why&How]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.
Prevent entering SS if we are on the edge case and cursor caching is not
From: Aurabindo Pillai
For calculating cursor size allocation, surface size was used, resulting
in over allocation
Reviewed-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
1 f
From: Leo Chen
[Why & How]
Number of encoder is set to 4 but only 3 instances are created.
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/a
From: Ian Chen
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |
From: Alvin Lee
[Description]
For SubVP scaling case we have to combine
the plane scaling and stream scaling.
Use UCLK dummy p-state WM for FCLK WM set C
[Description]
For DCN32/321 program dummy UCLK P-state watermark into FCLK
watermark set C register.
Reviewed-by: Jun Lei
Reviewed-by: Neve
From: "Leo (Hanghong) Ma"
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Leo (Hanghong) Ma
From: "Leo (Hanghong) Ma"
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this displ
From: Gabe Teeger
[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.
[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON, such as
when using MST or during resolution change. This is expected, so allow HW
programming to continue.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/g
From: Michael Strauss
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen
Acked-by: Brian Chang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5
From: "Chen, Leo"
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
di
From: Gabe Teeger
[Why]
On edp with psr1, we do not provide updates
of the cursor position regularly to firmware
like with PSR2. To send updates regularly,
the flag enable_sw_cntl_psr has to equal 1,
but cursor update should be provided
regularly to FW regardless of that flag.
[How]
Ensure that
From: Alvin Lee
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display
From: Wang Fudong
[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.
[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR
From: Charlene Liu
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h| 9 ++---
.../amd/display/
From: Duncan Ma
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acke
From: Lewis Huang
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito
Acked-by: B
From: George Shen
[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.
Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-t
From: Alvin Lee
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/d
From: Taimur Hassan
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../
This DC patchset brings improvements in multiple areas. In summary, we have:
* Correct cursor position on horizontal mirror;
* Fix black flash when switching from ODM2to1 to ODMBypass;
* Fix plane and stream check;
* Fix viewport after pipe merge;
* Correct plane for CAB cursor;
* Fix comment to c
From: Michael Strauss
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen
Acked-by: Brian Chang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5
From: "Chen, Leo"
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
di
From: Alvin Lee
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display
From: Wang Fudong
[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.
[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR
From: Charlene Liu
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h| 9 ++---
.../amd/display/
From: Alvin Lee
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/d
From: Duncan Ma
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu
Reviewed-by: Nicholas Kazlauskas
Acke
From: Lewis Huang
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito
Acked-by: B
From: George Shen
[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.
Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-t
From: Taimur Hassan
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../
This DC patchset brings improvements in multiple areas. In summary, we have:
* Correct cursor position on horizontal mirror;
* Fix black flash when switching from ODM2to1 to ODMBypass;
* Fix plane and stream check;
* Fix viewport after pipe merge;
* Correct plane for CAB cursor;
* Fix comment to c
On Sat, Aug 27, 2022 at 12:34:53AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename info->monitor_range to info->vrr_range to actually
> reflect its usage.
Okay makes sense.
Reviewed-by: Manasi Navare
Manasi
>
> Cc: Manasi Navare
> Cc: Nicholas Kazlauskas
> Cc: Harry Wentland
On Sat, Aug 27, 2022 at 12:34:52AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The current comment fails to clarify why we only accept
> the "range limits only" variant of the range descriptor.
> Reword it to make some actual sense.
>
Thanks Ville for adding this description for monito
BOs can be in a different location than was intended at allocation time,
for example when restoring fails after an eviction or BOs get pinned in
system memory. On some GPUs the MTYPE for coherent mappings depends on
the actual memory location.
Use the actual location to determine the pte_flags eve
On 2022-08-26 11:47, Alex Sierra wrote:
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device
From: Ville Syrjälä
Since we only use the parsed vrefresh range to determine
if VRR should be supported we should only accept continuous
frequency displays here.
Cc: Manasi Navare
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-gfx@lists.freedesktop.org
Si
From: Ville Syrjälä
Rename info->monitor_range to info->vrr_range to actually
reflect its usage.
Cc: Manasi Navare
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/amd/display/amdgpu_d
From: Ville Syrjälä
The current comment fails to clarify why we only accept
the "range limits only" variant of the range descriptor.
Reword it to make some actual sense.
Cc: Manasi Navare
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-gfx@lists.freedeskto
Applied. Thanks!
Alex
On Fri, Aug 26, 2022 at 4:50 AM Yang Yingliang wrote:
>
> Add missing pci_disable_device() if amdgpu_device_resume() fails.
>
> Fixes: 8e4d5d43cc6c ("drm/amdgpu: Handling of amdgpu_device_resume return
> value for graceful teardown")
> Signed-off-by: Yang Yingliang
> ---
Applied. Thanks!
Alex
On Fri, Aug 26, 2022 at 4:41 AM sunliming wrote:
>
> Fixes the following smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311
> dc_dmub_srv_p_state_delegate()
> warn: variable dereferenced before check 'dc' (see line 309)
>
> Reported-by: kernel
Applied. Thanks!
Alex
On Fri, Aug 26, 2022 at 3:24 AM wrote:
>
> From: ye xingchen
>
> Return the value sdma_v5_2_start() directly instead of storing it in
> another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: ye xingchen
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c |
On Fri, Aug 26, 2022 at 10:03 AM Jules Maselbas wrote:
>
> Remove redundant words `the` and `this`.
>
> CC: David Airlie
> CC: Maxime Ripard
> CC: Thomas Zimmermann
> CC: amd-gfx@lists.freedesktop.org
> CC: dri-de...@lists.freedesktop.org
> Signed-off-by: Jules Maselbas
Please split this up p
On Fri, Aug 26, 2022 at 11:48 AM Alex Sierra wrote:
>
> [Why] Devices with CPU XGMI iolink do not support PCIe peer access.
>
> Signed-off-by: Alex Sierra
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> di
From: Hawking Zhang
Add ip block support for lsdma v6_0_3.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/dr
From: Hawking Zhang
Add ip block support for sdma v6_0_3.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/dri
From: Hawking Zhang
To support new sdma ip block
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu
From: John Clements
Force to enable smu block for SMU v13.0.10
Signed-off-by: John Clements
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/a
From: John Clements
added sw pptable id for smu 13.0.10
Signed-off-by: John Clements
Signed-off-by: Likun Gao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/
From: Yang Wang
add smu_v13_0_10 support.
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu
From: Yang Wang
add smu_v13_0_10 driver if version
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/
From: Frank Min
Add ip block support for psp v13_0_10.
Signed-off-by: Frank Min
Signed-off-by: Hawking Zhang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgp
From: John Clements
added missing firmware module
Signed-off-by: John Clements
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/a
From: Frank Min
Add psp v13_0_10 ip block, initialize firmware and
psp functions
Signed-off-by: Frank Min
Signed-off-by: Hawking Zhang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 1 +
2 f
From: Sonny Jiang
This enable VCN PG, CG, DPG and JPEG PG, CG
Signed-off-by: Sonny Jiang
Reviewed-by: Leo Liu
Reviewed-by: John Clements
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/
From: Hawking Zhang
Add ip block support for soc21_common.
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/dr
From: Hawking Zhang
init cp/pg_flags and extenal_rev_id
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/am
From: Hawking Zhang
driver doesn't need to program any gc 11_0_0 golden
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 41 --
1 file changed, 41 deletions(-)
diff --git a/drivers/gpu/drm/am
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_devi
[AMD Official Use Only - General]
> -Original Message-
> From: Ghannam, Yazen
> Sent: Friday, August 26, 2022 11:20 AM
> To: Russell, Kent
> Cc: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Handle potential NULL pointer dereference
>
> On Thu, Aug 25,
On Thu, Aug 25, 2022 at 08:54:46AM -0400, Russell, Kent wrote:
> [AMD Official Use Only - General]
>
> It does indeed short-circuit on || (If the left side of an || statement is
> not 0, it doesn't evaluate the right side and returns true). So we can ignore
> this patch, since checking for each
On Fri, Aug 26, 2022 at 3:38 AM Simon Ser wrote:
>
> On Thursday, August 25th, 2022 at 20:22, Alex Deucher
> wrote:
>
> > On Wed, Aug 24, 2022 at 11:09 AM Simon Ser cont...@emersion.fr wrote:
> >
> > > amdgpu_dm_commit_planes already sets the flip_immediate flag for
> > > async page-flips. This
On Thu, Aug 25, 2022 at 6:34 PM Nathan Chancellor wrote:
>
> Hi AMD folks,
>
> Top posting because it might not have been obvious but I was looking for
> your feedback on this message (which can be viewed on lore.kernel.org if
> you do not have the original [1]) so that we can try to get this fixe
On Wed, Aug 24, 2022 at 03:08:55PM +, Simon Ser wrote:
> This new kernel capability indicates whether async page-flips are
> supported via the atomic uAPI. DRM clients can use it to check
> for support before feeding DRM_MODE_PAGE_FLIP_ASYNC to the kernel.
I think we'd need to clarify the sema
On Thursday, August 25th, 2022 at 20:22, Alex Deucher
wrote:
> On Wed, Aug 24, 2022 at 11:09 AM Simon Ser cont...@emersion.fr wrote:
>
> > amdgpu_dm_commit_planes already sets the flip_immediate flag for
> > async page-flips. This flag is used to set the UNP_FLIP_CONTROL
> > register. Thus, no
Am 25.08.22 um 19:48 schrieb Bjorn Helgaas:
On Thu, Aug 25, 2022 at 10:18:28AM +0200, Christian König wrote:
Am 25.08.22 um 09:54 schrieb Lazar, Lijo:
On 8/25/2022 1:04 PM, Christian König wrote:
Am 25.08.22 um 08:40 schrieb Stefan Roese:
On 24.08.22 16:45, Tom Seewald wrote:
On Wed, Aug 24,
On 8/25/22 9:37 AM, Hans de Goede wrote:
On some new laptop designs a new Nvidia specific WMI interface is present
which gives info about panel brightness control and may allow controlling
the brightness through this interface when the embedded controller is used
for brightness control.
When thi
Thanks, Hans.
Reviewed-by: Daniel Dadap
On 8/25/22 9:37 AM, Hans de Goede wrote:
Move the WMI interface definitions to a header, so that the definitions
can be shared with drivers/acpi/video_detect.c .
Changes in v2:
- Add missing Nvidia copyright header
- Move WMI_BRIGHTNESS_GUID to nvidia-w
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