Hi Paul, list
On Mon, Mar 31, 2025 at 8:21 PM Paul Menzel wrote:
> Dear Angel,
>
>
> Thank you for your reply.
>
> Am 31.03.25 um 21:36 schrieb Angel Pons:
>
> > On Mon, Mar 31, 2025 at 1:55 PM Paul Menzel
> wrote:
> >
> >> Dear coreboot folks,
&
Hi Paul,
On Mon, Mar 31, 2025 at 1:55 PM Paul Menzel wrote:
> Dear coreboot folks,
>
>
> Just a quick question, if there the 24.12 tag was renewed back in
> December(?).
>
> $ LANG= git fetch --tags
> From ssh://review.coreboot.org:29418/coreboot
> ! [rejected] 24.12
Hello list,
On Wed, Oct 2, 2024 at 7:40 AM David Hendricks via coreboot <
coreboot@coreboot.org> wrote:
> Dear coreboot community members,
>
> Recently there was some unpleasant activity on Gerrit which violated our
> community’s guidelines regarding respectful conduct. In this case the
> coreboo
Hi lödur,
Gitiles is disabled (I forget the reason, but it was severe enough to
require disabling Gitiles in the meantime). So you would have to clone the
relevant repository or use a mirror.
For the first Gitiles link, you can look at the GitHub mirror instead:
https://github.com/coreboot/corebo
Hi,
On Thu, Jul 4, 2024 at 3:48 PM Arthur Heymans wrote:
>
> Hi
>
> The coreboot trademark is registered as lowercase.
> We enforce this in for instance commits, even when normal grammar would
> dictate uppercase at the start of a sentence.
>
> This makes sense for very well known brands, compan
ashchips data could make it easier to compare against SFDP
information. But we'll cross the bridge when we get there (it'll be
easier to decide later, with more information).
> On Fri, Jun 28, 2024 at 9:27 AM Greg Troxel wrote:
> >
> > Angel Pons writes:
> >
> &
Hi list,
On Thu, Jun 27, 2024 at 2:00 PM mina--- via coreboot
wrote:
>
> # 2024-06-26 - coreboot Leadership Meeting
*snip*
> ### [Martin] Merge SLOs
> * Can we define objectives for timeframes to get patches merged to
> different areas in the codebase?
> An individual mainboard that doesn’t
Hi list,
On Thu, Jun 27, 2024 at 1:45 PM Greg Troxel wrote:
>
> Anastasia Klimchuk writes:
>
> > * As the time goes, chip vendors are producing newer models, which
> > sometimes re-use model IDs of old versions. Old versions are
> > considered as "end of life", and replaced with newer models wit
Issue #461 has been updated by Angel Pons.
Category changed from board support to chipset configuration
Status changed from New to In Progress
Start date changed from 02/16/2023 to 04/01/2020
% Done changed from 0 to 30
Related links updated
Affected hardware changed from T440p and other to All
Issue #540 has been updated by Angel Pons.
Even though bypassing Boot Guard is possible on Skylake, the ME on Broadwell
uses a completely different ISA for its CPU core (Skylake uses a mini-x86 core,
Broadwell and earlier use some ARCompact thing?). So backporting the bootguard
bypass thing
exposed the
flash contents to the chipset over LPC).
- It's likely this delay isn't needed for SPI because of all of this,
so let's consider skipping the delay for SPI. It's what most (but not
all) people use these flashrom for these days.
- Even if some non-SPI chips
Hi Brian, list,
Thanks for bringing this up on the mailing list.
On Wed, Apr 24, 2024 at 9:16 PM Brian Norris wrote:
>
> Background: https://review.coreboot.org/c/flashrom/+/80807
>
> A long time ago, in the pre-git times [1], flashrom added a 1 second
> delay to all verification, and claimed th
Hi Keith,
On Mon, Apr 15, 2024 at 12:49 AM Keith Hui wrote:
>
> What an eye opener.
>
> Yesterday I stumbled upon some boardviews for my board, and the pro
> variant. That could also let me sort out the pro's serial port without
> one actually on hand, but that's for another time.
Nice! Serial c
Hi Paul, list,
On Thu, Jun 8, 2023, 16:16 Paul Menzel wrote:
> [Annie, Yiwei, I only added you to Cc. It’d be great if you made sure
> that all involved people are subscribed to the coreboot mailing list.]
>
> Dear coreboot folks,
>
>
> Two server boards based on Intel Archer City board, commit
Issue #460 has been updated by Angel Pons.
akjuxr3 akjuxr3 wrote in #note-5:
> > The xNx naming scheme also doesn't work in the general case.
>
> I know. In x4x the best example is the Intel X48 chipset. Its not supported
> by coreboot. Reason for not supporting it is
Issue #455 has been updated by Angel Pons.
Have you tried running `sudo superiotool -d`? This should show the register
dump for the Nuvoton Super I/O on your board. The AST2400 detection procedure
is delusional (read random registers, if any returns non-zero then we have an
AST2400), so it
Issue #449 has been updated by Angel Pons.
https://review.coreboot.org/72806 fixes the UBSAN errors, please review. Note
that UBSAN-enabled coreboot still dies later on:
```
Loading module at 0x0003 with entry 0x0003. filesize: 0x178 memsize:
0x178
Processing 16 relocs. Offset value
Issue #449 has been updated by Angel Pons.
Assignee set to Angel Pons
Status changed from New to In Progress
Category changed from coreboot common code to board support
Looks like coreboot dies because UBSAN encounters a bug. Please disable UBSAN
and try again. Note that things like ASAN and
Issue #432 has been updated by Angel Pons.
File osboot_t440p_ifd_bin_is_also_borked.log added
Yes, it's definitely an osboot problem... Please report the issue to osboot
folks, and point them to this ticket.
After grabbing the T440p IFD.bin that osboot uses and using `util/ifdtool`&#
Issue #432 has been updated by Angel Pons.
*sigh* where is the "Edit" button?
Looks like the issue happens because something is messed up with the "ROM
size"...
```
flash size 0x280 bytes
SF: Detected 00 with sector size 0x1000, total 0x280
SF size 0x280
Issue #432 has been updated by Angel Pons.
Hmmm, looks like the issue happens because the MRC cache
Bug #432: t440p reboots on suspend
https://ticket.coreboot.org/issues/432#change-1215
* Author: Josh R
* Status: Response Needed
* Priority: Normal
Issue #432 has been updated by Angel Pons.
Affected hardware changed from Lenovo t440p to Lenovo ThinkPad T440p
Status changed from New to Response Needed
Hi, osboot is not the same as coreboot. Have you asked the people responsible
for osboot to provide support?
It would be great if you could
Issue #412 has been updated by Angel Pons.
Josh, could you please open a separate issue? Thanks.
Bug #412: x230 reboots on suspend
https://ticket.coreboot.org/issues/412#change-1204
* Author: Carson A.
* Status: New
* Priority: Normal
* Target version
Hi Richard,
Maybe it's not intentional, but your email sounds rather unpleasant
and very confusing. What would you like to achieve?
Also, out of curiosity, did you see
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/65BNRWRTKLTMS7EDOGCN2NJYIFX5QXBV/
before writing your rep
Hi all (again),
We (Angel) just took the time to reorder the previous replies so that
we can respond to them in-line.
On Mon, Oct 17, 2022 at 11:34 AM Richard Hughes wrote:
>
> On Mon, 17 Oct 2022 at 12:24, Edward O'Callaghan wrote:
> >
> > On Mon, 17 Oct 2022 at 20:27, Richard Hughes wrote:
>
Hi list,
We (Angel) sense that this thread might potentially drift towards an
unpleasant direction and we think the outcome wouldn't be
forward-useful, i.e. it would make things worse. How are all of you
doing? Is anyone feeling hurt?
On Sat, Oct 15, 2022 at 11:53 AM Nico Huber wrote:
>
> Hi all
Hi Sami,
On Sat, Oct 15, 2022 at 7:44 PM Sami via flashrom wrote:
>
> Is there anything I can do anymore?
See in-line messages.
> // Sami
>
> flashrom --programmer internal --ifd -i bios --noverify-all -w Z87A.bin
> flashrom v1.2 on Linux 5.10.0-18-amd64 (x86_64)
> flashrom is free software, ge
Issue #310 has been updated by Angel Pons.
Affected OS set to All (coreboot bug)
Affected hardware set to ThinkPad T440p
Status changed from Response Needed to Resolved
Bug #310: Coreboot 4.14 fails on a Lenvovo T440p
https://ticket.coreboot.org/issues
Issue #427 has been updated by Angel Pons.
Hi,
Yes, the EC should be reset by unplugging all power supplies, as it loses
power. The RTC/CMOS battery shouldn't matter, but it would be a good idea to
disconnect it as well if it's easy to do so.
---
Issue #427 has been updated by Angel Pons.
Could you please check if the "battery not charging" issues are still present
when *not* using any software to mess with the thresholds? To properly test,
please make sure the EC (Embedded Controller) gets reset: power off the laptop
and
Hi all,
On Tue, Oct 11, 2022 at 7:03 PM Angel Pons wrote:
>
> Hi Patrick,
>
> On Tue, Oct 11, 2022 at 6:43 PM Patrick Georgi wrote:
> >
> > "Angel Pons" schrieb:
> >
> > > We made the patches that made Coverity angry about this `format_pn()`
&
Hi Patrick,
On Tue, Oct 11, 2022 at 6:43 PM Patrick Georgi wrote:
>
> "Angel Pons" schrieb:
>
> > We made the patches that made Coverity angry about this `format_pn()`
> > function. However, this is not an actual bug: the
> > `eeprom_read_serial()` functio
Hi list,
We made the patches that made Coverity angry about this `format_pn()`
function. However, this is not an actual bug: the
`eeprom_read_serial()` function returns a buffer that is at most 32
(`HERMES_SN_PN_LENGTH`) characters long, and the length of the
`prefix` string is known at build-time
Hi all,
Having this documentation added to the flashrom Wiki sounds like a
great idea. Thank you for the proposal!
On Mon, Oct 10, 2022 at 12:11 PM Sergii Dmytruk
wrote:
>
> Hi Anastasia,
>
> On Mon, Oct 10, 2022 at 01:36:38PM +1100, Anastasia Klimchuk wrote:
> > I looked through the website, th
Hi Nils,
On Sun, Oct 2, 2022 at 9:25 PM Nils Woeste wrote:
>
> Hi, I encountered an Issue with flashing a BIOS and the message says
> "Get help on IRC at chat.freenode.net (channel #flashrom)"
>
> this points to an old server not monitored. The correct one (Libera.chat)
> should also be included
Issue #412 has been updated by Angel Pons.
I concur with Nico's assessment. I imagine you changed the "ROM chip size"
option to get a 4 MiB file to flash to the second flash chip (4 MiB).
Instead of doing that,
https://doc.coreboot.org/mainboard/lenovo/Ivy_Bridge_series.htm
flash writes or
> not? If not, who might know the answer?
>
These platforms should also support early writes, but it would be nice to
test them. I'd suggest making one change for each platform, so that it's
easier to keep track of the test status for each. I'll try to add review
e sort.
> Kind regards,
> Craft
>
> On Thu, Jul 21, 2022 at 3:59 AM Angel Pons wrote:
>>
>> Hi,
>>
>> On Thu, Jul 21, 2022 at 2:23 AM J. Craft wrote:
>> >
>> > Let me know if there's anything else needed and what might be suggested in
Hi,
On Thu, Jul 21, 2022 at 2:23 AM J. Craft wrote:
>
> Let me know if there's anything else needed and what might be suggested in
> this situation.
*snip*
> 0x84: 0x89ef09d0 PR0: Warning: 0x009d-0x009e is read-only.
flashrom errors out because this region is read-only. I'm pretty sur
Hi Andy,
On Tue, Jul 19, 2022 at 2:19 PM Andy Pont wrote:
>
> Ron wrote…
>
> >so how's it going?
> Slowly! The day job has got in the way a bit but I have been struggling
> to build the FSP binaries based on the instructions at [1]. I’m not
> sure whether that is down to me not fully understandi
Hi,
On Mon, Jul 18, 2022 at 8:34 AM Yu-Ping Wu via coreboot
wrote:
>
> Hi,
>
> There's an ongoing effort to expand vboot nvdata (nvstorage) from 16 to 64
> bytes [issue]. To reduce unnecessary complexity of our firmware code
> accessing nvdata, we'd like to drop 16-byte nvdata support from the
Issue #318 has been updated by Angel Pons.
Status changed from Response Needed to Resolved
Marked as resolved, I don't know if backports are done yet.
Bug #318: denverton_ns: Fix MRC cache write
https://ticket.coreboot.org/issues/318#change-967
* A
Hi Benjamin,
On Wed, Jun 15, 2022 at 9:23 PM Benjamin Doron
wrote:
>
> Hi all,
> `src/soc/intel/skylake/irq.c:soc_irq_settings()` dereferences NULL by
> memcpy'ing devintconfig to params->DevIntConfigPtr. As far as I can tell,
> this happens because we're copying a structure onto a UPD that's a
Hi Arthur, list,
On Sun, May 15, 2022 at 6:56 PM Arthur Heymans wrote:
>
> Hi
>
> To make sure headers don't create conflicts, guards are added to all of them.
> But the guard needs to be correct: e.g.
> https://review.coreboot.org/c/coreboot/+/64360/2
> Most compilers implement '#pragma once '
Hi Petr,
On Sun, Apr 24, 2022 at 7:33 AM Petr Cvek wrote:
>
> Hello again :-D,
>
> I'm working on a code for a simultaneous use of IGD (GMA950) and x16 PCIe
> slot GPU. I've made some success, but the code which handles the IGD
> initialization is really weird.
If your PCIe device is a graphic
Hi,
On Sat, Apr 23, 2022 at 11:37 AM Peter Stuge wrote:
>
> Martin Butt wrote:
> > Do you know if Coreboot would work on either of these systems?
> ..
> > Both the 3290 and the 3030 CPUs are a Intel Celeron N2807 1.58GHz
>
> That's the CPU marketing name which in firmware like coreboot doesn't
>
Hi Lahfa Samy,
I was a GSoC student in 2020. I had already been a coreboot
contributor for some time, so I came up with a project idea of my own:
add support for Intel Bay Trail to libgfxinit (see
https://blogs.coreboot.org/blog/2020/08/31/gsoc-libgfxinit-add-support-for-bay-trail/
for details). I
Hi Charles,
On Tue, Mar 8, 2022 at 2:13 PM Charles Parent
wrote:
> Hello,
>
> First thank you a lot for your amazing work on flashrom, I just discovered
> this software and it saved me a lot of time lately !
>
> I use it to flash a MT25QU256 through a FTDI4233H, and as software is
> telling me t
Hi,
On Wed, Jan 26, 2022 at 10:06 AM Jd Lyons via flashrom
wrote:
>
> What is the correct command to run flashrom for Promise ATA chipsets?
>
> Flashrom —programmer atapromise doesn’t work.
The atapromise programmer isn't compiled in by default. I'm pretty
sure it's because it cannot be used as
Hi,
On Sun, Jan 23, 2022 at 9:49 AM Mike Banon wrote:
>
> Good day! The flashrom software has the "internal" mode - using which,
> you may be able to access the BIOS chip directly from your OS, if your
> hardware is supported. In example:
>
> sudo flashrom -p
> internal:laptop=force_I_want_a_bric
Hi,
On Mon, Jan 24, 2022 at 8:26 AM Ganesh Kumar C via coreboot
wrote:
>
> Hi MariuszX,
>
>
> Thanks for you time .
>
>
> Yes . I have added the below memoryDownConfig struct in
>
> src/mainboard/intel/harcuvar/romstage.c file .
>
> const MEMORY_DOWN_CONFIG mMemoryDownConfig = {
> .SlotS
Hi Jeff,
On Fri, Jan 7, 2022 at 5:13 AM Jeff Daly wrote:
>
> Another thing I'd like to say (and it's probably pretty obvious once the
> majority of the commits start coming through) is that a lot of work has been
> done for this. In order to make the commit chunks more logical in their
> grou
Hi Billy,
On Tue, Dec 7, 2021 at 8:23 AM Billy Croan wrote:
>
> I've been tasked with updating bioses on some machines we have which have no
> manufacturer support. They were made by Quanta I think, as part of
> OpenCompute project. I have several boards that area all physically the
> same,
Hi list,
On Mon, Dec 6, 2021 at 7:37 AM Jianjun Wang wrote:
>
> On Sat, 2021-12-04 at 20:53 +0800, Hung-Te Lin wrote:
> > On Wed, Dec 1, 2021 at 10:08 PM Patrick Georgi
> > wrote:
> > > 1. Dezember 2021 12:06, "Paul Menzel"
> > > schrieb:
> > > > If I remember correctly, coreboot’s goal to only
Hi Branden,
On Mon, Nov 29, 2021 at 9:18 PM Branden Waldner wrote:
>
> I wasn't really sure that I wanted to comment on this, but seeing as
> how I have some of the affected boards I guess I should.
Thank you very much.
> Angel Pons wrote:
> > Besides AMD AGESA boards
Hi Pedro,
On Fri, Nov 26, 2021 at 11:02 PM Pedro Erencia wrote:
>
> Hi,
>
> I'm thinking about porting coreboot to a FM2A88X Extreme4+ board. This board
> has a DIP8 flash with a socket and I wondered what would be the best way to
> do an efficient development cycle. Ideally, I suppose that the
Hi Mike,
I typically don't indulge in mailing list drama, but I'm sick and
tired of seeing people waste their time and energy along with others'.
This is not the first time I've seen something like this: something
similar happened about two years ago when other AMD boards (KGPE-D16
and KCMA-D8, am
Hi Mickaël,
On Tue, Nov 23, 2021 at 11:29 AM Master wrote:
>
> Hello everyone,
>
> I hope you're doing fine
>
> I would like to do some trials to see if I may be able to support few boards
> I have cause they are aftermarket withoout EFI and without firmware updates
> and not working as I would
Hello,
On Thu, Nov 4, 2021 at 8:58 AM Simon Newton wrote:
>
> Hi there
> Yes it does. Rename mrc.bin to mrc.elf
Yes, the latest Bay Trail MRC binaries are ELF files, so their entry
point is not at the beginning of the file. MRC's position in flash
needs to be adjusted accordingly using the data
Hi Bernd,
On Tue, Nov 2, 2021 at 12:08 PM bernd...@web.de wrote:
>
> Hi. Just to ensure I don't go in the wrong direction: If I follow these
> instructions https://doc.coreboot.org/tutorial/part1.html do I install
> coreboot with OpenBIOS (because I've read something with SeaBIOS or so)?
These
Hi ___ (hmmm, I don't
think this is your name),
On Tue, Nov 2, 2021 at 11:19 AM bernd...@web.de wrote:
>
> Hi. I follow these instructions:
>
> https://doc.coreboot.org/tutorial/part1.html
>
> I'm on Step 5 - Configure the build > Check your configurati
Hi Rob,
On Sun, Oct 31, 2021 at 10:18 PM David Hendricks
wrote:
>
> On Sun, Oct 31, 2021 at 10:10 AM Rob Shore wrote:
>>
>> Hello!
>>
>> I've just discovered Flashrom as a way to use a Dediprog SPI programmer with
>> MacOS, which is awesome. I've got a bit of a strange question though:
>>
>> I
Hi Matt, list,
On Wed, Sep 8, 2021 at 3:29 PM Matt B wrote:
>
> Would an Ivybridge CPU even be expected to work with RDIMMs? Was this
> something anticipated when native raminit was written?
I don't think so. RDIMMs have higher latencies and very likely exceed
the maximum value that can be prog
Hi Stefano, Keith, list,
On Thu, Aug 19, 2021 at 10:17 PM Keith Emery
wrote:
>
> I think you meant to ask if it's possible to do. That can't be answered
> without more information about the hardware... A lot more.
>
> At a minimum the precise model of mainboard, or a precise model number.
>
> On
Hi Nico, Sven,
On Fri, Jun 11, 2021 at 9:19 AM Nico Huber wrote:
>
> Hi Sven,
>
> On 11.06.21 00:55, Sven Semmler wrote:
> > On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install,
> > I see these error messages when turning on the PC:
> >
> > mce: [Hardware Error]: CPU 0: Machine
Hi Branden, list,
On Tue, Jun 1, 2021 at 2:10 AM Branden Waldner wrote:
>
> The LTO patches seem to both compile and work/boot for me on the p2b.
>
> I built it both on a debian sid x86_64 system and on the gentoo i686
> setup I currently have for the p2b, both with the coreboot
> crossgcc-i386 t
Hi,
On Thu, May 27, 2021 at 10:05 AM Patrick Georgi wrote:
>
> For that reason I created https://review.coreboot.org/c/coreboot/+/55010 and
> https://review.coreboot.org/c/coreboot/+/55011 that retarget IRC links to
> libera.chat, promote the Matrix bridge and the Discord presence.
Last link d
Hi list,
On Thu, May 27, 2021 at 12:39 AM Stefan Reinauer
wrote:
>
> On Tue, May 25, 2021 at 6:01 AM Patrick Georgi via coreboot
> wrote:
>>
>> Hi everybody,
>>
>> you might have heard that freenode.org recently changed management under
>> weird circumstances. Given that we use their services f
Hi,
On Fri, May 14, 2021 at 7:38 PM lain via coreboot wrote:
>
> Probing for ITE Super I/O (init=standard) at 0x2e...
> Failed. Returned data: id=0x8613, rev=0x8
superiotool doesn't know about the IT8613E, but looks like there's one.
Best regards,
Angel
___
Hi Patrick, list,
On Mon, Apr 26, 2021 at 3:12 PM Patrick Georgi via coreboot
wrote:
>
> Hi everybody,
>
> This email starts the release process for coreboot 4.14, so we're now at the
> "~2 weeks prior to release" step in our
> https://doc.coreboot.org/releases/checklist.html
>
> As usual, our
Hi Peter, list,
On Mon, Apr 12, 2021 at 12:06 PM Peter Stuge wrote:
>
> ppbruhuwu--- via coreboot wrote:
> > Hello so i was talking to my friend about coreboot but i saw that
> > only the SFF version of the compaq 8200 was compatible and so i
> > wanted to know why that is?
>
> Those adding that
Hi Andrew, list
On Tue, Apr 6, 2021 at 6:52 PM Andrew A. I. wrote:
>
> Hello, Elyes!
> After "Convert to ASL 2.0 syntax" set of commits to current coreboot branch,
> i lost the data of battery current on BAT state from:
> cat /sys/class/power_supply/BAT0/current_now
> 0
> On AC state (charging)
Hi Andrew,
On Fri, Feb 5, 2021 at 6:06 PM Andrew Luke Nesbit
wrote:
>
> On 04/02/2021 09:41, Angel Pons wrote:
> > Hi Andrew,
>
> Hi Angel,
>
> Thanks for the reply.
>
> > On Wed, Feb 3, 2021 at 11:46 PM U'll Be King Of The Stars
> > wrote:
>
Hi Andrew,
On Wed, Feb 3, 2021 at 11:46 PM U'll Be King Of The Stars
wrote:
>
> - Intel D410PT (doesn't seem to be in current source tree)
The D410PT and the D510MO use the same code. Support was added in
https://review.coreboot.org/2 (which merely renames the Kconfig
option).
Best regard
Hi list,
I'm writing this email because there's one thing I always forget
about. Now that I am sure about it, I would like to write it down
somewhere so that I can't forget about it anymore. Anyway, that one
thing is:
On Intel memory controllers, one QCLK (Quadrature Clock) equals one
half of a f
Hi Peter,
On Tue, Jan 12, 2021 at 6:15 PM Peter Mueller wrote:
>
> https://pasteboard.co/JJknICr.jpg
Ah, I see it: it's on the top right quadrant next to the USB
connector. That gray thing is a socket, and should contain the flash
chip we're looking for. Lucky you! With the flash chip in a socke
Hi Peter,
On Tue, Jan 12, 2021 at 4:26 PM wrote:
>
> Hello coreboot community,
>
> as an open source fan I recently get to know coreboot and really like the
> idea behind.
> Sadly I bought my computer HW before learning more on libre friendly hardware
> that
> respects your freedom. Now I try t
Hi,
On Tue, Jan 12, 2021 at 11:24 AM Alif Ilhan wrote:
>
> Thank you. I will make sure it will not happen. But can anyone tell me where
> can I find MRC.bin from pineview? Which chromebook specifically?
Pineview Chromebooks did not use coreboot, so there's no MRC.bin to
use with coreboot. In an
Hi list,
Since register fields usually have more than one bit, I prefer to
always use explicit shifts for consistency. The one case where I
prefer the BIT() macro is to reduce the amount of nested braces when
testing for individual bits in a mask. GCC encourages adding
unnecessary braces for expre
ease. If there
is interest in maintaining support for these platforms beyond the next
release,
please ensure that the platforms are fixed to conform to the
expectations of resource
allocation.
Best regards,
Angel Pons
OpenPGP_0x53C88CBFBC4F65F3.asc
Descrip
Hi Andy
On Wed, Nov 18, 2020 at 1:22 PM Andy Pont wrote:
>
> Angel wrote...
>
> I can’t match what is printed on the top of the Micron devices (two lines of
> text “0JE75” and “D9ZFW”) to any part numbers on Micron’s website. Is it some
> kind of encoded version of the part number or is it just
Hi,
On Wed, Nov 18, 2020 at 10:00 AM Andy Pont wrote:
>
> Naresh wrote…
>
> Don't know how to recover SPD from UEFI but Try to read memory part number
> written on chip and provide that. Look for SPD file with that name if it's
> already present in coreboot.
>
> The schematics for the platform
Hello again,
Given that there's still some activity going on regarding deprecations
on the release notes, the release may be delayed one or two more days
to let things settle down, but no more. I look into having the release
done this week, but I'd also like to proceed without rushing as it's
my f
Hi Dario,
On Sun, Nov 15, 2020 at 5:42 PM wrote:
>
> Hi guys
> Thanks a lot for the great work on coreboot.
>
> I'm looking for install coreboot on my "HP-Compaq 8200 Elite SFF", so
> I was happy to found your site:
> https://doc.coreboot.org/mainboard/hp/compaq_8200_sff.html
>
> In this document
Hi again,
About a week ago, I announced our plans to do a new coreboot release,
which is scheduled to take place next Wednesday, November 18. This
means we're currently at the "~1 week prior to release" point of our
release checklist (at
https://doc.coreboot.org/releases/checklist.html).
To this
Hi Andy, Naresh,
On Wed, Nov 11, 2020 at 5:10 PM Andy Pont wrote:
>
> Naresh wrote…
>
> Looking at kconfig, the mainboard should select MAINBOARD_HAS_LIBGFXINIT.
> For example see "grep -rsn MAINBOARD_HAS_LIBGFXINIT src/"
>
> I haven't used this, so not sure what else might be needed.
>
> In or
Hi Werner, Ron, Nico, list,
While it would be great to not have to implement Bus Master
workarounds in coreboot, I guess it's sometimes unavoidable because of
external constraints. I would much prefer to have the actual problem
fixed instead (code assuming Bus Master is enabled by default), but if
Hi,
On Mon, Nov 9, 2020 at 6:42 PM wrote:
>
> Hello! I'm trying to find if my hardware supports Coreboot. I found 1 table
> which is retired, second that is probably not retired and then current
> documentation that doesn't seem to say as much. So, sorry if I missed it.
> Will Coreboot work wi
se take a look at the preliminary release notes in
Documentation/releases/coreboot-4.13-relnotes.md and add whatever
happened since 4.12 that is worth mentioning. If unsure, simply push a
change to Gerrit and have your fellow developers discuss it.
Thanks,
Angel Pons
___
Hi list,
On Wed, Oct 28, 2020 at 10:17 PM Julius Werner wrote:
> Okay, fair enough. Angel commented on the CL that this email thread
> needs to get resolved before the patch can land, so I wanted to try to
> help resolve it.
No, I never said that. I merely pointed out that discussion was taking
out which distros shipping flashrom are using,
> either the make-based version or the meson-based version. That might
> help you make up your mind.
It is very simple: the `-o` command-line option is unusable on the
distributions which have switched to meson to build flashrom.
> Ri
Hi list,
On Thu, Oct 15, 2020 at 5:48 PM Clay Daniels wrote:
>
> Paul, you are probably way ahead of this, but I found something pre-AGESA
> from 2003 that says:
>
> "Unlike minicomputer systems, the IBM PC was not designed to use a serial
> console. This has two consequences.
>
> Firstly, Powe
Hi Matej,
On Sun, Oct 4, 2020 at 7:37 AM Matej Voľanský
wrote:
>
> Hello,
> I have P8H61-m LX2 in my desktop right now. I want to switch from Win10 to
> Arch Linux and thought about also switching to coreboot. Unfortunately, I
> can’t find this MBO in your board status. There’s P8H61-m LX, LX3
Hi Clay,
On Sun, Sep 27, 2020 at 8:23 PM Clay Daniels wrote:
>
> Looking for schematic for:
> MSI X570-A PRO (MS-7C37)
>
> Ivan Ivanov pointed out a very nice detailed view which I could not find in
> MSI marketing propaganda, and it looks like I will need to use a CH341A
> external programmer.
Hi,
On Thu, Sep 17, 2020 at 2:50 PM Michal Zygowski
wrote:
>
> Hi,
>
> Please check out also this guide:
> https://www.coreboot.org/Git#Pushing_changes
>
> you need to tell git where to push: `HEAD:refs/for/master`. It seems the
> guide on https://doc.coreboot.org/tutorial/part2.html is missing o
Hi list,
On Wed, Sep 9, 2020 at 9:07 PM Clay Daniels wrote:
>
> Congrats, Aspen. I have a MSI X570-A PRO (MS-7C37) Motherboard and trying to
> get flashrom v1.2 on FreeBSD 13.0-CURRENT to recognize my mb. Looking at the
> supported hardware at https://www.flashrom.org/Supported_hardware I don't
Hi all,
That coreboot fork does not automate the process of obtaining mrc.bin
at all. Instead, it contains a disassembled/decompiled version of MRC
and uses that instead. I would not recommend using that fork because
it's outdated. On coreboot master, there's
https://review.coreboot.org/43559 whic
Dear mailing list,
I've been asked in https://review.coreboot.org/42134 to please start a
discussion on the mailing list about the naming convention of the
functions I've added in said patch.
I decided to use `unset_and_set` because that's what libgfxinit uses.
In coreboot, we already have `clrse
> 2. devicetree.cb
>
> 3. gpio.h (SATAXPCIE1 detect)
It would be nice to see which changes are needed. This would be very
easy if the code were public, e.g.: upstream or on review.
> Thanks a lot for your help on any of these issue.
&g
Hi Stephen,
On Tue, Aug 4, 2020 at 12:51 PM Stephen Wong wrote:
>
> Hello guys
>
> i have a laptop equipped with GIGADEVICE chip, attached the photo for
> the ram chip
I don't see any RAM chip in the picture. That GigaDevice chip is a
flash chip, though. Looks like it's a 512 KiB (kibibytes) par
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