Hello John, On Mon, Aug 17, 2020 at 11:31 PM john brown <john.brown89...@mail.com> wrote: > > Our new board has intel skylake I3-6100U CPU, BIOS use coreboot based on > kabylake RVP7 > it can boot linux OS successfully. but there are two issues:
Which mainboard do you have? *Is* your board an Intel Kaby Lake RVP7 reference board? If not, then it's expected that things don't work properly with a RVP7 image. > 1. > > intel Ethernet PHY I211 connected on I3-U6100 PCIE lane 1, I211 is not > shown in lspci. > > and serial port log: > > PCI: 00:1c.0 scanning... > do_pci_scan_bridge for PCI: 00:1c.0 > PCI: pci_scan_bus for bus 01 > POST: 0x24 > POST: 0x25 > POST: 0x55 > scan_bus: scanning of bus PCI: 00:1c.0 took 12591 usecs > > ------------------------------------------ > > In our previous version board, I211 is on PCIE lane 5, which is shown in > lspci and works fine. and serial port log: Sounds like you have custom mainboards. Instead of using a RVP image on them, I would recommend adding support for your boards to coreboot. You can even use the variants mechanism to account for differences between revisions. You can use https://doc.coreboot.org/tutorial/part2.html as a guide to submit patches upstream for review. Feel free to add me as a reviewer there. > PCI: 00:1c.0 scanning... > do_pci_scan_bridge for PCI: 00:1c.0 > PCI: pci_scan_bus for bus 01 > POST: 0x24 > PCI: 01:00.0 [8086/1539] enabled > POST: 0x25 > POST: 0x55 > Capability: type 0x01 @ 0x40 > Capability: type 0x05 @ 0x50 > Capability: type 0x11 @ 0x70 > Capability: type 0x10 @ 0xa0 > Capability: type 0x10 @ 0x40 > Enabling Common Clock Configuration > PCIE CLK PM is not supported by endpoint > ASPM: Enabled L1 > Capability: type 0x01 @ 0x40 > Capability: type 0x05 @ 0x50 > Capability: type 0x11 @ 0x70 > Capability: type 0x10 @ 0xa0 > Failed to enable LTR for dev = PCI: 01:00.0 > scan_bus: scanning of bus PCI: 00:1c.0 took 56231 usecs > > 2. > > A m.2 sata on pcie lane 11(sata 1B) doesn't work(not shown on lsblk). On the > previous version board, sata is on PCIE lane 8 (1A) and works fine. This is probably due to misconfigured settings, and related to the NIC problems. From what you've explained, looks like the new board revision uses different HSIO lanes, so the configuration needs to be adjusted accordingly. As explained before, adding support for your boards is probably the best option. > The following 3 files are changed for this new board from the previous > version board . > > 1.IFWI configuration file settings, > > 2. devicetree.cb > > 3. gpio.h (SATAXPCIE1 detect) It would be nice to see which changes are needed. This would be very easy if the code were public, e.g.: upstream or on review. > Thanks a lot for your help on any of these issue. > > John > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
