[USRP-users] x410/RFNoC xsim simulation support pertaining to rfnoc, x410, and system verilog.
Is there documentation that declares which simulations are not supported by xsim? I have used build.py to produce modules.json. I also found a git issue that states the qsfp wrapper simulation is not supported for xsim. Can you provide any details on the system verilog constructs that are utilized within the codebase that are incompatible with xsim? Thank you, Andrew ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: x410 RFNOC Endpooint YAML Configuration
Wade, Thank you very much for the detailed explanation. On Fri, Nov 1, 2024 at 10:35 AM Wade Fife wrote: > Hi Andrew, > > This is true of all RFNoC images. The "ctrl" setting refers to whether or > not that endpoint has a connection to the control crossbar, which is used > for sending control packets (e.g., register reads/writes) to/from RFNoC > blocks. Because you can send control packets to any RFNoC block from any > control port master, you only need one endpoint with a control port to be > able to do control communication with all the RFNoC blocks. So you have to > have at least one endpoint with a control port and having more than one > wastes logic because currently only the first one will be used. > > Wade > > On Thu, Oct 31, 2024 at 9:24 AM Andrew D wrote: > >> It appears that in all of the x410 and x440 image core yaml files, that >> EP0 is the only endpoint that is configured with `ctrl:True`. Is this >> necessary and why is EP0 the only endpoint that requires control? >> >> Thank you! >> Andrew >> ___ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-le...@lists.ettus.com >> > ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] X310 clock signal for aliasing (BasicRX daughter board)
I am investigating chopping a signal with a fast track and hold to bring a microwave signal to baseband without relying on a mixer (I can explain why if needed but I'll skip this background part for the moment). To achieve this result I would like to fit a BasicRX board installed in a X310 with a HMC760 [1] evaluation board, clocking the latter with the signal driving the ADC in order to use the upper Nyquist zones and aliasing on purpose. My questions: * I am confused between https://files.ettus.com/schematics/x300/x3xx.pdf page 4 which shows pin 11 of J3 as DB0_RX_CLK and pin13 which seems to be grounded (if I interpret the symbol correctly), and https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf which seems to connect J2 pin 11 to clk_p and pin 13 to clk_n leading to J38 pins 2 and 3 I am connecting to => is this clock a balanced (differential) or unbalanced signal? Connecting 11-13 of the BasicRX to a Minicircuits T1-1T balun and watching the output signal is not very convincing, but neither is connecting a RF probe to pin 11 either, so I am confused with this signal (signal visible when the X310 is idle, a bit more noisy when the X310 is running an acquisition flowgraph) * I understand that the X310 is sampling at 200 MS/s, but it seems that this clock signal I am looking at is 100 MHz. Am I looking at the right signal for aliasing a signal synchronously to the sampling, or should I be looking elsewhere? Thanks, best wishes, Jean-Michel [1] https://www.analog.com/media/en/technical-documentation/data-sheets/hmc760.pdf ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: X310 clock signal for aliasing (BasicRX daughter board)
On 20/12/2024 13:44, frie...@free.fr wrote: I am investigating chopping a signal with a fast track and hold to bring a microwave signal to baseband without relying on a mixer (I can explain why if needed but I'll skip this background part for the moment). To achieve this result I would like to fit a BasicRX board installed in a X310 with a HMC760 [1] evaluation board, clocking the latter with the signal driving the ADC in order to use the upper Nyquist zones and aliasing on purpose. My questions: * I am confused between https://files.ettus.com/schematics/x300/x3xx.pdf page 4 which shows pin 11 of J3 as DB0_RX_CLK and pin13 which seems to be grounded (if I interpret the symbol correctly), and https://files.ettus.com/schematics/basic_dbs/BasicRX.pdf which seems to connect J2 pin 11 to clk_p and pin 13 to clk_n leading to J38 pins 2 and 3 I am connecting to => is this clock a balanced (differential) or unbalanced signal? Connecting 11-13 of the BasicRX to a Minicircuits T1-1T balun and watching the output signal is not very convincing, but neither is connecting a RF probe to pin 11 either, so I am confused with this signal (signal visible when the X310 is idle, a bit more noisy when the X310 is running an acquisition flowgraph) * I understand that the X310 is sampling at 200 MS/s, but it seems that this clock signal I am looking at is 100 MHz. Am I looking at the right signal for aliasing a signal synchronously to the sampling, or should I be looking elsewhere? Thanks, best wishes, Jean-Michel [1] https://www.analog.com/media/en/technical-documentation/data-sheets/hmc760.pdf ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com My understanding is that the clock signal fed to the daughter-cards is typically some fraction of the master_clock frequency, and is designed to provide a REF signal for synthesizers, etc. It should be synchronized to the ADC clocks, but won't necessarily be at the same frequency. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: x410/RFNoC xsim simulation support pertaining to rfnoc, x410, and system verilog.
Hi Andrew, All of the testbenches that have a Makefile should work with XSim except for the ones listed in this file: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/tools/utils/testbenches.excludes And all of the testbenches that have a Makefile should work in ModelSim except for the ones listed in this file: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/tools/utils/modelsim.excludes There aren't specific constructs I'm aware of in the code that aren't supported by XSim. Most of the testbenches were written for one simulator or the other, and not always ported to the other simulator when it didn't just work as written. In some cases that might be because XSim didn't implement something correctly, but it could also be because of normal differences between simulators (e.g., non-deterministic execution of processes). It depends on the testbench. In general, if you want to know what constructs are supported by XSim, check out UG900, the Vivado Design Suite User Guide for Logic Simulation. Thanks, Wade On Fri, Dec 20, 2024 at 6:03 AM Andrew D wrote: > Is there documentation that declares which simulations are not supported > by xsim? I have used build.py to produce modules.json. I also found a git > issue that states the qsfp wrapper simulation is not supported for xsim. > Can you provide any details on the system verilog constructs that are > utilized within the codebase that are incompatible with xsim? > > Thank you, > Andrew > ___ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: RFNOC 4 equivalent of clear_tx_seqnum
RFNoC 4 tries to do this automatically at the start of a session. When UHD initializes a block, it will try to flush all of its FIFOs to clear any data from the previous session. There's no equivalent to clear_tx_seqnum. I suggest letting UHD do its thing and see if that's sufficient for your needs. Thanks, Wade On Fri, Dec 20, 2024 at 1:39 AM wrote: > Hi > > > In our RFNOC3 system we used clear_tx_seqnum to clear the input FIFOs of > our system when the application started. However I believe it was for > AXI_Wrapper and this was a useful side-effect? > > > What can we do in RFNOC4 to achieve the same functionality? > > > Thanks > ___ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
