Re: [USRP-users] USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Hi,

I am allowed to do that, but how am I able to do that using ISE 14.7 together 
with the USRP B210?

Thanks in advance!

From: Ian Buckley [i...@ionconcepts.com]
Sent: 07 April 2018 03:19
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] USRP B210

Making a hardware DDS to generate a chirp in the FPGA is easy, extremely so if 
you reuse the Ettus code that interfaces the B210 to AD3961 with correct timing.
What is very hard in what you propose, is controlling the AD9361 from within 
the FPGA without an external host. There is a *lot* of configuration 
functionality that needs to be captured.
Are the constraints of your project such that you are not allowed to have a 
host connected to USB?


On Apr 5, 2018, at 7:57 PM, Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:



From: Yeo Jin Kuang Alvin (IA)
Sent: Friday, 6 April 2018 10:55 AM
To: 'Neel Pandeya'
Subject: RE: [USRP-users] USRP B210

Hi Neel,

I am trying to output a chirp signal by creating a DDS in the FPGA using Xilinx 
ISE 14.7. The code is done from scratch and created a SPI module in the FPGA to 
control the AD9361 to output the signal. Set up the constraints file gotten 
from ettus research in git.

This are my usual steps:
1)  uhd_usrp_probe  - -args=”master_clock_rate=40e6”   (I am setting to 
40MHz as I am using the codec_main_clk in the AD9361 as my main clock, not sure 
if this is right but simulation/chipscope seems fine )
2)  Opened Xilinx ISE 14.7
3)  Generate .bit file
4)  Run on IMPACT using JTAG cable
5)  Program the file

But I couldn’t get any signal out from the transmitter, there is no software 
C++ or GNU Radio involve. Just solely on FPGA  as I am task to create a chirp 
signal using FPGA. I might have missed out something, like configuration or 
concept is not right. Just not sure where and how.

Thank you in advance!


From: Neel Pandeya [mailto:neel.pand...@ettus.com]
Sent: Friday, 6 April 2018 10:34 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] USRP B210

Hello Yeo Jin Kuang Alvin:
If you're modifying the FPGA, then there will likely be a corresponding 
modification needed on the host-side, especially for something as significant 
as starting a transmit stream and/or controlling the AD9361 in some way. We'll 
need much more detail in order to be able to help further. What changes did you 
make to the FPGA? What exactly are you trying to do overall?

--​Neel Pandeya


On 5 April 2018 at 18:07, Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:
Hi everyone,

I have tried to program the Spartan 6 FPGA using Xilinx 14.7 to send out a 
signal and to control the AD9361. However, I couldn’t get an output out from 
the transmitter. Can I just solely on FPGA or must I use the API for the USRP 
B210? What are the steps and procedures I have to do to configure the board, I 
just feel that I might miss out some important steps.

Thank you in advance!

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[USRP-users] Ettus Code (FPGA) for USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Hi everyone,

I want to use the ettus code for the USRP B210, however, may I know which is 
the Top file as I noticed there are 3 different ones. B200.v , B200_core.v , 
B200_io.v. Tried to add the source file to Xilinx ISE 14.7 but there are some 
files that I couldn't find, eg. Gpif_sync, slave_fifo32, uart_timing_fifo etc.

What are the essentials file and where do I find it?

Thanks in advance!
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Re: [USRP-users] Ettus Code (FPGA) for USRP B210

[Marcus D. Leech via USRP-users]

On 04/08/2018 10:59 PM, Yeo Jin Kuang Alvin (IA) via USRP-users wrote:


Hi everyone,

I want to use the ettus code for the USRP B210, however, may I know 
which is the Top file as I noticed there are 3 different ones. B200.v 
, B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE 
14.7 but there are some files that I couldn’t find, eg. Gpif_sync, 
slave_fifo32, uart_timing_fifo etc.


What are the essentials file and where do I find it?

Thanks in advance!



There is a directory called "top":

And under that is a subdirectory callled "B200":

uhd/fpga-src/usrp3/top/b200

That is the top-level for the B200, and there's a Makefile in there that 
you'll need to run:


make PROJECT_ONLY=1

which will generate a project file for the ISE GUI.

Note that Ettus don't use the ISE GUI environment for doing builds, 
which is why there are makefiles that are used to produce a consistent and
  reliable build process, with all the dependencies fully described, 
etc.  It's the only sensible way to do FPGA production builds.



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Re: [USRP-users] Ettus Code (FPGA) for USRP B210

[Robin Coxe via USRP-users]

B200.v is the top level Verilog file.  If you inspect this file, you will
see that B200_core.v and B200_io.v are instantiated within it.

All of our FPGA code is freely available-- please take some time to look
through the files in the usrp3/lib directories here: https://github.com/
EttusResearch/fpga/tree/maint/usrp3/lib

-Robin




On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi everyone,
>
>
>
> I want to use the ettus code for the USRP B210, however, may I know which
> is the Top file as I noticed there are 3 different ones. B200.v ,
> B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE 14.7
> but there are some files that I couldn’t find, eg. Gpif_sync, slave_fifo32,
> uart_timing_fifo etc.
>
>
>
> What are the essentials file and where do I find it?
>
>
>
> Thanks in advance!
>
> ___
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Re: [USRP-users] Ettus Code (FPGA) for USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Am I able to run make in Windows using Cygwin for ISE 14.7? I tried to run make 
PROJECT_ONLY=1 , and this is what I get.

$ make PROJECT_ONLY=1
/bin/sh: xtclsh: command not found
ISE Version:
make -f Makefile.b200.inc proj NAME=B200 DEVICE=XC6SLX75 EXTRA_DEFS=" "
make[1]: Entering directory 
'/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff

 6f1f9ae966edd531dc4b611d7/usrp3/top/b200'
/bin/sh: xtclsh: command not found
/bin/sh: xtclsh: command not found
build-B200//b200.xise
xtclsh 
/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff6f1f9ae966edd531dc4b61   

  
1d7/usrp3/top/tcl/ise_helper.tcl ""
/bin/sh: xtclsh: command not found
make[1]: *** [../Makefile.common:52: build-B200//b200.xise] Error 127
make[1]: Leaving directory 
'/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff6   

  f1f9ae966edd531dc4b611d7/usrp3/top/b200'
make: *** [Makefile:73: B200] Error 2

--

I ran source C:/Xilinx/14.7/ISE_DS/settings64.bat and I got this

$ source C:/Xilinx/14.7/ISE_DS/settings64.bat
-bash: @echo: command not found
-bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: syntax error near 
unexpected token `('
-bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: `REM Copyright (c) 
1995-201' Xilinx, Inc.  All rights reserved.


From: Robin Coxe [mailto:robin.c...@ettus.com]
Sent: Monday, 9 April 2018 11:16 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Ettus Code (FPGA) for USRP B210

B200.v is the top level Verilog file.  If you inspect this file, you will see 
that B200_core.v and B200_io.v are instantiated within it.

All of our FPGA code is freely available-- please take some time to look 
through the files in the usrp3/lib directories here: 
https://github.com/EttusResearch/fpga/tree/maint/usrp3/lib

-Robin




On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:
Hi everyone,

I want to use the ettus code for the USRP B210, however, may I know which is 
the Top file as I noticed there are 3 different ones. B200.v , B200_core.v , 
B200_io.v. Tried to add the source file to Xilinx ISE 14.7 but there are some 
files that I couldn’t find, eg. Gpif_sync, slave_fifo32, uart_timing_fifo etc.

What are the essentials file and where do I find it?

Thanks in advance!

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