[U-Boot] [PATCH] powerpc/pixis: Fix pixis help message
"pixis_reset help" command prints the message without a new line "\n", which makes the prompt on the same line. Signed-off-by: York Sun --- board/freescale/common/pixis.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 8d07061..577a542 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -552,5 +552,5 @@ U_BOOT_CMD( "pixis_reset [altbank]\n" "pixis_reset altbank wd\n" "pixis_reset altbank cf \n" - "pixis_reset cf " + "pixis_reset cf \n" ); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v2] powerpc/pixis: Fix pixis help message
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.
Signed-off-by: York Sun
---
board/freescale/common/pixis.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 8d07061..fbb709d 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -480,6 +480,7 @@ static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
|| unknown_param) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
+ putc('\n');
#endif
return 1;
}
@@ -512,6 +513,7 @@ static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
&& set_px_mpxpll(mpxpll))) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
+ putc('\n');
#endif
return 1;
}
--
1.7.9.5
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[U-Boot] [PATCH 07/11] powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff
When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0x together
with normal LAWs will guarantee the address is not mapped to DDR.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |4 ++--
arch/powerpc/cpu/mpc8xxx/ddr/main.c |8 +++-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 8c95cad..a6f8d95 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1588,8 +1588,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
| ((ea & 0xFFF) << 0) /* ending address MSB */
);
} else {
- debug("FSLDDR: setting bnds to 0 for inactive CS\n");
- ddr->cs[i].bnds = 0;
+ /* setting bnds to 0x for inactive CS */
+ ddr->cs[i].bnds = 0x;
}
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 7a8636d..c35405d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -504,7 +504,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
start_step,
fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
if (reg->cs[j].config & 0x8000) {
unsigned int end;
- end = reg->cs[j].bnds & 0xFFF;
+ /*
+* 0xfff is a special value we put
+* for unused bnds
+*/
+ if (reg->cs[j].bnds == 0x)
+ continue;
+ end = reg->cs[j].bnds & 0x;
if (end > max_end) {
max_end = end;
}
--
1.7.9.5
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[U-Boot] [PATCH 09/11] powerpc/mpc8xxx: Add x4 DDR device support
On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c|4 arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c |1 + arch/powerpc/cpu/mpc8xxx/ddr/interactive.c |4 arch/powerpc/cpu/mpc8xxx/ddr/options.c |2 ++ arch/powerpc/include/asm/fsl_ddr_dimm_params.h |1 + arch/powerpc/include/asm/fsl_ddr_sdram.h|1 + 6 files changed, 13 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index a6f8d95..3a63a04 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -684,6 +684,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int odt_cfg = 0; /* ODT configuration */ unsigned int num_pr;/* Number of posted refreshes */ unsigned int slow = 0; /* DDR will be run less than 1250 */ + unsigned int x4_en = 0; /* x4 DRAM enable */ unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ unsigned int ap_en; /* Address Parity Enable */ unsigned int d_init;/* DRAM data initialization */ @@ -728,6 +729,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, ap_en = 0; } + x4_en = popts->x4_en ? 1 : 0; + #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ d_init = popts->ECC_init_using_memctl; @@ -750,6 +753,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) | ((slow & 1) << 11) + | (x4_en << 10) | (qd_en << 9) | (unq_mrs_en << 8) | ((obc_cfg & 0x1) << 6) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 3e7c269..b67158c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -129,6 +129,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->ec_sdram_width = 0; pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; + pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); /* These are the types defined by the JEDEC DDR3 SPD spec */ pdimm->mirrored_dimm = 0; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index 46257c9..2bc3516 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -207,6 +207,7 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(primary_sdram_width), DIMM_PARM(ec_sdram_width), DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), DIMM_PARM(n_row_addr), DIMM_PARM(n_col_addr), @@ -265,6 +266,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(primary_sdram_width), DIMM_PARM(ec_sdram_width), DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), DIMM_PARM(n_row_addr), DIMM_PARM(n_col_addr), @@ -445,6 +447,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(twoT_en), CTRL_OPTIONS(threeT_en), CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), CTRL_OPTIONS(bstopre), CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), @@ -689,6 +692,7 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(threeT_en), CTRL_OPTIONS(registered_dimm_en), CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), CTRL_OPTIONS(bstopre), CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 2f13b8f..e02d76d 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -703,6 +703,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } #endif + popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; + /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) #if defined(CONFIG_E500MC) diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powe
[U-Boot] [PATCH 04/11] powerpc/t4qds: cleanup board header file
CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef. Signed-off-by: York Sun --- include/configs/t4qds.h | 68 --- 1 file changed, 68 deletions(-) diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 1032f12..3f7b82d 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -133,14 +133,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENABLE_36BIT_PHYS -#ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP64 /* number of TLB1 entries */ -#endif -#if 0 -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#endif #define CONFIG_SYS_MEMTEST_START 0x0020 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0040 #define CONFIG_SYS_ALT_MEMTEST @@ -151,10 +146,8 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_INIT_L3_ADDRCONFIG_RAMBOOT_TEXT_BASE -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf000 #define CONFIG_SYS_DCSRBAR_PHYS0xfull -#endif /* EEPROM */ #define CONFIG_ID_EEPROM @@ -192,11 +185,7 @@ unsigned long get_board_ddr_clk(void); * IFC Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS (0xfull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ @@ -248,11 +237,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#ifdef CONFIG_PHYS_64BIT #define QIXIS_BASE_PHYS(0xfull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYSQIXIS_BASE -#endif #define CONFIG_SYS_CSPR3_EXT (0xf) #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ @@ -275,11 +260,7 @@ unsigned long get_board_ddr_clk(void); /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_NAND_BASE 0xff80 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS (0xfull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif #define CONFIG_SYS_NAND_CSPR_EXT (0xf) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ @@ -380,18 +361,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd0 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ @@ -464,19 +439,11 @@ unsigned long get_board_ddr_clk(void); * RapidIO */ #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc2000ull -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa000 -#endif #define CONFIG_SYS_SRIO1_MEM_SIZE 0x1000 /* 256M */ #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc3000ull -#else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb000 -#endif #define CONFIG_SYS_SRIO2_MEM_SIZE 0x1000 /* 256M */ /* @@ -524,59 +491,32 @@ unsigned long get_board_ddr_clk(void); /* controller 1, direct to uli, tgtid 3, Base address 2 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 -#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 #define CONFIG_SYS_PCIE1_IO_BUS0x -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 -#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa
[U-Boot] [PATCH 01/11] powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h |5 + include/configs/B4860QDS.h|1 - include/configs/P2041RDB.h|1 - include/configs/corenet_ds.h |1 - include/configs/t4qds.h |1 - 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1009a31..057402b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -316,6 +316,7 @@ #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 @@ -350,6 +351,7 @@ #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 @@ -384,6 +386,7 @@ #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS32 @@ -430,6 +433,7 @@ #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS32 @@ -461,6 +465,7 @@ #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MAX_CPUS4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_LAWS32 diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c15bbd8..b5b7d08 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -40,7 +40,6 @@ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 9cd3a7c..f23b50a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -53,7 +53,6 @@ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 66c7b4f..590a4bc 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -58,7 +58,6 @@ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index aa90249..1032f12 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -41,7 +41,6 @@ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/11] drivers/fm: Fix compiling error if FW location is not defined
FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even remote. In case none of them is defined, set it to null. Signed-off-by: York Sun --- drivers/net/fm/fm.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 8d70586..0b1a8e5 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -409,6 +409,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; +#else + void *addr = NULL; #endif /* Upload the Fman microcode if it's present */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/11] powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/ddr-gen1.c |2 +-
arch/powerpc/cpu/mpc85xx/ddr-gen2.c |2 +-
arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 29 +++-
arch/powerpc/cpu/mpc86xx/ddr-8641.c |2 +-
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h |2 +-
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 54 ++
arch/powerpc/include/asm/fsl_ddr_sdram.h | 24 -
board/freescale/bsc9131rdb/ddr.c |2 +-
board/freescale/bsc9132qds/ddr.c |2 +-
board/freescale/common/qixis.c | 20 +++
board/freescale/corenet_ds/ddr.c |4 +--
board/freescale/p1010rdb/ddr.c |2 +-
board/freescale/p1_p2_rdb/ddr.c |2 +-
board/freescale/p1_p2_rdb_pc/ddr.c |2 +-
include/configs/T4240QDS.h |1 +
15 files changed, 130 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
index 8a86819..4dd8c0b 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
@@ -15,7 +15,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-unsigned int ctrl_num)
+unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index a705862..542bc84 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -16,7 +16,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-unsigned int ctrl_num)
+unsigned int ctrl_num, int step)
{
unsigned int i;
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 3e7a564..1be51d3 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -15,8 +15,18 @@
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-unsigned int ctrl_num)
+unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
volatile ccsr_ddr_t *ddr;
@@ -54,6 +64,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
return;
}
+ if (step == 2)
+ goto step2;
+
if (regs->ddr_eor)
out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
@@ -157,6 +170,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs,
out_be32(&ddr->debug[21], 0x2400);
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+ /*
+* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+* deasserted. Clocks start when any chip select is enabled and clock
+* control register is set. Because all DDR components are connected to
+* one reset signal, this needs to be done in two steps. Step 1 is to
+* get the clocks started. Step 2 resumes after reset signal is
+* deasserted.
+*/
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
index 92ba26d..33a91f9 100644
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
@@ -15,7 +15,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-unsigned int ctrl_num)
+unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 4dd55fc..c173a5a 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@
[U-Boot] [PATCH 05/11] powerpc/corenet: Move RCW print to cpu.c
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cpu.c | 23 +++
board/freescale/b4860qds/b4860qds.c | 15 ---
board/freescale/corenet_ds/corenet_ds.c | 17 +++--
board/freescale/p2041rdb/p2041rdb.c | 15 ---
board/freescale/t4qds/t4qds.c | 14 --
5 files changed, 22 insertions(+), 62 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6ce483e..d407373 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -60,10 +60,10 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if (defined(CONFIG_DDR_CLK_FREQ) || \
- defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif /* CONFIG_FSL_CORENET */
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
/*
* Cornet platforms use ddr sync bit in RCW to indicate sync vs async
@@ -227,6 +227,21 @@ int checkcpu (void)
puts("L1:D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
+#ifdef CONFIG_FSL_CORENET
+ /* Display the RCW, so that no one gets confused as to what RCW
+* we're actually using for this boot.
+*/
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+#endif
+
return 0;
}
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index a39c17a..8058c78 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -51,8 +51,6 @@ int checkboard(void)
char buf[64];
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- unsigned int i;
static const char *const freq[] = {"100", "125", "156.25", "161.13",
"122.88", "122.88", "122.88"};
int clock;
@@ -77,19 +75,6 @@ int checkboard(void)
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
- /* Display the RCW, so that no one gets confused as to what RCW
-* we're actually using for this boot.
-*/
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index 48f7155..22677a9 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -43,8 +43,10 @@ int checkboard (void)
{
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
+ defined(CONFIG_P5040DS)
unsigned int i;
+#endif
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
printf("Board: %sDS, ", cpu->name);
@@ -63,19 +65,6 @@ int checkboard (void)
else
printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
- /* Display the RCW, so that no one gets confused as to what RCW
-* we're actually using for this boot.
-*/
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
/* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers c
[U-Boot] [PATCH 11/11] powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c |8
arch/powerpc/cpu/mpc85xx/release.S| 15 +++
arch/powerpc/include/asm/config_mpc85xx.h |3 +++
4 files changed, 29 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 422782c..7db06ac 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -258,6 +258,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ puts("Work-around for Erratum A-005812 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index fd19d99..ca799ac 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -412,6 +412,14 @@ int cpu_init_r(void)
sync();
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ /*
+* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
+* in write shadow mode. Checking DCWS before setting SPR 976.
+*/
+ if (mfspr(L1CSR2) & L1CSR2_DCWS)
+ mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x8000));
+#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index a4a21b0..6af2efd 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -242,6 +242,21 @@ __secondary_start_page:
2:
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ /*
+* A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
+* write shadow mode. This code should run after other code setting
+* DCWS.
+*/
+ mfspr r3,L1CSR2
+ andis. r3,r3,(L1CSR2_DCWS)@h
+ beq 1f
+ mfspr r3, SPRN_HDBCR0
+ orisr3, r3, 0x8000
+ mtspr SPRN_HDBCR0, r3
+1:
+#endif
+
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
mfspr r3,SPRN_SVR
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 057402b..9370a89 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -383,6 +383,7 @@
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -429,6 +430,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004849
#define CONFIG_SYS_FSL_ERRATUM_A004580
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
@@ -491,6 +493,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf000
+#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS1
--
1.7.9.5
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[U-Boot] [PATCH 08/11] powerpc/t4240qds: Adjust DDR timing for RDIMM
RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.
Signed-off-by: York Sun
---
board/freescale/t4qds/ddr.h | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index cde0785..4f73285 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -64,16 +64,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2| ctl3 | |delay |
*/
- {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff,2, 0},
- {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff,2, 0},
- {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff,2, 0},
- {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff,2, 0},
- {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff,2, 0},
- {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff,2, 0},
- {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff,2, 0},
- {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff,2, 0},
- {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff,2, 0},
- {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff,2, 0},
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff,2, 0},
+ {4, 1666, 0, 5,11, 0x0a080706, 0x07090906, 0xff,2, 0},
+ {4, 2140, 0, 5,12, 0x0b090807, 0x080a0b07, 0xff,2, 0},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff,2, 0},
+ {2, 1666, 0, 5,11, 0x0a090806, 0x08090a06, 0xff,2, 0},
+ {2, 2140, 0, 5,12, 0x0b090807, 0x080a0b07, 0xff,2, 0},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff,2, 0},
+ {1, 1666, 0, 5,11, 0x0a090806, 0x08090a06, 0xff,2, 0},
+ {1, 2140, 0, 4,12, 0x0b090807, 0x080a0b07, 0xff,2, 0},
{}
};
--
1.7.9.5
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[U-Boot] [PATCH 03/11] mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun
---
README |5 +
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 ++
arch/powerpc/cpu/mpc85xx/ddr-gen3.c |7 +++
arch/powerpc/cpu/mpc85xx/fdt.c |6 +-
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |5 +
5 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/README b/README
index cd0336c..353d016 100644
--- a/README
+++ b/README
@@ -418,6 +418,11 @@ The following options need to be configured:
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
+ CONFIG_SYS_FSL_DDR_EMU
+
+ Specify emulator support for DDR. Some DDR features such as
deskew training
+ are not available.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4067f05..fd19d99 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -545,8 +545,10 @@ skip_l2:
enable_cpc();
+#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index c5b4720..3e7a564 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -123,10 +123,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs,
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+* Skip these two registers if running on emulator
+* because emulator doesn't have skew between bytes.
+*/
+
if (regs->ddr_wrlvl_cntl_2)
out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
if (regs->ddr_wrlvl_cntl_3)
out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 288f7b2..8072235 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -620,8 +620,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
+#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk(), 1);
+ "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+ 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 26c42f7..8c95cad 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1641,5 +1641,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
set_ddr_sdram_rcw(ddr, popts, common_dimm);
+#ifdef CONFIG_SYS_FSL_DDR_EMU
+ /* disble DDR training for emulator */
+ ddr->debug[2] = 0x0400;
+ ddr->debug[4] = 0xff80;
+#endif
return check_fsl_memctl_config_regs(ddr);
}
--
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Re: [U-Boot] [PATCH 06/11] powerpc/T4240EMU: Add T4240EMU target
On 06/25/2013 02:24 PM, Wolfgang Denk wrote: > > Entry to MAINTAINERS missing. And checkpatch reports a number of Didn't know we are enforcing this. Will add. > warnings that need to be fixed: > > - WARNING: quoted string split across lines Noticed. How are we going to balance the long lines vs split across lines? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2 06/11] powerpc/T4240EMU: Add T4240EMU target
On 06/26/2013 03:03 PM, Wolfgang Denk wrote: > Dear York Sun, > > In message <1372263479-10588-1-git-send-email-york...@freescale.com> you > wrote: >> Add emulator support for T4240. Emulator has limited peripherals and >> interfaces. Difference between emulator and T4240QDS includes: >> ECC for DDR is disabled due the procedure to load images >> No board FPGA (QIXIS) >> NOR flash has 32-bit port for higher loading speed >> IFC and I2C timing don't really matter, so set them fast >> No ethernet >> >> Signed-off-by: York Sun >> --- > > So what exactly are the changes compared to V1? Added entry to MAINTAINERS Fixed checkpatch warning - WARNING: quoted string split across lines - WARNING: Avoid unnecessary line continuations > >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -538,6 +538,10 @@ Detlev Zundel >> >> inka4x0 MPC5200 >> >> +York Sun >> + >> +T4240EMUT4240 >> + > > Can you please keep the list sorted? Thanks. The list is not sorted. I tried with my best guess, sort on "CPU". That's why I put it at the end of "PowerPC Systems". York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2 06/11] powerpc/T4240EMU: Add T4240EMU target
On 06/27/2013 10:35 AM, Scott Wood wrote: > On 06/27/2013 12:30:25 PM, York Sun wrote: >> On 06/26/2013 03:03 PM, Wolfgang Denk wrote: >> > >> >> --- a/MAINTAINERS >> >> +++ b/MAINTAINERS >> >> @@ -538,6 +538,10 @@ Detlev Zundel >> >> >> >> inka4x0MPC5200 >> >> >> >> +York Sun >> >> + >> >> +T4240EMUT4240 >> >> + >> > >> > Can you please keep the list sorted? Thanks. >> >> The list is not sorted. I tried with my best guess, sort on "CPU". >> That's why I put it at the end of "PowerPC Systems". > > It is sorted by maintainer name (as noted at the top of the file) within > each architecture section. > Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2 06/11] powerpc/T4240EMU: Add T4240EMU target
On 06/27/2013 10:51 AM, Wolfgang Denk wrote: > Dear York Sun, > > In message <51cc76b1.6030...@freescale.com> you wrote: >> >>> So what exactly are the changes compared to V1? >> >> Added entry to MAINTAINERS >> >> Fixed checkpatch warning >> - WARNING: quoted string split across lines >> - WARNING: Avoid unnecessary line continuations > > And why do you not include this information with the patch? You've > been around here long enough that you should know this requirement. I forgot. Updated in v3 patch. > >>>> --- a/MAINTAINERS >>>> +++ b/MAINTAINERS >>>> @@ -538,6 +538,10 @@ Detlev Zundel >>>> >>>>inka4x0 MPC5200 >>>> >>>> +York Sun >>>> + >>>> + T4240EMUT4240 >>>> + >>> >>> Can you please keep the list sorted? Thanks. >> >> The list is not sorted. I tried with my best guess, sort on "CPU". >> That's why I put it at the end of "PowerPC Systems". > > The list IS sorted. The sort key is the last name of the maintainer. > "Sun" clearly sorts before "Zundel". Got it. Updated in v3 patch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board/t1040qds: Add memory reset control
On Dec 25, 2013, at 10:48 PM, Prabhakar Kushwaha wrote:
> JEDEC spec requires the clocks to be stable before deasserting reset
> signal for RDIMMs. Clocks start when any chip select is enabled and
> clock control register is set. This patch also adds the interface to
> toggle memory reset signal if needed by the boards.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> board/freescale/t1040qds/t1040qds.c |5 +
> include/configs/T1040QDS.h |1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/board/freescale/t1040qds/t1040qds.c
> b/board/freescale/t1040qds/t1040qds.c
> index 2aa176c..de3ea5c 100644
> --- a/board/freescale/t1040qds/t1040qds.c
> +++ b/board/freescale/t1040qds/t1040qds.c
> @@ -239,3 +239,8 @@ void qixis_dump_switch(void)
> printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
> }
> }
> +
> +int board_need_mem_reset(void)
> +{
> + return 1;
> +}
> diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
> index 1cfbf06..7bae2c8 100644
> --- a/include/configs/T1040QDS.h
> +++ b/include/configs/T1040QDS.h
> @@ -232,6 +232,7 @@ unsigned long get_board_ddr_clk(void);
> #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
> +#define QIXIS_RST_FORCE_MEM 0x01
>
> #define CONFIG_SYS_CSPR3_EXT (0xf)
> #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
> --
> 1.7.9.5
Prabhakar,
Your patch doesn't do what the commit message says. It only enables this
feature for T1040QDS board.
York
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Re: [U-Boot] [PATCH] powerpc/83xx: fix compilation error for MPC8315ERDB
On 12/19/2013 07:54 PM, Nikhil Badola wrote: > From: Ramneek Mehresh > > Defines get_svr() for 83xx devices > > Signed-off-by: Ramneek Mehresh > --- > arch/powerpc/cpu/mpc83xx/start.S | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/arch/powerpc/cpu/mpc83xx/start.S > b/arch/powerpc/cpu/mpc83xx/start.S > index b4fafe6..7f74a50 100644 > --- a/arch/powerpc/cpu/mpc83xx/start.S > +++ b/arch/powerpc/cpu/mpc83xx/start.S > @@ -120,6 +120,11 @@ disable_addr_trans: > mtspr SRR1, r3 > rfi > > + .globl get_svr > +get_svr: > + mfspr r3, SVR > + blr > + > .globl get_pvr > get_pvr: > mfspr r3, PVR > Please share how to reproduce the compilation error. I don't see it. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
On 12/11/2013 11:10 PM, Shengzhou Liu wrote:
> - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
> - Remove unused patameters: 'cpo', 'wrdata delay', '2T',
> which are unrelated to DDR3/3L.
>
> Signed-off-by: Shengzhou Liu
> ---
> Against master branch of git://git.denx.de/u-boot-mpc85xx.git
> v3: remain old RDIMM code without updating for now.
> v2: throw an error in case of RDIMM.
>
> board/freescale/t2080qds/ddr.c | 11 ++-
> board/freescale/t2080qds/ddr.h | 65
> +-
> 2 files changed, 28 insertions(+), 48 deletions(-)
>
> diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
> index 5db5d21..4a4d570 100644
> --- a/board/freescale/t2080qds/ddr.c
> +++ b/board/freescale/t2080qds/ddr.c
> @@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
> ulong ddr_freq;
>
> - if (ctrl_num > 2) {
> + if (ctrl_num > 1) {
> printf("Not supported controller number %d\n", ctrl_num);
> return;
> }
> @@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> else
> pbsp = udimms[0];
>
> -
> - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
> + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
>* freqency and n_banks specified in board_specific_parameters table.
>*/
> ddr_freq = get_ddr_freq(0) / 100;
> @@ -49,9 +48,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> if (pbsp->n_ranks == pdimm->n_ranks &&
> (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
> if (ddr_freq <= pbsp->datarate_mhz_high) {
> - popts->cpo_override = pbsp->cpo;
> - popts->write_data_delay =
> - pbsp->write_data_delay;
> popts->clk_adjust = pbsp->clk_adjust;
> popts->wrlvl_start = pbsp->wrlvl_start;
> popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> @@ -69,13 +65,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
> printf("for data rate %lu MT/s\n", ddr_freq);
> printf("Trying to use the highest speed (%u) parameters\n",
> pbsp_highest->datarate_mhz_high);
> - popts->cpo_override = pbsp_highest->cpo;
> - popts->write_data_delay = pbsp_highest->write_data_delay;
> popts->clk_adjust = pbsp_highest->clk_adjust;
> popts->wrlvl_start = pbsp_highest->wrlvl_start;
> popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> - popts->twot_en = pbsp_highest->force_2t;
> } else {
> panic("DIMM is not supported by this board");
> }
> diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
> index 964eaad..5828596 100644
> --- a/board/freescale/t2080qds/ddr.h
> +++ b/board/freescale/t2080qds/ddr.h
> @@ -14,9 +14,6 @@ struct board_specific_parameters {
> u32 wrlvl_start;
> u32 wrlvl_ctl_2;
> u32 wrlvl_ctl_3;
> - u32 cpo;
> - u32 write_data_delay;
> - u32 force_2t;
> };
>
> /*
> @@ -28,58 +25,48 @@ struct board_specific_parameters {
> static const struct board_specific_parameters udimm0[] = {
> /*
>* memory controller 0
> - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
> - * ranks| mhz| GB |adjst| start | ctl2| ctl3 | |delay |
> + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
> + * ranks| mhz| GB |adjst| start | ctl2| ctl3 |
>*/
> - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff,2, 0},
> - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff,2, 0},
> - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff,2, 0},
> - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff,2, 0},
> - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff,2, 0},
> - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff,2, 0},
> - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff,2, 0},
> - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff,2, 0},
> - {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff,2, 0},
> - {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff,2, 0},
> - {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff,2, 0},
> - {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff,2, 0},
> - {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff,2, 0},
> + {2, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
> + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
> + {2, 1700, 2, 5, 8, 0x090b0b0d, 0x0
Re: [U-Boot] [PATCH][v2] powerpc/t1040qds: Update DDR initialization related settings
On 12/16/2013 09:42 PM, Priyanka Jain wrote:
> Update following DDR related settings for T1040QDS
> -Correct number of chip selects to two as t1040qds supports
> two Chip selects.
> -Update board_specific_parameters udimm structure with settings
> derived via calibration.
> -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
> read at 400KHz.
>
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Priyanka Jain
> ---
> Changes for v2:
> Reduced I2C speed to 50KHz.
>
> board/freescale/t1040qds/ddr.h | 22 --
> include/configs/T1040QDS.h |6 +++---
> 2 files changed, 15 insertions(+), 13 deletions(-)
>
> diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
> index 8ee206e..afa72af 100644
> --- a/board/freescale/t1040qds/ddr.h
> +++ b/board/freescale/t1040qds/ddr.h
> @@ -31,16 +31,18 @@ static const struct board_specific_parameters udimm0[] = {
>* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
>* ranks| mhz| GB |adjst| start | ctl2| ctl3 | |delay |
>*/
> - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff,2, 0},
> - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff,2, 0},
> - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff,2, 0},
> - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff,2, 0},
> - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff,2, 0},
> - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff,2, 0},
> - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff,2, 0},
> - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff,2, 0},
> - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff,2, 0},
> - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff,2, 0},
> + {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff,2, 0},
> + {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff,2, 0},
> + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff,2, 0},
> + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff,2, 0},
> + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff,2, 0},
> + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff,2, 0},
> + {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff,2, 0},
> + {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff,2, 0},
> + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff,2, 0},
> + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff,2, 0},
> + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff,2, 0},
> + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff,2, 0},
> {}
> };
Looks you are updating timing for all speeds. Can you add to commit message
about what DIMMs and speeds have you tested?
York
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Re: [U-Boot] [PATCH][v2] board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
On 12/10/2013 11:12 PM, Prabhakar Kushwaha wrote: > CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary > review purpose. > > So, use CONFIG_SPL_NAND_BOOT config. > > Signed-off-by: Prabhakar Kushwaha > --- > Changes for v2: Incorporated Scott's comments >- Add CONFIG_SPL_NAND_BOOT in README > Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board/t1040qds: Fix typo in t1040_pbi.cfg file
On 12/09/2013 11:43 PM, Prabhakar Kushwaha wrote: > T1040QDS has 256KB SRAM. Comment is showing wrong information. > > So update the comment. > > Signed-off-by: Prabhakar Kushwaha > --- Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] board/t1040qds: Relax IFC FPGA timings
On 12/11/2013 10:39 PM, Prabhakar Kushwaha wrote: > Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) > is 0 i.e. 0 ns hold time on writes. This may not work on higher clock > freqencies. > > So, Increase TCH as 0x8 i.e. 8 ip_clk. > > Signed-off-by: Prabhakar Kushwaha > --- Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v4] powerpc/mpc85xx: Add support for single source clocking
On 12/17/2013 12:55 AM, Priyanka Jain wrote: > Single-source clocking is new feature introduced in T1040. > In this mode, a single differential clock is supplied to the > DIFF_SYSCLK_P/N inputs to the processor, which in turn is > used to supply clocks to the sysclock, ddrclock and usbclock. > > So, both ddrclock and syclock are driven by same differential > sysclock in single-source clocking mode whereas in normal clocking > mode, generally separate DDRCLK and SYSCLK pins provides > reference clock for sysclock and ddrclock > > DDR_REFCLK_SEL rcw bit is used to determine DDR clock source > -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in > normal clocking mode by DDR_Reference clock > > -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in > single source clocking mode by DIFF_SYSCLK > > Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. > > Signed-off-by: Poonam Aggrwal > Signed-off-by: Priyanka Jain > --- > Changes for v4: > Updated README with CONFIG_SYS_FSL_SINGLE_SOURCE_CLK > description. > > Changes for v3: > Incorporated York's comment to move declaration to > beginning of function. > > Changes for v2: > Incorporated York's comment to separate out > DDR_CLK_FREQ and SINGLE_SOURCE_CLK code > Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] powerpc/P1022DS: Define new nand_ecclayout structure macros
On 12/17/2013 11:21 AM, York Sun wrote: > Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to > reduce the image size, by taking advantage of the new nand_ecclayout > structure. > > Signed-off-by: York Sun > CC: Prabhakar Kushwaha > CC: Scott Wood > --- Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] powerpc/B4860QDS: Define new nand_ecclayout structure macros
On 12/17/2013 11:21 AM, York Sun wrote: > Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to > reduce the image size, by taking advantage of the new nand_ecclayout > structure. > > Signed-off-by: York Sun > CC: Prabhakar Kushwaha > CC: Scott Wood > --- Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
On 12/17/2013 06:27 PM, Shengzhou Liu wrote: > CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used, > update it to new CONFIG_USB_MAX_CONTROLLER_COUNT. > > Signed-off-by: Shengzhou Liu > --- Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH] powerpc/cms700: limit NAND data structure size
On 12/17/2013 08:11 PM, Scott Wood wrote: > This fixes a build break due to excessively large NAND data structures. > > Signed-off-by: Scott Wood > Cc: Matthias Fuchs > --- Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH] powerpc/t4240: enable NAND boot support
On 12/17/2013 11:09 PM, shh@gmail.com wrote: > From: Shaohui Xie > > Signed-off-by: Shaohui Xie > --- Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH] powerpc/b4860/pbl: fix rcw cfg
On 12/18/2013 09:38 PM, shh@gmail.com wrote: > From: Shaohui Xie > > The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1. > > Signed-off-by: Shaohui Xie > --- Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] board/t1040qds: Enable memory reset control
On 12/25/2013 11:10 PM, Prabhakar Kushwaha wrote: > Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start > accessing it. > > Signed-off-by: Prabhakar Kushwaha > --- > Changes for v2: Incorporated York's comments > - Update subject and description > Applied to u-boot-mpc85xx/master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] linkstation_HGLAN and MPC824x support
On 12/18/2013 01:50 PM, Tom Rini wrote: > On 12/18/2013 04:35 PM, York Sun wrote: >> On 11/25/2013 07:45 AM, Tom Rini wrote: >>> Hello, >>> >>> With a recent change to U-Boot (as part of merging >>> http://patchwork.ozlabs.org/patch/293612/), we need cache support >>> for MPC824x, for the linkstation_HGLAN board to continue >>> building, as the network driver is now cache aware. >>> >>> Alternatively, if there is no interest in maintaining the >>> platform upstream anymore, we can remove it. Thanks! >>> > >> Tom, > >> Did you hear objection? I think we should remove support for this >> board. We'd better do it before next release. > > I would say this is "last call" for a patch now, yes. > Tom, Are you going to remove this platform, or waiting for someone to submit a patch to do so? Does removing this platform mean totally remove the code, or only modify boards.cfg to disable the build? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t208x: enable erratum a006379 for t208x
On 01/02/2014 09:46 PM, Shengzhou Liu wrote: > Erratum A006379 applies to T2080/T2081 also. > > Signed-off-by: Shengzhou Liu Please fix the subject. You are enabling a workaround for an erratum. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] MAKEALL
Wolfgang, I have some troubles to run MAKEALL with BUILD_NBUILDS. If I set BUILD_NBUILDS to 2 or greater, there is a good chance the total number of targets is not an integral multiple of BUILD_NBUILDS. It has two undesired results. 1. The status report has wrong number of passed builds. 2. This script throws out SIGTERM. The second one is troubling me. I am using Jenkins to monitor and build automatically. I can trap the SIGTERM on some hosts but not all of them. Can you shed some light on this? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx master
Tom, The following changes since commit fef24f4f38eb685a6da29097930e6e49b378f8fb: ARM: Samsung: Change GONI and Universal_C210 maintainers. (2013-12-20 10:48:06 -0500) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 8c618dd66adfab736b88a86f51c057b019988a90: board/t1040qds: Enable memory reset control (2014-01-02 14:10:14 -0800) Prabhakar Kushwaha (4): board/t1040qds: Fix typo in t1040_pbi.cfg file board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL board/t1040qds: Relax IFC FPGA timings board/t1040qds: Enable memory reset control Priyanka Jain (1): powerpc/mpc85xx: Add support for single source clocking Scott Wood (1): powerpc/cms700: limit NAND data structure size Shaohui Xie (2): powerpc/t4240: enable NAND boot support powerpc/b4860/pbl: fix rcw cfg Shengzhou Liu (1): powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS York Sun (2): powerpc/P1022DS: Define new nand_ecclayout structure macros powerpc/B4860QDS: Define new nand_ecclayout structure macros README|8 arch/powerpc/cpu/mpc85xx/speed.c | 25 +++-- arch/powerpc/include/asm/config_mpc85xx.h |3 ++- arch/powerpc/include/asm/immap_85xx.h |3 +++ board/freescale/b4860qds/b4_rcw.cfg |2 +- board/freescale/bsc9131rdb/tlb.c |2 +- board/freescale/bsc9132qds/tlb.c |2 +- board/freescale/p1010rdb/tlb.c|2 +- board/freescale/t1040qds/t1040_pbi.cfg|2 +- board/freescale/t1040qds/t1040qds.c |5 + boards.cfg|1 + include/configs/B4860QDS.h|2 ++ include/configs/BSC9131RDB.h |2 +- include/configs/BSC9132QDS.h |2 +- include/configs/CMS700.h |3 +++ include/configs/P1010RDB.h|2 +- include/configs/P1022DS.h |2 ++ include/configs/T1040QDS.h|3 ++- 18 files changed, 59 insertions(+), 12 deletions(-) Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] linkstation_HGLAN and MPC824x support
On 01/06/2014 06:14 AM, Tom Rini wrote: > On 01/02/2014 07:39 PM, Wolfgang Denk wrote: >> Dear York, > >> In message <52c5fea1.7040...@freescale.com> you wrote: >>> >>> Are you going to remove this platform, or waiting for someone to submit a >>> patch >>> to do so? Does removing this platform mean totally remove the code, or only >>> modify boards.cfg to disable the build? > >> We don't leave dead code behind - removal will nclude all related >> board code. > > Right. And I posted a patch on the 20th to remove the board. > >> Actually I still vote to remove all MPC82xx code; it's totally dead. > > York, does that work for you as well? PowerPC doesn't formally have the > same feeder structure that ARM has but I'd still like a quick "yes, > nothing there looks like it's about to come back elsewhere". Thanks! > I am OK to remove MPC82xx. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] t2080qds/ddr: update ddr parameters
On 01/06/2014 01:26 AM, Shengzhou Liu wrote: > - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s. > - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are > unrelated to DDR3/3L. > > Signed-off-by: Shengzhou Liu > --- > board/freescale/t2080qds/ddr.c | 12 ++-- > board/freescale/t2080qds/ddr.h | 65 > +- > 2 files changed, 28 insertions(+), 49 deletions(-) > First, please remember to update the version number when you submit an updated patch. Second, please add change log. Please add information about tested conditions, including DIMM model and speed. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: Fix a typo in workaround message for DDR erratum A003474
Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474".
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 1e5a43f..7693899 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -156,7 +156,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
- puts("Work-around for Erratum DDR-A003473 enabled\n");
+ puts("Work-around for Erratum DDR-A003474 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
--
1.7.9.5
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[U-Boot] [PATCH] powerpc/mpc85xx: Revise workaround for DDR A003474
Existing workaround only handles one RDIMM on reference design. In case
two RDIMMs are used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two registers changed by the workaround.
Signed-off-by: York Sun
---
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 59 ++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 9f04133..864976f 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -39,6 +39,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ u32 save1, save2;
+#endif
switch (ctrl_num) {
case 0:
@@ -197,6 +200,8 @@ step2:
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl &
0x7fff);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffeb);
out_be32(&ddr->mtcr, 0);
+ save1 = in_be32(&ddr->debug[12]);
+ save2 = in_be32(&ddr->debug[21]);
out_be32(&ddr->debug[12], 0x0015);
out_be32(&ddr->debug[21], 0x2400);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval &
0x);
@@ -214,6 +219,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x02));
+#endif
break;
case 0x0010:
out_be32(&ddr->sdram_md_cntl,
@@ -222,6 +237,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x0a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x0a));
+#endif
break;
case 0x0020:
out_be32(&ddr->sdram_md_cntl,
@@ -230,6 +255,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x12));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x12));
+#endif
break;
case 0x0030:
out_be32(&ddr->sdram_md_cntl,
@@ -238,6 +273,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x1a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x1a));
+#endif
break;
default:
out_be32(&ddr->sdram_md_cntl,
@@ -246,6 +291,16 @@ step2:
0x0400 |
MD_CNTL_W
Re: [U-Boot] [PATCH] powerpc/mpc85xx: Revise workaround for DDR A003474
On 01/08/2014 10:17 AM, York Sun wrote: > Existing workaround only handles one RDIMM on reference design. In case > two RDIMMs are used, the workaround requires two separate writes to > DDR_SDRAM_MD_CNTL register. > > This patch also restores two registers changed by the workaround. > > Signed-off-by: York Sun Ignore this patch. I made a typo on the subject. v2 is coming. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v2] powerpc/mpc85xx: Revise workaround for DDR-A003
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two debug registers changed by the workaround.
This change has been tested on P4080 v2 platform with one and two RDIMMs
for each controller.
Signed-off-by: York Sun
Tested-by: Ben Collins
CC: James Yang
---
Change log:
v2: Revise commit message
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 59 ++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 9f04133..864976f 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -39,6 +39,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ u32 save1, save2;
+#endif
switch (ctrl_num) {
case 0:
@@ -197,6 +200,8 @@ step2:
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl &
0x7fff);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffeb);
out_be32(&ddr->mtcr, 0);
+ save1 = in_be32(&ddr->debug[12]);
+ save2 = in_be32(&ddr->debug[21]);
out_be32(&ddr->debug[12], 0x0015);
out_be32(&ddr->debug[21], 0x2400);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval &
0x);
@@ -214,6 +219,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x02));
+#endif
break;
case 0x0010:
out_be32(&ddr->sdram_md_cntl,
@@ -222,6 +237,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x0a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x0a));
+#endif
break;
case 0x0020:
out_be32(&ddr->sdram_md_cntl,
@@ -230,6 +255,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x12));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x12));
+#endif
break;
case 0x0030:
out_be32(&ddr->sdram_md_cntl,
@@ -238,6 +273,16 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x1a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x1a));
+#endif
br
Re: [U-Boot] [Patch v2] powerpc/mpc85xx: Revise workaround for DDR-A003
On 01/08/2014 11:24 AM, Gerhard Sittig wrote: > On Wed, Jan 08, 2014 at 10:28 -0800, York Sun wrote: >> >> [ ... ] > > Is "474" missing at the end of the subject line? > No. I made a mistake to put A003474. It should be A003. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3] powerpc/mpc85xx: Revise workaround for DDR-A003
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two debug registers changed by the workaround.
Signed-off-by: York Sun
CC: Ben Collins
CC: James Yang
---
Change log:
v3: Add polling of sdram_md_cntl of each writing. Feed back from James.
v2: Revise commit message
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 69 ++--
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 9f04133..c805086 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -39,6 +39,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
+ u32 save1, save2;
+#endif
switch (ctrl_num) {
case 0:
@@ -197,6 +200,8 @@ step2:
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl &
0x7fff);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffeb);
out_be32(&ddr->mtcr, 0);
+ save1 = in_be32(&ddr->debug[12]);
+ save2 = in_be32(&ddr->debug[21]);
out_be32(&ddr->debug[12], 0x0015);
out_be32(&ddr->debug[21], 0x2400);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval &
0x);
@@ -214,6 +219,18 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x02));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x02));
+#endif
break;
case 0x0010:
out_be32(&ddr->sdram_md_cntl,
@@ -222,6 +239,18 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x0a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x0a));
+#endif
break;
case 0x0020:
out_be32(&ddr->sdram_md_cntl,
@@ -230,6 +259,18 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x12));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
+ ;
+ out_be32(&ddr->sdram_md_cntl,
+MD_CNTL_MD_EN |
+MD_CNTL_CS_SEL_CS2_CS3 |
+0x0400 |
+MD_CNTL_WRCW |
+MD_CNTL_MD_VALUE(0x12));
+#endif
break;
case 0x0030:
out_be32(&ddr->sdram_md_cntl,
@@ -238,6 +279,18 @@ step2:
0x0400 |
MD_CNTL_WRCW|
MD_CNTL_MD_VALUE(0x1a));
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+ if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
+ break;
+ while (
[U-Boot] mxc_i2c driver
Troy, I am trying to use mxc_i2c driver with multiple buses. I didn't figure out how the bases are set. Can you shed some light on this? Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mxc_i2c driver
On 01/14/2014 03:25 PM, Troy Kisky wrote:
> On 1/14/2014 2:26 PM, York Sun wrote:
>> Troy,
>>
>> I am trying to use mxc_i2c driver with multiple buses. I didn't figure out
>> how
>> the bases are set. Can you shed some light on this?
>>
>> Thanks,
>>
>> York
>>
> see board/boundary/nitrogen6x/nitrogen6x.c
>
> It calls
> setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
> setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
> which is in
> arch/arm/imx-common/i2c-mxv7.c
>
> This file has an array of base addresses
>
> static void * const i2c_bases[] = {
> (void *)I2C1_BASE_ADDR,
> (void *)I2C2_BASE_ADDR,
> #ifdef I2C3_BASE_ADDR
> (void *)I2C3_BASE_ADDR,
> #endif
> };
>
Great! Thanks.
York
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Re: [U-Boot] [PATCH][v2] driver/ifc:Change accessor function to take care of endianness
Dear Wolfgang, On Jan 20, 2014, at 10:34 PM, Wolfgang Denk wrote: > Dear Scott, > > In message <20140121054228.de994382...@gemini.denx.de> I wrote: >> >> I fear that more IP blocks will follow that have similar requirements, >> and if we implemnt similar wrappers for each of them separately, we >> will have a mess of hard to maintain code. For example, it will then >> be impossible to share common parts of code because driver A uses >> A_out32() and driver B uses B_out32(). >> >> We should rather try and find a generic solution where the same >> functions can be used by mulltiple drivers which have the same needs. > > On second thought, I also think we should avoid solutions where the > BE/LE test has to be done for each and every I/O accessor call again > and again. We should rather do this just once, and for example set > function pointers as needed (hoping that this driver will only be > needed after relocation, so we have writable data segment). I like the idea of setting it just once, but I don't see how to implement it. A pointer is probably not the solution, because we do need some drivers before relocation. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] driver/ifc:Change accessor function to take care of endianness
On 01/21/2014 09:29 AM, Scott Wood wrote: > On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote: >> Dear York, >> >> In message you wrote: >>> On second thought, I also think we should avoid solutions where the BE/LE test has to be done for each and every I/O accessor call again and again. We should rather do this just once, and for example set function pointers as needed (hoping that this driver will only be needed after relocation, so we have writable data segment). >>> >>> I like the idea of setting it just once, but I don't see how to >>> implement it. A pointer is probably not the solution, because we do need >>> some drivers before relocation. >> >> "some drivers before relocation" - how many which are these? IFC, DDR, I2C (only 32-bit controller is concerned), GUT >> >> Also, is it really necessary to make the decision about endianess at >> runtime? We don't have multi-board support in U-Boot yet, so when you >> build an image you know exactly which SoC you are building for, so you >> should be able to make the selection at compile time? > > It is done at compile time in this patch. > No. It is not necessary to do it at run time. It would be easier to use a switch to decide at compiling time. It does involve many changes to implement the wrapper. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3 V3] esdhc: Workaround for card can't be detected on T4240QDS
Pantelis, On 01/09/2014 09:52 PM, Haijun Zhang wrote: > Card detection pin is ineffective on T4240QDS Rev1.0. > There are two cards can be connected to board. > 1. eMMC card is built-in board, can not be removed. so >For eMMC card it is always there. > 2. Card detecting pin is functional for SDHC card in Rev2.0. > > This workaround force sdhc driver scan and initialize the card > regardless of whether the card is inserted or not in case Rev1.0. > > Signed-off-by: Haijun Zhang > --- > changes for V3: > - Define quirk in board specific file instead of code in driver > changes for V2: > - Add the judgement condition for this broken card > I think this set of patches are in your backyard. If you ack them, I can apply them to mpc85xx. http://patchwork.ozlabs.org/patch/309168/ http://patchwork.ozlabs.org/patch/309167/ http://patchwork.ozlabs.org/patch/309170/ York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/2] powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
On 01/10/2014 11:03 AM, Scott Wood wrote: > On Fri, 2014-01-10 at 10:10 +0800, Po Liu wrote: >> Using the TPL method for nand boot by sram was already >> supported. Here add some code for mpc85xx ifc nand boot. >> >> - For ifc, elbc, esdhc, espi, all need the SPL without >> section .resetvec. >> - Use a clear function name for nand spl boot. >> - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c >> in spl/Makefile; >> >> Signed-off-by: Po Liu >> --- >> changes for v2: >> - seperate public code and c29xpcie board code >> - add ifc support >> changes for v3: >> - remove the redundant plus >> - ifc support use CONFIG_SPL_DRIVERS_MISC_SUPPORT >> changes for v4: >> - modify the nand_load function >> - add comments in README.SPL >> changes for v5: >> -none >> changes for v6: >> - modify the readme file for the include lib file >> >> arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 --- >> doc/README.SPL | 1 + >> drivers/mtd/nand/fsl_ifc_spl.c | 31 --- >> spl/Makefile| 1 + >> 4 files changed, 34 insertions(+), 14 deletions(-) > > Acked-by: Scott Wood > Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
On 01/09/2014 06:10 PM, Po Liu wrote: > Using the TPL/SPL method to booting from 8k page NAND flash. > - Add 256kB size SRAM tlb for second step booting; > - Add spl.c for TPL image boot; > - Add spl_minimal.c for minimal SPL image; > - Add C29XPCIE_NAND configure; > - Modify C29XPCIE.h for nand config and enviroment; > > Signed-off-by: Po Liu > --- > changes for v2: > - seperate the public code and c29xpcie board code; > changes for v3: > - booting log simple to "SPL" "TPL" > - remove the 8k TLB from 0xe000 to 0x > - change the ddr tlb mapping condition > changes for v4: > - None. > changes for v5: > - code style change. > changes for v6: > - none Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI
On 01/12/2014 09:58 PM, Prabhakar Kushwaha wrote: > Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG. > > Also add their details in README. > > Signed-off-by: Prabhakar Kushwaha > --- > changes for v2: Incorporated Wolfgang's comments > - Added more description in README > Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v3] powerpc/t1040qds: Update DDR initialization related settings
On 01/02/2014 09:54 PM, Priyanka Jain wrote: > Update following DDR related settings for T1040QDS > -Correct number of chip selects to two as t1040qds supports > two Chip selects. > -Update board_specific_parameters udimm structure with settings > derived via calibration. > -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably > read at 400KHz. > > Verified the updated settings to be working fine with dual-ranked > Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and > 1600MT/s. > > > Signed-off-by: Poonam Aggrwal > Signed-off-by: Priyanka Jain > --- > Changes for v3: > Updated description based on York's comments. > > Changes for v2: > Reduced I2C speed to 50KHz. > Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/83xx: Add support for get_svr() for 83xx devices
On 01/02/2014 10:41 PM, Nikhil Badola wrote: > From: Ramneek Mehresh > > Defines get_svr() for 83xx devices > > Signed-off-by: Ramneek Mehresh > --- > Changes for v2: > - Changed patch heading > Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] powerpc/t2080qds: some update for t2080qds
On 01/02/2014 10:48 PM, Shengzhou Liu wrote: > - add more serdes protocols support. > - fix some serdes lanes route. > - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. > - correct boot location info for SD/SPI boot. > > Signed-off-by: Shengzhou Liu > --- > v2: update to support more serdes, applied in Gerrit sdk. > Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/85xx: update erratum a006379
On 01/05/2014 09:23 PM, Shengzhou Liu wrote: > Enable Erratum A006379 for T2080, T2081, T4160, B4420. > > Signed-off-by: Shengzhou Liu > --- Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] t2080qds/ddr: update ddr parameters
On 01/12/2014 09:01 PM, Shengzhou Liu wrote: > - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s. > - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are > unrelated to DDR3/3L. > > Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s. > > Signed-off-by: Shengzhou Liu > --- > v3: fix issue of two line with same parameters and add more commit > description. > v2: rebase. Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/mpc85xx:Increase binary size for P, B & T series boards.
On 01/13/2014 10:04 PM, Prabhakar Kushwaha wrote: > u-boot binary size for Freescale mpc85xx platforms is 512KB. > This has been reached to upper limit for some of the platforms causig > linker error. > > So, Increase the u-boot binary size to 768KB. > > Signed-off-by: York Sun > Signed-off-by: Prabhakar Kushwaha > --- > This patch depends upon following patches: > a) powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL > http://patchwork.ozlabs.org/patch/309094/ > b) powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL >http://patchwork.ozlabs.org/patch/309095/ > c) powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI > http://patchwork.ozlabs.org/patch/309685/ > > Limitation: > - NAND boot, SD boot, SPI boot will not work for T4, B4, T2080 >(workig on 2 stage boot loaader for these platforms) Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90f
On 01/12/2014 11:32 PM, Shengzhou Liu wrote: > This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'. > When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before. > > Signed-off-by: Shengzhou Liu > --- Applied to u-boot-mpc85xx master branch. Awaiting upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request u-boot-mpc85xx
Tom, The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b: Prepare v2014.01 (2014-01-20 17:52:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to e222b1f36fedb0363dbc21e0add7dc3848bae553: powerpc/mpc85xx:Increase binary size for P, B & T series boards. (2014-01-21 14:06:30 -0800) Po Liu (2): powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Prabhakar Kushwaha (2): powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI powerpc/mpc85xx:Increase binary size for P, B & T series boards. Priyanka Jain (1): powerpc/t1040qds: Update DDR initialization related settings Ramneek Mehresh (1): powerpc/83xx: Add support for get_svr() for 83xx devices Shengzhou Liu (4): powerpc/t2080qds: some update for t2080qds powerpc/85xx: update erratum a006379 t2080qds/ddr: update ddr parameters net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90f York Sun (2): powerpc/mpc85xx: Fix a typo in workaround message for DDR erratum A003474 powerpc/mpc85xx: Revise workaround for DDR-A003 Makefile|4 +- README |9 ++ arch/powerpc/cpu/mpc83xx/start.S|5 + arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 +-- arch/powerpc/include/asm/fsl_errata.h |6 +- board/freescale/c29xpcie/Makefile | 15 +++ board/freescale/c29xpcie/README | 12 +-- board/freescale/c29xpcie/cpld.c |2 + board/freescale/c29xpcie/spl.c | 77 +++ board/freescale/c29xpcie/spl_minimal.c | 63 board/freescale/c29xpcie/tlb.c | 13 ++- board/freescale/p1010rdb/README.P1010RDB-PA | 12 +-- board/freescale/p1010rdb/README.P1010RDB-PB |4 +- board/freescale/p1023rds/README |4 +- board/freescale/p1_p2_rdb/README| 12 +-- board/freescale/p2041rdb/README | 12 +-- board/freescale/t1040qds/README | 12 +-- board/freescale/t1040qds/ddr.h | 22 +++-- board/freescale/t104xrdb/README | 12 +-- board/freescale/t2080qds/ddr.c | 12 +-- board/freescale/t2080qds/ddr.h | 65 + board/freescale/t2080qds/eth_t2080qds.c | 12 ++- board/freescale/t2080qds/t2080qds.c | 66 +++-- boards.cfg | 67 ++--- doc/README.SPL |1 + doc/README.b4860qds | 12 +-- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 69 +- drivers/mtd/nand/fsl_ifc_spl.c | 31 -- drivers/net/fm/init.c | 53 +- drivers/net/fm/t2080.c | 10 +- include/configs/B4860QDS.h | 12 +-- include/configs/BSC9131RDB.h|6 +- include/configs/BSC9132QDS.h| 17 ++-- include/configs/C29XPCIE.h | 138 +-- include/configs/P1010RDB.h | 16 ++-- include/configs/P1022DS.h | 12 +-- include/configs/P1023RDB.h |8 +- include/configs/P1023RDS.h | 12 +-- include/configs/P1_P2_RDB.h | 14 +-- include/configs/P2020DS.h | 10 +- include/configs/P2041RDB.h | 21 ++-- include/configs/T1040QDS.h | 26 ++--- include/configs/T1040RDB.h | 16 ++-- include/configs/T1042RDB_PI.h | 16 ++-- include/configs/T2080QDS.h | 20 ++-- include/configs/T4240EMU.h |4 +- include/configs/T4240QDS.h | 18 ++-- include/configs/corenet_ds.h| 30 +++--- include/configs/km/kmp204x-common.h |4 +- include/configs/p1_p2_rdb_pc.h | 12 +-- include/configs/p1_twr.h|8 +- include/configs/t4qds.h |2 +- spl/Makefile|1 + 54 files changed, 742 insertions(+), 392 deletions(-) create mode 100644 board/freescale/c29xpcie/spl.c create mode 100644 board/freescale/c29xpcie/spl_minimal.c Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx
Tom, The following changes since commit e222b1f36fedb0363dbc21e0add7dc3848bae553: powerpc/mpc85xx:Increase binary size for P, B & T series boards. (2014-01-21 14:06:30 -0800) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to f28bea0003536976ebe2fb299cfc140702fec489: eSDHC: Calculate envaddr accroding to the address format (2014-01-22 08:56:44 -0800) Haijun.Zhang (3): esdhc: Workaround for card can't be detected on T4240QDS esdhc: Detecting 8 bit width before mmc initialization eSDHC: Calculate envaddr accroding to the address format arch/powerpc/include/asm/config_mpc85xx.h |3 +++ board/freescale/common/sdhc_boot.c| 29 + drivers/mmc/fsl_esdhc.c |9 + include/configs/T4240QDS.h|8 4 files changed, 49 insertions(+) Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] driver/ifc:Change accessor function to take care of endianness
On 01/21/2014 09:34 AM, York Sun wrote: > On 01/21/2014 09:29 AM, Scott Wood wrote: >> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote: >>> Dear York, >>> >>> In message you wrote: >>>> >>>>> On second thought, I also think we should avoid solutions where the >>>>> BE/LE test has to be done for each and every I/O accessor call again >>>>> and again. We should rather do this just once, and for example set >>>>> function pointers as needed (hoping that this driver will only be >>>>> needed after relocation, so we have writable data segment). >>>> >>>> I like the idea of setting it just once, but I don't see how to >>>> implement it. A pointer is probably not the solution, because we do need >>>> some drivers before relocation. >>> >>> "some drivers before relocation" - how many which are these? > > IFC, DDR, I2C (only 32-bit controller is concerned), GUT > >>> >>> Also, is it really necessary to make the decision about endianess at >>> runtime? We don't have multi-board support in U-Boot yet, so when you >>> build an image you know exactly which SoC you are building for, so you >>> should be able to make the selection at compile time? >> >> It is done at compile time in this patch. >> > > No. It is not necessary to do it at run time. It would be easier to use a > switch > to decide at compiling time. It does involve many changes to implement the > wrapper. > Acked-by: York Sun Do we all agree on this patch? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] T4QDS e6500 core and U-Boot 64-bit
On 01/25/2014 07:46 AM, Timur Tabi wrote: > On Fri, Jan 24, 2014 at 7:45 AM, Wolfgang Denk wrote: >> >> For the "test" >> part, it is probably much easier to add a customized memory test (or >> fix just the existing memory test such that it can be built for a 64 >> bit mode) and use this, then trying to run all of U-Boot in 64 bit >> mode. > > There already is PowerPC memory test code in U-Boot that supports more > than 2GB. It uses sliding TLB windows. If it doesn't already support > 12GB, then it should be easy to add that support. If the target is to test memory, current u-boot supports 36-bit address to cover 64GB memory. As everybody explained, only 2GB is "visible" at a time. But actually all memory are read to use (by Linux or other OS). The POST memory test slides the 2GB window to cover all DDR. It will remap back the window, as you would see the message on the console. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] PPC 85xx: Add qemu-ppce500 machine
On 01/24/2014 06:19 AM, Alexander Graf wrote: > Hrm, let me try that. > Looks you got plenty feedback from Scott. I am going to mark this set as "change requested" so they will drop off from my to-do list. Please submit a v2 when they are ready (all three patches together) with change log. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl_esdhc: Add Auto command 12 interrupt bit detecting
On 11/01/2013 12:47 AM, Zhang Haijun wrote: > :-) > > Thanks. > > 于 2013/11/1 15:45, Pantelis Antoniou 写道: >> Hi Zhang, >> >> I'll take a look at it over the weekend. >> >> Regards >> >> -- Pantelis >> Where are we on this patch? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] powerpc/t2081qds: Add T2081 QDS board support
On 01/20/2014 10:15 PM, Shengzhou Liu wrote: > --- a/boards.cfg > +++ b/boards.cfg > @@ -973,11 +973,16 @@ Active powerpc mpc85xx- > freescale t4qds > Active powerpc mpc85xx- freescale t1040qds > T1040QDS T1040QDS:PPC_T1040 > > Poonam Aggrwal > Active powerpc mpc85xx- freescale t104xrdb > T1040RDB T1040RDB:PPC_T1040 > > Poonam Aggrwal > Active powerpc mpc85xx- freescale t104xrdb > T1042RDB_PI T1042RDB_PI:PPC_T1042 > > Poonam Aggrwal > -Active powerpc mpc85xx- freescale t2080qds > T2080QDS T2080QDS:PPC_T2080 > -Active powerpc mpc85xx- freescale t2080qds > T2080QDS_SDCARD > T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8 > -Active powerpc mpc85xx- freescale t2080qds > T2080QDS_SPIFLASH > T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8 > -Active powerpc mpc85xx- freescale t2080qds > T2080QDS_NAND > T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8 > -Active powerpc mpc85xx- freescale t2080qds > T2080QDS_SRIO_PCIE_BOOT > T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2080QDS T208xQDS:PPC_T2080 > +Active powerpc mpc85xx- freescale t208xqds > T2080QDS_SDCARD T208xQDS:PPC_T2080, > RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2080QDS_SPIFLASH T208xQDS:PPC_T2080, > RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2080QDS_NAND T208xQDS:PPC_T2080, > RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2080QDS_SRIO_PCIE_BOOT > T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2081QDS T208xQDS:PPC_T2081 > +Active powerpc mpc85xx- freescale t208xqds > T2081QDS_SDCARD T208xQDS:PPC_T2081, > RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2081QDS_SPIFLASH T208xQDS:PPC_T2081, > RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2081QDS_NAND T208xQDS:PPC_T2081, > RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF8 > +Active powerpc mpc85xx- freescale t208xqds > T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081, > SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF8 > Active powerpc mpc85xx- gdsys p1022 > controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD > > Dirk Eibach > Active powerpc mpc85xx- gdsys p1022 > controlcenterd_36BIT_SDCARD_DEVELOP > controlcenterd:36BIT,SDCARD,DEVELOP > Dirk Eibach > > Active powerpc mpc85xx- gdsys p1022 > controlcenterd_TRAILBLAZER > controlcenterd:TRAILBLAZER,SPIFLASH > Dirk Eibach > Shengzhou, Do you want to update this patch to use 768KB size? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t104xrdb: Add basic ethernet support
On 01/27/2014 10:44 PM, Priyanka Jain wrote:
> This covers only non-L2 switch ethernet interfaces i.e.
> RGMII and SGMII interface for both
> -T1040RDB
> -T1042RDB_PI
>
> T1040RDB is configured as serdes protocol 0x66 which can
> support following interfaces
> -2 RGMIIS on DTSEC4, DTSEC5
> -1 SGMII on DTSEC3
>
> T1042RDB_PI is configured as serdes protocol 0x06 which can
> support following interfaces
> -2 RGMIIS on DTSEC4, DTSEC5
>
>
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Priyanka Jain
> ---
> board/freescale/t104xrdb/Makefile |1 +
> board/freescale/t104xrdb/eth.c| 72
> +
> include/configs/T1040RDB.h|9 ++---
> include/configs/T1042RDB_PI.h |5 ++-
> 4 files changed, 81 insertions(+), 6 deletions(-)
> create mode 100644 board/freescale/t104xrdb/eth.c
>
> diff --git a/board/freescale/t104xrdb/Makefile
> b/board/freescale/t104xrdb/Makefile
> index 76c0c94..e51fb7a 100644
> --- a/board/freescale/t104xrdb/Makefile
> +++ b/board/freescale/t104xrdb/Makefile
> @@ -7,6 +7,7 @@
>
> obj-y+= t104xrdb.o
> obj-y+= ddr.o
> +obj-y+= eth.o
> obj-$(CONFIG_PCI)+= pci.o
> obj-y+= law.o
> obj-y+= tlb.o
> diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
> new file mode 100644
> index 000..448434b
> --- /dev/null
> +++ b/board/freescale/t104xrdb/eth.c
> @@ -0,0 +1,72 @@
> +/*
> + * Copyright 2014 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "../common/fman.h"
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_FMAN_ENET
> + struct memac_mdio_info memac_mdio_info;
> + unsigned int i;
> + int phy_addr;
> + printf("Initializing Fman\n");
> +
> + memac_mdio_info.regs =
> + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
> + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
> +
> + /* Register the real 1G MDIO bus */
> + fm_memac_mdio_init(bis, &memac_mdio_info);
> +
> + /*
> + * Program on board RGMII, SGMII PHY addresses.
> + */
> + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
> + int idx = i - FM1_DTSEC1;
> +
> + switch (fm_info_get_enet_if(i)) {
> +#ifdef CONFIG_T1040RDB
> + case PHY_INTERFACE_MODE_SGMII:
> + /* T1040RDB only supports SGMII on DTSEC3 */
> + fm_info_set_phy_address(FM1_DTSEC3,
> + CONFIG_SYS_SGMII1_PHY_ADDR);
> +#endif
> + case PHY_INTERFACE_MODE_RGMII:
> + if (FM1_DTSEC4 == i)
> + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
> + if (FM1_DTSEC5 == i)
> + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
> + fm_info_set_phy_address(i, phy_addr);
Compiling warning here
warning: 'phy_addr' may be used uninitialized in this function
York
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Re: [U-Boot] [PATCH v2 3/9] kmp204x: I2C deblocking for I2C-bus1 added
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > From: Rainer Boschung > > -uses common deblocking algorithm from ../common/common.c I don't see any algorithm in the common.c file. > -supports deblocking of of I2C-bus1 by means of QRIO GPIO > - SCL1 = GPIO_A16 > - SDA1 = GPIO_A17 > > QRIO GPIOs act in an open-drain-like manner, for 0 GPIO drives > low and for 1 the GPIO is an input and must be pulled up externaly! > > Signed-off-by: Rainer Boschung > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > > board/keymile/kmp204x/kmp204x.c | 53 > ++--- > include/configs/km/kmp204x-common.h | 10 +++ > 2 files changed, 60 insertions(+), 3 deletions(-) > > diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c > index bbb2453..8d6eecb 100644 > --- a/board/keymile/kmp204x/kmp204x.c > +++ b/board/keymile/kmp204x/kmp204x.c > @@ -33,12 +33,51 @@ int checkboard(void) > return 0; > } > > -/* TODO: implement the I2C deblocking function */ > -int i2c_make_abort(void) > +/* I2C deblocking uses the algorithm defined in ../common/common.c, which > + * makes use of 2 QRIO GPIOs to act on the SCL and SDA signals of an I2C bus. > + * According to the standard I2C IOs must not drive HI-Levels, so the > + * QRIO GPIOs are used in open-drain fashion: > + * -> 0 GPIO configured as output that drives low > + * -> 1 GPIO configured as input pull-up ties high > + */ > + I failed to understand these comments as well. Are these comments copy-n-paste? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/9] kmp204x: I2C deblocking for I2C-bus1 added
On 01/30/2014 01:17 AM, Boschung, Rainer wrote: > On 01/30/2014 08:32 AM, Valentin Longchamp wrote: >> On 01/30/2014 03:30 AM, York Sun wrote: >>> On 01/27/2014 02:49 AM, Valentin Longchamp wrote: >>>> From: Rainer Boschung >>>> >>>> -uses common deblocking algorithm from ../common/common.c >>> >>> I don't see any algorithm in the common.c file. >> >> The file is board/keymile/common/common.c, where the i2c_make_abort() and the >> i2c_write_start_seq() functions are defined. I guess that's what Rainer >> means with "algorithm". > > That is what I meant. I will add a more precise comment. >> Please send v3 for this patch only, or an incremental patch. I will swap/squash the patch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/9] kmp204x: I2C deblocking support
On 01/31/2014 04:46 AM, Valentin Longchamp wrote:
> From: Rainer Boschung
>
> This patch adds support for using some GPIOs that are connected to the
> I2C bus to force the bus lines state and perform some bus deblocking
> sequences.
>
> The KM common deblocking algorithm from board/keymile/common/common.c is
> used. The GPIO lines used for deblocking the I2C bus are some external
> GPIOs provided by the QRIO CPLD:
> - SCL = GPIOA_20
> - SDA = GPIOA_21
>
> The QRIO GPIOs act in an open-drain-like manner, for 0 the line is
> driven low and for 1 the GPIO is set as input and the line gets
> pulled-up.
>
> Signed-off-by: Rainer Boschung
> Signed-off-by: Valentin Longchamp
>
> ---
>
> Changes in v3:
> - rewrite the commit message and and the comments for more clarity
> - fix the GPIO numbers that where not correct
>
> Changes in v2: None
>
> board/keymile/kmp204x/kmp204x.c | 53
> ++---
> include/configs/km/kmp204x-common.h | 10 +++
> 2 files changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
> index bbb2453..726d26e 100644
> --- a/board/keymile/kmp204x/kmp204x.c
> +++ b/board/keymile/kmp204x/kmp204x.c
> @@ -33,12 +33,51 @@ int checkboard(void)
> return 0;
> }
>
> -/* TODO: implement the I2C deblocking function */
> -int i2c_make_abort(void)
> +/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
> + * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
> + * For I2C only the low state is activly driven and high state is pulled-up
> + * by a resistor. Therefore the deblock GPIOs are used
> + * -> as an active output to drive a low state
> + * -> as an open-drain input to have a pulled-up high state
> + */
> +
> +/* QRIO GPIOs used for deblocking */
> +#define DEBLOCK_PORT1GPIO_A
> +#define DEBLOCK_SCL1 20
> +#define DEBLOCK_SDA1 21
You changed these macros but didn't change those below. This causes compiling
errors. Please fix it and compile before sending v4.
> +
> +/* By default deblock GPIOs are floating */
> +static void i2c_deblock_gpio_cfg(void)
> +{
> + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
> + qrio_gpio_direction_input(DBLK_PORT1, DBLK_SCL1);
> + qrio_gpio_direction_input(DBLK_PORT1, DBLK_SDA1);
> +
> + qrio_set_gpio(DBLK_PORT1, DBLK_SCL1, 0);
> + qrio_set_gpio(DBLK_PORT1, DBLK_SDA1, 0);
> +}
York
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Re: [U-Boot] [PATCH v2 3/6] PPC 85xx: Add qemu-ppce500 machine
On 01/31/2014 03:16 AM, Alexander Graf wrote: > For KVM we have a special PV machine type called "ppce500". This machine > is inspired by the MPC8544DS board, but implements a lot less features > than that one. > > It also provides more PCI slots and is supposed to be enumerated by > device tree only. > > This patch adds support for the current generation ppce500 machine as > it is implemented today. > > Signed-off-by: Alexander Graf > > --- > > v1 -> v2: > > - Write device tree offset directly into global variable > - use r4 rather than r2 for that > - access fdt directly from in-memory copy > - remove unneeded header includes > - clean up pci enumeration > - coding style fixes > - populate and only use fdt_addr_r > - remove unused exported functions > - remove unused TLB0 entries > - make TLB1 I/O maps non-executable > - remove unused defines in board header > - make -kernel boot variables more clear > - remove TLB0 invalidation > - use tlb1.14 for temporary as=1 map > - use CONFIG_SYS_MPC85XX_NO_RESETVEC > - store fdt pointer in gd through cpu_init_early_f() > - replace fixup_tlb1() with dynamic TLB creation hook > --- > diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c > index 8748ecd..c899d9e 100644 > --- a/arch/powerpc/cpu/mpc85xx/tlb.c > +++ b/arch/powerpc/cpu/mpc85xx/tlb.c > @@ -36,6 +36,10 @@ void init_tlbs(void) > tlb_table[i].mas7); > } > > +#ifdef CONFIG_USE_DYNAMIC_TLBS > + init_tlbs_dynamic(); > +#endif > + You are adding a new CONFIG to common files. Please document it. > return ; > } > > diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h > new file mode 100644 > index 000..1ebaf51 > --- /dev/null > +++ b/include/configs/qemu-ppce500.h > @@ -0,0 +1,209 @@ > +/* > + * Copyright 2011-2014 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/* > + * Corenet DS style board configuration file > + */ > +#ifndef __QEMU_PPCE500_H > +#define __QEMU_PPCE500_H > + > +#define CONFIG_CMD_REGINFO > + > +/* High Level Configuration Options */ > +#define CONFIG_BOOKE > +#define CONFIG_E500 /* BOOKE e500 family */ > +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ > +#define CONFIG_QEMU_E500 > + > +#undef CONFIG_SYS_TEXT_BASE > +#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ > + > +#define CONFIG_SYS_MPC85XX_NO_RESETVEC > + > +#define CONFIG_SYS_RAMBOOT > + > +#define CONFIG_PCI /* Enable PCI/PCIE */ > +#define CONFIG_PCI1 1 /* PCI controller 1 */ > +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ > +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > + > +#define CONFIG_ENV_OVERWRITE > + > +#define CONFIG_ENABLE_36BIT_PHYS > + > +#define CONFIG_ADDR_MAP > +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 > entries */ > + > +#define CONFIG_USE_DYNAMIC_TLBS > + > +#define CONFIG_SYS_MEMTEST_START 0x0020 /* memtest works on */ > +#define CONFIG_SYS_MEMTEST_END 0x0040 > +#define CONFIG_SYS_ALT_MEMTEST > +#define CONFIG_PANIC_HANG/* do not reset board on panic */ > + > +#define CONFIG_SYS_CCSRBAR 0xe000 > +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR > + > +/* > + * DDR Setup > + */ > +#define CONFIG_VERY_BIG_RAM > +#define CONFIG_SYS_DDR_SDRAM_BASE0x > +#define CONFIG_SYS_SDRAM_BASECONFIG_SYS_DDR_SDRAM_BASE > + > +#define CONFIG_CHIP_SELECTS_PER_CTRL 0 I don't know if the qemu has PCI, DDR, etc. Setting the above line to 0 will actually disable DDR controllers. Is that what you want? > + > +/* Get RAM size from device tree */ > +#define CONFIG_DDR_SPD You enabled SPD but I don't see the I2C address. Did you miss something, or you don't really use SPD? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/6] PPC 85xx: Detect e500v2 / e500mc during runtime
On 01/31/2014 03:16 AM, Alexander Graf wrote: > With the qemu-ppce500 machine type we can run the same board with > either an e500v2 or an e500mc core plugged in. > > This means that the IVOR setup can't be based on compile time decisions, > so instead we have to do a runtime check which CPU generation we're > running on. > > Signed-off-by: Alexander Graf > --- > arch/powerpc/cpu/mpc85xx/fixed_ivor.S | 21 - > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S > b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S > index ebbb8c0..635a97e 100644 > --- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S > +++ b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S > @@ -36,17 +36,25 @@ > SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ > SET_IVOR(15, 0x040) /* Debug */ > > -/* e500v1 & e500v2 only */ > -#ifndef CONFIG_E500MC > + /* Check for CPU */ > + mfpvr r3 > + srwir3, r3, 16 > + /* Compare with e500mc PVR major number */ > + li r4, 0 > + ori r4, r4, 0x8023 > + cmpwr3, r4 > + > + /* e500v1 & e500v2 only */ > + bge 1f > SET_IVOR(32, 0x200) /* SPE Unavailable */ > SET_IVOR(33, 0x220) /* Embedded FP Data */ > SET_IVOR(34, 0x240) /* Embedded FP Round */ > -#endif > +1: > > SET_IVOR(35, 0x260) /* Performance monitor */ > > -/* e500mc only */ > -#ifdef CONFIG_E500MC > + /* e500mc only */ > + blt 2f This "blt" has a risk. Please put a comment warning developers who will modify the code to be sure the flag has not been updated since last "cmpw". York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx master
Tom, The following changes since commit 07e2822d158940a0e8ba45b6ab0344ffa1011a07: board: nios2: Check if flash is configured before calling early_flash_cmd_reset() (2014-01-29 16:44:18 -0500) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba: driver/ifc:Change accessor function to take care of endianness (2014-02-03 08:38:51 -0800) Nikhil Badola (1): powerpc/usb: Enable dual phy for T1040 Prabhakar Kushwaha (6): driver/fsl_pci:Update print to display PCIe generation powerpc/mpc85xx:Fix README to show correct flash memory map powerpc/mpc85xx: Update serdes protocols for T1040 boards/t1040qds: Adds ethernet support for T1040 powerpc/t104xrdb: Update T1042RDB.h in config folder driver/ifc:Change accessor function to take care of endianness Priyanka Jain (2): powerpc/t104xrdb: Update T1040RDB.h in config folder powerpc/t104xrdb: Add basic ethernet support Rainer Boschung (2): kmp204x: support for QRIO1 bootcounter kmp204x: I2C deblocking support Valentin Longchamp (7): kmp204x: introduce QRIO GPIO functions kmp204x: implement workaround for A-006559 kmp204x: add support for the kmcoge4 board kmp204x: update I2C field of RCW KM: add the KM_UBI_PART_BOOT_OPTS #define kmp204x: enable support for SPANSION SPI NOR kmp204x: initial support for PCIe FPGA configuration poonam aggrwal (1): powerpc/mpc85xx: Update LIODNs for T1040 README |6 + arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c |2 + arch/powerpc/cpu/mpc85xx/t1040_ids.c | 36 -- arch/powerpc/cpu/mpc85xx/t1040_serdes.c| 63 ++- arch/powerpc/include/asm/config_mpc85xx.h |6 +- arch/powerpc/include/asm/fsl_serdes.h |8 +- arch/powerpc/include/asm/immap_85xx.h | 11 + board/freescale/t1040qds/Makefile |1 + board/freescale/t1040qds/README|6 +- board/freescale/t1040qds/eth.c | 492 board/freescale/t1040qds/t1040qds.c|1 + board/freescale/t104xrdb/Makefile |1 + board/freescale/t104xrdb/README|6 +- board/freescale/t104xrdb/eth.c | 72 board/keymile/kmp204x/Makefile |2 +- board/keymile/kmp204x/kmp204x.c| 128 +++--- board/keymile/kmp204x/kmp204x.h| 10 + board/keymile/kmp204x/pbi.cfg | 10 + board/keymile/kmp204x/pci.c| 85 board/keymile/kmp204x/qrio.c | 146 +++ board/keymile/kmp204x/rcw_kmp204x.cfg |2 +- boards.cfg |1 + doc/README.b4860qds|4 +- drivers/mtd/nand/fsl_ifc_nand.c| 243 ++-- drivers/mtd/nand/fsl_ifc_spl.c | 60 +-- drivers/net/fm/t1040.c | 56 +++ drivers/pci/fsl_pci_init.c |4 +- include/configs/T1040QDS.h |5 +- include/configs/T1040RDB.h | 24 +- include/configs/T1042RDB_PI.h | 20 +- include/configs/km/keymile-common.h| 10 +- include/configs/km/kmp204x-common.h| 21 +- include/configs/kmp204x.h |7 +- include/fsl_ifc.h | 42 +- 34 files changed, 1230 insertions(+), 361 deletions(-) create mode 100644 board/freescale/t1040qds/eth.c create mode 100644 board/freescale/t104xrdb/eth.c create mode 100644 board/keymile/kmp204x/qrio.c Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/mpc85xx: Update serdes protocols for T1040
On 01/24/2014 04:21 AM, Prabhakar Kushwaha wrote: > T1040 has only one SerDes block. so update the code accordingly. > > Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85, > 0xA7 and 0xAA > > Signed-off-by: Arpit Goel > Signed-off-by: Poonam Aggrwal > Signed-off-by: Priyanka Jain > Signed-off-by: Prabhakar Kushwaha > --- Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/2, v2] boards/t1040qds: Adds ethernet support for T1040
On 01/27/2014 02:25 AM, Prabhakar Kushwaha wrote: > Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 > - Define MDIO related configs > - Added eth.c file > - Update t1040.c to support RGMII and SGMII > - Update t1040qds.c to support ethernet > - Define the PHY address > > Signed-off-by: Arpit Goel > Signed-off-by: Bhupesh Sharma > Signed-off-by: Poonam Aggrwal > Signed-off-by: Priyanka Jain > Signed-off-by: Prabhakar Kushwaha > > --- > Changes for v2: > - Added missed sign off > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] driver/fsl_pci:Update print to display PCIe generation
On 01/24/2014 11:23 PM, Prabhakar Kushwaha wrote: > Current print only display width of PCIe device. Add print to display > PCIe generation supported by the device. > > Signed-off-by: Prabhakar Kushwaha > --- Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] powerpc/t104xrdb: Update T1040RDB.h in config folder
On 01/27/2014 12:37 AM, Priyanka Jain wrote: > -Add usb2 node entry in "hwconfig string" > > -Remove controller interleaving from hwconfig string as T1040 > has only one DDR conroller > > -SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH > are move outside so that they are defined for all cases as these > macros are also used by other u-boot code > > -Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot > > Signed-off-by: Poonam Aggrwal > Signed-off-by: Priyanka Jain > > --- > Changes for v2: > correct usb1 string for ; > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v0] powerpc/mpc85xx: Update LIODNs for T1040
On 01/23/2014 12:54 PM, Poonam Aggrwal wrote: > Removed LIODNs for RMAN, RIO, 10G. T1040 has 10 QMAN portals so assigned > LIODNs accordingly. > > Signed-off-by: Poonam Aggrwal > --- Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] powerpc/t104xrdb: Update T1042RDB.h in config folder
On 01/27/2014 01:11 AM, Prabhakar Kushwaha wrote: > -Add usb2 node entry in "hwconfig string" > > -Remove controller interleaving from hwconfig string as T1040 > has only one DDR conroller > > -SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH > are move outside so that they are defined for all cases as these > macros are also used by other u-boot code > > -Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot > > Signed-off-by: Prabhakar Kushwaha > > --- > Changes for v2: > correct usb1 string for ; Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/mpc85xx:Fix README to show correct flash memory map
On 01/24/2014 10:41 PM, Prabhakar Kushwaha wrote: > Due to increased size of u-boot, FMAN ucode start address has been shifted > by 256KB causing a overlap with rootfs start address. > > Update rootfs start address to reflect correct memory map. > > Also fix minor typo in README > > Signed-off-by: Prabhakar Kushwaha > --- Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/t104xrdb: Add basic ethernet support
On 01/29/2014 10:00 PM, Priyanka Jain wrote: > This covers only non-L2 switch ethernet interfaces i.e. > RGMII and SGMII interface for both > -T1040RDB > -T1042RDB_PI > > T1040RDB is configured as serdes protocol 0x66 which can > support following interfaces > -2 RGMIIS on DTSEC4, DTSEC5 > -1 SGMII on DTSEC3 > > T1042RDB_PI is configured as serdes protocol 0x06 which can > support following interfaces > -2 RGMIIS on DTSEC4, DTSEC5 > > > Signed-off-by: Poonam Aggrwal > Signed-off-by: Priyanka Jain > --- > Changes for v2: > Initialized phy_addr to remove compilation warning. > > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc/usb: Enable dual phy for T1040
On 01/27/2014 01:51 AM, Nikhil Badola wrote: > Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual > phy in t1040 > > Signed-off-by: Nikhil Badola > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/9] kmp204x: implement workaround for A-006559
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > According to the errata, some bits of an undocumented register in the > DCSR must be set for every core in order to avoid a possible data or > instruction corruption. > > This is required for the 2.0 revision of the P2041 that should be used > as soon as available in our design. > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/9] kmp204x: support for QRIO1 bootcounter
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > From: Rainer Boschung > > - make use of the QRIO1 32bit register at 0x20 as bootcounter register > - check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read > > Signed-off-by: Rainer Boschung > Signed-off-by: Valentin Longchamp > > --- > > Changes in v2: > - change bootcounter implementation to use generic driver > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/9] kmp204x: introduce QRIO GPIO functions
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > The QRIO GPIO functions can be of general interest. They are thus added > to a qrio.c and their prototype are available from kmp204x.h. The QRIO > prst function are also included in this file, as well as the functions > required for the I2C deblocking support (open-drain). > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/9] kmp204x: update I2C field of RCW
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > On the previous HW revision (now unsupported), there was a need for > external DMA signals and thus the I2C3/4 signals were used > DMA1_DONE/ACK/REQ. > > These signals now are configured as GPIO[16:19]. > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/9] kmp204x: add support for the kmcoge4 board
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > The kmcoge4 board is the product board derived from the kmlion1 > prototype. The main difference between the 2 boards is that the kmcoge4 > does not configure the Local Bus controller for LCS2. > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 9/9] kmp204x: initial support for PCIe FPGA configuration
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > The PEXHC PCIe configuration mechanism ensures that the FPGA get > configured at power-up. Since all the PCIe devices should be configured > when the kernel start, u-boot has to take care that the FPGA gets > configured also in other reset scenarios, mostly because of possible > configuration change. > > The used mechanism is taken from the km_kirkwood design and adapted to > the kmp204x case (slightly different HW and PCIe configuration). > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/9] KM: add the KM_UBI_PART_BOOT_OPTS #define
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > This define can be used if the ubi boot partition (defined for all > Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs > some additionnal boot options. > > This is the case for the kmp204x boards since u-boot does not support > NAND Flash subpage accesses on this platform, an additionnal argument > that defines the VID offstet must be given to the kernel. > > The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this > platform. > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 8/9] kmp204x: enable support for SPANSION SPI NOR
On 01/27/2014 02:49 AM, Valentin Longchamp wrote: > The new prototype and the final series was moved from Micron to Spansion > to have a better reset sequence that is easier to support. > > Signed-off-by: Valentin Longchamp > --- > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/9] kmp204x: I2C deblocking support
On 02/02/2014 11:45 PM, Valentin Longchamp wrote: > From: Rainer Boschung > > This patch adds support for using some GPIOs that are connected to the > I2C bus to force the bus lines state and perform some bus deblocking > sequences. > > The KM common deblocking algorithm from board/keymile/common/common.c is > used. The GPIO lines used for deblocking the I2C bus are some external > GPIOs provided by the QRIO CPLD: > - SCL = GPIOA_20 > - SDA = GPIOA_21 > > The QRIO GPIOs act in an open-drain-like manner, for 0 the line is > driven low and for 1 the GPIO is set as input and the line gets > pulled-up. > > Signed-off-by: Rainer Boschung > Signed-off-by: Valentin Longchamp > > --- > > Changes in v4: > - fix usage of the #define names that got wrong in the merge process > > Changes in v3: > - rewrite the commit message and and the comments for more clarity > - fix the GPIO numbers that where not correct > > Changes in v2: None > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] driver/ifc:Change accessor function to take care of endianness
On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote: > IFC registers can be of type Little Endian or big Endian depending upon > Freescale SoC. Here SoC defines the register type of IFC IP. > > So update acessor functions with common IFC acessor functions to take care > both type of endianness. > > Signed-off-by: Prabhakar Kushwaha > --- > Changes for v2: > - fix spelling mistakes > Applied to u-boot-mpc85xx master branch. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] driver/ifc:Change accessor function to take care of endianness
On 02/03/2014 01:35 PM, Scott Wood wrote: > On Mon, 2014-02-03 at 12:28 -0800, York Sun wrote: >> On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote: >>> IFC registers can be of type Little Endian or big Endian depending upon >>> Freescale SoC. Here SoC defines the register type of IFC IP. >>> >>> So update acessor functions with common IFC acessor functions to take care >>> both type of endianness. >>> >>> Signed-off-by: Prabhakar Kushwaha >>> --- >>> Changes for v2: >>> - fix spelling mistakes >>> >> >> Applied to u-boot-mpc85xx master branch. > > I thought this was supposed to wait until there was a user. > We have one. I am clearing the path to push patches for LS2100. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/t104xrdb, t1040qds : Update FMAN microcode NOR address
On 02/04/2014 10:12 PM, Priyanka Jain wrote: > FMAN microcode image address range on NOR flash changed from > (0xeff0 to 0xebf1) to (0xeff1 to 0xeff1) > > The change has been done > - to support FMAN microcode flashing via promjet mechanism as > promjet uses address based on offsets. Based on this > address of FMAN microcode flash on promjet flash should be 0x0 > But 0x0 offset is already use for rcw on promjet flash. > To take care of this limitation FMAN microcode address has been > changed. Now, FMAN microcode address on promjet flash is 0x1 > > - FMAN microcode is of size 64KB so it will fit into > 0xeff1 to 0xeff1. > NACK. The tool is not broken. I have made a configuration to use PROMJET to download all images successfully. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++-
arch/powerpc/cpu/mpc85xx/cpu_init.c |8 +---
arch/powerpc/cpu/mpc85xx/release.S|8
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2ed5a98..d7a62e9 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -51,7 +51,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
puts("Work-around for Erratum SERDES-A005 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- puts("Work-around for Erratum CPU22 enabled\n");
+ if (SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum CPU22 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2cd5db7..3637972 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -309,9 +309,11 @@ int cpu_init_r(void)
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- flush_dcache();
- mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
- sync();
+ if (SVR_MAJ(svr) < 3) {
+ flush_dcache();
+ mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+ sync();
+ }
#endif
puts ("L2:");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index c81e19c..fe3b6d6 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -144,9 +144,17 @@ __secondary_start_page:
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ /* apply to P4080 rev 1 and rev 2 */
+ mfspr r3,SPRN_SVR
+ rlwinm r3,r3,0,0xf0
+ li r4,0x30
+ cmpwr3,r4
+ bge 2f
+
mfspr r8,L1CSR2
orisr8,r8,(L1CSR2_DCWS)@h
mtspr L1CSR2,r8
+2:
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
--
1.7.0.4
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[U-Boot] [PATCH 3/4] powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |8
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 --
arch/powerpc/cpu/mpc85xx/release.S| 28
arch/powerpc/include/asm/config_mpc85xx.h |3 +++
4 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 35c2b1a..4e1a54a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -52,6 +52,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (SVR_MAJ(svr) < 3)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+ /*
+* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+*/
+ if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum CPU-A011 enabled\n");
+#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 50ee506..4f03d25 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -308,8 +308,14 @@ int cpu_init_r(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- if (SVR_MAJ(svr) < 3) {
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+ /*
+* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+*/
+ if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index fe3b6d6..36c79d3 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -143,17 +143,29 @@ __secondary_start_page:
mtspr L1CSR2,r8
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- /* apply to P4080 rev 1 and rev 2 */
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+ /*
+* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+*/
mfspr r3,SPRN_SVR
+ rlwinm r6,r3,24,~0x800 /* clear E bit */
+
+ lis r5,SVR_P4080@h
+ ori r5,r5,SVR_P4080@l
+ cmpwr6,r5
+ bne 1f
+
rlwinm r3,r3,0,0xf0
- li r4,0x30
- cmpwr3,r4
+ li r5,0x30
+ cmpwr3,r5
bge 2f
-
- mfspr r8,L1CSR2
- orisr8,r8,(L1CSR2_DCWS)@h
- mtspr L1CSR2,r8
+1:
+ mfspr r3,L1CSR2
+ orisr3,r3,(L1CSR2_DCWS)@h
+ mtspr L1CSR2,r3
2:
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 191629b..756a2ad 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -359,6 +359,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -383,6 +384,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -446,6 +448,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
--
1.7.0.4
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[U-Boot] [PATCH 2/4] powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 -
arch/powerpc/cpu/mpc85xx/cpu_init.c | 13 +++---
arch/powerpc/cpu/mpc85xx/fdt.c | 11 +++-
arch/powerpc/cpu/mpc85xx/p2041_serdes.c |4 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 39 +
arch/powerpc/include/asm/processor.h| 41 +-
6 files changed, 13 insertions(+), 97 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d7a62e9..35c2b1a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
- case SVR_P1013_E:
case SVR_P1022:
- case SVR_P1022_E:
puts("Work-around for Erratum SATA A001 enabled\n");
}
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 3637972..50ee506 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -356,8 +356,7 @@ int cpu_init_r(void)
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E) {
+ ver == SVR_8541 || ver == SVR_8555) {
puts("128 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
cache_ctl = 0xc400;
@@ -368,8 +367,7 @@ int cpu_init_r(void)
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E) {
+ ver == SVR_8541 || ver == SVR_8555) {
puts("256 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc800;
@@ -405,8 +403,7 @@ int cpu_init_r(void)
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
- if ((SVR_SOC_VER(svr) == SVR_P2040) ||
- (SVR_SOC_VER(svr) == SVR_P2040_E)) {
+ if (SVR_SOC_VER(svr) == SVR_P2040) {
puts("N/A\n");
goto skip_l2;
}
@@ -508,9 +505,7 @@ skip_l2:
*/
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
-(SVR_SOC_VER(svr) == SVR_P1022_E) ||
-(SVR_SOC_VER(svr) == SVR_P1013) ||
-(SVR_SOC_VER(svr) == SVR_P1013_E))) {
+(SVR_SOC_VER(svr) == SVR_P1013))) {
fsl_sata_reg_t *reg;
/* first SATA controller */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 90e..21c3ad4 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -139,16 +139,14 @@ static inline u32 l2cache_size(void)
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E)
+ ver == SVR_8541 || ver == SVR_8555)
return 128;
else
return 256;
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E)
+ ver == SVR_8541 || ver == SVR_8555)
return 256;
else
return 512;
@@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob)
int has_l2 = 1;
/* P2040/P2040E has no L2, so dont set any L2 props */
- if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
- (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+ if (SVR_SOC_VER(get_svr()) == SVR_P2040)
has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
@@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob)
unsigned int svr;
svr = mfspr(SPRN_SVR);
- if (SVR_SOC_VER(svr) == SVR_8569_E) {
+ if (SVR_SOC_VER(svr) == SVR_8569) {
if(IS_SVR_REV(svr, 1, 0))
do_fixup_by_compat_u32(blob, "fsl,qe",
[U-Boot] [PATCH 4/4] powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E
Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/release.S | 11 --- 1 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 36c79d3..1860684 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -171,15 +171,12 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ - mfspr r2,SPRN_SVR + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ + lis r3,SVR_P2040@h ori r3,r3,SVR_P2040@l - cmpwr2,r3 - beq 3f - - lis r3,SVR_P2040_E@h - ori r3,r3,SVR_P2040_E@l - cmpwr2,r3 + cmpwr6,r3 beq 3f /* Enable/invalidate the L2 cache */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v2 2/4] powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun
---
Change since v1:
Remove three SVRs, SVR_P1014_E, SVR_P1020_E, SVR_P1011_E
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 -
arch/powerpc/cpu/mpc85xx/cpu_init.c | 13 +++---
arch/powerpc/cpu/mpc85xx/fdt.c | 11 +++-
arch/powerpc/cpu/mpc85xx/p2041_serdes.c |4 +-
arch/powerpc/cpu/mpc8xxx/cpu.c | 39 +
arch/powerpc/include/asm/processor.h| 41 +-
board/freescale/p1010rdb/ddr.c |6 ++--
board/freescale/p1010rdb/p1010rdb.c |4 +-
board/freescale/p1_p2_rdb/ddr.c |6 +---
9 files changed, 20 insertions(+), 106 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d7a62e9..35c2b1a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
- case SVR_P1013_E:
case SVR_P1022:
- case SVR_P1022_E:
puts("Work-around for Erratum SATA A001 enabled\n");
}
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 3637972..50ee506 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -356,8 +356,7 @@ int cpu_init_r(void)
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E) {
+ ver == SVR_8541 || ver == SVR_8555) {
puts("128 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
cache_ctl = 0xc400;
@@ -368,8 +367,7 @@ int cpu_init_r(void)
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E) {
+ ver == SVR_8541 || ver == SVR_8555) {
puts("256 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc800;
@@ -405,8 +403,7 @@ int cpu_init_r(void)
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
- if ((SVR_SOC_VER(svr) == SVR_P2040) ||
- (SVR_SOC_VER(svr) == SVR_P2040_E)) {
+ if (SVR_SOC_VER(svr) == SVR_P2040) {
puts("N/A\n");
goto skip_l2;
}
@@ -508,9 +505,7 @@ skip_l2:
*/
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
-(SVR_SOC_VER(svr) == SVR_P1022_E) ||
-(SVR_SOC_VER(svr) == SVR_P1013) ||
-(SVR_SOC_VER(svr) == SVR_P1013_E))) {
+(SVR_SOC_VER(svr) == SVR_P1013))) {
fsl_sata_reg_t *reg;
/* first SATA controller */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 90e..21c3ad4 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -139,16 +139,14 @@ static inline u32 l2cache_size(void)
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E)
+ ver == SVR_8541 || ver == SVR_8555)
return 128;
else
return 256;
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
- ver == SVR_8541 || ver == SVR_8541_E ||
- ver == SVR_8555 || ver == SVR_8555_E)
+ ver == SVR_8541 || ver == SVR_8555)
return 256;
else
return 512;
@@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob)
int has_l2 = 1;
/* P2040/P2040E has no L2, so dont set any L2 props */
- if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
- (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+ if (SVR_SOC_VER(get_svr()) == SVR_P2040)
has_l2 = 0;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
@@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob)
unsigned int svr;
svr = mfspr(SPRN_SVR)
[U-Boot] [Patch v2 3/4] powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun
---
Change since v1:
No change
arch/powerpc/cpu/mpc85xx/cmd_errata.c |8
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 --
arch/powerpc/cpu/mpc85xx/release.S| 28
arch/powerpc/include/asm/config_mpc85xx.h |3 +++
4 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 35c2b1a..4e1a54a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -52,6 +52,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (SVR_MAJ(svr) < 3)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+ /*
+* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+*/
+ if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum CPU-A011 enabled\n");
+#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 50ee506..4f03d25 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -308,8 +308,14 @@ int cpu_init_r(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- if (SVR_MAJ(svr) < 3) {
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+ /*
+* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+*/
+ if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index fe3b6d6..36c79d3 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -143,17 +143,29 @@ __secondary_start_page:
mtspr L1CSR2,r8
#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- /* apply to P4080 rev 1 and rev 2 */
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+ /*
+* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+*/
mfspr r3,SPRN_SVR
+ rlwinm r6,r3,24,~0x800 /* clear E bit */
+
+ lis r5,SVR_P4080@h
+ ori r5,r5,SVR_P4080@l
+ cmpwr6,r5
+ bne 1f
+
rlwinm r3,r3,0,0xf0
- li r4,0x30
- cmpwr3,r4
+ li r5,0x30
+ cmpwr3,r5
bge 2f
-
- mfspr r8,L1CSR2
- orisr8,r8,(L1CSR2_DCWS)@h
- mtspr L1CSR2,r8
+1:
+ mfspr r3,L1CSR2
+ orisr3,r3,(L1CSR2_DCWS)@h
+ mtspr L1CSR2,r3
2:
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 191629b..756a2ad 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -359,6 +359,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -383,6 +384,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -446,6 +448,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
--
1.7.0.4
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[U-Boot] [Patch v2 1/4] powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun
---
Change since v1:
No change.
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++-
arch/powerpc/cpu/mpc85xx/cpu_init.c |8 +---
arch/powerpc/cpu/mpc85xx/release.S|8
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2ed5a98..d7a62e9 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -51,7 +51,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
puts("Work-around for Erratum SERDES-A005 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- puts("Work-around for Erratum CPU22 enabled\n");
+ if (SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum CPU22 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2cd5db7..3637972 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -309,9 +309,11 @@ int cpu_init_r(void)
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- flush_dcache();
- mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
- sync();
+ if (SVR_MAJ(svr) < 3) {
+ flush_dcache();
+ mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+ sync();
+ }
#endif
puts ("L2:");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index c81e19c..fe3b6d6 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -144,9 +144,17 @@ __secondary_start_page:
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ /* apply to P4080 rev 1 and rev 2 */
+ mfspr r3,SPRN_SVR
+ rlwinm r3,r3,0,0xf0
+ li r4,0x30
+ cmpwr3,r4
+ bge 2f
+
mfspr r8,L1CSR2
orisr8,r8,(L1CSR2_DCWS)@h
mtspr L1CSR2,r8
+2:
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
--
1.7.0.4
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