Nand write from uboot
Hello all, I'm using the evaluation board for davinci. I'm using uboot 2013 because the project started 10 years ago. I want to write to the NAND from u-boot code. I saw there is a driver for davinci in davinci_nand.c. How to write in the nand from u-boot code ? I need to write in a block (page) of NAND. [image: image.png] I attached the source code for driver of davinci nand . Thank you for your answers Best regards, Aubin davinci_nand.c Description: Binary data
Aw: Nand write from uboot
Hi, this is how i do nand-write on a mediatek board, if your driver is capable with mtd it should be similar: https://www.fw-web.de/dokuwiki/doku.php?id=en:bpi-r3:uboot#nand_flash HTH regards Frank
Don't use sudo in python tests
Hello Simon, As described in doc/develop/py_testing.doc using sudo in python tests should be avoided. * users building U-Boot may not be sudoers * running code as sudo comes with a risk You added sudo in test/py/tests/test_ut.py Can we use virt-make-fs here? Best regards Heinrich
Re: [PATCH v3 0/6] eficonfig: add UEFI Secure Boot key maintenance interface
On 10/14/22 08:56, Masahisa Kojima wrote: This series adds the UEFI Secure Boot key maintenance interface to the eficonfig command. User can enroll and delete the PK, KEK, db and dbx. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/eficonfig_sbkey_v3 [Major Changes] - rebased on top of u-boot/master Masahisa Kojima (6): eficonfig: refactor eficonfig_select_file_handler() eficonfig: expose append entry function eficonfig: add UEFI Secure Boot Key enrollment interface eficonfig: add "Show/Delete Signature Database" menu entry test/eficonfig: support secure boot key maintenance menu test: add test for eficonfig secure boot key management cmd/Makefile | 3 + cmd/eficonfig.c | 48 +- cmd/eficonfig_sbkey.c | 751 ++ include/efi_config.h | 10 + test/py/tests/test_eficonfig/conftest.py | 84 +- test/py/tests/test_eficonfig/defs.py | 14 + .../py/tests/test_eficonfig/test_eficonfig.py | 4 +- .../test_eficonfig/test_eficonfig_sbkey.py| 472 +++ 8 files changed, 1360 insertions(+), 26 deletions(-) create mode 100644 cmd/eficonfig_sbkey.c create mode 100644 test/py/tests/test_eficonfig/defs.py create mode 100644 test/py/tests/test_eficonfig/test_eficonfig_sbkey.py Python tests with this series fail. See https://source.denx.de/u-boot/custodians/u-boot-efi/-/jobs/518130 Please, run 'make tests' before resubmitting. Best regards Heinrich
[BUG] poweroff command in ./u-boot -T -l causes SIG_SEGV
Hello Simon, when running ./u-boot -T -l and issuing the poweroff command a crash occurs: os_exit() results in std::ostream::flush() calling U-Boot's fflush with file = -138447008 (or any other negative number) Man fflush shows the following definition: int fflush(FILE *stream); U-Boot's fflush() is defined as void fflush(int file); The pointer FILE *stream is truncated to int which may result in a negative number when invoking U-Boot's fflush() but anyway we want std::ostream::flush() to invoke glibc's fflush(). Can we ensure correct linking or do we have to rename fflush()? Best regards Heinrich
[PATCH 1/1] cli: always show cursor
We may enter the command line interface in a state where on the remote
console the cursor is not shown. Send an escape sequence to enable it.
Signed-off-by: Heinrich Schuchardt
---
common/main.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/main.c b/common/main.c
index 682f3359ea..4e7e7b17d6 100644
--- a/common/main.c
+++ b/common/main.c
@@ -7,6 +7,7 @@
/* #define DEBUG */
#include
+#include
#include
#include
#include
@@ -66,6 +67,9 @@ void main_loop(void)
autoboot_command(s);
+ if (!CONFIG_IS_ENABLED(DM_VIDEO) || CONFIG_IS_ENABLED(VIDEO_ANSI))
+ printf(ANSI_CURSOR_SHOW "\n");
+
cli_loop();
panic("No CLI available");
}
--
2.37.2
Re: Nand write from uboot
Thanks for frank your answer. > On 22 Oct 2022, at 9:57 AM, Frank Wunderlich wrote: > > Hi, > > this is how i do nand-write on a mediatek board, if your driver is capable > with mtd it should be similar: > > https://www.fw-web.de/dokuwiki/doku.php?id=en:bpi-r3:uboot#nand_flash > > HTH > > regards Frank I have forgotten to mention how to read inside NAND from uboot code too. The goal is the make a patch using da Vinci driver.
[PATCH 1/1] console: file should always be non-negative
We use the parameter file in console function to choose from an array after
checking against MAX_FILES but we never check if the value of file is
negative.
Running ./u-boot -T -l and issuing the poweroff command has resulted in
crashes because
os_exit() results in std::ostream::flush() calling U-Boot's fflush with
file being a pointer which when converted to int may be represented by a
negative number.
This shows that checking against MAX_FILES is not enough we have to ensure
that the file argument is always positive.
Signed-off-by: Heinrich Schuchardt
---
common/console.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/console.c b/common/console.c
index 0c9bf66c3f..10ab361d00 100644
--- a/common/console.c
+++ b/common/console.c
@@ -497,7 +497,7 @@ int serial_printf(const char *fmt, ...)
int fgetc(int file)
{
- if (file < MAX_FILES) {
+ if ((unsigned int)file < MAX_FILES) {
/*
* Effectively poll for input wherever it may be available.
*/
@@ -530,7 +530,7 @@ int fgetc(int file)
int ftstc(int file)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
return console_tstc(file);
return -1;
@@ -538,20 +538,20 @@ int ftstc(int file)
void fputc(int file, const char c)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
console_putc(file, c);
}
void fputs(int file, const char *s)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
console_puts(file, s);
}
#ifdef CONFIG_CONSOLE_FLUSH_SUPPORT
void fflush(int file)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
console_flush(file);
}
#endif
--
2.37.2
[PATCH 1/1] console: file should always be non-negative
We use the parameter file in console function to choose from an array after
checking against MAX_FILES but we never check if the value of file is
negative.
Running ./u-boot -T -l and issuing the poweroff command has resulted in
crashes because
os_exit() results in std::ostream::flush() calling U-Boot's fflush with
file being a pointer which when converted to int may be represented by a
negative number.
This shows that checking against MAX_FILES is not enough we have to ensure
that the file argument is always positive.
Signed-off-by: Heinrich Schuchardt
---
common/console.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/console.c b/common/console.c
index 0c9bf66c3f..10ab361d00 100644
--- a/common/console.c
+++ b/common/console.c
@@ -497,7 +497,7 @@ int serial_printf(const char *fmt, ...)
int fgetc(int file)
{
- if (file < MAX_FILES) {
+ if ((unsigned int)file < MAX_FILES) {
/*
* Effectively poll for input wherever it may be available.
*/
@@ -530,7 +530,7 @@ int fgetc(int file)
int ftstc(int file)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
return console_tstc(file);
return -1;
@@ -538,20 +538,20 @@ int ftstc(int file)
void fputc(int file, const char c)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
console_putc(file, c);
}
void fputs(int file, const char *s)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
console_puts(file, s);
}
#ifdef CONFIG_CONSOLE_FLUSH_SUPPORT
void fflush(int file)
{
- if (file < MAX_FILES)
+ if ((unsigned int)file < MAX_FILES)
console_flush(file);
}
#endif
--
2.37.2
Re: [PATCH v2 1/4] riscv: dts: Update memory configuration
On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> In the v2022.10 Icicle reference design, the seg registers are going to be
Hey Padmarao,
Since the release was done the other day I think that this should be
s/are going to be/have been
> changed, resulting in a required change to the memory map.
> A small 4MB reservation is made at the end of 32-bit DDR to provide some
> memory for the HSS to use, so that it can cache its payload between
> reboots of a specific context.
>
> Co-developed-by: Conor Dooley
> Signed-off-by: Conor Dooley
> Signed-off-by: Padmarao Begari
> Reviewed-by: Conor Dooley
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70
> 1 file changed, 14 insertions(+), 56 deletions(-)
>
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> index 287ef3d23b..876c475069 100644
> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> - * Copyright (C) 2021 Microchip Technology Inc.
> + * Copyright (C) 2021-2022 Microchip Technology Inc.
> * Padmarao Begari
> */
>
> @@ -28,70 +28,28 @@
> timebase-frequency = ;
> };
FWIW I think we should add the compatible that the linux dt has,
signifying that this memory layout is compatible with the v2022.10
release and later (w/ appropriate line-wrapping ofc):
compatible = "microchip,mpfs-icicle-reference-rtlv2210",
"microchip,mpfs-icicle-kit", "microchip,mpfs";
Other than that:
Reviewed-by: Conor Dooley
>
> - reserved-memory {
> - ranges;
> - #size-cells = <2>;
> - #address-cells = <2>;
> -
> - fabricbuf0: fabricbuf@0 {
> - compatible = "shared-dma-pool";
> - reg = <0x0 0xae00 0x0 0x200>;
> - label = "fabricbuf0-ddr-c";
> - };
> -
> - fabricbuf1: fabricbuf@1 {
> - compatible = "shared-dma-pool";
> - reg = <0x0 0xc000 0x0 0x800>;
> - label = "fabricbuf1-ddr-nc";
> - };
> -
> - fabricbuf2: fabricbuf@2 {
> - compatible = "shared-dma-pool";
> - reg = <0x0 0xd800 0x0 0x800>;
> - label = "fabricbuf2-ddr-nc-wcb";
> - };
> - };
> -
> - udmabuf0 {
> - compatible = "ikwzm,u-dma-buf";
> - device-name = "udmabuf-ddr-c0";
> - minor-number = <0>;
> - size = <0x0 0x200>;
> - memory-region = <&fabricbuf0>;
> - sync-mode = <3>;
> - };
> -
> - udmabuf1 {
> - compatible = "ikwzm,u-dma-buf";
> - device-name = "udmabuf-ddr-nc0";
> - minor-number = <1>;
> - size = <0x0 0x800>;
> - memory-region = <&fabricbuf1>;
> - sync-mode = <3>;
> - };
> -
> - udmabuf2 {
> - compatible = "ikwzm,u-dma-buf";
> - device-name = "udmabuf-ddr-nc-wcb0";
> - minor-number = <2>;
> - size = <0x0 0x800>;
> - memory-region = <&fabricbuf2>;
> - sync-mode = <3>;
> - };
> -
> ddrc_cache_lo: memory@8000 {
> device_type = "memory";
> - reg = <0x0 0x8000 0x0 0x2e00>;
> - clocks = <&clkcfg CLK_DDRC>;
> + reg = <0x0 0x8000 0x0 0x4000>;
> status = "okay";
> };
>
> ddrc_cache_hi: memory@10 {
> device_type = "memory";
> - reg = <0x10 0x0 0x0 0x4000>;
> - clocks = <&clkcfg CLK_DDRC>;
> + reg = <0x10 0x4000 0x0 0x4000>;
> status = "okay";
> };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + hss_payload: region@BFC0 {
> + reg = <0x0 0xBFC0 0x0 0x40>;
> + no-map;
> + };
> + };
> };
>
> &uart1 {
> --
> 2.25.1
>
[PATCH] imx28-xea: Add missing imx28-lwe.dtsi
From: Fabio Estevam
The following build error is seen when building imx28_xea_defconfig:
arch/arm/dts/.imx28-xea.dtb.pre.tmp:8:10: fatal error: imx28-lwe.dtsi: No such
file or directory
This happens because commit ebcca534f557 ("imx28: synchronise device tree
with linux") missed to import the imx28-lwe.dtsi file from Linux.
Fix it by importing the file from Linux 6.1-rc1.
Fixes: ebcca534f557 ("imx28: synchronise device tree with linux")
Signed-off-by: Fabio Estevam
---
This applies against u-boot-imx master-next branch.
arch/arm/dts/imx28-lwe.dtsi | 170
1 file changed, 170 insertions(+)
create mode 100644 arch/arm/dts/imx28-lwe.dtsi
diff --git a/arch/arm/dts/imx28-lwe.dtsi b/arch/arm/dts/imx28-lwe.dtsi
new file mode 100644
index ..bb971e660db8
--- /dev/null
+++ b/arch/arm/dts/imx28-lwe.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+
+/ {
+ aliases {
+ spi2 = &ssp3;
+ };
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait
console=ttyAMA0,115200 panic=1";
+ };
+
+ memory@4000 {
+ reg = <0x4000 0x0800>;
+ };
+
+ reg_3v3: regulator-reg-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_usb_5v: regulator-reg-usb-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ reg_fec_3v3: regulator-reg-fec-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clks 53>;
+ assigned-clock-rates = <1200>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&spi3_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__SSP3_D4
+ MX28_PAD_AUART2_TX__SSP3_D5
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ >;
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a>;
+ bus-width = <8>;
+ vmmc-supply = <®_3v3>;
+ non-removable;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&ssp3 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <4000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x8>;
+ read-only;
+ };
+
+ partition@8 {
+ label = "env0";
+ reg = <0x8 0x1>;
+ };
+
+ partition@9 {
+ label = "env1";
+ reg = <0x9 0x1>;
+ };
+
+ partition@10 {
+ label = "kernel";
+ reg = <0x10 0x40>;
+ };
+
+ partition@50 {
+ label = "swupdate";
+ reg = <0x50 0x80>;
+ };
+ };
+ };
+};
+
+&usb0 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+
Re: [PATCH v2 2/4] riscv: dts: Add QSPI NAND device node
On Fri, Oct 21, 2022 at 12:29:20PM +0530, Padmarao Begari wrote:
> Add QSPI NAND device node to the Microchip PolarFire SoC
> Icicle kit device tree.
>
> The Winbond NAND flash memory can be connected to the
> Icicle Kit by using the Mikroe Flash 5 click board and
> the Pi 3 Click shield.
>
> Signed-off-by: Padmarao Begari
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> index 876c475069..e1fbedc507 100644
> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> @@ -18,6 +18,7 @@
> aliases {
> serial1 = &uart1;
> ethernet0 = &mac1;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -113,3 +114,17 @@
> ti,fifo-depth = <0x1>;
> };
> };
> +
> +&qspi {
> + status = "okay";
> + num-cs = <1>;
Convention suggests a blank line before children, right?
Other than that, LGTM..
Reviewed-by: Conor Dooley
> + flash0: flash@0 {
> + compatible = "spi-nand";
> + reg = <0x0>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <2000>;
> + spi-cpol;
> + spi-cpha;
> + };
> +};
> --
> 2.25.1
>
Re: [PATCH v2 3/4] spi: Add Microchip PolarFire SoC QSPI driver
On Fri, Oct 21, 2022 at 12:29:21PM +0530, Padmarao Begari wrote: > Add QSPI driver code for the Microchip PolarFire SoC. > This driver supports the QSPI standard, dual and quad > mode interfaces. > > Co-developed-by: Naga Sureshkumar Relli > Signed-off-by: Naga Sureshkumar Relli > Signed-off-by: Padmarao Begari > --- > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/microchip_coreqspi.c | 505 +++ > 3 files changed, 512 insertions(+) > create mode 100644 drivers/spi/microchip_coreqspi.c > > +/* QSPI ready time out value */ > +#define TIMEOUT_MS (1000 * 60) Hey Padmarao, just zipping through and cross referencing against the linux driver.. Why's this a 60 * 1000 when linux times out after 500 ms? Other than that, things look identical modulo the required interrupt and clocking changes for U-Boot. Reviewed-by: Conor Dooley Thanks, Conor.
[PATCH] imx8qm-cgtqmx8: Introduce imx8qm-cgtqmx8-u-boot.dtsi
From: Fabio Estevam
Since commit 02682bf82568 ("imx: imx8qm: cgtqmx8: switch to binman")
the following build error is seen:
arch/arm/dts/.imx8qm-cgtqmx8.dtb.pre.tmp:15:10: fatal error:
imx8qm-u-boot.dtsi: No such file or directory
This commit included "imx8qm-u-boot.dtsi", but this file does not exist.
Fix the problem by introducing the board specific imx8qm-cgtqmx8-u-boot.dtsi
instead.
Fixes: 02682bf82568 ("imx: imx8qm: cgtqmx8: switch to binman")
Signed-off-by: Fabio Estevam
---
Oliver,
This applies against u-boot-imx master-next branch:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/commits/master-next
I don't have access to this board, so I cannot test it.
I just tested that it builds fine now.
arch/arm/dts/imx8qm-cgtqmx8-u-boot.dtsi | 164
arch/arm/dts/imx8qm-cgtqmx8.dts | 2 +-
2 files changed, 165 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8qm-cgtqmx8-u-boot.dtsi
diff --git a/arch/arm/dts/imx8qm-cgtqmx8-u-boot.dtsi
b/arch/arm/dts/imx8qm-cgtqmx8-u-boot.dtsi
new file mode 100644
index ..756762d6c7f5
--- /dev/null
+++ b/arch/arm/dts/imx8qm-cgtqmx8-u-boot.dtsi
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018, 2021 NXP
+ */
+
+&{/imx8qm-pm} {
+
+ u-boot,dm-spl;
+};
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&pd_dma {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+ u-boot,dm-spl;
+};
+
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
index 919d00644ff3..26e435dc96a7 100644
--- a/arch/arm/dts/imx8qm-cgtqmx8.dts
+++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
@@ -12,7 +12,7 @@
/memreserve/ 0x8000 0x0002;
#include "fsl-imx8qm.dtsi"
-#include "imx8qm-u-boot.dtsi"
+#include "imx8qm-cgtqmx8-u-boot.dtsi"
/ {
model = "Congatec QMX8 Qseven series";
--
2.25.1
Re: Don't use sudo in python tests
On Sat, Oct 22, 2022 at 10:24:33AM +0200, Heinrich Schuchardt wrote: > Hello Simon, > > As described in doc/develop/py_testing.doc using sudo in python tests > should be avoided. > > * users building U-Boot may not be sudoers > * running code as sudo comes with a risk > > You added sudo in test/py/tests/test_ut.py > > Can we use virt-make-fs here? Note that virt-make-fs is only suitable for trivial cases as it's otherwise too slow. This is possibly one of the cases where it's too slow. -- Tom signature.asc Description: PGP signature
Re: [PATCH] imx8mn-venice-u-boot: Fix broken boot
Hi Stefano,
On Fri, Oct 21, 2022 at 8:50 AM wrote:
>
> > When the imx8mm.dtsi file was pulled in from Linux, the UARTs
> > were moved into an spba sub-node which wasn't being included
> > in the SPL device tree. This meant the references to the UART
> > weren't being handled properly and when booting the system would
> > constantly reboot. Fix this by adding the spba node to the spl
> > device tree to restore normal booting.
> > Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot
> > board.
> > Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")
> > Signed-off-by: Fabio Estevam
> > Reviewed-by: Michael Trimarchi
> Applied to u-boot-imx, master, thanks !
Thanks, but this one is already present in U-Boot 2022.10 final.
Tom applied it directly to avoid the boot regression.
It seems that the u-boot-imx base is not up to date.
Re: [BUG] poweroff command in ./u-boot -T -l causes SIG_SEGV
> Date: Sat, 22 Oct 2022 11:14:34 +0200 > From: Heinrich Schuchardt > > Hello Simon, > > when running ./u-boot -T -l and issuing the poweroff command a crash occurs: > > os_exit() results in std::ostream::flush() calling U-Boot's fflush with > file = -138447008 (or any other negative number) > > Man fflush shows the following definition: > > int fflush(FILE *stream); > > U-Boot's fflush() is defined as > > void fflush(int file); > > The pointer FILE *stream is truncated to int which may result in a > negative number when invoking U-Boot's fflush() but anyway we want > std::ostream::flush() to invoke glibc's fflush(). > > Can we ensure correct linking or do we have to rename fflush()? Probably have to rename it. The name is reserved by the ISO C standard, at least when building in a non-freestanding environment. And the sandbox stuff means that U-Boot isn't always compiled in a free-standing environment. I do wonder though how you end up building the sandbox with a C++ compiler. There is some logic in the build system (inherited from the Linux kernel?) to build host tools with C++. But I'd hope the sandbox doesn't use that.
Re: [PATCH v2 3/8] imxrt1050: synchronise device tree with linux
Hi Jesse
Sorry, I kinda missed your reply and imx maintainership was quiet for quite
some time. I am now preparing a v3
taking your feedback into account. Thanks!
On Sun, 2022-08-28 at 02:50 -0400, Jesse Taube wrote:
>
>
> On 8/26/22 14:31, Marcel Ziswiler wrote:
> > From: Marcel Ziswiler
> >
> > Synchronise device tree with linux v6.0-rc1.
> >
> > Signed-off-by: Marcel Ziswiler
> >
> > ---
> >
> > Changes in v2:
> > - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio.
> > Thanks!
> >
> > arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 155 ++--
> > arch/arm/dts/imxrt1050-evk.dts | 257 +++-
> > arch/arm/dts/imxrt1050-pinfunc.h | 2 +-
> > arch/arm/dts/imxrt1050.dtsi | 168 ++---
> > include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
> > 5 files changed, 248 insertions(+), 343 deletions(-)
> >
> > diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > index 617cece448a..7db53b19c2f 100644
> > --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
> > @@ -4,6 +4,8 @@
> > * Author(s): Giulio Benetti
> > */
> >
> > +#include
> > +
> #include "imxrt1050-pinfunc.h"
Okay.
> > / {
> > chosen {
> > u-boot,dm-spl;
> diff says `tick-timer = &gpt;` its important for boot
Okay.
> > @@ -15,6 +17,52 @@
> >
> > soc {
> > u-boot,dm-spl;
> > +
> > + semc@402f {
> > + compatible = "fsl,imxrt-semc";
> > + clocks = <&clks IMXRT1050_CLK_SEMC>;
> > + pinctrl-0 = <&pinctrl_semc>;
> > + pinctrl-names = "default";
> > + reg = <0x402f 0x4000>;
> > + status = "okay";
> > + u-boot,dm-spl;
> I dont think this part under should go here tell me if im wrong. It
> should be move outside as a reference.
Not sure what you mean as this is the U-Boot specific device tree include file
after all.
> > + /*
> > + * Memory configuration from sdram datasheet
> > IS42S16160J-6BLI
> > + */
> > + fsl,sdram-mux = /bits/ 8 > + MUX_CSX0_SDRAM_CS1
> > + 0
> > + 0
> > + 0
> > + 0>;
> > + fsl,sdram-control = /bits/ 8 > + BL_8
> > + COL_9BITS
> > + CL_3>;
> > + fsl,sdram-timing = /bits/ 8 <0x2
> > + 0x2
> > + 0x9
> > + 0x1
> > + 0x5
> > + 0x6
> > +
> > + 0x20
> > + 0x09
> > + 0x01
> > + 0x00
> > +
> > + 0x04
> > + 0x0A
> > + 0x21
> > + 0x50>;
> > +
> > + bank1: bank@0 {
> > + fsl,base-address = <0x8000>;
> > + fsl,memory-size = ;
> > + u-boot,dm-spl;
> > + };
> > + };
> > };
> > };
> >
> > @@ -50,7 +98,7 @@
> > u-boot,dm-spl;
> > };
> >
> > -&gpt1 {
> > +&gpt {
> Add diff:
> clocks = <&osc>;
> compatible = "fsl,imxrt-gpt";
> status = "okay";
Okay.
> > u-boot,dm-spl;
> > };
> >
> > @@ -58,33 +106,108 @@
> > u-boot,dm-spl;
> > };
> >
> > -&semc {
> > - u-boot,dm-spl;
> > -
> > - bank1: bank@0 {
> > - u-boot,dm-spl;
> > - };
> > -};
> > -
> > &iomuxc {
> > u-boot,dm-spl;
> >
> > imxrt1050-evk {drop unneeded node ^^^
> > u-boot,dm-spl;
> > - pinctrl_lpuart1: lpuart1grp {
> > - u-boot,dm-spl;
> > - };
> >
> > pinctrl_semc: semcgrp {
> > - u-boot,dm-spl;
> > - };
> > -
> > - pinctrl_usdhc0: usdhc0grp {
> > + fsl,pins =
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
Hi Fabio
On Sat, 2022-10-22 at 08:22 -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> The following build error is seen when building imx28_xea_defconfig:
>
> arch/arm/dts/.imx28-xea.dtb.pre.tmp:8:10: fatal error: imx28-lwe.dtsi: No
> such file or directory
>
> This happens because commit ebcca534f557 ("imx28: synchronise device tree
> with linux") missed to import the imx28-lwe.dtsi file from Linux.
Thanks for this fix and sorry about that.
> Fix it by importing the file from Linux 6.1-rc1.
>
> Fixes: ebcca534f557 ("imx28: synchronise device tree with linux")
> Signed-off-by: Fabio Estevam
Reviewed-by: Marcel Ziswiler
> ---
> This applies against u-boot-imx master-next branch.
>
> arch/arm/dts/imx28-lwe.dtsi | 170
> 1 file changed, 170 insertions(+)
> create mode 100644 arch/arm/dts/imx28-lwe.dtsi
>
> diff --git a/arch/arm/dts/imx28-lwe.dtsi b/arch/arm/dts/imx28-lwe.dtsi
> new file mode 100644
> index ..bb971e660db8
> --- /dev/null
> +++ b/arch/arm/dts/imx28-lwe.dtsi
> @@ -0,0 +1,170 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright 2021
> + * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
> + */
> +
> +/dts-v1/;
> +#include "imx28.dtsi"
> +
> +/ {
> + aliases {
> + spi2 = &ssp3;
> + };
> +
> + chosen {
> + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait
> console=ttyAMA0,115200 panic=1";
> + };
> +
> + memory@4000 {
> + reg = <0x4000 0x0800>;
> + };
> +
> + reg_3v3: regulator-reg-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + };
> +
> + reg_usb_5v: regulator-reg-usb-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_vbus";
> + regulator-min-microvolt = <500>;
> + regulator-max-microvolt = <500>;
> + };
> +
> + reg_fec_3v3: regulator-reg-fec-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "fec-phy";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + };
> +};
> +
> +&duart {
> + pinctrl-names = "default";
> + pinctrl-0 = <&duart_pins_a>;
> + status = "okay";
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins_a>;
> + status = "okay";
> +};
> +
> +&saif0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&saif0_pins_a>;
> + #sound-dai-cells = <0>;
> + assigned-clocks = <&clks 53>;
> + assigned-clock-rates = <1200>;
> + status = "okay";
> +};
> +
> +&saif1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&saif1_pins_a>;
> + fsl,saif-master = <&saif0>;
> + #sound-dai-cells = <0>;
> + status = "okay";
> +};
> +
> +&spi3_pins_a {
> + fsl,pinmux-ids = <
> + MX28_PAD_AUART2_RX__SSP3_D4
> + MX28_PAD_AUART2_TX__SSP3_D5
> + MX28_PAD_SSP3_SCK__SSP3_SCK
> + MX28_PAD_SSP3_MOSI__SSP3_CMD
> + MX28_PAD_SSP3_MISO__SSP3_D0
> + MX28_PAD_SSP3_SS0__SSP3_D3
> + MX28_PAD_AUART2_TX__GPIO_3_9
> + >;
> +};
> +
> +&ssp0 {
> + compatible = "fsl,imx28-mmc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_8bit_pins_a>;
> + bus-width = <8>;
> + vmmc-supply = <®_3v3>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&ssp2 {
> + compatible = "fsl,imx28-spi";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi2_pins_a>;
> + status = "okay";
> +};
> +
> +&ssp3 {
> + compatible = "fsl,imx28-spi";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi3_pins_a>;
> + status = "okay";
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <4000>;
> + reg = <0>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "u-boot";
> + reg = <0 0x8>;
> + read-only;
> + };
> +
> + partition@8 {
> + label = "env0";
> + reg = <0x8 0x1>;
> + };
> +
> + partition@9 {
> + label = "env1";
> + reg = <0x9 0x1>;
> + };
> +
> +
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
Hi Fabio
On Sat, Oct 22, 2022 at 3:02 PM Marcel Ziswiler
wrote:
>
> Hi Fabio
>
> On Sat, 2022-10-22 at 08:22 -0300, Fabio Estevam wrote:
> > From: Fabio Estevam
> >
> > The following build error is seen when building imx28_xea_defconfig:
> >
> > arch/arm/dts/.imx28-xea.dtb.pre.tmp:8:10: fatal error: imx28-lwe.dtsi: No
> > such file or directory
> >
> > This happens because commit ebcca534f557 ("imx28: synchronise device tree
> > with linux") missed to import the imx28-lwe.dtsi file from Linux.
>
> Thanks for this fix and sorry about that.
>
> > Fix it by importing the file from Linux 6.1-rc1.
> >
> > Fixes: ebcca534f557 ("imx28: synchronise device tree with linux")
> > Signed-off-by: Fabio Estevam
>
I have seen patches that fix build issues but how they land in the
first place. I mean
CI is used to avoid build regression
Michael
> Reviewed-by: Marcel Ziswiler
>
> > ---
> > This applies against u-boot-imx master-next branch.
> >
> > arch/arm/dts/imx28-lwe.dtsi | 170
> > 1 file changed, 170 insertions(+)
> > create mode 100644 arch/arm/dts/imx28-lwe.dtsi
> >
> > diff --git a/arch/arm/dts/imx28-lwe.dtsi b/arch/arm/dts/imx28-lwe.dtsi
> > new file mode 100644
> > index ..bb971e660db8
> > --- /dev/null
> > +++ b/arch/arm/dts/imx28-lwe.dtsi
> > @@ -0,0 +1,170 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> > +/*
> > + * Copyright 2021
> > + * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
> > + */
> > +
> > +/dts-v1/;
> > +#include "imx28.dtsi"
> > +
> > +/ {
> > + aliases {
> > + spi2 = &ssp3;
> > + };
> > +
> > + chosen {
> > + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait
> > console=ttyAMA0,115200 panic=1";
> > + };
> > +
> > + memory@4000 {
> > + reg = <0x4000 0x0800>;
> > + };
> > +
> > + reg_3v3: regulator-reg-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3V3";
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + };
> > +
> > + reg_usb_5v: regulator-reg-usb-5v {
> > + compatible = "regulator-fixed";
> > + regulator-name = "usb_vbus";
> > + regulator-min-microvolt = <500>;
> > + regulator-max-microvolt = <500>;
> > + };
> > +
> > + reg_fec_3v3: regulator-reg-fec-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fec-phy";
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + };
> > +};
> > +
> > +&duart {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&duart_pins_a>;
> > + status = "okay";
> > +};
> > +
> > +&i2c0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c0_pins_a>;
> > + status = "okay";
> > +};
> > +
> > +&saif0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&saif0_pins_a>;
> > + #sound-dai-cells = <0>;
> > + assigned-clocks = <&clks 53>;
> > + assigned-clock-rates = <1200>;
> > + status = "okay";
> > +};
> > +
> > +&saif1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&saif1_pins_a>;
> > + fsl,saif-master = <&saif0>;
> > + #sound-dai-cells = <0>;
> > + status = "okay";
> > +};
> > +
> > +&spi3_pins_a {
> > + fsl,pinmux-ids = <
> > + MX28_PAD_AUART2_RX__SSP3_D4
> > + MX28_PAD_AUART2_TX__SSP3_D5
> > + MX28_PAD_SSP3_SCK__SSP3_SCK
> > + MX28_PAD_SSP3_MOSI__SSP3_CMD
> > + MX28_PAD_SSP3_MISO__SSP3_D0
> > + MX28_PAD_SSP3_SS0__SSP3_D3
> > + MX28_PAD_AUART2_TX__GPIO_3_9
> > + >;
> > +};
> > +
> > +&ssp0 {
> > + compatible = "fsl,imx28-mmc";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc0_8bit_pins_a>;
> > + bus-width = <8>;
> > + vmmc-supply = <®_3v3>;
> > + non-removable;
> > + status = "okay";
> > +};
> > +
> > +&ssp2 {
> > + compatible = "fsl,imx28-spi";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi2_pins_a>;
> > + status = "okay";
> > +};
> > +
> > +&ssp3 {
> > + compatible = "fsl,imx28-spi";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi3_pins_a>;
> > + status = "okay";
> > +
> > + flash@0 {
> > + compatible = "jedec,spi-nor";
> > + spi-max-frequency = <4000>;
> > + reg = <0>;
> > +
> > + partitions {
> > + compatible = "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + partition@0 {
> > + label = "u-boot";
> > +
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
Hi Michael, On Sat, Oct 22, 2022 at 10:19 AM Michael Nazzareno Trimarchi wrote: > I have seen patches that fix build issues but how they land in the > first place. I mean > CI is used to avoid build regression I am sorry, but I could not understand your message. Care to clarify? Thanks
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
Hi On Sat, Oct 22, 2022 at 3:24 PM Fabio Estevam wrote: > > Hi Michael, > > On Sat, Oct 22, 2022 at 10:19 AM Michael Nazzareno Trimarchi > wrote: > > > I have seen patches that fix build issues but how they land in the > > first place. I mean > > CI is used to avoid build regression > > I am sorry, but I could not understand your message. Care to clarify? > > Thanks On my side the Continuous Integration using gitlab-ci, verify board combinations and test the build. I'm asking if this build breakage happen because those boards are not built. Michael -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH] configs: imx8mn_beacon_fspi: Add config for booting from QSPI
On Sun, Jul 31, 2022 at 8:24 PM Adam Ford wrote:
>
> The imx8mn-beacon SOM has a QSPI part on it connected to the
> FlexSPI controller. Add a defconfig option which supports
> booting from the QSPI NOR flash instead of sd/mmc.
>
> Signed-off-by: Adam Ford
> ---
>
> This won't fully function without this series:
> https://patchwork.ozlabs.org/project/uboot/list/?series=312016
Stefano,
The link above has been replaced with V2 [1]
I confirmed that this applies to u-boot-imx cleanly after V2.
adam
[1] - https://patchwork.ozlabs.org/project/uboot/list/?series=324057
>
> diff --git a/configs/imx8mn_beacon_fspi_defconfig
> b/configs/imx8mn_beacon_fspi_defconfig
> new file mode 100644
> index 00..ecaefd8930
> --- /dev/null
> +++ b/configs/imx8mn_beacon_fspi_defconfig
> @@ -0,0 +1,156 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x4020
> +CONFIG_SYS_MALLOC_LEN=0x200
> +CONFIG_SPL_GPIO=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x2000
> +CONFIG_ENV_OFFSET=0xDE00
> +CONFIG_DM_GPIO=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
> +CONFIG_SPL_TEXT_BASE=0x912000
> +CONFIG_TARGET_IMX8MN_BEACON=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SPL=y
> +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
> +CONFIG_SYS_LOAD_ADDR=0x4048
> +CONFIG_SYS_MEMTEST_START=0x4000
> +CONFIG_SYS_MEMTEST_END=0x4400
> +CONFIG_LTO=y
> +CONFIG_REMAKE_ELF=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_USE_BOOTCOMMAND=y
> +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run
> loadbootscript; then run bootscript; else if run loadimage; then run mmcboot;
> else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
> +CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
> +CONFIG_ARCH_MISC_INIT=y
> +CONFIG_SPL_MAX_SIZE=0x25000
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x95e000
> +CONFIG_SPL_BSS_MAX_SIZE=0x2000
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_STACK=0x187ff0
> +CONFIG_SYS_SPL_MALLOC=y
> +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
> +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4220
> +CONFIG_SYS_SPL_MALLOC_SIZE=0x8
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
> +CONFIG_SPL_I2C=y
> +CONFIG_SPL_POWER=y
> +CONFIG_SPL_WATCHDOG=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +CONFIG_SYS_MAXARGS=64
> +CONFIG_SYS_CBSIZE=2048
> +CONFIG_SYS_PBSIZE=2074
> +# CONFIG_BOOTM_NETBSD is not set
> +CONFIG_SYS_BOOTM_LEN=0x80
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_ERASEENV=y
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PART=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_NOWHERE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=2
> +CONFIG_SYS_MMC_ENV_PART=2
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_USE_ETHPRIME=y
> +CONFIG_ETHPRIME="FEC"
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_CLK_IMX8MN=y
> +CONFIG_CLK_IMX8MN=y
> +CONFIG_USB_FUNCTION_FASTBOOT=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x4280
> +CONFIG_FASTBOOT_BUF_SIZE=0x4000
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_PCA953X=y
> +CONFIG_DM_I2C=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS400_ES_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_MTD=y
> +CONFIG_DM_MTD=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_SPEED=4000
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_PMIC=y
> +# CONFIG_SPL_PMIC_CHILDREN is not set
> +CONFIG_DM_PMIC_BD71837=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_BD71837=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_RESET=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_MXC_UART=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_NXP_FSPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_SPL_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_SYSRESET_WATCHDOG=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +#
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
On Sat, Oct 22, 2022 at 10:31 AM Michael Nazzareno Trimarchi wrote: > On my side the Continuous Integration using gitlab-ci, verify board > combinations > and test the build. I'm asking if this build breakage happen because > those boards > are not built. All boards are built by CI and the build error was reported at: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/517428
[PATCH V2 1/4] configs: imx8mn_beacon: Re-align memory to standard imx8mn settings
The imx8mn_beacon board does not use the same memory map as the reference design from NXP or other imx8mn boards. As such, memory is more limited in SPL. Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases the amount of available meory for the SPL stack. Doing this allows the board to no longer define CONFIG_MALLOC_F_ADDR. Since SYS_LOAD_ADDR also does not align with other boards, move it too. Signed-off-by: Adam Ford --- V2: Rebase on u-boot-imx Depends on: https://patchwork.ozlabs.org/project/uboot/list/?series=324057 https://patchwork.ozlabs.org/project/uboot/list/?series=312020 diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 613945a9ec..5708ba5c69 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -16,10 +16,9 @@ CONFIG_IMX8MN_BEACON_2GB_LPDDR=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 -CONFIG_SYS_LOAD_ADDR=0x4048 +CONFIG_SYS_LOAD_ADDR=0x4200 CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x4400 CONFIG_LTO=y @@ -35,12 +34,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_START_ADDR=0x95 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_STACK=0x98 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4220 diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index cc1583524b..0793db0bd6 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -15,10 +15,9 @@ CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 -CONFIG_SYS_LOAD_ADDR=0x4048 +CONFIG_SYS_LOAD_ADDR=0x4200 CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x4400 CONFIG_LTO=y @@ -34,12 +33,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_START_ADDR=0x95 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_STACK=0x98 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4220 diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index ecaefd8930..6da2182eb3 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -14,10 +14,9 @@ CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 -CONFIG_SYS_LOAD_ADDR=0x4048 +CONFIG_SYS_LOAD_ADDR=0x4200 CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x4400 CONFIG_LTO=y @@ -33,12 +32,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x95e000 +CONFIG_SPL_BSS_START_ADDR=0x95 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x187ff0 +CONFIG_SPL_STACK=0x98 CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4220 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 6faecbde77..930b11b75e 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -13,14 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x184000 - -/* For RAW image gives a error info not panic */ - -#endif /* CONFIG_SPL_BUILD */ - /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ -- 2.34.1
[PATCH V2 2/4] regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled
If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
driver throws a compile error. Fix this by putting the function
to bind children into an if-statement checking for PMIC_CHILDREN.
Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
still permits some read/write functions to access the PMIC in
early startup.
Signed-off-by: Adam Ford
Reviewed-by: Simon Glass
diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
index cb9238972f..fdbbd6f559 100644
--- a/drivers/power/pmic/bd71837.c
+++ b/drivers/power/pmic/bd71837.c
@@ -63,10 +63,11 @@ static int bd71837_bind(struct udevice *dev)
debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
- children = pmic_bind_children(dev, regulators_node, pmic_children_info);
- if (!children)
- debug("%s: %s - no child found\n", __func__, dev->name);
-
+ if (CONFIG_IS_ENABLED(PMIC_CHILDREN)) {
+ children = pmic_bind_children(dev, regulators_node,
pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+ }
/* Always return success for this device */
return 0;
}
--
2.34.1
[PATCH V2 3/4] configs: imx8mn_beacon: Enable SPL_DM_PMIC_BD71837
To properly operate the Nano with LPDDR4 at 1.6GHz, the voltage needs to be adjusted before DDR is initialized. Enable the PMIC in SPL to do this. Signed-off-by: Adam Ford diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 5708ba5c69..4931f836f0 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -120,6 +120,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 0793db0bd6..ae29da 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -124,6 +124,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 6da2182eb3..94d069cbfa 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -125,6 +125,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y CONFIG_DM_REGULATOR_FIXED=y -- 2.34.1
[PATCH V2 4/4] imx: imx8mn-beacon: Fix out of spec voltage
The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.
Signed-off-by: Adam Ford
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index 029f71bc99..9acd916180 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -74,6 +74,38 @@ static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@4b", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic\n");
+ return 0;
+ }
+
+ if (ret != 0)
+ return ret;
+
+ /* decrease RESET key long push time from the default 10s to 10ms */
+ pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+ /* unlock the PMIC regs */
+ pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+ /* increase VDD_SOC to typical value 0.85v before first DRAM access */
+ pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+ /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+ pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+ /* lock the PMIC regs */
+ pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+ return 0;
+}
+
int board_early_init_f(void)
{
/* Claiming pwm pins prevents LCD flicker during startup*/
@@ -107,6 +139,9 @@ void board_init_f(ulong dummy)
enable_tzc380();
+ /* LPDDR4 at 1.6GHz requires a voltage adjustment on the PMIC */
+ power_init_board();
+
/* DDR initialization */
spl_dram_init();
--
2.34.1
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
Hi On Sat, Oct 22, 2022 at 3:35 PM Fabio Estevam wrote: > > On Sat, Oct 22, 2022 at 10:31 AM Michael Nazzareno Trimarchi > wrote: > > > On my side the Continuous Integration using gitlab-ci, verify board > > combinations > > and test the build. I'm asking if this build breakage happen because > > those boards > > are not built. > > All boards are built by CI and the build error was reported at: > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/517428 Should the patches need to be resend if they are not building? so you want to take care of them Michael -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
[PATCH 1/3] imx: imx8mm_beacon: Eliminate a few extras to free up SPL space
There are a few functions which are not essential for use in
SPL, but they take up enough space to make other preferred
features not fit. Remove the extras.
Signed-off-by: Adam Ford
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index a93cc93878..b0e9d918da 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -44,11 +44,6 @@ static void spl_dram_init(void)
ddr_init(&dram_timing);
}
-void spl_board_init(void)
-{
- debug("Normal Boot\n");
-}
-
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index e37ce01c19..f6a1012d8a 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -29,7 +29,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x92
CONFIG_SYS_SPL_MALLOC=y
@@ -88,12 +87,9 @@ CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -113,14 +109,12 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
-CONFIG_SPL_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
--
2.34.1
[PATCH 2/3] imx: imx8mm-beacon: Enable USB booting via SDP
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL. Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode. Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.
Signed-off-by: Adam Ford
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index c94b4ffa4c..00ac413f36 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -13,6 +13,10 @@
};
};
+&aips4 {
+ u-boot,dm-spl;
+};
+
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <2>;
};
@@ -77,12 +81,24 @@
u-boot,dm-spl;
};
+®_usbotg1 {
+
+};
+
&uart2 {
u-boot,dm-spl;
};
+&usbmisc1 {
+ u-boot,dm-spl;
+};
+
&usbotg1 {
- dr_mode="host";
+ u-boot,dm-spl;
+};
+
+&usbphynop1 {
+ u-boot,dm-spl;
};
&usdhc2 {
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index b0e9d918da..a5f337aa17 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -34,6 +34,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC2;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
default:
return BOOT_DEVICE_NONE;
}
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index f6a1012d8a..90a623515e 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -39,6 +39,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
@@ -56,6 +59,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@@ -103,6 +107,8 @@ CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_SPL_PHY=y
+CONFIG_SPL_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
@@ -127,12 +133,13 @@ CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x4040
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
--
2.34.1
[PATCH 3/3] imx: imx8mm-beacon: Move Environment to eMMC partition 2
The downstream U-Boot distributed by Beacon stores the environment in the eMMC and the end of partition 2. This allow the environment to stay on the SOM regardless of the boot source. Signed-off-by: Adam Ford diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 90a623515e..4dd87914b8 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x200 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x40 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" CONFIG_SPL_TEXT_BASE=0x7E1000 @@ -76,7 +76,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" -- 2.34.1
[PATCH] xen: pvblock: Use uclass_probe_all
Also eliminate useless code and variables.
Signed-off-by: Michal Suchanek
---
drivers/xen/pvblock.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c
index 95e298d7dd..4ad548d599 100644
--- a/drivers/xen/pvblock.c
+++ b/drivers/xen/pvblock.c
@@ -818,8 +818,6 @@ static void print_pvblock_devices(void)
void pvblock_init(void)
{
struct driver_info info;
- struct udevice *udev;
- struct uclass *uc;
int ret;
/*
@@ -828,15 +826,12 @@ void pvblock_init(void)
* virtual block devices.
*/
info.name = DRV_NAME;
- ret = device_bind_by_name(gd->dm_root, false, &info, &udev);
+ ret = device_bind_by_name(gd->dm_root, false, &info, NULL);
if (ret < 0)
printf("Failed to bind " DRV_NAME ", ret: %d\n", ret);
/* Bootstrap virtual block devices class driver */
- ret = uclass_get(UCLASS_PVBLOCK, &uc);
- if (ret)
- return;
- uclass_foreach_dev_probe(UCLASS_PVBLOCK, udev);
+ uclass_probe_all(UCLASS_PVBLOCK);
print_pvblock_devices();
}
--
2.38.0
PSCI: prefetch abort with Mainline linux (even with rockchip u-boot)
Hi Kever and Heiko, Rockchip 32-bit SoC, like rv1126 seems to depend on PSCI to bring SMP in linux. With rockchip u-boot and Mainline U-Boot the psci in linux-next triggers the abort. (note that I have added rockchip_smcc and enabled PSCI in u-boot) [0.00] Booting Linux on physical CPU 0xf00 [0.00] Linux version 6.1.0-rc1-00029-gb09e57e6064a (j@j-ThinkPad-E14-Gen-2) (arm-linux-gnueabihf-gcc (GCC) 11.0.1 20210310 (experimental) [master revision 5987d8a79cda1069c774e5c302d5597310270026], GNU ld (Linaro_Binutils-2021.03) 2.36.50.20210310) #12 SMP Sat Oct 22 19:44:56 IST 2022 [0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [0.00] CPU: div instructions available: patching division code [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] OF: fdt: Machine model: Edgeble Neu2 IO Board [0.00] earlycon: uart8250 at MMIO32 0xff57 (options '') [0.00] printk: bootconsole [uart8250] enabled [0.00] Memory policy: Data cache writealloc [0.00] efi: UEFI not found. [0.00] cma: Reserved 64 MiB at 0x7c00 [0.00] Zone ranges: [0.00] DMA [mem 0x-0x2fff] [0.00] Normal empty [0.00] HighMem [mem 0x3000-0x7fff] [0.00] Movable zone start for each node [0.00] Early memory node ranges [0.00] node 0: [mem 0x-0x7fff] [0.00] Initmem setup node 0 [mem 0x-0x7fff] [0.00] psci: probing for conduit method from DT. [0.00] Bad mode in prefetch abort handler detected [0.00] Internal error: Oops - bad mode: 0 [#1] SMP ARM [0.00] Modules linked in: [0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 6.1.0-rc1-00029-gb09e57e6064a #12 [0.00] Hardware name: Generic DT based system [0.00] PC is at 0x133fd468 [0.00] LR is at __invoke_psci_fn_smc+0x38/0x58 [0.00] pc : [<133fd468>]lr : []psr: 61d6 [0.00] sp : c1e01e68 ip : c1e01ec0 fp : 8200 [0.00] r10: c1e01f58 r9 : 7fff r8 : c1e09410 [0.00] r7 : r6 : r5 : r4 : [0.00] r3 : r2 : r1 : r0 : 8400 [0.00] Flags: nZCv IRQs off FIQs off Mode MON_32 ISA ARM Segment none [0.00] Control: 10c5387d Table: 0020406a DAC: c1e09980 [0.00] Register r0 information: non-paged memory [0.00] Register r1 information: NULL pointer [0.00] Register r2 information: NULL pointer [0.00] Register r3 information: NULL pointer [0.00] Register r4 information: NULL pointer [0.00] Register r5 information: NULL pointer [0.00] Register r6 information: NULL pointer [0.00] Register r7 information: NULL pointer [0.00] Register r8 information: non-slab/vmalloc memory [0.00] Register r9 information: non-paged memory [0.00] Register r10 information: non-slab/vmalloc memory [0.00] Register r11 information: non-paged memory [0.00] Register r12 information: non-slab/vmalloc memory [0.00] Process swapper (pid: 0, stack limit = 0x(ptrval)) [0.00] Stack: (0xc1e01e68 to 0xc1e02000) [0.00] 1e60: 8400 [0.00] 1e80: c1e09410 7fff c1e01f58 8200 c1e01ec0 c1e01e68 [0.00] 1ea0: c0eb20f0 133fd468 61d6 c1e09980 c20891c0 c1b1c168 [0.00] 1ec0: c1e01edc c20891c0 c1245ac8 [0.00] 1ee0: ff8005a8 c1d2fca0 eefea2fc c1c93594 eefea2fc c1e09980 [0.00] 1f00: c20891c0 c1b1c168 c1e09410 c1c93a10 eefea2fc c1c939d8 c1d2fbdc [0.00] 1f20: 7fff c1caf854 c1e0afa0 c1c04c44 c1e01f4c c1e01f50 [0.00] 1f40: c1e09980 c198cfec c1e01f9c 8000 c1e09980 [0.00] 1f60: c2089064 0830 410fc075 10c5387d c039de88 c1e01f9c [0.00] 1f80: c1e09980 c1c00420 c1e04ec0 c1e09980 c2089064 0830 410fc075 10c5387d [0.00] 1fa0: c1c00b08 [0.00] 1fc0: c1cc8a6c c1c00420 0051 10c0387d [0.00] 1fe0: 0830 410fc075 10c5387d [0.00] __invoke_psci_fn_smc from 0xc1e01e68 [0.00] Code: bad PC value Any comments? Thanks, Jagan.
Re: [PATCH 1/3] imx: imx8mm_beacon: Eliminate a few extras to free up SPL space
On Sat, Oct 22, 2022 at 11:28 AM Adam Ford wrote: > > There are a few functions which are not essential for use in > SPL, but they take up enough space to make other preferred > features not fit. Remove the extras. > > Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam
Re: [PATCH 2/3] imx: imx8mm-beacon: Enable USB booting via SDP
On Sat, Oct 22, 2022 at 11:28 AM Adam Ford wrote: > > In order to boot over USB, the device tree needs to enable > a few extra nodes in SPL. Since the USB driver has the > ability to detect host/device, the dr_mode can be removed > from the device tree since it needs to act as a device when > booting and OTG is the default mode. Add USB boot support > to spl_board_boot_device and enable the corresponding config > options. > > Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam
Re: [PATCH 3/3] imx: imx8mm-beacon: Move Environment to eMMC partition 2
On Sat, Oct 22, 2022 at 11:28 AM Adam Ford wrote: > > The downstream U-Boot distributed by Beacon stores the environment > in the eMMC and the end of partition 2. This allow the environment > to stay on the SOM regardless of the boot source. > > Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam
Re: [PATCH V2 1/4] configs: imx8mn_beacon: Re-align memory to standard imx8mn settings
On Sat, Oct 22, 2022 at 10:44 AM Adam Ford wrote: > > The imx8mn_beacon board does not use the same memory map as the reference > design from NXP or other imx8mn boards. As such, memory is more limited > in SPL. > > Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases > the amount of available meory for the SPL stack. Doing this allows s/meory/memory > the board to no longer define CONFIG_MALLOC_F_ADDR. > > Since SYS_LOAD_ADDR also does not align with other boards, move it too. > > Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam
Re: [PATCH V2 2/4] regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled
On Sat, Oct 22, 2022 at 10:44 AM Adam Ford wrote: > > If the bd718x7 is required, but PMIC_CHILDREN is disabled, this > driver throws a compile error. Fix this by putting the function > to bind children into an if-statement checking for PMIC_CHILDREN. > > Allowing PMIC_CHILDREN to be disabled in SPL saves some space and > still permits some read/write functions to access the PMIC in > early startup. Cool, that's a good hint. I was not aware of it. Reviewed-by: Fabio Estevam
Re: [PATCH V2 3/4] configs: imx8mn_beacon: Enable SPL_DM_PMIC_BD71837
On Sat, Oct 22, 2022 at 10:44 AM Adam Ford wrote: > > To properly operate the Nano with LPDDR4 at 1.6GHz, the > voltage needs to be adjusted before DDR is initialized. > Enable the PMIC in SPL to do this. > > Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam
Re: [PATCH V2 4/4] imx: imx8mn-beacon: Fix out of spec voltage
On Sat, Oct 22, 2022 at 10:44 AM Adam Ford wrote: > > The DDR is configured for LPDDR4 running at 1.6GHz which requires > the voltage on the PMIC to rise a bit before initializing LPDDR4 > or it will be running out of spec. > > Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
Hi everybody, On 22.10.22 15:44, Michael Nazzareno Trimarchi wrote: Hi On Sat, Oct 22, 2022 at 3:35 PM Fabio Estevam wrote: On Sat, Oct 22, 2022 at 10:31 AM Michael Nazzareno Trimarchi wrote: On my side the Continuous Integration using gitlab-ci, verify board combinations and test the build. I'm asking if this build breakage happen because those boards are not built. All boards are built by CI and the build error was reported at: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/517428 Should the patches need to be resend if they are not building? so you want to take care of them Just to clarify: the broken patches *are* not applied. As pointed by Michael, CI is used to check build *before* applying. What you are looking is my master-next branch, that is patches are applied first to a test branch (master-next) before going to master. If CI is broken, they are simply removed. That is my next step, I have seen that imx28-lwe.dtsi is missing, too. But as patch is not applied, I will kindly ask Marcel to squash Fabio's in his series and repost. Thanks, Stefano Michael
Re: Don't use sudo in python tests
On 10/22/22 08:04, Tom Rini wrote: On Sat, Oct 22, 2022 at 10:24:33AM +0200, Heinrich Schuchardt wrote: Hello Simon, As described in doc/develop/py_testing.doc using sudo in python tests should be avoided. * users building U-Boot may not be sudoers * running code as sudo comes with a risk You added sudo in test/py/tests/test_ut.py Can we use virt-make-fs here? Note that virt-make-fs is only suitable for trivial cases as it's otherwise too slow. This is possibly one of the cases where it's too slow. An easy way to do this is to use fuse2fs/fusefat. --Sean
Re: [PATCH v2] tests: Build correct sandbox configuration on 32bit
On Fri, Oct 21, 2022 at 06:05:51PM -0700, Simon Glass wrote: > Hi, > > On Mon, 17 Oct 2022 at 01:28, Michal Suchánek wrote: > > > > On Sat, Oct 15, 2022 at 10:27:43PM +0200, Heinrich Schuchardt wrote: > > > On 10/15/22 21:46, Simon Glass wrote: > > > > Hi Heinrich, > > > > > > > > On Sat, 15 Oct 2022 at 13:29, Heinrich Schuchardt > > > > wrote: > > > > > > > > > > > > > > > > > > > > Am 15. Oktober 2022 21:24:36 MESZ schrieb Simon Glass > > > > > : > > > > > > Hi Heinrich, > > > > > > > > > > > > On Sat, 15 Oct 2022 at 13:05, Heinrich Schuchardt > > > > > > wrote: > > > > > > > > > > > > > > On 10/15/22 20:39, Simon Glass wrote: > > > > > > > > Hi Heinrich, > > > > > > > > > > > > > > > > On Sat, 15 Oct 2022 at 12:31, Heinrich Schuchardt > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On 10/15/22 19:53, Simon Glass wrote: > > > > > > > > > > Hi Michal, > > > > > > > > > > > > > > > > > > > > On Fri, 14 Oct 2022 at 14:53, Michal Suchanek > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Currently sandbox configuration defautls to 64bit and > > > > > > > > > > > there is no > > > > > > > > > > > automation for building 32bit sandbox on 32bit hosts. > > > > > > > > > > > > > > > > > > > > > > Use _LP64 macro as heuristic for detecting 64bit targets. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Michal Suchanek > > > > > > > > > > > --- > > > > > > > > > > > > > > > > > > > > > > Changes in v2: > > > > > > > > > > > simplify and move detection to kconfig > > > > > > > > > > > > > > > > > > > > > > --- > > > > > > > > > > > arch/sandbox/Kconfig| 18 +++--- > > > > > > > > > > > scripts/Kconfig.include | 4 > > > > > > > > > > > 2 files changed, 7 insertions(+), 15 deletions(-) > > > > > > > > > > > > > > > > > > > > Reviewed-by: Simon Glass > > > > > > > > > > > > > > > > > > > > My only question is whether we can allow building the > > > > > > > > > > 32-bit version > > > > > > > > > > on a 64-bit machine? That would need a separate option I > > > > > > > > > > think, to > > > > > > > > > > say: > > > > > > > > > > > > > > > > > > > > I don't want you to automatically determine HOST_32/64BIT. > > > > > > > > > > Instead, > > > > > > > > > > use 32 (or 64). > > > > > > > > > > > > > > > > > > > > This is along the lines of what Heinrich is saying, except > > > > > > > > > > that I > > > > > > > > > > strongly feel that we must do the right thing by default, > > > > > > > > > > as your > > > > > > > > > > patch does. > > > > > > > > > > > > > > > > > > The whole point of phys_addr_t and phys_size_t is that it can > > > > > > > > > be 64bit > > > > > > > > > or 32bit on ilp32. > > > > > > > > > > > > > > > > > > With this patch we cannot build with CONFIG_PHYS_64BIT=y on > > > > > > > > > ilp32 and > > > > > > > > > that is bad. > > > > > > > > > > > > > > > > > > 32 bit phys_addr_t on lp64 is irrelevant for actual hardware > > > > > > > > > but this is > > > > > > > > > what we currently test with sandbox_defconfig on Gitlab CI. > > > > > > > > > > > > > > > > > > My patch is ending up in the same behavior as Michal's patch > > > > > > > > > except that > > > > > > > > > it allows to have 64bit phys_addr_t on ilp32. > > > > > > > > > > > > > > > > It needs to automatically default to 32 or 64 bit depending on > > > > > > > > the > > > > > > > > host. If the user wants to fiddle with Kconfig to force it to > > > > > > > > the > > > > > > > > other one, that should be possible to. > > > > > > > > > > > > > > > > It looks like your patch requires manual configuration, but > > > > > > > > perhaps I > > > > > > > > just misunderstood it? > > > > > > > > > > > > > > __LP64__ is a symbol defined by the compiler when compiling for > > > > > > > 64bit > > > > > > > and not defined when compiling for 32bit systems. There is nothing > > > > > > > manual about it. > > > > > > > > > > > > > > My patch uses this symbol to replace HOST_32BIT and HOST_64BIT. > > > > > > > > > > > > > > Michal's patch compiles a program tools/bits-per-long.c that ends > > > > > > > up > > > > > > > returning 64 on 64 bit systems (where __LP64__ is defined) and 32 > > > > > > > on 32 > > > > > > > bit systems (where __LP64__ is not defined) and then chooses > > > > > > > HOST_32BIT > > > > > > > and HOST_64BIT accordingly. This part of Michal's patch is not > > > > > > > wrong. > > > > > > > The solution is only overly complicated. > > > > > > > > > > > > > > What has to be chosen manually with both patches is PHYS_64BIT > > > > > > > e.g. by > > > > > > > selecting sandbox64_defconfig instead of sandbox_defconfig. > > > > > > > > > > > > > > Unfortunately Michal did not understand that PHYS_64BIT=y, > > > > > > > HOST_32BIT=y > > > > > > > is a necessary test scenario and introduced an invalid dependency. > > > > > > > > > > > > > > With my patch sandbox64_defconfig on a 32bit system uses 64bit > > > > > > > phys_addr_t. > > > > > > > >
Re: Don't use sudo in python tests
On Sat, Oct 22, 2022 at 02:44:27PM -0400, Sean Anderson wrote: > On 10/22/22 08:04, Tom Rini wrote: > > On Sat, Oct 22, 2022 at 10:24:33AM +0200, Heinrich Schuchardt wrote: > > > Hello Simon, > > > > > > As described in doc/develop/py_testing.doc using sudo in python tests > > > should be avoided. > > > > > > * users building U-Boot may not be sudoers > > > * running code as sudo comes with a risk > > > > > > You added sudo in test/py/tests/test_ut.py > > > > > > Can we use virt-make-fs here? > > > > Note that virt-make-fs is only suitable for trivial cases as it's > > otherwise too slow. This is possibly one of the cases where it's too > > slow. > > An easy way to do this is to use fuse2fs/fusefat. I guess at this point some patches to migrate a test or two over, so we can see how they perform, would be much appreciated. -- Tom signature.asc Description: PGP signature
[PATCH] test: Don't use sudo in unit test
I originally did this with fusefat, but it was unbearably slow. It could be
useful with some optimization work... I switched to mtools instead. I have used
fuse2fs on another project and it worked great.
I didn't test this too throughoughly; I just made sure that the contents were
intact (by using a loopback mount).
Signed-off-by: Sean Anderson
---
test/py/tests/test_ut.py | 44
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 9d42390373..8bd7153ed7 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -21,26 +21,14 @@ def setup_bootflow_image(u_boot_console):
"""Create a 20MB disk image with a single FAT partition"""
cons = u_boot_console
fname = os.path.join(cons.config.source_dir, 'mmc1.img')
+fatpart = os.path.join(cons.config.source_dir, 'mmc1p1.img')
mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
mkdir_cond(mnt)
-u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
-u_boot_utils.run_and_log(cons, 'sudo sfdisk %s' % fname,
- stdin=b'type=c')
-
-loop = None
-mounted = False
-complete = False
try:
-out = u_boot_utils.run_and_log(cons,
- 'sudo losetup --show -f -P %s' % fname)
-loop = out.strip()
-fatpart = '%sp1' % loop
-u_boot_utils.run_and_log(cons, 'sudo mkfs.vfat %s' % fatpart)
-u_boot_utils.run_and_log(
-cons, 'sudo mount -o loop %s %s -o uid=%d,gid=%d' %
-(fatpart, mnt, os.getuid(), os.getgid()))
-mounted = True
+with open(fatpart, 'ab') as part:
+part.truncate(19 * 1024 * 1024)
+u_boot_utils.run_and_log(cons, f'mkfs.vfat {fatpart}')
vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
@@ -78,17 +66,22 @@ label Fedora-Workstation-armhfp-31-1.9
(5.3.7-301.fc31.armv7hl)
dtb_file = os.path.join(mnt, '%s/sandbox.dtb' % dtbdir)
u_boot_utils.run_and_log(
cons, 'dtc -o %s' % dtb_file, stdin=b'/dts-v1/; / {};')
-complete = True
+
+u_boot_utils.run_and_log(cons, ('mcopy', '-bQmsi', fatpart,
+*(os.path.join(mnt, file) for file in
+ (vmlinux, initrd, dtbdir,
'extlinux')),
+'::'))
+
+with open(fname, 'ab') as image:
+image.truncate(20 * 1024 * 1024)
+u_boot_utils.run_and_log(cons, f'sfdisk {fname}',
+ stdin=b'type=c, start=1M, size=19M')
+image.seek(1 * 1024 * 1024)
+with open(fatpart, 'rb') as part:
+image.write(part.read())
except ValueError as exc:
-print('Falled to create image, failing back to prepared copy: %s',
+print('Failed to create image, failing back to prepared copy:',
str(exc))
-finally:
-if mounted:
-u_boot_utils.run_and_log(cons, 'sudo umount %s' % mnt)
-if loop:
-u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
-
-if not complete:
# Use a prepared image since we cannot create one
infname = os.path.join(cons.config.source_dir,
'test/py/tests/bootstd/mmc1.img.xz')
@@ -96,7 +89,6 @@ label Fedora-Workstation-armhfp-31-1.9
(5.3.7-301.fc31.armv7hl)
cons,
['sh', '-c', 'xz -dc %s >%s' % (infname, fname)])
-
@pytest.mark.buildconfigspec('ut_dm')
def test_ut_dm_init(u_boot_console):
"""Initialize data for ut dm tests."""
--
2.37.1
Re: [PATCH] test: Don't use sudo in unit test
On Sat, Oct 22, 2022 at 04:16:49PM -0400, Sean Anderson wrote:
> I originally did this with fusefat, but it was unbearably slow. It could be
> useful with some optimization work... I switched to mtools instead. I have
> used
> fuse2fs on another project and it worked great.
>
> I didn't test this too throughoughly; I just made sure that the contents were
> intact (by using a loopback mount).
>
> Signed-off-by: Sean Anderson
> ---
>
> test/py/tests/test_ut.py | 44
> 1 file changed, 18 insertions(+), 26 deletions(-)
>
> diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
> index 9d42390373..8bd7153ed7 100644
> --- a/test/py/tests/test_ut.py
> +++ b/test/py/tests/test_ut.py
> @@ -21,26 +21,14 @@ def setup_bootflow_image(u_boot_console):
> """Create a 20MB disk image with a single FAT partition"""
> cons = u_boot_console
> fname = os.path.join(cons.config.source_dir, 'mmc1.img')
> +fatpart = os.path.join(cons.config.source_dir, 'mmc1p1.img')
> mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
> mkdir_cond(mnt)
>
> -u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
> -u_boot_utils.run_and_log(cons, 'sudo sfdisk %s' % fname,
> - stdin=b'type=c')
> -
> -loop = None
> -mounted = False
> -complete = False
> try:
> -out = u_boot_utils.run_and_log(cons,
> - 'sudo losetup --show -f -P %s' %
> fname)
> -loop = out.strip()
> -fatpart = '%sp1' % loop
> -u_boot_utils.run_and_log(cons, 'sudo mkfs.vfat %s' % fatpart)
> -u_boot_utils.run_and_log(
> -cons, 'sudo mount -o loop %s %s -o uid=%d,gid=%d' %
> -(fatpart, mnt, os.getuid(), os.getgid()))
> -mounted = True
> +with open(fatpart, 'ab') as part:
> +part.truncate(19 * 1024 * 1024)
> +u_boot_utils.run_and_log(cons, f'mkfs.vfat {fatpart}')
>
> vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
> initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
> @@ -78,17 +66,22 @@ label Fedora-Workstation-armhfp-31-1.9
> (5.3.7-301.fc31.armv7hl)
> dtb_file = os.path.join(mnt, '%s/sandbox.dtb' % dtbdir)
> u_boot_utils.run_and_log(
> cons, 'dtc -o %s' % dtb_file, stdin=b'/dts-v1/; / {};')
> -complete = True
> +
> +u_boot_utils.run_and_log(cons, ('mcopy', '-bQmsi', fatpart,
> +*(os.path.join(mnt, file) for file in
> + (vmlinux, initrd, dtbdir,
> 'extlinux')),
> +'::'))
> +
> +with open(fname, 'ab') as image:
> +image.truncate(20 * 1024 * 1024)
> +u_boot_utils.run_and_log(cons, f'sfdisk {fname}',
> + stdin=b'type=c, start=1M, size=19M')
> +image.seek(1 * 1024 * 1024)
> +with open(fatpart, 'rb') as part:
> +image.write(part.read())
> except ValueError as exc:
> -print('Falled to create image, failing back to prepared copy: %s',
> +print('Failed to create image, failing back to prepared copy:',
>str(exc))
> -finally:
> -if mounted:
> -u_boot_utils.run_and_log(cons, 'sudo umount %s' % mnt)
> -if loop:
> -u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
> -
> -if not complete:
> # Use a prepared image since we cannot create one
> infname = os.path.join(cons.config.source_dir,
> 'test/py/tests/bootstd/mmc1.img.xz')
> @@ -96,7 +89,6 @@ label Fedora-Workstation-armhfp-31-1.9
> (5.3.7-301.fc31.armv7hl)
> cons,
> ['sh', '-c', 'xz -dc %s >%s' % (infname, fname)])
>
> -
> @pytest.mark.buildconfigspec('ut_dm')
> def test_ut_dm_init(u_boot_console):
> """Initialize data for ut dm tests."""
The test still passes and here the run time doesn't change either.
--
Tom
signature.asc
Description: PGP signature
[PATCH] sandbox: Correctly define BITS_PER_LONG
SANDBOX_BITS_PER_LONG is the number of bits in long on the sandbox platform. Signed-off-by: Michal Suchanek --- arch/sandbox/include/asm/types.h | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index c1a5d2af82..5f4b649ee3 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -18,11 +18,7 @@ typedef unsigned short umode_t; /* * Number of bits in a C 'long' on this architecture. */ -#ifdef CONFIG_PHYS_64BIT -#define BITS_PER_LONG 64 -#else /* CONFIG_PHYS_64BIT */ -#define BITS_PER_LONG 32 -#endif /* CONFIG_PHYS_64BIT */ +#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG #ifdef CONFIG_PHYS_64BIT typedef unsigned long long dma_addr_t; -- 2.38.0
[PATCH v3 1/8] vf610: synchronise device tree with linux
From: Marcel Ziswiler Synchronise device tree with linux v6.0-rc1 plus the recent DDR pinmux addition still being in-flight. Signed-off-by: Marcel Ziswiler --- (no changes since v1) arch/arm/dts/vf610-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index 740276431a..b7b7322a2d 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -802,7 +802,6 @@ #define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 #define VF610_PAD_PTA7__VIU_PIX_CLK0x218 0x3AC ALT1 0x1 - #define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 #define VF610_PAD_DDR_A15__DDR_A_150x220 0x000 ALT0 0x0 #define VF610_PAD_DDR_A14__DDR_A_140x224 0x000 ALT0 0x0 @@ -853,4 +852,5 @@ #define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 #define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 #define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 + #endif -- 2.35.1
[PATCH v3 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1
From: Marcel Ziswiler This series synchronises them imx device trees with the upstream Linux kernel (v6.0-rc1). I split it into two parts. This is part 1. It also fixes a few issues as discussed during/after the pre-mature application of my first series [1]. I am not touching kontron-sl-mx6ul as Frieder already took care of those [2]. Feedback welcome. Thanks! [1] https://patchwork.ozlabs.org/project/uboot/cover/20220721132748.1052244-1-mar...@ziswiler.com/ [2] https://patchwork.ozlabs.org/project/uboot/cover/20220823142917.306176-1-frie...@fris.de/ Changes in v3: - Incorporate feedback from Jesse. Changes in v2: - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks! - imx8ulp: Re-added s400_mu device tree node. Marcel Ziswiler (8): vf610: synchronise device tree with linux imxrt1020: fix lpuart issue in common u-boot device tree imxrt1050: synchronise device tree with linux imx8ulp: synchronise device tree with linux imx8mq: synchronise device tree with linux imx8mp: synchronise device tree with linux imx8mn: synchronise device tree with linux imx8mm: synchronise device tree with linux arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 43 ++ arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 12 +- arch/arm/dts/imx8mm-mx8menlo.dts | 4 +- arch/arm/dts/imx8mm-u-boot.dtsi | 2 +- arch/arm/dts/imx8mm-venice-gw700x.dtsi| 24 +- arch/arm/dts/imx8mm-venice-gw7901.dts | 8 +- arch/arm/dts/imx8mm-venice-gw7902.dts | 10 +- arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +- arch/arm/dts/imx8mm-verdin.dtsi | 10 +- arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 2 +- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 2 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn-evk.dtsi | 45 +- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +- arch/arm/dts/imx8mn-venice-gw7902.dts | 8 +- arch/arm/dts/imx8mn-venice-u-boot.dtsi| 2 +- arch/arm/dts/imx8mn.dtsi | 13 +- arch/arm/dts/imx8mp-dhcom-pdk2.dts| 27 +- arch/arm/dts/imx8mp-dhcom-som.dtsi| 20 +- arch/arm/dts/imx8mp-evk.dts | 126 ++-- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48 +- arch/arm/dts/imx8mp-u-boot.dtsi | 2 +- arch/arm/dts/imx8mp-venice-gw74xx.dts | 116 ++-- arch/arm/dts/imx8mp-verdin.dtsi | 14 +- arch/arm/dts/imx8mp.dtsi | 33 +- arch/arm/dts/imx8mq-evk.dts | 43 ++ arch/arm/dts/imx8mq-u-boot.dtsi | 10 +- arch/arm/dts/imx8mq.dtsi | 15 +- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +- arch/arm/dts/imx8ulp-evk.dts | 191 +- arch/arm/dts/imx8ulp-pinfunc.h| 4 +- arch/arm/dts/imx8ulp.dtsi | 564 +- arch/arm/dts/imxrt1020-evk-u-boot.dtsi| 7 +- arch/arm/dts/imxrt1020-evk.dts| 1 - arch/arm/dts/imxrt1050-evk-u-boot.dtsi| 162 - arch/arm/dts/imxrt1050-evk.dts| 257 +--- arch/arm/dts/imxrt1050-pinfunc.h | 2 +- arch/arm/dts/imxrt1050.dtsi | 168 +++--- arch/arm/dts/vf610-pinfunc.h | 2 +- include/dt-bindings/clock/imx8mp-clock.h | 13 +- include/dt-bindings/clock/imx8ulp-clock.h | 49 +- include/dt-bindings/clock/imxrt1050-clock.h | 9 +- include/dt-bindings/interconnect/imx8mm.h | 50 ++ include/dt-bindings/interconnect/imx8mn.h | 41 ++ include/dt-bindings/power/imx8mp-power.h | 15 +- include/dt-bindings/power/imx8ulp-power.h | 26 + include/dt-bindings/reset/imx8mp-reset.h | 50 ++ include/dt-bindings/reset/imx8mq-reset.h | 61 +- include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++ 52 files changed, 1153 insertions(+), 1256 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mm.h create mode 100644 include/dt-bindings/interconnect/imx8mn.h create mode 100644 include/dt-bindings/power/imx8ulp-power.h create mode 100644 include/dt-bindings/reset/imx8mp-reset.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h -- 2.35.1
[PATCH v3 2/8] imxrt1020: fix lpuart issue in common u-boot device tree
From: Marcel Ziswiler
Fix lpuart issue in common U-Boot device tree.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ---
arch/arm/dts/imxrt1020-evk.dts | 1 -
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 9e1b074d2e..7cab486f5f 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -67,9 +67,6 @@
imxrt1020-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
u-boot,dm-spl;
@@ -81,6 +78,10 @@
};
};
+&pinctrl_lpuart1 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index 22ae5ed735..d4d1de4ea8 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1020.dtsi"
-#include "imxrt1020-evk-u-boot.dtsi"
#include "imxrt1020-pinfunc.h"
/ {
--
2.35.1
[PATCH v3 3/8] imxrt1050: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 255 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448..bf40ada234 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,8 +4,12 @@
* Author(s): Giulio Benetti
*/
+#include
+#include "imxrt1050-pinfunc.h"
+
/ {
chosen {
+ tick-timer = &gpt;
u-boot,dm-spl;
};
@@ -15,6 +19,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f {
+ compatible = "fsl,imxrt-semc";
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f 0x4000>;
+ status = "okay";
+ u-boot,dm-spl;
+
+ /*
+* Memory configuration from sdram datasheet
IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0x9
+0x1
+0x5
+0x6
+
+0x20
+0x09
+0x01
+0x00
+
+0x04
+0x0A
+0x21
+0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,41 +100,121 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
+ clocks = <&osc>;
+ compatible = "fsl,imxrt-gpt";
+ status = "okay";
u-boot,dm-spl;
};
&lpuart1 { /* console */
+ compatible = "fsl,imxrt-lpuart";
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
imxrt1050-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1/* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1/* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1/* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1/* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1/* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1/* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1/* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1/* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1/* SEMC_A0 */
+ MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+
[PATCH v3 4/8] imx8ulp: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v2)
Changes in v2:
- imx8ulp: Re-added s400_mu device tree node.
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +-
arch/arm/dts/imx8ulp-evk.dts | 191 +-
arch/arm/dts/imx8ulp-pinfunc.h| 4 +-
arch/arm/dts/imx8ulp.dtsi | 564 +-
include/dt-bindings/clock/imx8ulp-clock.h | 49 +-
include/dt-bindings/power/imx8ulp-power.h | 26 +
include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++
7 files changed, 278 insertions(+), 630 deletions(-)
create mode 100644 include/dt-bindings/power/imx8ulp-power.h
create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 7c1dab2acf..ad264f271e 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -3,7 +3,16 @@
* Copyright 2021 NXP
*/
-&{/soc@0} {
+/ {
+ mu@2702 {
+ compatible = "fsl,imx8ulp-mu";
+ reg = <0 0x2702 0 0x1>;
+ status = "okay";
+ u-boot,dm-spl;
+ };
+};
+
+&soc {
u-boot,dm-spl;
};
@@ -23,10 +32,6 @@
u-boot,dm-spl;
};
-&s400_mu {
- u-boot,dm-spl;
-};
-
&lpuart5 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
index da09ff48ff..33e84c4e9e 100644
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
@@ -8,17 +8,16 @@
#include "imx8ulp.dtsi"
/ {
- model = "FSL i.MX8ULP EVK";
+ model = "NXP i.MX8ULP EVK";
compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
chosen {
stdout-path = &lpuart5;
- bootargs = "console=ttyLP1,115200 earlycon";
};
- usdhc2_pwrseq: usdhc2_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x0 0x8000 0 0x8000>;
};
};
@@ -30,24 +29,25 @@
status = "okay";
};
+&usdhc0 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
&iomuxc1 {
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
- MX8ULP_PAD_PTF14__LPUART5_TX0x03
- MX8ULP_PAD_PTF15__LPUART5_RX0x03
- >;
- };
-
- pinctrl_lpi2c7: lpi2c7grp {
- fsl,pins = <
- MX8ULP_PAD_PTE12__LPI2C7_SCL0x27
- MX8ULP_PAD_PTE13__LPI2C7_SDA0x27
+ MX8ULP_PAD_PTF14__LPUART5_TX0x3
+ MX8ULP_PAD_PTF15__LPUART5_RX0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
- MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
MX8ULP_PAD_PTD10__SDHC0_D0 0x43
@@ -61,163 +61,4 @@
MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
>;
};
-
- pinctrl_usdhc2_pte: usdhc2ptegrp {
- fsl,pins = <
- MX8ULP_PAD_PTE1__SDHC2_D0 0x43
- MX8ULP_PAD_PTE0__SDHC2_D1 0x43
- MX8ULP_PAD_PTE5__SDHC2_D2 0x43
- MX8ULP_PAD_PTE4__SDHC2_D3 0x43
- MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042
- MX8ULP_PAD_PTE3__SDHC2_CMD 0x43
- MX8ULP_PAD_PTE7__PTE7 0x10003
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8ULP_PAD_PTE14__ENET0_MDIO0x43
- MX8ULP_PAD_PTE15__ENET0_MDC 0x43
- MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
- MX8ULP_PAD_PTE17__ENET0_RXER0x43
- MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
- MX8ULP_PAD_PTE20__ENET0_RXD10x43
- MX8ULP_PAD_PTE16__ENET0_TXEN0x43
- MX8ULP_PAD_PTE23__ENET0_TXD00x43
- MX8ULP_PAD_PTE22__ENET0_TXD10x43
- MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043
- MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
- >;
- };
-
- pinctrl_usbotg0_id: otg0idgrp {
- fsl,pins = <
-
[PATCH v3 5/8] imx8mq: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx8mq-evk.dts | 43 +
arch/arm/dts/imx8mq-u-boot.dtsi | 10 ++--
arch/arm/dts/imx8mq.dtsi | 15 +++---
include/dt-bindings/reset/imx8mq-reset.h | 61 +---
4 files changed, 88 insertions(+), 41 deletions(-)
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 99fed35168..82387b9cb8 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -71,12 +71,36 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@@ -386,6 +410,16 @@
status = "okay";
};
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -548,6 +582,15 @@
>;
};
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT0xd6
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index e8b5f83706..e6448ab8ad 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -10,23 +10,23 @@
};
-&{/soc@0} {
+&soc {
u-boot,dm-spl;
};
-&{/soc@0/bus@3000} {
+&aips1 {
u-boot,dm-spl;
};
-&{/soc@0/bus@3040} {
+&aips2 {
u-boot,dm-spl;
};
-&{/soc@0/bus@3080} {
+&aips3 {
u-boot,dm-spl;
};
-&{/soc@0/bus@32c0} {
+&aips4 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 49eadb081b..e9f0cdd10a 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -94,7 +94,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency= <13300>;
+ clock-frequency = <13300>;
clock-output-names = "clk_ext4";
};
@@ -320,7 +320,7 @@
arm,no-tick-in-suspend;
};
- soc@0 {
+ soc: soc@0 {
compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -329,7 +329,7 @@
nvmem-cells = <&imx8mq_uid>;
nvmem-cell-names = "soc_unique_id";
- bus@3000 { /* AIPS1 */
+ aips1: bus@3000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x3000 0x40>;
#address-cells = <1>;
@@ -507,7 +507,7 @@
<0x00030005 0x0053>,
<0x00030006 0x005f>,
<0x00030007 0x0071>;
- #thermal-sensor-cells = <1>;
+ #thermal-sensor-cells = <1>;
};
wdog1: watchdog@3028 {
@@ -784,7 +784,7 @@
};
};
- bus@3040 { /* AIPS2 */
+ aips2:
[PATCH v3 7/8] imx8mn: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +-
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 2 +-
.../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 2 +-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mn-evk.dtsi | 45 ++-
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +--
arch/arm/dts/imx8mn-venice-gw7902.dts | 8 ++--
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 2 +-
arch/arm/dts/imx8mn.dtsi | 13 +++---
include/dt-bindings/interconnect/imx8mn.h | 41 +
11 files changed, 106 insertions(+), 21 deletions(-)
create mode 100644 include/dt-bindings/interconnect/imx8mn.h
diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
index 02f37dcda7..9e82069c94 100644
--- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
@@ -146,7 +146,7 @@
};
&easrc {
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
status = "okay";
};
@@ -182,7 +182,7 @@
&usbotg1 {
vbus-supply = <®_usb_otg_vbus>;
disable-over-current;
- dr_mode="otg";
+ dr_mode = "otg";
status = "okay";
};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 0efa6862eb..5e6018c25b 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -15,7 +15,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index c4ae7ca4f3..8312b64bcc 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -16,7 +16,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 3a9ba8b8c9..88b4e8dc50 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -21,7 +21,7 @@
};
};
-&{/soc@0} {
+&soc {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
index d1f6cccfa0..261c365400 100644
--- a/arch/arm/dts/imx8mn-evk.dtsi
+++ b/arch/arm/dts/imx8mn-evk.dtsi
@@ -47,6 +47,11 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@@ -57,6 +62,25 @@
clock-names = "mclk";
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
@@ -78,7 +102,7 @@
};
&easrc {
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
status = "okay";
};
@@ -183,6 +207,16 @@
};
};
+&sai2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -354,6 +388,15 @@
>;
};
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA00xd6
+ MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA00xd6
+ >;
+ };
+
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SA
[PATCH v3 6/8] imx8mp: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx8mp-dhcom-pdk2.dts | 27 +++--
arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 +---
arch/arm/dts/imx8mp-evk.dts | 126 +++-
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48
arch/arm/dts/imx8mp-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mp-venice-gw74xx.dts | 116 +-
arch/arm/dts/imx8mp-verdin.dtsi | 14 ++-
arch/arm/dts/imx8mp.dtsi| 33 -
include/dt-bindings/clock/imx8mp-clock.h| 13 +-
include/dt-bindings/power/imx8mp-power.h| 15 ++-
include/dt-bindings/reset/imx8mp-reset.h| 50
11 files changed, 284 insertions(+), 180 deletions(-)
create mode 100644 include/dt-bindings/reset/imx8mp-reset.h
diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index c9a481ac9a..408db1c410 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -24,7 +24,6 @@
};
gpio-keys {
- #size-cells = <0>;
compatible = "gpio-keys";
button-0 {
@@ -67,7 +66,7 @@
led {
compatible = "gpio-leds";
- led-5 {
+ led-0 {
color = ;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -76,7 +75,7 @@
pinctrl-names = "default";
};
- led-6 {
+ led-1 {
color = ;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -85,7 +84,7 @@
pinctrl-names = "default";
};
- led-7 {
+ led-2 {
color = ;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -94,7 +93,7 @@
pinctrl-names = "default";
};
- led-8 {
+ led-3 {
color = ;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
@@ -123,10 +122,11 @@
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
compatible = "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ max-speed = <100>;
reg = <7>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
@@ -143,7 +143,6 @@
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
- max-speed = <100>;
};
};
};
@@ -155,3 +154,15 @@
&usb3_1 {
fsl,over-current-active-low;
};
+
+&iomuxc {
+ /*
+* GPIO_A,B,C,D are connected to buttons.
+* GPIO_E,F,H,I are connected to LEDs.
+* GPIO_M is connected to CLKOUT2.
+*/
+ pinctrl-0 = <&pinctrl_hog_base
+&pinctrl_dhcom_g &pinctrl_dhcom_j
+&pinctrl_dhcom_k &pinctrl_dhcom_l
+&pinctrl_dhcom_int>;
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi
b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index 197840d1a6..0f13ee3627 100644
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021-2022 Marek Vasut
*/
@@ -224,10 +224,6 @@
};
&i2c3 {
- /*
-* iMX8MP 1P33A Errata ERR007805
-* I2C is limited to 384 kHz due to SoC bug.
-*/
clock-frequency = <10>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
@@ -393,10 +389,6 @@
};
&i2c4 {
- /*
-* iMX8MP 1P33A Errata ERR007805
-* I2C is limited to 384 kHz due to SoC bug.
-*/
clock-frequency = <10>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
@@ -407,10 +399,6 @@
};
&i2c5 {/* HDMI EDID bus */
- /*
-* iMX8MP 1P33A Errata ERR007805
-* I2C is limited to 384 kHz due to SoC bug.
-*/
clock-frequency = <10>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
@@ -802,8 +790,8 @@
pinctrl_i2c5: dhcom-i2c5-grp {
fsl,pins = <
-
[PATCH v3 8/8] imx8mm: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +-
arch/arm/dts/imx8mm-evk.dtsi | 43 +++
arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 12 +++---
arch/arm/dts/imx8mm-mx8menlo.dts | 4 +-
arch/arm/dts/imx8mm-u-boot.dtsi | 2 +-
arch/arm/dts/imx8mm-venice-gw700x.dtsi| 24 +--
arch/arm/dts/imx8mm-venice-gw7901.dts | 8 ++--
arch/arm/dts/imx8mm-venice-gw7902.dts | 10 ++---
arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +--
arch/arm/dts/imx8mm-verdin.dtsi | 10 -
include/dt-bindings/interconnect/imx8mm.h | 50 +++
11 files changed, 137 insertions(+), 36 deletions(-)
create mode 100644 include/dt-bindings/interconnect/imx8mm.h
diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
index f338a886d8..03266bd90a 100644
--- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@@ -285,14 +285,14 @@
&usbotg1 {
vbus-supply = <®_usbotg1>;
disable-over-current;
- dr_mode="otg";
+ dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
- dr_mode="host";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index c42b966f7a..7d6317d95b 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -75,6 +75,11 @@
linux,autosuspend-period = <125>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
@@ -83,6 +88,25 @@
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
+ };
+
sound-wm8524 {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio";
@@ -346,6 +370,16 @@
status = "okay";
};
+&sai2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -494,6 +528,15 @@
>;
};
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA00xd6
+ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA00xd6
+ >;
+ };
+
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
index b40148d728..9e6170d939 100644
--- a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
+++ b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
@@ -84,42 +84,42 @@
};
reg_buck1: buck1 {
- regulator-min-microvolt = <40>;
+ regulator-min-microvolt = <40>;
regulator-max-microvolt = <180>;
regulator-always-on;
regulator-boot-on;
};
reg_buck2: buck2 {
- regulator-min-microvolt = <40>;
+ regulator-min-microvolt = <40>;
regulator-max-microvolt = <180>;
regulator-always-on;
regulator-boot-on;
};
reg_buck3: buck3 {
- regulator-min-microvolt =
Re: [PATCH] sandbox: Correctly define BITS_PER_LONG
Am 22. Oktober 2022 23:22:01 MESZ schrieb Michal Suchanek : >SANDBOX_BITS_PER_LONG is the number of bits in long on the sandbox >platform. Please, explain in the commit message what this patch is good for. Aren't further patches needed to make use of it? Best regards Heinrich > >Signed-off-by: Michal Suchanek >--- > > arch/sandbox/include/asm/types.h | 6 +- > 1 file changed, 1 insertion(+), 5 deletions(-) > >diff --git a/arch/sandbox/include/asm/types.h >b/arch/sandbox/include/asm/types.h >index c1a5d2af82..5f4b649ee3 100644 >--- a/arch/sandbox/include/asm/types.h >+++ b/arch/sandbox/include/asm/types.h >@@ -18,11 +18,7 @@ typedef unsigned short umode_t; > /* > * Number of bits in a C 'long' on this architecture. > */ >-#ifdefCONFIG_PHYS_64BIT >-#define BITS_PER_LONG 64 >-#else /* CONFIG_PHYS_64BIT */ >-#define BITS_PER_LONG 32 >-#endif/* CONFIG_PHYS_64BIT */ >+#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG > > #ifdefCONFIG_PHYS_64BIT > typedef unsigned long long dma_addr_t;
[PATCH v2 02/16] imx7d: synchronise device tree with linux
From: Marcel Ziswiler Synchronise device tree with linux v6.0-rc1. Signed-off-by: Marcel Ziswiler --- (no changes since v1) include/dt-bindings/reset/imx7-reset.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h index bb92452ffb..a5b35b4754 100644 --- a/include/dt-bindings/reset/imx7-reset.h +++ b/include/dt-bindings/reset/imx7-reset.h @@ -50,3 +50,4 @@ #define IMX7_RESET_NUM 26 #endif + -- 2.35.1
[PATCH v2 00/16] arm: dts: imx: sync device trees with upstream linux kernel part 2
From: Marcel Ziswiler This series synchronises them imx device trees with the upstream Linux kernel (v6.0-rc1). I split it into two parts. This is part 2. It also fixes a few issues as discussed during/after the pre-mature application of my first series [1]. I am not touching kontron-sl-mx6ul as Frieder already took care of those [2]. Feedback welcome. Thanks! [1] https://patchwork.ozlabs.org/project/uboot/cover/20220721132748.1052244-1-mar...@ziswiler.com/ [2] https://patchwork.ozlabs.org/project/uboot/cover/20220823142917.306176-1-frie...@fris.de/ Changes in v2: - Add missing imx28-lwe.dtsi as pointed out by Fabio. Thanks! Marcel Ziswiler (16): imx7ulp: synchronise device tree with linux imx7d: synchronise device tree with linux imx6ul: synchronise device tree with linux imx6ull: synchronise device tree with linux imx6ulz: synchronise device tree with linux imx6sx: synchronise device tree with linux imx6sll: synchronise device tree with linux imx6sl: synchronise device tree with linux imx6qp: synchronise device tree with linux imx6qdl: synchronise device tree with linux imx53: synchronise device tree with linux imx51: synchronise device tree with linux imx28: synchronise device tree with linux imx23: synchronise device tree with linux tbs2910: revert prepare to synchronise device trees with linux imx28: avoid num_cs and spi_max_frequency build errors arch/arm/dts/imx23-evk.dts | 1 - arch/arm/dts/imx23-pinfunc.h| 8 +- arch/arm/dts/imx23-u-boot.dtsi | 7 +- arch/arm/dts/imx23.dtsi | 2 +- arch/arm/dts/imx28-evk.dts | 2 +- arch/arm/dts/imx28-lwe.dtsi | 170 arch/arm/dts/imx28-pinfunc.h| 8 +- arch/arm/dts/imx28-xea-u-boot.dtsi | 2 + arch/arm/dts/imx28-xea.dts | 188 ++-- arch/arm/dts/imx28.dtsi | 20 +- arch/arm/dts/imx51.dtsi | 24 +- arch/arm/dts/imx53-cx9020.dts | 414 arch/arm/dts/imx53-kp.dts | 2 + arch/arm/dts/imx53-m53menlo.dts | 306 -- arch/arm/dts/imx53-pinfunc.h| 11 +- arch/arm/dts/imx53-ppd.dts | 87 +- arch/arm/dts/imx53-usbarmory.dts| 1 - arch/arm/dts/imx53.dtsi | 39 +- arch/arm/dts/imx6q-sabrelite.dts| 11 +- arch/arm/dts/imx6q-tbs2910-u-boot.dtsi | 4 +- arch/arm/dts/imx6qdl-sabrelite.dtsi | 11 +- arch/arm/dts/imx6qp-sabreauto.dts | 7 +- arch/arm/dts/imx6qp-sabresd.dts | 10 +- arch/arm/dts/imx6qp.dtsi| 3 +- arch/arm/dts/imx6sl-evk.dts | 183 ++-- arch/arm/dts/imx6sl-pinfunc.h | 6 +- arch/arm/dts/imx6sl.dtsi| 362 --- arch/arm/dts/imx6sll-evk.dts| 879 +++-- arch/arm/dts/imx6sll-pinfunc.h | 6 +- arch/arm/dts/imx6sll.dtsi | 445 + arch/arm/dts/imx6sx-sabreauto.dts | 623 +--- arch/arm/dts/imx6sx-sdb.dts | 8 +- arch/arm/dts/imx6sx-sdb.dtsi| 56 +- arch/arm/dts/imx6sx-softing-vining-2000.dts | 50 +- arch/arm/dts/imx6sx-udoo-neo.dtsi | 86 +- arch/arm/dts/imx6sx.dtsi| 129 ++- arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi | 2 +- arch/arm/dts/imx6ul-phytec-segin.dtsi | 5 - arch/arm/dts/imx6ul.dtsi| 36 +- arch/arm/dts/imx6ull-colibri.dtsi | 10 +- arch/arm/dts/imx6ull.dtsi | 2 +- arch/arm/dts/imx6ulz.dtsi | 1 - arch/arm/dts/imx7ulp-com-u-boot.dtsi| 2 +- arch/arm/dts/imx7ulp-com.dts| 32 +- arch/arm/dts/imx7ulp-evk.dts| 430 ++--- arch/arm/dts/imx7ulp-pinfunc.h | 990 ++-- arch/arm/dts/imx7ulp.dtsi | 681 +- arch/arm/dts/mxs-pinfunc.h | 8 +- include/dt-bindings/clock/imx6sl-clock.h| 10 +- include/dt-bindings/clock/imx6sll-clock.h | 16 +- include/dt-bindings/clock/imx7ulp-clock.h | 170 ++-- include/dt-bindings/reset/imx7-reset.h | 1 + 52 files changed, 3197 insertions(+), 3370 deletions(-) create mode 100644 arch/arm/dts/imx28-lwe.dtsi -- 2.35.1
[PATCH v2 04/16] imx6ull: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx6ull-colibri.dtsi | 10 +++---
arch/arm/dts/imx6ull.dtsi | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx6ull-colibri.dtsi
b/arch/arm/dts/imx6ull-colibri.dtsi
index 15621e03fa..577a424b0e 100644
--- a/arch/arm/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/dts/imx6ull-colibri.dtsi
@@ -94,7 +94,6 @@
};
&adc1 {
- num-channels = <10>;
vref-supply = <®_module_3v3_avdd>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
@@ -166,7 +165,7 @@
atmel_mxt_ts: touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_atmel_conn>;
+ pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
reg = <0x4a>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 /
INT */
@@ -331,7 +330,6 @@
pinctrl_atmel_conn: atmelconngrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /*
SODIMM 106 */
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /*
SODIMM 107 */
>;
};
@@ -684,6 +682,12 @@
};
&iomuxc_snvs {
+ pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /*
SODIMM 107 */
+ >;
+ };
+
pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /*
SODIMM 93 */
diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
index 9bf67490ac..2bccd45e9f 100644
--- a/arch/arm/dts/imx6ull.dtsi
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -50,7 +50,7 @@
};
/ {
- soc {
+ soc: soc {
aips3: bus@220 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
--
2.35.1
[PATCH v2 03/16] imx6ul: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi | 2 +-
arch/arm/dts/imx6ul-phytec-segin.dtsi | 5
arch/arm/dts/imx6ul.dtsi | 36 +++
3 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
index 3bd6edb42e..301838d2d0 100644
--- a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
@@ -8,7 +8,7 @@
display0 = &lcdif;
};
-&{/soc} {
+&soc {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/imx6ul-phytec-segin.dtsi
b/arch/arm/dts/imx6ul-phytec-segin.dtsi
index 0d4ba9494c..38ea4dcfa2 100644
--- a/arch/arm/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-segin.dtsi
@@ -83,11 +83,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
vref-supply = <®_adc1_vref_3v3>;
- /*
-* driver can not separate a specific channel so we request 4 channels
-* here - we need only the fourth channel
-*/
- num-channels = <4>;
status = "disabled";
};
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index afeec01f65..c95efd1d8c 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -64,20 +64,18 @@
clock-frequency = <69600>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 696000 1275000
- 528000 1175000
- 396000 1025000
- 198000 95
- >;
- fsl,soc-operating-points = <
+ <696000 1275000>,
+ <528000 1175000>,
+ <396000 1025000>,
+ <198000 95>;
+ fsl,soc-operating-points =
/* KHz uV */
- 696000 1275000
- 528000 1175000
- 396000 1175000
- 198000 1175000
- >;
+ <696000 1275000>,
+ <528000 1175000>,
+ <396000 1175000>,
+ <198000 1175000>;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,
<&clks IMX6UL_CLK_PLL2_PFD2>,
@@ -139,7 +137,7 @@
interrupts = ;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -149,6 +147,9 @@
ocram: sram@90 {
compatible = "mmio-sram";
reg = <0x0090 0x2>;
+ ranges = <0 0x0090 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
intc: interrupt-controller@a01000 {
@@ -543,7 +544,7 @@
};
kpp: keypad@20b8000 {
- compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp",
"fsl,imx21-kpp";
+ compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = ;
clocks = <&clks IMX6UL_CLK_KPP>;
@@ -923,7 +924,6 @@
reg = <0x02198000 0x4000>;
interrupts = ;
clocks = <&clks IMX6UL_CLK_ADC1>;
- num-channels = <2>;
clock-names = "adc";
fsl,adck-max-frequency = <3000>, <4000>,
<2000>;
@@ -998,7 +998,7 @@
};
csi: csi@21c4000 {
- compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
+ compatible = "fsl,imx6ul-csi";
reg = <0x021c4000 0x4000>;
interrupts = ;
clocks = <&clks IMX6UL_CLK_CSI>;
@@ -1007,7 +1007,7 @@
};
lcdif: lcdif@21c8000 {
- compatible = "fsl,imx6ul-lcdif",
"fsl,imx28-lcdif";
+
[PATCH v2 05/16] imx6ulz: synchronise device tree with linux
From: Marcel Ziswiler Synchronise device tree with linux v6.0-rc1. Signed-off-by: Marcel Ziswiler --- (no changes since v1) arch/arm/dts/imx6ulz.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imx6ulz.dtsi b/arch/arm/dts/imx6ulz.dtsi index aeb2ddc540..0b5f1a7635 100644 --- a/arch/arm/dts/imx6ulz.dtsi +++ b/arch/arm/dts/imx6ulz.dtsi @@ -16,7 +16,6 @@ /delete-property/ serial7; /delete-property/ spi2; /delete-property/ spi3; - /delete-property/ spi4; }; }; -- 2.35.1
[PATCH v2 08/16] imx6sl: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx6sl-evk.dts | 183 ++--
arch/arm/dts/imx6sl-pinfunc.h| 6 +-
arch/arm/dts/imx6sl.dtsi | 362 ++-
include/dt-bindings/clock/imx6sl-clock.h | 10 +-
4 files changed, 325 insertions(+), 236 deletions(-)
diff --git a/arch/arm/dts/imx6sl-evk.dts b/arch/arm/dts/imx6sl-evk.dts
index 0a90eea170..f16c830f1e 100644
--- a/arch/arm/dts/imx6sl-evk.dts
+++ b/arch/arm/dts/imx6sl-evk.dts
@@ -1,10 +1,6 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+//Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
@@ -16,11 +12,16 @@
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
- memory {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
reg = <0x8000 0x4000>;
};
- backlight {
+ backlight_display: backlight_display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -39,62 +40,62 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- gpio = <&gpio4 0 0>;
- enable-active-high;
- vin-supply = <&swbst_reg>;
- };
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&swbst_reg>;
+ };
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- gpio = <&gpio4 2 0>;
- enable-active-high;
- vin-supply = <&swbst_reg>;
- };
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&swbst_reg>;
+ };
- reg_aud3v: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "wm8962-supply-3v15";
- regulator-min-microvolt = <315>;
- regulator-max-microvolt = <315>;
- regulator-boot-on;
- };
+ reg_aud3v: regulator-aud3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <315>;
+ regulator-max-microvolt = <315>;
+ regulator-boot-on;
+ };
- reg_aud4v: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "wm8962-supply-4v2";
- regulator-min-microvolt = <4325000>;
- regulator-max-microvolt = <4325000>;
- regulator-boot-on;
- };
+ reg_aud4v: regulator-aud4v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
- reg_lcd_3v3: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-nam
[PATCH v2 06/16] imx6sx: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx6sx-sabreauto.dts | 623 +++-
arch/arm/dts/imx6sx-sdb.dts | 8 +-
arch/arm/dts/imx6sx-sdb.dtsi| 56 +-
arch/arm/dts/imx6sx-softing-vining-2000.dts | 50 +-
arch/arm/dts/imx6sx-udoo-neo.dtsi | 86 ++-
arch/arm/dts/imx6sx.dtsi| 129 ++--
6 files changed, 709 insertions(+), 243 deletions(-)
diff --git a/arch/arm/dts/imx6sx-sabreauto.dts
b/arch/arm/dts/imx6sx-sabreauto.dts
index 9643d1fe06..83ee97252f 100644
--- a/arch/arm/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/dts/imx6sx-sabreauto.dts
@@ -1,10 +1,6 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2014 Freescale Semiconductor, Inc.
/dts-v1/;
@@ -14,29 +10,171 @@
model = "Freescale i.MX6 SoloX Sabre Auto Board";
compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
- memory {
+ memory@8000 {
+ device_type = "memory";
reg = <0x8000 0x8000>;
};
- regulators {
- compatible = "simple-bus";
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ user {
+ label = "debug";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc_sd3: regulator-vcc-sd3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_sd3>;
+ regulator-name = "VCC_SD3";
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can_wake: regulator-can-wake {
+ compatible = "regulator-fixed";
+ regulator-name = "can-wake";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can_en: regulator-can-en {
+ compatible = "regulator-fixed";
+ regulator-name = "can-en";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can_wake>;
+ };
+
+ reg_can_stby: regulator-can-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can-stby";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can_en>;
+ };
+
+ reg_cs42888: cs42888_supply {
+ compatible = "regulator-fixed";
+ regulator-name = "cs42888_supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ sound-cs42888 {
+ compatible = "fsl,imx6-sabreauto-cs42888",
+"fsl,imx-audio-cs42888";
+ model = "imx-cs42888";
+ audio-cpu = <&esai>;
+ audio-asrc = <&asrc>;
+ audio-codec = <&cs42888>;
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "Line In Jack",
+ "AIN1R", "Line In Jack",
+ "AIN2L", "Line In Jack",
+ "AIN2R", "Line In Jack";
+ };
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-in;
+ };
+};
+
+&anaclk2 {
+ clock-frequency = <24576000>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
+ <&clks IMX6SX_PLL4_BYPASS>,
+
[PATCH v2 09/16] imx6qp: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx6qp-sabreauto.dts | 7 ++-
arch/arm/dts/imx6qp-sabresd.dts | 10 +-
arch/arm/dts/imx6qp.dtsi | 3 +--
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx6qp-sabreauto.dts
b/arch/arm/dts/imx6qp-sabreauto.dts
index d4caeeb0af..2bb3bfb18e 100644
--- a/arch/arm/dts/imx6qp-sabreauto.dts
+++ b/arch/arm/dts/imx6qp-sabreauto.dts
@@ -47,7 +47,12 @@
};
&pcie {
- status = "disabled";
+ reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
};
&vgen3_reg {
diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts
index f1b9cb104f..f69eec18d8 100644
--- a/arch/arm/dts/imx6qp-sabresd.dts
+++ b/arch/arm/dts/imx6qp-sabresd.dts
@@ -50,6 +50,14 @@
};
};
+&vgen3_reg {
+ regulator-always-on;
+};
+
&pcie {
- status = "disabled";
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
};
diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
index 93b89dc1f5..0503655138 100644
--- a/arch/arm/dts/imx6qp.dtsi
+++ b/arch/arm/dts/imx6qp.dtsi
@@ -77,7 +77,6 @@
};
&fec {
- /delete-property/interrupts-extended;
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
<0 119 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -111,5 +110,5 @@
};
&pcie {
- compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx6qp-pcie";
};
--
2.35.1
[PATCH v2 10/16] imx6qdl: synchronise device tree with linux
From: Marcel Ziswiler Synchronise device tree with linux v6.0-rc1. Signed-off-by: Marcel Ziswiler --- (no changes since v1) arch/arm/dts/imx6q-sabrelite.dts| 11 ++- arch/arm/dts/imx6qdl-sabrelite.dtsi | 11 ++- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/imx6q-sabrelite.dts b/arch/arm/dts/imx6q-sabrelite.dts index 434b1433e7..7c6a2f234c 100644 --- a/arch/arm/dts/imx6q-sabrelite.dts +++ b/arch/arm/dts/imx6q-sabrelite.dts @@ -1,8 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013-2019 Boundary Devices, Inc. -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + */ /dts-v1/; #include "imx6q.dtsi" diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi b/arch/arm/dts/imx6qdl-sabrelite.dtsi index a757817a3c..22f8e2783c 100644 --- a/arch/arm/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi @@ -1,8 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2013-2019 Boundary Devices, Inc. -// Copyright 2012 Freescale Semiconductor, Inc. -// Copyright 2011 Linaro Ltd. +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + */ #include #include -- 2.35.1
[PATCH v2 12/16] imx51: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx51.dtsi | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/imx51.dtsi b/arch/arm/dts/imx51.dtsi
index 7ebb46ce9e..592d9c23a4 100644
--- a/arch/arm/dts/imx51.dtsi
+++ b/arch/arm/dts/imx51.dtsi
@@ -48,25 +48,25 @@
clocks {
ckil {
- compatible = "fsl,imx-ckil", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
- compatible = "fsl,imx-ckih1", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
- compatible = "fsl,imx-ckih2", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
- compatible = "fsl,imx-osc", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2400>;
};
@@ -114,7 +114,7 @@
ports = <&ipu_di0>, <&ipu_di1>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -171,14 +171,14 @@
};
};
- bus@7000 { /* AIPS1 */
+ aips1: bus@7000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x7000 0x1000>;
ranges;
- spba@7000 {
+ spba-bus@7000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -215,6 +215,8 @@
clocks = <&clks
IMX5_CLK_UART3_IPG_GATE>,
<&clks
IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -426,6 +428,8 @@
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -436,6 +440,8 @@
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -454,7 +460,7 @@
};
};
- bus@8000 { /* AIPS2 */
+ aips2: bus@8000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -467,7 +473,7 @@
};
iim: efuse@83f98000 {
- compatible = "fsl,imx51-iim", "fsl,imx27-iim";
+ compatible = "fsl,imx51-iim", "fsl,imx27-iim",
"syscon";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
--
2.35.1
[PATCH v2 11/16] imx53: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx53-cx9020.dts| 414 ++-
arch/arm/dts/imx53-kp.dts| 2 +
arch/arm/dts/imx53-m53menlo.dts | 306 ++-
arch/arm/dts/imx53-pinfunc.h | 11 +-
arch/arm/dts/imx53-ppd.dts | 87 +--
arch/arm/dts/imx53-usbarmory.dts | 1 -
arch/arm/dts/imx53.dtsi | 39 +--
7 files changed, 577 insertions(+), 283 deletions(-)
diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts
index e08850999b..cfb18849a9 100644
--- a/arch/arm/dts/imx53-cx9020.dts
+++ b/arch/arm/dts/imx53-cx9020.dts
@@ -1,195 +1,133 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2016 Beckhoff Automation
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 Beckhoff Automation GmbH & Co. KG
+ * based on imx53-qsb.dts
*/
/dts-v1/;
#include "imx53.dtsi"
-#define MX53_PAD_EIM_D26__UART2_RXD_MUX0x144 0x48c 0x880 0x2 0x0
-#define MX53_PAD_EIM_D27__UART2_TXD_MUX0x148 0x490 0x000 0x2 0x0
-#define MX53_PAD_EIM_D28__UART2_RTS0x14c 0x494 0x87c 0x2 0x0
-#define MX53_PAD_EIM_D29__UART2_CTS0x150 0x498 0x000 0x2 0x0
-
/ {
- model = "Beckhoff CX9020-0100 i.MX53";
- compatible = "fsl,imx53-qsb", "fsl,imx53";
+ model = "Beckhoff CX9020 Embedded PC";
+ compatible = "bhf,cx9020", "fsl,imx53";
chosen {
stdout-path = &uart2;
};
-};
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
+ memory@7000 {
+ device_type = "memory";
+ reg = <0x7000 0x2000>,
+ <0xb000 0x2000>;
+ };
+
+ display-0 {
+ #address-cells =<1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_disp0>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display0_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+ };
+
+ dvi-connector {
+ compatible = "dvi-connector";
+ ddc-i2c-bus = <&i2c2>;
+ digital;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
- imx53-qsb {
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x8000
- MX53_PAD_GPIO_8__GPIO1_8 0x8000
- MX53_PAD_PATA_DATA14__GPIO2_140x8000
- MX53_PAD_PATA_DATA15__GPIO2_150x8000
- MX53_PAD_GPIO_1__GPIO1_1 0x8000
- MX53_PAD_GPIO_4__GPIO1_4 0x8000
- MX53_PAD_PATA_DA_0__GPIO7_6 0x8000
- MX53_PAD_GPIO_16__GPIO7_110x8000
-
- MX53_PAD_EIM_OE__EMI_WEIM_OE
0x8000
- MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT
0x8000
- MX53_PAD_EIM_LBA__EMI_WEIM_LBA
0x8000
- MX53_PAD_EIM_RW__EMI_WEIM_RW
0x8000
- MX53_PAD_EIM_EB0__EMI_WEIM_EB_0
0x8000
- MX53_PAD_EIM_EB1__EMI_WEIM_EB_1
0x8000
- MX53_PAD_EIM_EB2__EMI_WEIM_EB_2
0x8000
- MX53_PAD_EIM_EB3__EMI_WEIM_EB_3
0x8000
- MX53_PAD_EIM_CS0__EMI_WEIM_CS_0
0x8000
- MX53_PAD_EIM_CS1__EMI_WEIM_CS_1
0x8000
- MX53_PAD_EIM_A16__EMI_WEIM_A_16
0x8000
- MX53_PAD_EIM_A17__EMI_WEIM_A_17
0x8000
- MX53_PAD_EIM_A18__EMI_WEIM_A_18
0x8000
- MX53_PAD_EIM_A19__EMI_WEIM_A_19
0x8000
- MX53_PAD_EIM_A20__EMI_WEIM_A_20
0x8000
- MX53_PAD_EIM_A21__EM
[PATCH v2 07/16] imx6sll: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx6sll-evk.dts | 879 --
arch/arm/dts/imx6sll-pinfunc.h| 6 +-
arch/arm/dts/imx6sll.dtsi | 445 ++-
include/dt-bindings/clock/imx6sll-clock.h | 16 +-
4 files changed, 551 insertions(+), 795 deletions(-)
diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
index b4af007c98..32b3d82fec 100644
--- a/arch/arm/dts/imx6sll-evk.dts
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/dts-v1/;
@@ -16,11 +15,16 @@
model = "Freescale i.MX6SLL EVK Board";
compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
- memory {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@8000 {
+ device_type = "memory";
reg = <0x8000 0x8000>;
};
- backlight {
+ backlight_display: backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -28,108 +32,114 @@
status = "okay";
};
- battery: max8903@0 {
- compatible = "fsl,max8903-charger";
+ leds {
+ compatible = "gpio-leds";
pinctrl-names = "default";
- dok_input = <&gpio4 13 1>;
- uok_input = <&gpio4 13 1>;
- chg_input = <&gpio4 15 1>;
- flt_input = <&gpio4 14 1>;
- fsl,dcm_always_high;
- fsl,dc_valid;
- fsl,adc_disable;
- status = "okay";
+ pinctrl-0 = <&pinctrl_led>;
+
+ user {
+ label = "debug";
+ gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
};
- pxp_v4l2_out {
- compatible = "fsl,imx6sl-pxp-v4l2";
- status = "okay";
+ reg_usb_otg1_vbus: regulator-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ reg_usb_otg2_vbus: regulator-otg2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_aud3v: regulator-aud3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <315>;
+ regulator-max-microvolt = <315>;
+ regulator-boot-on;
+ };
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_aud4v: regulator-aud4v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
Re: Don't use sudo in python tests
Am 22. Oktober 2022 20:44:27 MESZ schrieb Sean Anderson : >On 10/22/22 08:04, Tom Rini wrote: >> On Sat, Oct 22, 2022 at 10:24:33AM +0200, Heinrich Schuchardt wrote: >>> Hello Simon, >>> >>> As described in doc/develop/py_testing.doc using sudo in python tests >>> should be avoided. >>> >>> * users building U-Boot may not be sudoers >>> * running code as sudo comes with a risk >>> >>> You added sudo in test/py/tests/test_ut.py >>> >>> Can we use virt-make-fs here? >> >> Note that virt-make-fs is only suitable for trivial cases as it's >> otherwise too slow. This is possibly one of the cases where it's too >> slow. >> > >An easy way to do this is to use fuse2fs/fusefat. My experience with fusefat is that it was terribly buggy 2-3 years ago. Last upstream source is from 2018. Best regards Heinrich > >--Sean
[PATCH v2 13/16] imx28: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v2:
- Add missing imx28-lwe.dtsi as pointed out by Fabio. Thanks!
arch/arm/dts/imx28-evk.dts | 2 +-
arch/arm/dts/imx28-lwe.dtsi | 170 +++
arch/arm/dts/imx28-pinfunc.h | 8 +-
arch/arm/dts/imx28-xea.dts | 188 ++-
arch/arm/dts/imx28.dtsi | 20 +++-
arch/arm/dts/mxs-pinfunc.h | 8 +-
6 files changed, 261 insertions(+), 135 deletions(-)
create mode 100644 arch/arm/dts/imx28-lwe.dtsi
diff --git a/arch/arm/dts/imx28-evk.dts b/arch/arm/dts/imx28-evk.dts
index 7e2b0f198d..1053b7c584 100644
--- a/arch/arm/dts/imx28-evk.dts
+++ b/arch/arm/dts/imx28-evk.dts
@@ -129,7 +129,7 @@
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b",
"jedec,spi-nor";
diff --git a/arch/arm/dts/imx28-lwe.dtsi b/arch/arm/dts/imx28-lwe.dtsi
new file mode 100644
index 00..bb971e660d
--- /dev/null
+++ b/arch/arm/dts/imx28-lwe.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+
+/ {
+ aliases {
+ spi2 = &ssp3;
+ };
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait
console=ttyAMA0,115200 panic=1";
+ };
+
+ memory@4000 {
+ reg = <0x4000 0x0800>;
+ };
+
+ reg_3v3: regulator-reg-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ reg_usb_5v: regulator-reg-usb-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ reg_fec_3v3: regulator-reg-fec-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clks 53>;
+ assigned-clock-rates = <1200>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&spi3_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__SSP3_D4
+ MX28_PAD_AUART2_TX__SSP3_D5
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ >;
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a>;
+ bus-width = <8>;
+ vmmc-supply = <®_3v3>;
+ non-removable;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&ssp3 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <4000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x8>;
+ read-only;
+ };
+
+ partition@8 {
+ label = "env0";
+ reg = <0x8 0x1>;
+ };
+
+ partition@9 {
+ label = "env1";
+ reg = <0x9 0x1>;
+
[PATCH v2 16/16] imx28: avoid num_cs and spi_max_frequency build errors
From: Marcel Ziswiler
Avoid the following build errors after the device tree sync:
drivers/spi/mxs_spi.c: In function ‘mxs_spi_probe’:
drivers/spi/mxs_spi.c:327:25: error: ‘struct dtd_fsl_imx23_spi’ has no
member named ‘spi_max_frequency’
327 | priv->max_freq = dtplat->spi_max_frequency;
| ^~
drivers/spi/mxs_spi.c:328:23: error: ‘struct dtd_fsl_imx23_spi’ has no
member named ‘num_cs’
328 | plat->num_cs = dtplat->num_cs;
| ^~
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx28-xea-u-boot.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx28-xea-u-boot.dtsi
b/arch/arm/dts/imx28-xea-u-boot.dtsi
index cc2ced5d2d..8b5d7e10b3 100644
--- a/arch/arm/dts/imx28-xea-u-boot.dtsi
+++ b/arch/arm/dts/imx28-xea-u-boot.dtsi
@@ -42,5 +42,7 @@
};
&ssp3 {
+ num-cs = <2>;
+ spi-max-frequency = <4000>;
u-boot,dm-spl;
};
--
2.35.1
[PATCH v2 14/16] imx23: synchronise device tree with linux
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imx23-evk.dts | 1 -
arch/arm/dts/imx23-pinfunc.h | 8 +---
arch/arm/dts/imx23-u-boot.dtsi | 7 +++
arch/arm/dts/imx23.dtsi| 2 +-
4 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/imx23-evk.dts b/arch/arm/dts/imx23-evk.dts
index 8cbaf1c811..3b609d987d 100644
--- a/arch/arm/dts/imx23-evk.dts
+++ b/arch/arm/dts/imx23-evk.dts
@@ -79,7 +79,6 @@
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
-
MX23_PAD_SSP1_DETECT__SSP1_DETECT
>;
fsl,drive-strength = ;
fsl,voltage = ;
diff --git a/arch/arm/dts/imx23-pinfunc.h b/arch/arm/dts/imx23-pinfunc.h
index 5c0f32ca3a..468c079f3c 100644
--- a/arch/arm/dts/imx23-pinfunc.h
+++ b/arch/arm/dts/imx23-pinfunc.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
diff --git a/arch/arm/dts/imx23-u-boot.dtsi b/arch/arm/dts/imx23-u-boot.dtsi
index 5e87aca61b..5de62bbb90 100644
--- a/arch/arm/dts/imx23-u-boot.dtsi
+++ b/arch/arm/dts/imx23-u-boot.dtsi
@@ -1,14 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+ gpio-ranges = <&{/apb@8000/apbh@8000/pinctrl@80018000} 0 0 32>;
};
&gpio1 {
- gpio-ranges = <&pinctrl 0 32 31>;
+ gpio-ranges = <&{/apb@8000/apbh@8000/pinctrl@80018000} 0 32 31>;
};
&gpio2 {
- gpio-ranges = <&pinctrl 0 63 32>;
+ gpio-ranges = <&{/apb@8000/apbh@8000/pinctrl@80018000} 0 63 32>;
};
-
diff --git a/arch/arm/dts/imx23.dtsi b/arch/arm/dts/imx23.dtsi
index 4cfec77849..7f4c602454 100644
--- a/arch/arm/dts/imx23.dtsi
+++ b/arch/arm/dts/imx23.dtsi
@@ -105,7 +105,7 @@
status = "disabled";
};
- pinctrl: pinctrl@80018000 {
+ pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";
--
2.35.1
Re: Pending imx patch sets
On Fri, 2022-10-21 at 14:30 +0200, Stefano Babic wrote: > On 21.10.22 14:22, Marcel Ziswiler wrote: > > Hi Stefano > > > > On Fri, 2022-10-21 at 12:05 +0200, Stefano Babic wrote: > > > Hi Marcel, > > > > > > I have picked up several of yours as first attempt to merge most i.MX, > > > CI is running. What is missing, it will go in the "second attempt": > > > > Okay, thanks. > > > > > On 21.10.22 11:55, Marcel Ziswiler wrote: > > > > Hi Stefano and Fabio > > > > > > > > As follows a list of patch sets which have not yet been applied/merged. > > > > Some without any feedback from > > > > any > > > > of > > > > them imx maintainers since almost 3 months: > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220803112009.271563-1-francesco.dolc...@toradex.com/ > > > > > > I have not yet picked up this. > > > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/cover/20220826094834.693236-1-mar...@ziswiler.com/ > > > > > > > > > > Same here, DT sync is in my second attempt when first is okay. > > > > > > > https://patchwork.ozlabs.org/project/uboot/cover/20220826183141.789236-1-mar...@ziswiler.com/ > > > > I just noticed that Jesse gave some feedback on the 3rd patch of this > > series which I somehow missed. Should > > I > > send a v3 with his fixes/suggestions incorporated and you drop v2 and apply > > the new v3? > > This is not yet applied and I missed, too, that there are comments. > Please send them V3. https://patchwork.ozlabs.org/project/uboot/cover/20221022214233.82467-1-mar...@ziswiler.com/ > Stefano > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220829175953.249441-1-...@pschenker.ch/ > > > > > > > > > > Picked up (all already merged and in my test are set to "Under Review" > > > in patchworks) > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220907095105.21630-1-francesco.dolc...@toradex.com/ > > > > > > > > > > Picked up > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220921113419.1088398-1-mar...@ziswiler.com/ > > > > > > > > > > Picked up > > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/cover/20220922212834.2419255-1-mar...@ziswiler.com/ > > > > > > Picked up > > > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220927155052.40056-1-mar...@ziswiler.com/ > > > > > > > > > > Picked up > > > > > > > https://patchwork.ozlabs.org/project/uboot/cover/20221004110632.21045-1-andrejs.cainik...@toradex.com/ > > > > > > > > > > Not picked up, I have not merged most of patches sent in October. They > > > will come to the second attempt, too. > > > > > > > After almost up to 3 months some of those may require re-basing. > > > > However, it would be nice if there > > > > would > > > > be > > > > some subsequent action from the maintainers side after we did do so. > > > > > > > > Please advice how we may proceed. > > > > > > > > > > If CI runs, from your list are stioll open a couple of single patches > > > (that I have simply forgotten) + the DT sync series. They will follow. > > > > > > > > > Ci is running here, last attempt still a MX8 was failing, I have fix > > > myself and I hope it goes to the end. > > > > > > Stefano > > > > Cheers > > > > Marcel
Re: [PATCH] imx28-xea: Add missing imx28-lwe.dtsi
On Sat, 2022-10-22 at 17:44 +0200, Stefano Babic wrote: > Hi everybody, > > On 22.10.22 15:44, Michael Nazzareno Trimarchi wrote: > > Hi > > > > On Sat, Oct 22, 2022 at 3:35 PM Fabio Estevam wrote: > > > > > > On Sat, Oct 22, 2022 at 10:31 AM Michael Nazzareno Trimarchi > > > wrote: > > > > > > > On my side the Continuous Integration using gitlab-ci, verify board > > > > combinations > > > > and test the build. I'm asking if this build breakage happen because > > > > those boards > > > > are not built. > > > > > > All boards are built by CI and the build error was reported at: > > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/517428 > > > > Should the patches need to be resend if they are not building? so you > > want to take care of them > > > > Just to clarify: the broken patches *are* not applied. As pointed by > Michael, CI is used to check build *before* applying. What you are > looking is my master-next branch, that is patches are applied first to a > test branch (master-next) before going to master. If CI is broken, they > are simply removed. That is my next step, I have seen that > imx28-lwe.dtsi is missing, too. But as patch is not applied, I will > kindly ask Marcel to squash Fabio's in his series and repost. https://patchwork.ozlabs.org/project/uboot/cover/20221022215945.84052-1-mar...@ziswiler.com/ > Thanks, > Stefano > > > Michael
Re: [PATCH v3 2/8] imxrt1020: fix lpuart issue in common u-boot device tree
Hi Marcel,
thanks for contributing,
Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
From: Marcel Ziswiler
Fix lpuart issue in common U-Boot device tree.
There's no need to repeat in commit log the subject.
Signed-off-by: Marcel Ziswiler
---
(no changes since v1)
arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 ---
arch/arm/dts/imxrt1020-evk.dts | 1 -
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index 9e1b074d2e..7cab486f5f 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -67,9 +67,6 @@
imxrt1020-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
u-boot,dm-spl;
@@ -81,6 +78,10 @@
};
};
+&pinctrl_lpuart1 {
+ u-boot,dm-spl;
+};
+
I don't understand the goal of this change, can you elaborate?
As I remember pinctrl_lpuart1 already works correctly. The same goes
for:
pinctrl_semc
pinctrl_usdhc0
So you're not fixing something.
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index 22ae5ed735..d4d1de4ea8 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "imxrt1020.dtsi"
-#include "imxrt1020-evk-u-boot.dtsi"
This ^^^ is needed, please revert it.
#include "imxrt1020-pinfunc.h"
/ {
Have you also tested the change on a board?
Best regards
--
Giulio Benetti
CEO/CTO@Benetti Engineering sas
Re: [PATCH v3 3/8] imxrt1050: synchronise device tree with linux
Hi Marcel,
Il 22/10/2022 23:42, Marcel Ziswiler ha scritto:
From: Marcel Ziswiler
Synchronise device tree with linux v6.0-rc1.
Signed-off-by: Marcel Ziswiler
---
Changes in v3:
- Incorporate feedback from Jesse.
Changes in v2:
- imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks!
arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++--
arch/arm/dts/imxrt1050-evk.dts | 257 +++-
arch/arm/dts/imxrt1050-pinfunc.h| 2 +-
arch/arm/dts/imxrt1050.dtsi | 168 ++---
include/dt-bindings/clock/imxrt1050-clock.h | 9 +-
5 files changed, 255 insertions(+), 343 deletions(-)
diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index 617cece448..bf40ada234 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -4,8 +4,12 @@
* Author(s): Giulio Benetti
*/
+#include
+#include "imxrt1050-pinfunc.h"
+
/ {
chosen {
+ tick-timer = &gpt;
u-boot,dm-spl;
};
@@ -15,6 +19,52 @@
soc {
u-boot,dm-spl;
+
+ semc@402f {
+ compatible = "fsl,imxrt-semc";
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ reg = <0x402f 0x4000>;
+ status = "okay";
+ u-boot,dm-spl;
+
+ /*
+* Memory configuration from sdram datasheet
IS42S16160J-6BLI
+*/
+ fsl,sdram-mux = /bits/ 8 ;
+ fsl,sdram-control = /bits/ 8 ;
+ fsl,sdram-timing = /bits/ 8 <0x2
+0x2
+0x9
+0x1
+0x5
+0x6
+
+0x20
+0x09
+0x01
+0x00
+
+0x04
+0x0A
+0x21
+0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x8000>;
+ fsl,memory-size = ;
+ u-boot,dm-spl;
+ };
+ };
};
};
@@ -50,41 +100,121 @@
u-boot,dm-spl;
};
-&gpt1 {
+&gpt {
+ clocks = <&osc>;
+ compatible = "fsl,imxrt-gpt";
+ status = "okay";
u-boot,dm-spl;
};
&lpuart1 { /* console */
+ compatible = "fsl,imxrt-lpuart";
u-boot,dm-spl;
};
-&semc {
- u-boot,dm-spl;
-
- bank1: bank@0 {
- u-boot,dm-spl;
- };
-};
-
&iomuxc {
u-boot,dm-spl;
imxrt1050-evk {
u-boot,dm-spl;
- pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
- };
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
- };
-
- pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1/* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1/* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1/* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1/* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1/* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1/* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1/* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1/* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1/* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1/* SEMC_A0 */
+
Re: Don't use sudo in python tests
On 10/22/22 18:00, Heinrich Schuchardt wrote: Am 22. Oktober 2022 20:44:27 MESZ schrieb Sean Anderson : On 10/22/22 08:04, Tom Rini wrote: On Sat, Oct 22, 2022 at 10:24:33AM +0200, Heinrich Schuchardt wrote: Hello Simon, As described in doc/develop/py_testing.doc using sudo in python tests should be avoided. * users building U-Boot may not be sudoers * running code as sudo comes with a risk You added sudo in test/py/tests/test_ut.py Can we use virt-make-fs here? Note that virt-make-fs is only suitable for trivial cases as it's otherwise too slow. This is possibly one of the cases where it's too slow. An easy way to do this is to use fuse2fs/fusefat. My experience with fusefat is that it was terribly buggy 2-3 years ago. Last upstream source is from 2018. Yeah, I had not used it before. fuse2fs is nice. It doesn't support replaying the journal, but this doesn't matter when creating a filesystem. mtools seems incredibly clunky, but it appears to work, and has reasonable performance. LKL [1] seemed like it might have been the most robust solution (with lklfuse), but it hasn't made it upstream yet (and the primary author seems to have stopped trying). --Sean [1] https://github.com/lkl/linux
Re: [PATCH 0/3] mtd: spi-nor-core: Add support for s28hl512t, s28hl01gt, and s28hs01gt
On Thu, Aug 25, 2022 at 1:19 PM wrote: > > From: Takahiro Kuwano > > These devices are variants of s28hs512t(1.8V 512Mb) with different > density(1Gb) and power supply voltage(3V). > > Datasheet: > https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HS512T_S28HS01GT_S28HL256T_S28HL512T_S28HL01GT_256-Mb_(32-MB)_512-Mb_(64-MB)_1-Gb_(128-MB)_HS-T_(1.8-V)_HL-T_(3.0-V)_Semper_Flash_with_Octal_Interface-DataSheet-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee6bca96f97&da=t > > Tested on Zynq-7000 platform with Infineon SPI controller > > Takahiro Kuwano (3): > mtd: spi-nor-core: Rename s28hs512t prefix > mtd: spi-nor-core: Rename configuration macro for S28 support > mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs Applied to u-boot-spi/master
Re: [PATCH 0/4] mtd: spi-nor-core: Track flash's internal address mode in s25hx-t
On Thu, Sep 1, 2022 at 11:36 AM wrote: > > From: Takahiro Kuwano > > For S25hx-T support in Linux (single die package only), flash's internal > address mode is not changed and it is assumed as factory default. Current > implementation of u-boot forces to 4-byte address mode while some parts > are 3-byte address mode by default. That will cause a problem when we use > u-boot to load the Linux kernel. This series tries to avoid the problem, > by porting two changes from linux [0][1] and additional rework. > > [0] > https://patchwork.ozlabs.org/project/linux-mtd/patch/20200525091544.17270-7-p.ya...@ti.com/ > [1] > https://patchwork.ozlabs.org/project/linux-mtd/patch/20220725092505.446315-6-tudor.amba...@microchip.com/ > > Takahiro Kuwano (4): > mtd: spi-nor-core: Default to addr_width of 3 for configurable widths > mtd: spi-nor-core: Track flash's internal address mode > mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use > addr_mode_nbytes > mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's > internal address mode Applied to u-boot-spi/master
Re: [PATCH] spi: spi-mem: ease checks in dtr_supports_op()
On Thu, Oct 20, 2022 at 2:04 PM Dhruva Gole wrote: > > Remove the extra conditions that cause some cases to fail prematurely > like if the data number of bytes is odd. The controller can handle odd > number of bytes data read in DTR Mode. Don't fail supports op for this > condition. > > Signed-off-by: Dhruva Gole > --- > > For a deeper context, refer to a cover letter from an earlier patch > series: > https://lore.kernel.org/u-boot/20221019064759.493607-1-d-g...@ti.com/T/#m3fd93bdcc30b3b5faada6abe45a4104388afc300 > Here, I am trying to boot from OSPI Flash present on board the AM62-SK > EVM. However, despite enabling the necessary configs and DT nodes, my > boot flow seemed to be failing. I then came to know that the condition > causing this failure was that my generated DTB was of odd number of > bytes. > So, while loading the dtb from the Octal SPI NOR Flash to the memory, > the data.nbytes was odd which made the supports_op > function return false. This check feels a little too strict at the > spi-mem stage and we should let the controller decide what to do in case > of odd bytes in DTR. After applying this patch, I was able to > succesfully boot the AM62SK EVM without any issues. > > I would also like to justify this patch by pointing the community to the > equivalent code in the linux kernel, in drivers/spi/spi-mem.c, where this > check > is absent as well. > > The controller does work with odd number of bytes and I have not seen > any sort of bugs in the absence of this supports_op check. Hence, feel > that it is safe enough to discard this check from here. Require better wrapup of above text to be part of commit body.
Re: [PATCH] mtd: spi-nor-core: Fix index value for SCCR dwords
On Mon, Sep 12, 2022 at 10:56 AM wrote:
>
> From: Takahiro Kuwano
>
> Array index for SCCR 22th DWORD should be 21.
>
> Fixes: bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map")
> Signed-off-by: Takahiro Kuwano
> ---
Applied to u-boot-spi/master
Re: [PATCH] cmd: sf: Handle unaligned 'update' start offset
On Wed, Sep 28, 2022 at 10:15 PM Marek Vasut wrote: > > Currently the 'sf update' command fails in case the 'start' offset is > not aligned to SPI NOR erase block size. Add the missing alignment > calculation. In case the start offset is in the middle of erase block, > round start address down to the nearest aligned one, compare only the > updated data between what is in the SPI NOR and what is being written, > copy new data at offset of the compare buffer, and write back the entire > erase block. > > This is useful e.g. on i.MX6Q where the u-boot-with-spl.imx is at > offset 0x400 in the SPI NOR, while the SPI NOR may have erase block > size e.g. 0x1000 bytes. > > Signed-off-by: Marek Vasut > --- Reviewed-by: Jagan Teki
Re: [PATCH 016/347] FogBugz #516535: Fix QSPI write issues
On Tue, Aug 30, 2022 at 11:50 AM Jit Loon Lim wrote: > > From: Chee Hong Ang > > QSPI driver perform chip select on every flash read/write > access. The driver need to disable/enable the QSPI controller > while performing chip select. This may cause some data lost > especially the QSPI controller is configured to run at slower > speed as it may take longer time to access the flash device. > This patch prevent the driver from disable/enable the QSPI > controller too soon and inadvertently halting any ongoing flash > read/write access by ensuring the QSPI controller is always in > idle mode after each read/write access. > > Signed-off-by: Chee Hong Ang > -- "FogBugz #516535:" This commit head is invalid for the upstream patch.
Re: [PATCH v3 0/6] eficonfig: add UEFI Secure Boot key maintenance interface
Hi Heinrich, On Sat, 22 Oct 2022 at 17:31, Heinrich Schuchardt wrote: > > On 10/14/22 08:56, Masahisa Kojima wrote: > > This series adds the UEFI Secure Boot key maintenance interface > > to the eficonfig command. > > User can enroll and delete the PK, KEK, db and dbx. > > > > Source code can be cloned with: > > $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b > > kojima/eficonfig_sbkey_v3 > > > > [Major Changes] > > - rebased on top of u-boot/master > > > > Masahisa Kojima (6): > >eficonfig: refactor eficonfig_select_file_handler() > >eficonfig: expose append entry function > >eficonfig: add UEFI Secure Boot Key enrollment interface > >eficonfig: add "Show/Delete Signature Database" menu entry > >test/eficonfig: support secure boot key maintenance menu > >test: add test for eficonfig secure boot key management > > > > cmd/Makefile | 3 + > > cmd/eficonfig.c | 48 +- > > cmd/eficonfig_sbkey.c | 751 ++ > > include/efi_config.h | 10 + > > test/py/tests/test_eficonfig/conftest.py | 84 +- > > test/py/tests/test_eficonfig/defs.py | 14 + > > .../py/tests/test_eficonfig/test_eficonfig.py | 4 +- > > .../test_eficonfig/test_eficonfig_sbkey.py| 472 +++ > > 8 files changed, 1360 insertions(+), 26 deletions(-) > > create mode 100644 cmd/eficonfig_sbkey.c > > create mode 100644 test/py/tests/test_eficonfig/defs.py > > create mode 100644 test/py/tests/test_eficonfig/test_eficonfig_sbkey.py > > > > Python tests with this series fail. See > > https://source.denx.de/u-boot/custodians/u-boot-efi/-/jobs/518130 Failing item is test_capsule_firmware_raw.py, not eficonfig. test_eficonfig_sbkey.py test is successful. Thanks, Masahisa Kojima > > Please, run 'make tests' before resubmitting. > > Best regards > > Heinrich
