Re: [U-Boot] [PATCH v4 1/1] efi_loader: PSCI reset and shutdown
On 17.10.18 20:06, Heinrich Schuchardt wrote:
> On 10/17/2018 07:37 PM, Alexander Graf wrote:
>>
>>
>> On 17.10.18 19:05, Heinrich Schuchardt wrote:
>>> When an operating system started via bootefi tries to reset or power off
>>> this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
>>> the actual reset relies on PSCI. Depending on whether the PSCI firmware
>>> resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
>>> or an SMC command has to be issued.
>>>
>>> The current implementation always uses SMC. This results in crashes on
>>> systems where the PSCI firmware is implemented in the hypervisor, e.g.
>>> qemu-arm64_defconfig.
>>>
>>> The logic to decide which call is needed based on the device tree is
>>> already implemented in the PSCI firmware driver. During the EFI runtime
>>> the device driver model is not available. But we can minimize code
>>> duplication by merging the EFI runtime reset and poweroff code with
>>> the PSCI firmware driver.
>>>
>>> As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
>>> and reset_misc routines let's move them into the same code module.
>>>
>>> Signed-off-by: Heinrich Schuchardt
>>> Reviewed-by: Sumit Garg
>>> Tested-by: Sumit Garg
>>> ---
>>> Travis reporteded no errors in
>>> https://travis-ci.org/xypron2/u-boot/builds/442613876
>>>
>>> v4:
>>> fix reset_misc() too
>>> avoid switch statement
>>> v3:
>>> update commit message
>>> v2:
>>> Use PSCI firmware driver to detect call method.
>>> Thanks to Sumit for pointing me at dtb parsing as part of
>>> "psci_probe()
>>> ---
>>> arch/arm/cpu/armv7/smccc-call.S | 2 +
>>> arch/arm/cpu/armv8/Kconfig | 1 +
>>> arch/arm/cpu/armv8/fwcall.c | 52 ++---
>>> arch/arm/cpu/armv8/smccc-call.S | 2 +
>>> drivers/firmware/psci.c | 100 +++-
>>> include/linux/psci.h| 6 +-
>>> 6 files changed, 96 insertions(+), 67 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/smccc-call.S
>>> b/arch/arm/cpu/armv7/smccc-call.S
>>> index 0d8b59eb6b..eae69e36c3 100644
>>> --- a/arch/arm/cpu/armv7/smccc-call.S
>>> +++ b/arch/arm/cpu/armv7/smccc-call.S
>>> @@ -7,6 +7,8 @@
>>> #include
>>> #include
>>>
>>> + .section.text.efi_runtime
>>> +
>>> #define UNWIND(x...)
>>> /*
>>> * Wrap c macros in asm macros to delay expansion until after the
>>> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
>>> index c8bebabdf6..d643981b73 100644
>>> --- a/arch/arm/cpu/armv8/Kconfig
>>> +++ b/arch/arm/cpu/armv8/Kconfig
>>> @@ -96,6 +96,7 @@ endmenu
>>> config PSCI_RESET
>>> bool "Use PSCI for reset and shutdown"
>>> default y
>>> + select ARM_SMCCC if OF_CONTROL
>>> depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
>>>!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
>>>!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
>>> diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
>>> index 0ba3dad8cc..9957c2974b 100644
>>> --- a/arch/arm/cpu/armv8/fwcall.c
>>> +++ b/arch/arm/cpu/armv8/fwcall.c
>>> @@ -7,7 +7,6 @@
>>>
>>> #include
>>> #include
>>> -#include
>>> #include
>>> #include
>>> #include
>>> @@ -19,7 +18,7 @@
>>> * x0~x7: input arguments
>>> * x0~x3: output arguments
>>> */
>>> -static void __efi_runtime hvc_call(struct pt_regs *args)
>>> +static void hvc_call(struct pt_regs *args)
>>> {
>>> asm volatile(
>>> "ldr x0, %0\n"
>>> @@ -53,7 +52,7 @@ static void __efi_runtime hvc_call(struct pt_regs *args)
>>> * x0~x3: output arguments
>>> */
>>>
>>> -void __efi_runtime smc_call(struct pt_regs *args)
>>> +void smc_call(struct pt_regs *args)
>>> {
>>> asm volatile(
>>> "ldr x0, %0\n"
>>> @@ -83,9 +82,9 @@ void __efi_runtime smc_call(struct pt_regs *args)
>>> * use PSCI on U-Boot running below a hypervisor, please detect
>>> * this and set the flag accordingly.
>>> */
>>> -static const __efi_runtime_data bool use_smc_for_psci = true;
>>> +static const bool use_smc_for_psci = true;
>>>
>>> -void __noreturn __efi_runtime psci_system_reset(void)
>>> +void __noreturn psci_system_reset(void)
>>> {
>>> struct pt_regs regs;
>>>
>>> @@ -100,7 +99,7 @@ void __noreturn __efi_runtime psci_system_reset(void)
>>> ;
>>> }
>>>
>>> -void __noreturn __efi_runtime psci_system_off(void)
>>> +void __noreturn psci_system_off(void)
>>> {
>>> struct pt_regs regs;
>>>
>>> @@ -114,44 +113,3 @@ void __noreturn __efi_runtime psci_system_off(void)
>>> while (1)
>>> ;
>>> }
>>> -
>>> -#ifdef CONFIG_CMD_POWEROFF
>>> -int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>> -{
>>> - puts("poweroff ...\n");
>>> -
>>> - udelay(5); /* wait 50 ms */
>>> -
>>> - disable_interrupts();
>>> -
>>> - psci_system_off();
>>> -
>>> - /*NOTREACHED*/
>>> - return 0;
>>> -}
>>> -#endif
>>> -
>>> -#i
Re: [U-Boot] [PATCH 2/2] ARM: qemu-arm: define fdt_addr_r
On 18.10.18 00:25, Tuomas Tynkkynen wrote:
> Hi Alexander,
>
> On Tue, 16 Oct 2018 15:04:26 +0200
> Alexander Graf wrote:
>
> ...
>>>
Glancing at cmd/pxe.c,
there is a problem though, in that if ${fdt_addr_r} were defined,
a PXE file using the FDTDIR directive would attempt loading a dtb
file named "-qemu-arm.dtb" instead of falling back to using
${fdt_addr}. That bug would need to be fixed first before applying
this patch.
>>
>> Well, and that load will fail and everyone's happy, no?
>
> No, because currently if DTB loading from the filesystem/tftp is
> attempted and it fails, it aborts the boot. It doesn't matter if it's
> via a 'FDT' or 'FDTDIR' directive. In the case of typical hardware
> that's probably the desired behaviour.
>
> I guess the qemu_arm + FDTDIR case can be fixed by not attempting
> a .dtb load if the default fdtfile is not known due to $soc or $board
> being unset. At least I doubt that some other board could be relying
> on a filename containing literally "" :)
Well - IIRC $soc and $board should also always be defined ;). So yet
another thing to fix in the QEMU port.
>
>> IMHO we should
>> fall back to $fdtcontroladdr always
>
> FWIW, to me the idea of passing $fdtcontroladdr to the OS has always
> filled me with dread. On top of the usual backwards- and
> forwards-compatibility problems that happen when mixing and matching
> kernels and DTBs from different releases, you now have to deal with
That's something that we seriously as a community need to get sorted
out. We're pushing hard for it in the EBBR context. The fact that people
are afraid of putting *hardware desciption* into their firmware is just
mind boggling.
> issues like U-Boot specific .dts that are majorly diverged from Linux
> ones, or where the .dts is otherwise from Linux but the U-Boot specific
These case should really be the minority. And if you see those, please
fix them.
> additions break it for Linux, or where the .dts used is wrong for the
I've never seen a case where a U-Boot addition broke the DT for Linux.
> specific hardware revision but close enough for U-Boot's purposes,
> and so on...
Again, something that just needs fixing. Device trees belong to the
entity that knows hardware, not to the OS. Otherwise you lose the
abstraction layer that DT gives you and you lose the ability to run
"generic" kernels. And of course you break the ecosystem, because now
good luck running BSD, your own little toy OS, etc ;)
Alex
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Re: [U-Boot] [PATCH 1/2] efi_loader: rework fdt handling in distro boot script
On 18.10.18 04:07, AKASHI Takahiro wrote:
> On Tue, Oct 16, 2018 at 03:15:13PM +0200, Alexander Graf wrote:
>>
>>
>> On 12.10.18 07:07, AKASHI Takahiro wrote:
>>> The current scenario for default UEFI booting, scan_dev_for_efi, has
>>> several issues:
>>> * invoke 'bootmgr' only if BOOTEFI_NAME binary does exit even though
>>> 'bootmgr' can and should work independently whether or not the binary
>>> exist,
>>> * always assume that a 'fdtfile' variable is defined,
>>> * redundantly check for 'fdt_addr_r' in boot_efi_binary
>>>
>>> In this patch, all the issues above are sorted out.
>>>
>>> Signed-off-by: AKASHI Takahiro
>>> ---
>>> include/config_distro_bootcmd.h | 43 -
>>> 1 file changed, 21 insertions(+), 22 deletions(-)
>>>
>>> diff --git a/include/config_distro_bootcmd.h
>>> b/include/config_distro_bootcmd.h
>>> index 373fee78a999..76e12b7bf4ee 100644
>>> --- a/include/config_distro_bootcmd.h
>>> +++ b/include/config_distro_bootcmd.h
>>> @@ -124,42 +124,41 @@
>>>
>>> #define BOOTENV_SHARED_EFI\
>>> "boot_efi_binary="\
>>> - "if fdt addr ${fdt_addr_r}; then "\
>>> - "bootefi bootmgr ${fdt_addr_r};" \
>>> - "else " \
>>> - "bootefi bootmgr ${fdtcontroladdr};" \
>>> - "fi;" \
>>> "load ${devtype} ${devnum}:${distro_bootpart} " \
>>> "${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \
>>> - "if fdt addr ${fdt_addr_r}; then "\
>>> - "bootefi ${kernel_addr_r} ${fdt_addr_r};" \
>>> - "else " \
>>> - "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
>>> - "fi\0"\
>>> + "bootefi ${kernel_addr_r} ${efi_fdt_addr};\0" \
>>> \
>>> "load_efi_dtb=" \
>>> "load ${devtype} ${devnum}:${distro_bootpart} " \
>>> - "${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \
>>> + "${fdt_addr_r} ${prefix}${efi_fdtfile};" \
>>> + "if fdt addr ${fdt_addr_r}; then "\
>>> + "setenv efi_fdt_addr ${fdt_addr_r}; " \
>>> + "else; " \
>>> + "setenv efi_fdt_addr ${fdtcontroladdr}; " \
>>> + "fi;\0" \
>>> \
>>> - "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"\
>>> - "scan_dev_for_efi=" \
>>> + "set_efi_fdt_addr=" \
>>> "setenv efi_fdtfile ${fdtfile}; " \
>>> BOOTENV_EFI_SET_FDTFILE_FALLBACK \
>>> - "for prefix in ${efi_dtb_prefixes}; do " \
>>
>> I fail to see where the prefix logic went? Without that, our distro's
>> dtb loading will break.
>
> Oops, I missed it.
>
>>
>>> - "if test -e ${devtype} " \
>>> - "${devnum}:${distro_bootpart} " \
>>> - "${prefix}${efi_fdtfile}; then " \
>>> - "run load_efi_dtb; " \
>>> - "fi;" \
>>> - "done;" \
>>> + "if test x${efi_fdtfile} != x -a x{$fdt_addr_r} != x ; then " \
>>> + "run load_efi_dtb; " \
>>> + "else; " \
>>> + "setenv efi_fdt_addr ${fdtcontroladdr}; " \
>>> + "fi; "\
>>
>> Just unconditionally set efi_fdt_addr=$fdtcontrolladdr before the check
>> (and invocation of load_efi_dtb).
>
> OK.
>
>> That way you don't need to check for
>> the failure case in load_efi_dtb again.
>
> Well, I think that we need a check for validity with "fdt addr" command
> just in case that a fdt file exist but its content be corrupted.
>
> My modified version looks like:
> ===8<===
> #define BOOTENV_SHARED_EFI\
> "boot_efi_binary="\
> "load ${devtype} ${devnum}:${distro_bootpart} " \
> "${kernel_addr_r} efi/boot/"BOOTEF
[U-Boot] [PATCH] distro: Imply USB_STORAGE when USB is available
When you support distro boot and you support USB, you usually want to also support booting from USB storage. Reflect that in the Kconfig, so that we don't have to explicitly add USB storage support to every defconfig individually. Reported-by: AKASHI Takahiro Signed-off-by: Alexander Graf --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 1aadf5dd2d..8d515fe18c 100644 --- a/Kconfig +++ b/Kconfig @@ -86,6 +86,7 @@ config DISTRO_DEFAULTS select SUPPORT_RAW_INITRD select SYS_LONGHELP imply CMD_MII if NET + imply USB_STORAGE if USB imply USE_BOOTCOMMAND help Select this to enable various options and commands which are suitable -- 2.12.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] efi_loader: bootmgr: add load option helper functions
On Wed, Oct 17, 2018 at 10:40:26AM +0200, Alexander Graf wrote:
>
>
> On 17.10.18 09:32, AKASHI Takahiro wrote:
> > In this patch, helper functions for an load option variable (Boot)
> > are added:
> > * efi_parse_load_option(): parse a string into load_option data
> >(renamed from parse_load_option and exported)
> > * efi_marshel_load_option(): convert load_option data into a string
> >
> > Those functions will be used to implement efishell command.
> >
> > Signed-off-by: AKASHI Takahiro
> > ---
> > include/efi_loader.h | 25 +
> > lib/efi_loader/efi_bootmgr.c | 68
> > 2 files changed, 70 insertions(+), 23 deletions(-)
> >
> > diff --git a/include/efi_loader.h b/include/efi_loader.h
> > index b73fbb6de23f..1cabb1680d20 100644
> > --- a/include/efi_loader.h
> > +++ b/include/efi_loader.h
> > @@ -502,6 +502,31 @@ efi_status_t EFIAPI efi_set_variable(u16
> > *variable_name, efi_guid_t *vendor,
> > u32 attributes, efi_uintn_t data_size,
> > void *data);
> >
> > +/*
> > + * See section 3.1.3 in the v2.7 UEFI spec for more details on
> > + * the layout of EFI_LOAD_OPTION. In short it is:
> > + *
> > + *typedef struct _EFI_LOAD_OPTION {
> > + *UINT32 Attributes;
> > + *UINT16 FilePathListLength;
> > + *// CHAR16 Description[]; <-- variable length, NULL terminated
> > + *// EFI_DEVICE_PATH_PROTOCOL FilePathList[];
> > + * <-- FilePathListLength bytes
> > + *// UINT8 OptionalData[];
> > + *} EFI_LOAD_OPTION;
> > + */
> > +struct load_option {
> > + u32 attributes;
> > + u16 file_path_length;
> > + u16 *label;
> > + struct efi_device_path *file_path;
> > + u8 *optional_data;
> > +};
>
> If this is part of the spec, shouldn't it rather be in efi_api.h?
While uefi spec mentions this structure, I don't have good confidence
that I can say that it is part of spec or API because there is no interface
(or function) that handles this structure.
> It
> probably also wants an efi_ prefix then :).
OK.
> > +
> > +void efi_parse_load_option(struct load_option *lo, void *ptr);
> > +unsigned long efi_marshal_load_option(u32 attr, u16 *label,
> > + struct efi_device_path *file_path,
> > + char *option, void **data);
> > void *efi_bootmgr_load(struct efi_device_path **device_path,
> >struct efi_device_path **file_path);
> >
> > diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
> > index 0c5764db127b..c2d29f956065 100644
> > --- a/lib/efi_loader/efi_bootmgr.c
> > +++ b/lib/efi_loader/efi_bootmgr.c
> > @@ -30,28 +30,8 @@ static const struct efi_runtime_services *rs;
> > */
> >
> >
> > -/*
> > - * See section 3.1.3 in the v2.7 UEFI spec for more details on
> > - * the layout of EFI_LOAD_OPTION. In short it is:
> > - *
> > - *typedef struct _EFI_LOAD_OPTION {
> > - *UINT32 Attributes;
> > - *UINT16 FilePathListLength;
> > - *// CHAR16 Description[]; <-- variable length, NULL terminated
> > - *// EFI_DEVICE_PATH_PROTOCOL FilePathList[]; <--
> > FilePathListLength bytes
> > - *// UINT8 OptionalData[];
> > - *} EFI_LOAD_OPTION;
> > - */
> > -struct load_option {
> > - u32 attributes;
> > - u16 file_path_length;
> > - u16 *label;
> > - struct efi_device_path *file_path;
> > - u8 *optional_data;
> > -};
> > -
> > /* parse an EFI_LOAD_OPTION, as described above */
> > -static void parse_load_option(struct load_option *lo, void *ptr)
> > +void efi_parse_load_option(struct load_option *lo, void *ptr)
>
> I think you want to rename this to "deserialize" to better align with ...
>
> > {
> > lo->attributes = *(u32 *)ptr;
> > ptr += sizeof(u32);
> > @@ -60,7 +40,7 @@ static void parse_load_option(struct load_option *lo,
> > void *ptr)
> > ptr += sizeof(u16);
> >
> > lo->label = ptr;
> > - ptr += (u16_strlen(lo->label) + 1) * 2;
> > + ptr += (u16_strlen(lo->label) + 1) * sizeof(u16);
> >
> > lo->file_path = ptr;
> > ptr += lo->file_path_length;
> > @@ -68,6 +48,48 @@ static void parse_load_option(struct load_option *lo,
> > void *ptr)
> > lo->optional_data = ptr;
> > }
> >
> > +unsigned long efi_marshal_load_option(u32 attr, u16 *label,
>
> ... this function which really should be called "serialize" rather than
> "marshal". "Marshalling" is what you do to convert from one API to
> another. Here, we want to write an in-memory object to disk.
Well, as you know, I borrow this word from RPC world.
While I believe that those two are interchangeable in most contexts,
I don't care either way if you prefer 'serialize'.
> I also think the API would make more sense if you pass in a struct
> efi_load_option *. It's more symmetric to the deserialize one then.
Absolutely ag
Re: [U-Boot] [PATCH 3/6] efi_loader: bootmgr: add load option helper functions
On 18.10.18 09:57, AKASHI Takahiro wrote:
> On Wed, Oct 17, 2018 at 10:40:26AM +0200, Alexander Graf wrote:
>>
>>
>> On 17.10.18 09:32, AKASHI Takahiro wrote:
>>> In this patch, helper functions for an load option variable (Boot)
>>> are added:
>>> * efi_parse_load_option(): parse a string into load_option data
>>>(renamed from parse_load_option and exported)
>>> * efi_marshel_load_option(): convert load_option data into a string
>>>
>>> Those functions will be used to implement efishell command.
>>>
>>> Signed-off-by: AKASHI Takahiro
>>> ---
>>> include/efi_loader.h | 25 +
>>> lib/efi_loader/efi_bootmgr.c | 68
>>> 2 files changed, 70 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/include/efi_loader.h b/include/efi_loader.h
>>> index b73fbb6de23f..1cabb1680d20 100644
>>> --- a/include/efi_loader.h
>>> +++ b/include/efi_loader.h
>>> @@ -502,6 +502,31 @@ efi_status_t EFIAPI efi_set_variable(u16
>>> *variable_name, efi_guid_t *vendor,
>>> u32 attributes, efi_uintn_t data_size,
>>> void *data);
>>>
>>> +/*
>>> + * See section 3.1.3 in the v2.7 UEFI spec for more details on
>>> + * the layout of EFI_LOAD_OPTION. In short it is:
>>> + *
>>> + *typedef struct _EFI_LOAD_OPTION {
>>> + *UINT32 Attributes;
>>> + *UINT16 FilePathListLength;
>>> + *// CHAR16 Description[]; <-- variable length, NULL terminated
>>> + *// EFI_DEVICE_PATH_PROTOCOL FilePathList[];
>>> + * <-- FilePathListLength bytes
>>> + *// UINT8 OptionalData[];
>>> + *} EFI_LOAD_OPTION;
>>> + */
>>> +struct load_option {
>>> + u32 attributes;
>>> + u16 file_path_length;
>>> + u16 *label;
>>> + struct efi_device_path *file_path;
>>> + u8 *optional_data;
>>> +};
>>
>> If this is part of the spec, shouldn't it rather be in efi_api.h?
>
> While uefi spec mentions this structure, I don't have good confidence
> that I can say that it is part of spec or API because there is no interface
> (or function) that handles this structure.
Good point, it's internal only. Then efi_loader.h is probably a good fit.
>
>> It
>> probably also wants an efi_ prefix then :).
>
> OK.
>
>>> +
>>> +void efi_parse_load_option(struct load_option *lo, void *ptr);
>>> +unsigned long efi_marshal_load_option(u32 attr, u16 *label,
>>> + struct efi_device_path *file_path,
>>> + char *option, void **data);
>>> void *efi_bootmgr_load(struct efi_device_path **device_path,
>>>struct efi_device_path **file_path);
>>>
>>> diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
>>> index 0c5764db127b..c2d29f956065 100644
>>> --- a/lib/efi_loader/efi_bootmgr.c
>>> +++ b/lib/efi_loader/efi_bootmgr.c
>>> @@ -30,28 +30,8 @@ static const struct efi_runtime_services *rs;
>>> */
>>>
>>>
>>> -/*
>>> - * See section 3.1.3 in the v2.7 UEFI spec for more details on
>>> - * the layout of EFI_LOAD_OPTION. In short it is:
>>> - *
>>> - *typedef struct _EFI_LOAD_OPTION {
>>> - *UINT32 Attributes;
>>> - *UINT16 FilePathListLength;
>>> - *// CHAR16 Description[]; <-- variable length, NULL terminated
>>> - *// EFI_DEVICE_PATH_PROTOCOL FilePathList[]; <--
>>> FilePathListLength bytes
>>> - *// UINT8 OptionalData[];
>>> - *} EFI_LOAD_OPTION;
>>> - */
>>> -struct load_option {
>>> - u32 attributes;
>>> - u16 file_path_length;
>>> - u16 *label;
>>> - struct efi_device_path *file_path;
>>> - u8 *optional_data;
>>> -};
>>> -
>>> /* parse an EFI_LOAD_OPTION, as described above */
>>> -static void parse_load_option(struct load_option *lo, void *ptr)
>>> +void efi_parse_load_option(struct load_option *lo, void *ptr)
>>
>> I think you want to rename this to "deserialize" to better align with ...
>>
>>> {
>>> lo->attributes = *(u32 *)ptr;
>>> ptr += sizeof(u32);
>>> @@ -60,7 +40,7 @@ static void parse_load_option(struct load_option *lo,
>>> void *ptr)
>>> ptr += sizeof(u16);
>>>
>>> lo->label = ptr;
>>> - ptr += (u16_strlen(lo->label) + 1) * 2;
>>> + ptr += (u16_strlen(lo->label) + 1) * sizeof(u16);
>>>
>>> lo->file_path = ptr;
>>> ptr += lo->file_path_length;
>>> @@ -68,6 +48,48 @@ static void parse_load_option(struct load_option *lo,
>>> void *ptr)
>>> lo->optional_data = ptr;
>>> }
>>>
>>> +unsigned long efi_marshal_load_option(u32 attr, u16 *label,
>>
>> ... this function which really should be called "serialize" rather than
>> "marshal". "Marshalling" is what you do to convert from one API to
>> another. Here, we want to write an in-memory object to disk.
>
> Well, as you know, I borrow this word from RPC world.
> While I believe that those two are interchangeable in most contexts,
> I don't care either way if you prefer 'serialize'.
Ye
Re: [U-Boot] [U-Boot, 1/1] efi_loader: fix typos in efi_device_path.c
> Fix some typos in comments. > > Signed-off-by: Heinrich Schuchardt Thanks, applied to efi-next Alex ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] efi_loader: bootmgr: run an EFI application of a given load option
On 18.10.18 07:48, AKASHI Takahiro wrote: > On Wed, Oct 17, 2018 at 10:43:22AM +0200, Alexander Graf wrote: >> >> >> On 17.10.18 09:32, AKASHI Takahiro wrote: >>> With this patch applied, we will be able to selectively execute >>> an EFI application by specifying a load option, say "-1" for Boot0001, >>> "-2" for Boot0002 and so on. >>> >>> => bootefi bootmgr -1 >> >> I don't think -1 is very good user experience :). How about >> => bootefi bootmgr Boot0001 > > It looks like u-boot's run command with six more characters! > How about this: > > => bootefi bootmgr #1 So what is the problem with making it Boot0001? That way at least the variable name is consistent across the board ;). > or allowing "-" as empty fdt, > > => bootefi bootmgr - 1 > > Otherwise, a new sub command? > > => bootefi run 1, or > => efi(shell) run 1 > > # Discussing UI is a fun or mess. Yeah :(. What we really need would be that "bootefi bootmgr" becomes "efiboot". But that would be even more confusing ;). So the whole rationale of why "bootefi" is the way it is today is that it's trying to lean on the existing "bootm", "booti", "bootz" etc syntax as much as it can. In other words, it's trying to fit into the U-Boot ecosystem much rather than the existing edk2 one. I would like to keep following that path going forward. Whenever there is an option between "U-Boot like" and "edk2 like" I would always opt for the "U-Boot like" user experience, because if they want edk2 they may as well use edk2 ;). Alex ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/6] efi: make efi and bootmgr more usable
On 18.10.18 07:24, AKASHI Takahiro wrote: > On Wed, Oct 17, 2018 at 10:06:58AM +0200, Alexander Graf wrote: >> >> >> On 17.10.18 09:32, AKASHI Takahiro wrote: >>> This patch set is a collection of patches to enhance efi user interfaces >>> /commands. It will help improve user experience on efi boot and make it >>> more usable without edk2's shell utility. >> >> That's amazing, thanks a lot :) >> >>> Patch#1 to #4 are for efishell. >>> Patch#5 and #6 are for bootmgr. >>> >>> Let's see how it works: >>> => efishell boot add 1 SHELL mmc 0:1 /Shell.efi "" >>> => efishell boot add 2 HELLO mmc 0:1 /hello.efi "" >>> => efishell boot dump >> >> IMHO those 3 belong semantically to the "bootmgr" command. I can see how >> "bootefi bootmgr add 1 SHELL ..." is terrible UX. But then again it's >> not too much more to type than "efishell boot", right? ;) >> >> So at the end of the day, these should probably be >> >> => bootefi bootmgr add 1 SHELL mmc 0:1 /Shell.efi "" >> => bootefi bootmgr add 2 HELLO mmc 0:1 /hello.efi "" >> => bootefi bootmgr dump > > To be frank, I hesitate to agree with you for several reasons. > * Boot manager is a sort of boot loader application while adding/showing > Boot variables can be part of more generic system utility. > (My interface here mimics uefi shell's bcfg command with slightly >different syntax.) If you look at it from a U-Boot perspective, the only consumer of Boot variables will realistically be bootmgr. So I don't quite see how setting Boot variables doesn't belong to the same command line syntax? > * In future, we may want to have another sub command, "driver," to support > driver loading, namely DriverOrder/Driver. Hm. Who would read that order? When would it get parsed? Would that be part of the script (and thus a command again) or would we want to have them get loaded at an earlier stage? My current stance would be that driver loading would happen very similar to application loading: Using a command from a script / the shell. So the same command could again be responsible for changing the order and adding/removing driver entries. > * Anyhow, we need another command for "setvar"( and "dumpvar"). I would much much rather like to integrate with existing U-Boot commands (setenv, printenv, print) than invent new commands. The UEFI bits in U-Boot shouldn't be alien - they should just seamlessly integrate :). > >>> Boot0001: >>> attributes: A-- (0x0001) >>> label: SHELL >>> file_path: >>> /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(0)/SD(0)/HD(1,MBR,0x086246ba,0x800,0x4)/\\Shell.efi >>> data: >>> Boot0002: >>> attributes: A-- (0x0001) >>> label: HELLO >>> file_path: >>> /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(0)/SD(0)/HD(1,MBR,0x086246ba,0x800,0x4)/\\hello.efi >>> data: >>> >>> => efishell boot order 1 2 >>> => efishell boot order >> >> Same thing here :). >> >>> 1: Boot0001: SHELL >>> 2: Boot0002: HELLO >>> >>> => bootefi bootmgr -2 >>> WARNING: booting without device tree >>> Booting: HELLO >>> ## Starting EFI application at 7db8b040 ... >>> Hello, world! >>> ## Application terminated, r = 0 >>> >>> => efishell setvar PlatformLang en<--- important! >> >> That one is slightly more complicated. How about we introduce a -e flag >> to all the env operations? Then this would become >> >> => setenv -e PlatformLang en >> >> and you could print only EFI variables using >> >> => printenv -e >> >> maybe one day we could then also just implement partial variable storage >> for UEFI variables: >> >> => saveenv -e >> >> which we could then reuse in the ExitBootServices() call to persist EFI >> variables? > > I didn't get your point. Can you please elaborate it? Currently we have: => help printenv printenv - print environment variables Usage: printenv [-a] - print [all] values of all environment variables printenv name ... - print value of environment variable 'name' => help setenv setenv - set environment variables Usage: setenv [-f] name value ... - [forcibly] set environment variable 'name' to 'value ...' setenv [-f] name - [forcibly] delete environment variable 'name' What if we add UEFI variable awareness to those commands? So instead of => efishell setvar PlatformLang en you would get => setenv -e PlatformLang en The same would apply for printenv. Something like => printenv -e would just show UEFI variables with potential additional decoding? Or was your question on saveenv? The saveenv command is used to make the variable storage persistent. One problem we have with variable storage is that you want to only persist variables that are a) marked to persist b) UEFI variables So for example if you're in the middle of a script and you want to change the boot order, you want to say "please make the UEFI variable store persistent now", but you definitely do now want to make the U-Boot variable store persistent, because your varia
[U-Boot] [PATCH v5 1/1] efi_loader: PSCI reset and shutdown
When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.
The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.
The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.
As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
---
Travis reporteded no errors in
https://travis-ci.org/xypron2/u-boot/builds/442613876
v5:
depend on CONFIG_PSCI_reset for EFI runtime support
v4:
fix reset_misc() too
avoid switch statement
v3:
update commit message
v2:
Use PSCI firmware driver to detect call method.
Thanks to Sumit for pointing me at dtb parsing as part of
"psci_probe()
---
arch/arm/cpu/armv7/smccc-call.S | 2 +
arch/arm/cpu/armv8/Kconfig | 1 +
arch/arm/cpu/armv8/fwcall.c | 52 ++---
arch/arm/cpu/armv8/smccc-call.S | 2 +
drivers/firmware/psci.c | 100 +++-
include/linux/psci.h| 6 +-
6 files changed, 96 insertions(+), 67 deletions(-)
diff --git a/arch/arm/cpu/armv7/smccc-call.S b/arch/arm/cpu/armv7/smccc-call.S
index 0d8b59eb6b..eae69e36c3 100644
--- a/arch/arm/cpu/armv7/smccc-call.S
+++ b/arch/arm/cpu/armv7/smccc-call.S
@@ -7,6 +7,8 @@
#include
#include
+ .section.text.efi_runtime
+
#define UNWIND(x...)
/*
* Wrap c macros in asm macros to delay expansion until after the
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index c8bebabdf6..d643981b73 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -96,6 +96,7 @@ endmenu
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
default y
+ select ARM_SMCCC if OF_CONTROL
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 0ba3dad8cc..9957c2974b 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -7,7 +7,6 @@
#include
#include
-#include
#include
#include
#include
@@ -19,7 +18,7 @@
* x0~x7: input arguments
* x0~x3: output arguments
*/
-static void __efi_runtime hvc_call(struct pt_regs *args)
+static void hvc_call(struct pt_regs *args)
{
asm volatile(
"ldr x0, %0\n"
@@ -53,7 +52,7 @@ static void __efi_runtime hvc_call(struct pt_regs *args)
* x0~x3: output arguments
*/
-void __efi_runtime smc_call(struct pt_regs *args)
+void smc_call(struct pt_regs *args)
{
asm volatile(
"ldr x0, %0\n"
@@ -83,9 +82,9 @@ void __efi_runtime smc_call(struct pt_regs *args)
* use PSCI on U-Boot running below a hypervisor, please detect
* this and set the flag accordingly.
*/
-static const __efi_runtime_data bool use_smc_for_psci = true;
+static const bool use_smc_for_psci = true;
-void __noreturn __efi_runtime psci_system_reset(void)
+void __noreturn psci_system_reset(void)
{
struct pt_regs regs;
@@ -100,7 +99,7 @@ void __noreturn __efi_runtime psci_system_reset(void)
;
}
-void __noreturn __efi_runtime psci_system_off(void)
+void __noreturn psci_system_off(void)
{
struct pt_regs regs;
@@ -114,44 +113,3 @@ void __noreturn __efi_runtime psci_system_off(void)
while (1)
;
}
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- puts("poweroff ...\n");
-
- udelay(5); /* wait 50 ms */
-
- disable_interrupts();
-
- psci_system_off();
-
- /*NOTREACHED*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_PSCI_RESET
-void reset_misc(void)
-{
- psci_system_reset();
-}
-
-#ifdef CONFIG_EFI_LOADER
-void __efi_runtime EFIAPI efi_reset_system(
- enum efi_reset_type reset_type,
- efi_status_t reset_status,
- unsigned long data_size, void *reset_data)
-{
- if (reset_type == EFI_RESET_COLD ||
- reset_type == EFI_RESET_WARM ||
- reset_type == EFI_RESET_PLATFORM_SPECIFIC) {
- psci_system_reset();
- } else if (re
[U-Boot] [PATCH] Kconfig: Convert CONFIG_IMX_WATCHDOG to Kconfig
Move this option to Kconfig and tidy up the config file of eight boards which use it. Signed-off-by: Xiaoliang Yang --- configs/aristainetos2_defconfig |1 + configs/aristainetos2b_defconfig |1 + configs/aristainetos_defconfig|1 + configs/dh_imx6_defconfig |1 + configs/display5_defconfig|1 + configs/display5_factory_defconfig|1 + configs/ge_bx50v3_defconfig |1 + configs/kp_imx6q_tpc_defconfig|1 + configs/mx53ppd_defconfig |1 + configs/tqma6s_wru4_mmc_defconfig |1 + configs/warp_defconfig|1 + drivers/watchdog/Kconfig |7 +++ include/configs/aristainetos-common.h |3 --- include/configs/dh_imx6.h |2 -- include/configs/display5.h|2 -- include/configs/ge_bx50v3.h |2 -- include/configs/kp_imx6q_tpc.h|2 -- include/configs/mx53ppd.h |2 -- include/configs/tqma6_wru4.h |2 -- include/configs/warp.h|2 -- scripts/config_whitelist.txt |1 - 21 files changed, 18 insertions(+), 18 deletions(-) diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 5044a59..c55e39c 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -50,4 +50,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 6641382..95c3063 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -50,4 +50,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index 6a31ee6..4082b12 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -49,4 +49,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 2cb7164..92b2377 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -59,4 +59,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 697138e..ab5ec59 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -75,3 +75,4 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 5962b64..5d1c746 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -82,4 +82,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 729377d..c907779 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -41,5 +41,6 @@ CONFIG_CMD_E1000=y CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 84ca1ce..5ebbe1d 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -40,4 +40,5 @@ CONFIG_MII=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 7be5c04..34328fd 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -37,4 +37,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index df4c87e..c1be704 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -65,4 +65,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 6a9c91e..63eee27 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -37,4 +37,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d545b3e..02f4e1e 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -111,4 +111,11 @@ co
[U-Boot] [PATCH v2 1/2] watchdog: driver support for fsl-lsch2
Support watchdog driver for fsl-lsch2. It's disabled in default. If you want to use it, please enable CONFIG_IMX_WATCHDOG. Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout. Signed-off-by: Xiaoliang Yang --- v1->v2: Remove LSCH3 config from imx-watchdog.c, because it only support LSCH2 platforms. Use Kconfig option IMX_WATCHDOG to introduce how to use watchdog driver in README.lsch2. --- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 |9 + drivers/watchdog/Makefile |2 ++ drivers/watchdog/imx_watchdog.c|7 +++ 3 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 index a6ef830..9176546 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 @@ -8,3 +8,12 @@ Freescale LayerScape with Chassis Generation 2 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, for example LS1043A. + +Watchdog support Overview +--- +Support watchdog driver for LSCH2. The driver is disabled in default. +You can enable it by setting CONFIG_IMX_WATCHDOG. +Use following config to set watchdog timeout, if this config is not defined, +the default timeout value is 128s which is the maximum. Set 10 seconds for +example: +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 1 diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 08406ca..19c631b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o +else +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 3f826d1..ddcf474 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,6 +8,9 @@ #include #include #include +#ifdef CONFIG_FSL_LSCH2 +#include +#endif #include #ifdef CONFIG_IMX_WATCHDOG @@ -33,8 +36,12 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; +#ifdef CONFIG_FSL_LSCH2 + writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); +#else writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); +#endif /* CONFIG_FSL_LSCH2*/ hw_watchdog_reset(); } #endif -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] watchdog: imx: add config to disable wdog reset
Add Kconfig option WATCHDOG_RESET_DISABLE to disable watchdog reset
in imx_watchdog driver, so that the watchdog will not be fed in
u-boot if CONFIG_WATCHDOG_RESET_DISABLE is enabled.
Signed-off-by: Xiaoliang Yang
---
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 |2 ++
drivers/watchdog/Kconfig |6 ++
drivers/watchdog/imx_watchdog.c|2 ++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
index 9176546..9583bf7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
@@ -17,3 +17,5 @@ Use following config to set watchdog timeout, if this config
is not defined,
the default timeout value is 128s which is the maximum. Set 10 seconds for
example:
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 1
+Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the
+watchdog will not be fed in u-boot.
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d545b3e..d5dbc80 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -11,6 +11,12 @@ config WATCHDOG
config HW_WATCHDOG
bool
+config WATCHDOG_RESET_DISABLE
+ bool "Disable reset watchdog"
+ help
+ Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
+ that the watchdog will not be fed in u-boot.
+
config BCM2835_WDT
bool "Enable BCM2835/2836 watchdog driver"
select HW_WATCHDOG
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index ddcf474..14cc618 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -16,10 +16,12 @@
#ifdef CONFIG_IMX_WATCHDOG
void hw_watchdog_reset(void)
{
+#ifndef CONFIG_WATCHDOG_RESET_DISABLE
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
writew(0x, &wdog->wsr);
writew(0x, &wdog->wsr);
+#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
}
void hw_watchdog_init(void)
--
1.7.1
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Re: [U-Boot] [RFC PATCH v2 3/3] tools: Add a tool to get an overview of the usage of CONFIG options
Simon, On 09/10/2018 18:20, Simon Glass wrote: Hi Jean-Jacques, On 3 October 2018 at 07:53, Jean-Jacques Hiblot wrote: configs2csv.py is tool that allow to check how some options are used for a particular subset of platforms. The purpose is to identify the targets that are actually using one or more options of interest. For example, it can tell what targets are still using CONFIG_DM_I2_COMPAT. It relies on the config database produced by tools/moveconfig.py. If the database doesn't exist, it will build it for the restricted set of the selected platforms. Once the database is built, it is much faster than greping the configs directory and more accurate as it relies on the information found in u-boot.cfg instead of defconfigs. It possible to look for options in the u-boot, the SPL or the TPL configurations. It can also perform diffs between those configurations. usage: configs2csv.py [-h] [-X] [--u-boot] [--spl] [--tpl] [--diff] [--rebuild-db] [-j JOBS] [-o OUTPUT] [--no-header] [--discard-empty] [-i] [--soc SOC] [--vendor VENDOR] [--arch ARCH] [--cpu CPU] [--board BOARD] [--target TARGET] OPTION [OPTION ...] all filtering parameters (OPTION, vendor, arch, ...) accept regexp. ex: configs2csv.py .*DM_I2C.* --soc 'omap[2345]|k3' will match CONFIG_DM_I2C and CONFIG_DM_I2C_COMPAT and look for it only for targets using the omap2, omap3, omap4, omap5 or k3 SOCs. Signed-off-by: Jean-Jacques Hiblot --- Changes in v2: - basically rewrote the whole thing - use tools/moveconfig.py to generate the database of configs - use tools/find_defconfigs.py to get the list of defconfigs off interest - removed diff with .config. tools/moveconfig.py does a better job tools/configs2csv.py | 387 +++ 1 file changed, 387 insertions(+) create mode 100755 tools/configs2csv.py This looks like a useful tool and a big improvement on the movconfig starting point. Style comments below. Thanks for the review. I'll send a v3 taking care of the comments in a couple of days. diff --git a/tools/configs2csv.py b/tools/configs2csv.py new file mode 100755 index 000..70b6602 --- /dev/null +++ b/tools/configs2csv.py @@ -0,0 +1,387 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: GPL-2.0+ +# +# Author: JJ Hiblot +# + +""" +scan the configuration of specified targets (ie defconfigs) and outputs a +summary in a csv file. +Useful tool to check what platform is using a particular set of options. + + +How does it work? +- + +This tools uses the config database produced by tools/moveconfig.py (called +with option -B to get all the configs: SPl, TPL and u-boot). If the database +is not present, it will build it. A rebuild can be forced with the option +'--rebuild-db'. + +The list of the targets of interest can be specified by a set of filter (soc, +vendor, defconfig name, ..). All those filters are actually regexp, allowing +for complex selection. The selection process is done by +tools/find_defconfigs.py +ex: --soc omap[23] --vendor 'ti|compulab' will inspect the omap2 and omap3 +platforms from TI and compulab + + +examples: +- + + +1) Get an overview of the usage of CONFIG_DM, CONFIG_SPL_DM, and DM/I2C related + options for platforms with omap5 or k3 SOC in u-boot and in SPL + +$ tools/configs2csv.py CONFIG_SPL_DM CONFIG_DM CONFIG_DM_I2C.* --vendor ti \ + --soc 'omap5|k3' -X --u-boot --spl -o dummy.csv + Is this output below showing the contents of the ,csv file in a non-CVS format? Yes. This represents what we would see in a spreadsheet viewer. The csv output is not easily readable. +vendor socdefconfigtype CONFIG_DM CONFIG_DM_I2C CONFIG_DM_I2C_COMPAT CONFIG_SPL_DM +ti omap5 am57xx_evm_defconfigSPL X X +ti omap5 am57xx_evm_defconfigu-boot X X XX +ti omap5 am57xx_hs_evm_defconfig SPL X X +ti omap5 am57xx_hs_evm_defconfig u-boot X X XX +ti k3am65x_evm_a53_defconfig SPL X X +ti k3am65x_evm_a53_defconfig u-boot X X +ti omap5 dra7xx_evm_defconfigSPL X X +ti omap5 dra7xx_evm_defconfigu-boot X X XX +ti omap5 dra7xx_hs_evm_defconfig SPL X X +ti omap5 dra7xx_hs_evm_defconfig u-boot X X XX +ti omap5 omap5_uevm_defconfigSPL
[U-Boot] [PATCH] ARM: mvebu: dts: add Clearfog GT-8K
From: Rabeeh Khoury
The SolidRun Clearfog GT-8K is based on Armada 8040.
https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k
Signed-off-by: Rabeeh Khoury
Signed-off-by: Baruch Siach
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 315
2 files changed, 316 insertions(+)
create mode 100644 arch/arm/dts/armada-8040-clearfog-gt-8k.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 44ebc50bfab1..c9a23ea68450 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-7040-db-nand.dtb \
armada-8040-db.dtb \
armada-8040-mcbin.dtb \
+ armada-8040-clearfog-gt-8k.dtb \
armada-xp-gp.dtb\
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
new file mode 100644
index ..015ef35b0d81
--- /dev/null
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 SolidRun ltd
+ */
+
+#include "armada-8040.dtsi"
+
+/ {
+ model = "ClearFog-GT-8K";
+ compatible = "solidrun,armada8040-cf-gt-8k",
+"marvell,armada8040";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cpm_i2c0;
+ i2c1 = &cpm_i2c1;
+ spi0 = &cps_spi1;
+ };
+
+ memory@ {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ simple-bus {
+ compatible = "simple-bus";
+
+ reg_usb3h0_vbus: usb3-vbus0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ regulator-name = "reg-usb3h0-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ startup-delay-us = <30>;
+ shutdown-delay-us = <50>;
+ regulator-force-boot-off;
+ gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&ap_pinctl {
+ /*
+* MPP Bus:
+* eMMC [0-10]
+* UART0 [11,19]
+*/
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+1 3 0 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&cpm_pinctl {
+ /*
+* MPP Bus:
+* [0-31] = 0xff: Keep default CP0_shared_pins:
+* [11] CLKOUT_MPP_11 (out)
+* [23] LINK_RD_IN_CP2CP (in)
+* [25] CLKOUT_MPP_25 (out)
+* [29] AVS_FB_IN_CP2CP (in)
+* [32, 33, 34] pci0/1/2 reset
+* [35-38] CP0 I2C1 and I2C0
+* [39] GPIO reset button
+* [40,41] LED0 and LED1
+* [43] 1512 phy reset
+* [47] USB VBUS EN (active low)
+* [48] FAN PWM
+* [49] SFP+ present signal
+* [50] TPM interrupt
+* [51] WLAN0 disable
+* [52] WLAN1 disable
+* [53] LTE disable
+* [54] NFC reset
+* [55] Micro SD card detect
+* [56-61] Micro SD
+*/
+ /* 0123456789 */
+ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0xff 000022220
+0000000000
+0000000xe 0xe 0xe 0xe
+0xe 0xe 0 >;
+
+ cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ marvell,pins = < 47 >;
+ marvell,function = <0>;
+ };
+
+ cps_1g_phy_reset: cps-1g-phy-reset {
+ marvell,pins = < 43 >;
+ marvell,function = <0>;
+ };
+};
+
+/* uSD slot */
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&cpm_pcie0 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+&cpm_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <10>;
+};
+
+&cpm_i2c1 {
+ pinctrl-names = "default";
Re: [U-Boot] [RFC PATCH v2 2/3] tools: Add a tool to get a list of defconfigs based on filters
On 09/10/2018 18:20, Simon Glass wrote:
Hi Jean-Jacques,
On 3 October 2018 at 07:53, Jean-Jacques Hiblot wrote:
The possible filters are "arch", "vendor", "soc", "cpu" and "arch".
The list of all the defconfigs is read from boards.cfg. If this file
doesn't exist, then tools/genboardscfg.py is called to generate it.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
tools/find_defconfigs.py | 167 +++
1 file changed, 167 insertions(+)
create mode 100755 tools/find_defconfigs.py
This looks good, but I have some style comments below.
Also it seems to do a similar thing to tools/buildman/board.py. Should
we replace that impl with what you have here? It looks more flexible
that what buildman currently provides.
It is very similar indeed and they certainly overlap. When time permits,
I'll look at the possibility to re-use this code in buildman.
diff --git a/tools/find_defconfigs.py b/tools/find_defconfigs.py
new file mode 100755
index 000..9d68cef
--- /dev/null
+++ b/tools/find_defconfigs.py
@@ -0,0 +1,167 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Author: JJ Hiblot
+#
+
+"""
+Output a list of defconfig matching criteria.
I think you mean defconfig-matching?
+
+The possible criteria are soc, vendor, arch, cpu, board and defconfig name.
+The criteria are expressed as regexp, allowing for complex selection.
+
+How does it work?
+-
+
+This tools uses the boards.cfg file produced by tools/genboardscfg.py
+It reads the file to get a list of all the defconfigs and the information
+about the soc, vendor etc. for each of them.
+Then it walks this list and outputs the defconfigs for which the info match
+the regexp passed to the program.
+
+examples:
+-
+
+1) Get the list of defconfigs for boards built around omap5, omap4 and k3, not
built by TI
+
+$ tools/find_defconfigs.py --soc 'omap[45]|k3' --vendor '(?!ti)'
+kc1_defconfig
+duovero_defconfig
+cl-som-am57x_defconfig
+cm_t54_defconfig
+
+2) Same list but iwth more details on the items that were used as filters
+
+$ tools/find_defconfigs.py --soc 'omap[45]|k3' --vendor '(?!ti)'
--show-details
+kc1_defconfig | omap4 | amazon
+duovero_defconfig | omap4 | gumstix
+cl-som-am57x_defconfig | omap5 | compulab
+cm_t54_defconfig | omap5 | compulab
+
+
+"""
+
+import re
+import os
+import argparse
Please sort these
+
+
+class board:
+
Need a class comment here, also use Board since it is a class name
+def __init__(self, status, arch, cpu, soc,
+ vendor, board, target, options, maintainer):
+self.status = status
+self.arch = arch
+self.cpu = cpu
+self.soc = soc
+self.vendor = vendor
+self.board = board
+self.target = target
+self.defconfig = "{}_defconfig".format(target)
+self.options = options
+self.maintainer = maintainer
+
+def show(self, sep=' | ', props=None):
Function comment (see other tools for style). Need to document args
and any return value.
+if not props:
+print(
+sep.join([self.defconfig,
+ self.vendor,
+ self.arch,
+ self.cpu,
+ self.soc,
+ self.board,
+ self.status,
+ self.maintainer]))
+else:
+print(sep.join([self.defconfig] + [getattr(self, prop) for prop in
props]))
Does this need to import print_function from __future__ for Python 2?
+
+def cleanup(self):
+""" remove the directory in which the cfg files have been built """
Please use comment style from other tools. Same below.
+shutil.rmtree(self.temp_dir)
+
+def match(self, rules):
+""" return True if the board match all the criteria """
+for prop, r in rules:
+val = getattr(self, prop)
+if not val or val == "-":
+return False
+if not r.match(val):
+return False
+return True
+
+
+def get_all_boards():
+""" extract a list of boards from 'boards.cfg' """
+result = []
+if not os.path.isfile("boards.cfg"):
+os.system('tools/genboardscfg.py')
+
+with open('boards.cfg', 'r') as f:
+for l in f.readlines():
+if not l or l[0] == "#":
+continue
+props = l.strip().split(None, 8)
+if not props:
+continue
+if len(props) < 9:
+props.extend(["-"] * (9 - len(props)))
+result.append(board(*props))
+return result
+
+
+def get_default_options():
+return ["board", "soc", "vendor", "arch", "cpu", "target"]
+
+
+def update_parser_with_default_options(parser):
+parser.add_argument('-i', '--ignore-case', action="store_true")
+parser.add_argument("--soc",
+help="r
[U-Boot] [PATCH v6 00/34] i.MX: Add i.MX8QXP support
This patchset is to upstream basic i.MX8QXP and MEK board support, with some drivers update to support i.MX8QXP. The information about the processor could be found under https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource management/thermal and etc. V6: This series was rebased on master and addresses some v5 review comments and additionally adds FEC support. Summary of the changes to v5 patches is below. Patch 08/32: - fixed error string: s/clk/iomux Patch 09/32: - minor coding style fix (dropped empty lines), added API functions for reading SCFW buildinfo and for reading MAC address from fuses Patch 18/32: - fixed typo in subject and one line over 80 chars warning Patch 19/32: - s/u-boot/U-Boot in comments Added two new patches (20/34 and 21/34) for adding uclass cpu driver and extension for reading MAC address from fuses (required for FEC driver) Extended original patch 25/32: - added support for more I2C/ENET/UART clocks, added 'clk dump' command - fixed to propagate error codes (if returned by sc_pm_* API) to the caller - fixed printf formatting in debug() - extended for clock ID range checks to differentiate between not yet supported and invalid clock IDs. Patch 28/32: - guard get_lpuart_clk_rate() by IS_ENABLED to prevent build issues Patch 30/32: - propagate error code if clk api calls fail Patch 31/32: - added FEC nodes and aliases Patch 32/32: In DTS: - added fec1 support, pca9646 switch description on i2c1 bus with i2c slaves - removed not used 'pinctrl-assert-gpios' property - s/lpi1cgrp/lpi2c1grp/ - added 'dm-pre-reloc' to cpu0 node (needed for print_cpuinfo()!) In board code: - reworked gpio init (repaced by init via properties in DTS), dropped GPIO5_9 mux init (was unused, will be added later when adding USB support) - added board_phy_config() for FEC0 support - added SCFW build info output - moved CONFIG_MXC_GPIO from board config header to defconfig - added required FEC driver options to the board config header - updated defconfig: enabled 'clk', 'cpu' and 'dm' commands, PHY, FEC, MII and MXC GPIO support V5: Addressed Lothar Waßmann's comments for patch 24 and 32. Rebased on master. V4: Add reviewed tag from Anatolij Gustschin Addressed comments from Anatolig for patch "misc: add i.MX8 misc driver" Addressed comments from Anatolig for patch "misc: imx8: add scfw api impementation" Merged the files into one Moved one error handle to patch 4 Moved patch "arm: global_data: add scu_dev for i.MX8" to patch 7 For Fabio's comments to imx-mkimage, I'll start the porting work, but needs more time, it will be not be in this patchset. V3: patch 7: use CONFIG_IMX8 patch 29: use CONFIG_IMX8 patch 32: Added README with scfw_tcm.bin link added misc: remove sc_rpc_msg_t typedef, use struct sc_rpc_msg_s in patchset. V2: In this V2 patchset, the SCFW API is replaced by uclass driver implementation, but the api name is not changed from scfw api. The related macro definitions are kept in different api.h file following SCFW API file structure. Impelemnted scu misc driver to handle the low level communication between Acore and SCU. Implemented rm/pm/pad/misc protocol code to invoke misc_call for different functionality. The dm clk/pinctrl/power and others will invokde the protocol api to communicate with SCU. The arch/arm/mach-imx/imx8/clock.c currently is only a dummy file to avoid build break for mxc_get_clock. The i2c patch and common power domain patches are removed from this patchset. The imx8 name still kept, this is because NXP marketing requires to use this name for i.MX branding. Anatolij Gustschin (2): imx8: cpu: add function for reading FEC MAC from fuse imx8: cpu: add uclass based CPU driver Peng Fan (30): dt-bindings: pinctrl: add i.MX8QXP pads definition dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition dt-bindings: soc: add i.MX8QXP pm and rsrc definition imx8: add scfw macro definition imx: add Kconfig entry for i.MX8QXP arm: build mach-imx for i.MX8 arm: global_data: add scu_dev for i.MX8 misc: add i.MX8 misc driver misc: imx8: add scfw api impementation imx: boot_mode: Add FLEXSPI boot entry imx8: add imx-regs header file imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined imx: add i.MX8 cpu type armv8: add cpu core helper functions imx8: add basic cpu support imx8: add boot device detection imx8: implement mmc_get_env_dev imx8: add mmu and dram related functions imx8: add arch_cpu_init arch_cpu_init_dm imx8: add iomux configuration api imx8: add dummy clock gpio: mxc_gpio: add support for i.MX8 pinctrl: Add pinctrl d
[U-Boot] [PATCH v6 01/34] dt-bindings: pinctrl: add i.MX8QXP pads definition
From: Peng Fan Add i.MX8QXP pads definition Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 + 1 file changed, 757 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 00..41f4fe564c --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,757 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_PADS_H +#define _SC_PADS_H + +#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */ +#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO8 /* */ +#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10/* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15/* */ +#define SC_P_EMMC0_DATA4 16/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 17/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 18/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 19/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE20/* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 21/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22/* */ +#define SC_P_USDHC1_RESET_B 23/* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */ +#define SC_P_USDHC1_VSELECT 24/* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */ +#define SC_P_CTL_NAND_RE_P_N 25/* */ +#define SC_P_USDHC1_WP 26/* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */ +#define SC_P_USDHC1_CD_B 27/* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_CTL_NAND_DQS_P_N28/* */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29/* */ +#define SC_P_USDHC1_CLK 30/* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ +#define SC_P_USDHC1_CMD 31/* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ +#define SC_P_USDHC1_DATA032/* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */ +#define SC_P_USDHC1_DATA133/* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ +#define SC_P_USDHC1_DATA234/* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */ +#define SC_P_USDHC1_DATA335/* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36/* */ +#define SC_P_ENET0_RGMII_TXC 37/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */ +#define SC_P_ENET0_RGMII_TX_CTL 38/* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ +#define SC_P
[U-Boot] [PATCH v6 02/34] dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition
From: Peng Fan Add i.MX8QXP clocks definition Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- include/dt-bindings/clock/imx8qxp-clock.h | 583 ++ 1 file changed, 583 insertions(+) create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h new file mode 100644 index 00..d0334ea398 --- /dev/null +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -0,0 +1,583 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H +#define __DT_BINDINGS_CLOCK_IMX8QXP_H + +#define IMX8QXP_CLK_DUMMY 0 + +#define IMX8QXP_UART0_IPG_CLK 1 +#define IMX8QXP_UART0_DIV 2 +#define IMX8QXP_UART0_CLK 3 + +#define IMX8QXP_IPG_DMA_CLK_ROOT 4 + +/* GPU Clocks. */ +#define IMX8QXP_GPU0_CORE_DIV 5 +#define IMX8QXP_GPU0_CORE_CLK 6 +#define IMX8QXP_GPU0_SHADER_DIV7 +#define IMX8QXP_GPU0_SHADER_CLK8 + +#define IMX8QXP_24MHZ 9 +#define IMX8QXP_GPT_3M 10 +#define IMX8QXP_32KHZ 11 + +/* LSIO SS */ +#define IMX8QXP_LSIO_MEM_CLK 12 +#define IMX8QXP_LSIO_BUS_CLK 13 +#define IMX8QXP_LSIO_PWM0_DIV 14 +#define IMX8QXP_LSIO_PWM0_IPG_S_CLK15 +#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK 16 +#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK 17 +#define IMX8QXP_LSIO_PWM0_HF_CLK 18 +#define IMX8QXP_LSIO_PWM0_CLK 19 +#define IMX8QXP_LSIO_PWM1_DIV 20 +#define IMX8QXP_LSIO_PWM1_IPG_S_CLK21 +#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK 22 +#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK 23 +#define IMX8QXP_LSIO_PWM1_HF_CLK 24 +#define IMX8QXP_LSIO_PWM1_CLK 25 +#define IMX8QXP_LSIO_PWM2_DIV 26 +#define IMX8QXP_LSIO_PWM2_IPG_S_CLK27 +#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_PWM2_HF_CLK 30 +#define IMX8QXP_LSIO_PWM2_CLK 31 +#define IMX8QXP_LSIO_PWM3_DIV 32 +#define IMX8QXP_LSIO_PWM3_IPG_S_CLK33 +#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK 34 +#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK 35 +#define IMX8QXP_LSIO_PWM3_HF_CLK 36 +#define IMX8QXP_LSIO_PWM3_CLK 37 +#define IMX8QXP_LSIO_PWM4_DIV 38 +#define IMX8QXP_LSIO_PWM4_IPG_S_CLK39 +#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK 40 +#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK 42 +#define IMX8QXP_LSIO_PWM4_HF_CLK 43 +#define IMX8QXP_LSIO_PWM4_CLK 44 +#define IMX8QXP_LSIO_PWM5_DIV 45 +#define IMX8QXP_LSIO_PWM5_IPG_S_CLK46 +#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK 47 +#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK 48 +#define IMX8QXP_LSIO_PWM5_HF_CLK 49 +#define IMX8QXP_LSIO_PWM5_CLK 50 +#define IMX8QXP_LSIO_PWM6_DIV 51 +#define IMX8QXP_LSIO_PWM6_IPG_S_CLK52 +#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_PWM6_HF_CLK 55 +#define IMX8QXP_LSIO_PWM6_CLK 56 +#define IMX8QXP_LSIO_PWM7_DIV 57 +#define IMX8QXP_LSIO_PWM7_IPG_S_CLK58 +#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK 59 +#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK 60 +#define IMX8QXP_LSIO_PWM7_HF_CLK 61 +#define IMX8QXP_LSIO_PWM7_CLK 62 +#define IMX8QXP_LSIO_GPT0_DIV 63 +#define IMX8QXP_LSIO_GPT0_IPG_S_CLK
[U-Boot] [PATCH v6 03/34] dt-bindings: soc: add i.MX8QXP pm and rsrc definition
From: Peng Fan Add i.MX8QXP power and resource definition Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- include/dt-bindings/soc/imx8_pd.h | 188 ++ include/dt-bindings/soc/imx_rsrc.h | 557 + 2 files changed, 745 insertions(+) create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h new file mode 100644 index 00..682b608eef --- /dev/null +++ b/include/dt-bindings/soc/imx8_pd.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __DT_BINDINGS_IMX8_PD_H +#define __DT_BINDINGS_IMX8_PD_H + +/*! + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +#define PD_DC_0 dc0_power_domain +#define PD_DC_0_PLL_0 dc0_pll0 +#define PD_DC_0_PLL_1 dc0_pll1 +#define PD_LVDS0lvds0_power_domain +#define PD_LVDS0_I2C0 lvds0_i2c0 +#define PD_LVDS0_I2C1 lvds0_i2c1 +#define PD_LVDS0_PWMlvds0_pwm +#define PD_LVDS0_PWMlvds0_pwm +#define PD_LVDS0_GPIO lvds0_gpio +#define PD_DC_1 dc1_power_domain +#define PD_DC_1_PLL_0 dc1_pll0 +#define PD_DC_1_PLL_1 dc1_pll1 +#define PD_LVDS1lvds1_power_domain +#define PD_LVDS1_I2C0 lvds1_i2c0 +#define PD_LVDS1_I2C1 lvds1_i2c1 +#define PD_LVDS1_PWMlvds1_pwm +#define PD_LVDS1_GPIO lvds1_gpio + +#define PD_DMA dma_power_domain +#define PD_DMA_SPI_0dma_spi0 +#define PD_DMA_SPI_1dma_spi1 +#define PD_DMA_SPI_2dma_spi2 +#define PD_DMA_SPI_3dma_spi3 +#define PD_DMA_UART0dma_lpuart0 +#define PD_DMA_UART1dma_lpuart1 +#define PD_DMA_UART2dma_lpuart2 +#define PD_DMA_UART3dma_lpuart3 +#define PD_DMA_UART4dma_lpuart4 +#define PD_DMA_EMVSIM_0 dma_emvsim0 +#define PD_DMA_EMVSIM_1 dma_emvsim1 +#define PD_DMA_I2C_0dma_lpi2c0 +#define PD_DMA_I2C_1dma_lpi2c1 +#define PD_DMA_I2C_2dma_lpi2c2 +#define PD_DMA_I2C_3dma_lpi2c3 +#define PD_DMA_I2C_4dma_lpi2c4 +#define PD_DMA_ADC_0dma_adc0 +#define PD_DMA_ADC_1dma_adc1 +#define PD_DMA_FTM_0dma_ftm0 +#define PD_DMA_FTM_1dma_ftm1 +#define PD_DMA_CAN_0dma_flexcan0 +#define PD_DMA_CAN_1dma_flexcan1 +#define PD_DMA_CAN_2dma_flexcan2 +#define PD_DMA_PWM_0dma_pwm0 +#define PD_DMA_LCD_0dma_lcd0 + +#define PD_HSIO hsio_power_domain +#define PD_HSIO_PCIE_A hsio_pcie0 +#define PD_HSIO_PCIE_B hsio_pcie1 +#define PD_HSIO_SATA_0 hsio_sata0 +#define PD_HSIO_GPIOhsio_gpio + +#define PD_LCD_0lcd0_power_domain +#define PD_LCD_0_I2C_0 lcd0_i2c0 +#define PD_LCD_0_I2C_1 lcd0_i2c1 +#define PD_LCD_PWM_0lcd0_pwm0 + +#define PD_LSIO lsio_power_domain +#define PD_LSIO_GPIO_0 lsio_gpio0 +#define PD_LSIO_GPIO_1 lsio_gpio1 +#define PD_LSIO_GPIO_2 lsio_gpio2 +#define PD_LSIO_GPIO_3 lsio_gpio3 +#define PD_LSIO_GPIO_4 lsio_gpio4 +#define PD_LSIO_GPIO_5 lsio_gpio5 +#define PD_LSIO_GPIO_6 lsio_gpio6 +#define PD_LSIO_GPIO_7 lsio_gpio7 +#define PD_LSIO_GPT_0 lsio_gpt0 +#define PD_LSIO_GPT_1 lsio_gpt1 +#define PD_LSIO_GPT_2 lsio_gpt2 +#define PD_LSIO_GPT_3 lsio_gpt3 +#define PD_LSIO_GPT_4 lsio_gpt4 +#define PD_LSIO_KPP lsio_kpp +#define PD_LSIO_FSPI_0 lsio_fspi0 +#define PD_LSIO_FSPI_1 lsio_fspi1 +#define PD_LSIO_PWM_0 lsio_pwm0 +#define PD_LSIO_PWM_1 lsio_pwm1 +#define PD_LSIO_PWM_2 lsio_pwm2 +#define PD_LSIO_PWM_3 lsio_pwm3 +#define PD_LSIO_PWM_4 lsio_pwm4 +#define PD_LSIO_PWM_5 lsio_pwm5 +#define PD_LSIO_PWM_6 lsio_pwm6 +#define PD_LSIO_PWM_7 lsio_pwm7 + +#define PD_CONN connectivity_power_domain +#define PD_CONN_SDHC_0 conn_sdhc0 +#define PD_CONN_SDHC_1 conn_sdhc1 +#define PD_CONN_SDHC_2 conn_sdhc2 +#define PD_CONN_ENET_0 conn_enet0 +#define PD_CONN_ENET
[U-Boot] [PATCH v6 05/34] imx: add Kconfig entry for i.MX8QXP
From: Peng Fan Add Kconfig entry for i.MX8QXP Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/Kconfig | 8 arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 13 + 3 files changed, 22 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c7168e0cc3..afc5a77a53 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -668,6 +668,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_IMX8 + bool "NXP i.MX8 platform" + select ARM64 + select DM + select OF_CONTROL + config ARCH_MX8M bool "NXP i.MX8M platform" select ARM64 @@ -1416,6 +1422,8 @@ source "arch/arm/mach-imx/mx7/Kconfig" source "arch/arm/mach-imx/mx7ulp/Kconfig" +source "arch/arm/mach-imx/imx8/Kconfig" + source "arch/arm/mach-imx/mx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 733c308670..375789efb2 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -141,3 +141,4 @@ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_ARCH_IMX8) += imx8/ diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig new file mode 100644 index 00..28910c1509 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -0,0 +1,13 @@ +if ARCH_IMX8 + +config IMX8 + bool + +config IMX8QXP + select IMX8 + bool + +config SYS_SOC + default "imx8" + +endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 04/34] imx8: add scfw macro definition
From: Peng Fan
Add SCFW macro definition.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 +
arch/arm/include/asm/arch-imx8/sci/sci.h | 58 +
.../include/asm/arch-imx8/sci/svc/misc/api.h | 30 +++
.../include/asm/arch-imx8/sci/svc/pad/api.h | 57 +
.../include/asm/arch-imx8/sci/svc/pm/api.h| 44
.../include/asm/arch-imx8/sci/svc/rm/api.h| 69 ++
arch/arm/include/asm/arch-imx8/sci/types.h| 220 ++
7 files changed, 636 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h
b/arch/arm/include/asm/arch-imx8/sci/rpc.h
new file mode 100644
index 00..746c2fa24d
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#ifndef SC_RPC_H
+#define SC_RPC_H
+
+/* Note: Check SCFW API Released DOC before you want to modify something */
+#define SC_RPC_VERSION 1U
+
+#define SC_RPC_MAX_MSG 8U
+
+#define RPC_VER(MSG)((MSG)->version)
+#define RPC_SIZE(MSG) ((MSG)->size)
+#define RPC_SVC(MSG)((MSG)->svc)
+#define RPC_FUNC(MSG) ((MSG)->func)
+#define RPC_R8(MSG) ((MSG)->func)
+#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
+#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
+#define RPC_I8(MSG, IDX)((MSG)->DATA.i8[(IDX)])
+#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
+#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
+#define RPC_U8(MSG, IDX)((MSG)->DATA.u8[(IDX)])
+
+#define SC_RPC_SVC_UNKNOWN 0U
+#define SC_RPC_SVC_RETURN 1U
+#define SC_RPC_SVC_PM 2U
+#define SC_RPC_SVC_RM 3U
+#define SC_RPC_SVC_TIMER5U
+#define SC_RPC_SVC_PAD 6U
+#define SC_RPC_SVC_MISC 7U
+#define SC_RPC_SVC_IRQ 8U
+#define SC_RPC_SVC_ABORT9U
+
+/* Types */
+
+struct sc_rpc_msg_s {
+ u8 version;
+ u8 size;
+ u8 svc;
+ u8 func;
+ union {
+ s32 i32[(SC_RPC_MAX_MSG - 1U)];
+ s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
+ s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
+ u32 u32[(SC_RPC_MAX_MSG - 1U)];
+ u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
+ u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
+ } DATA;
+};
+
+/* PM RPC */
+#define PM_FUNC_UNKNOWN0
+#define PM_FUNC_SET_SYS_POWER_MODE 19U
+#define PM_FUNC_SET_PARTITION_POWER_MODE 1U
+#define PM_FUNC_GET_SYS_POWER_MODE 2U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE3U
+#define PM_FUNC_GET_RESOURCE_POWER_MODE4U
+#define PM_FUNC_REQ_LOW_POWER_MODE 16U
+#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
+#define PM_FUNC_SET_CPU_RESUME_ADDR17U
+#define PM_FUNC_SET_CPU_RESUME 21U
+#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U
+#define PM_FUNC_SET_CLOCK_RATE 5U
+#define PM_FUNC_GET_CLOCK_RATE 6U
+#define PM_FUNC_CLOCK_ENABLE 7U
+#define PM_FUNC_SET_CLOCK_PARENT 14U
+#define PM_FUNC_GET_CLOCK_PARENT 15U
+#define PM_FUNC_RESET 13U
+#define PM_FUNC_RESET_REASON 10U
+#define PM_FUNC_BOOT 8U
+#define PM_FUNC_REBOOT 9U
+#define PM_FUNC_REBOOT_PARTITION 12U
+#define PM_FUNC_CPU_START 11U
+
+/* MISC RPC */
+#define MISC_FUNC_UNKNOWN 0
+#define MISC_FUNC_SET_CONTROL 1U
+#define MISC_FUNC_GET_CONTROL 2U
+#define MISC_FUNC_SET_MAX_DMA_GROUP4U
+#define MISC_FUNC_SET_DMA_GROUP5U
+#define MISC_FUNC_SECO_IMAGE_LOAD 8U
+#define MISC_FUNC_SECO_AUTHENTICATE9U
+#define MISC_FUNC_SECO_FUSE_WRITE 20U
+#define MISC_FUNC_SECO_ENABLE_DEBUG21U
+#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
+#define MISC_FUNC_SECO_RETURN_LIFECYCLE23U
+#define MISC_FUNC_SECO_BUILD_INFO 24U
+#define MISC_FUNC_DEBUG_OUT10U
+#define MISC_FUNC_WAVEFORM_CAPTURE 6U
+#define MISC_FUNC_BUILD_INFO 15U
+#define MISC_FUNC_UNIQUE_ID19U
+#define MISC_FUNC_SET_ARI
[U-Boot] [PATCH v6 06/34] arm: build mach-imx for i.MX8
From: Peng Fan Build mach-imx for i.MX8 Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e52a35db18..4b6c5e1935 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -106,7 +106,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 07/34] arm: global_data: add scu_dev for i.MX8
From: Peng Fan
Add scu_dev for i.MX8, this will be used as a handle
to communite with SCU from A35.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/global_data.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 287a7bd5b1..c3ee5f0c7b 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -74,6 +74,10 @@ struct arch_global_data {
#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
unsigned long mem2_clk;
#endif
+
+#ifdef CONFIG_ARCH_IMX8
+ struct udevice *scu_dev;
+#endif
};
#include
--
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[U-Boot] [PATCH v6 20/34] imx8: cpu: add function for reading FEC MAC from fuse
FEC driver requires imx_get_mac_from_fuse(). Add it in preparation
for ENETx support.
Signed-off-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/cpu.c | 38
1 file changed, 38 insertions(+)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index d80b4b175d..da34a94a23 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -543,3 +543,41 @@ u64 get_page_table_size(void)
return size;
}
#endif
+
+#define FUSE_MAC0_WORD0 708
+#define FUSE_MAC0_WORD1 709
+#define FUSE_MAC1_WORD0 710
+#define FUSE_MAC1_WORD1 711
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ u32 word[2], val[2] = {};
+ int i, ret;
+
+ if (dev_id == 0) {
+ word[0] = FUSE_MAC0_WORD0;
+ word[1] = FUSE_MAC0_WORD1;
+ } else {
+ word[0] = FUSE_MAC1_WORD0;
+ word[1] = FUSE_MAC1_WORD1;
+ }
+
+ for (i = 0; i < 2; i++) {
+ ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
+ if (ret < 0)
+ goto err;
+ }
+
+ mac[0] = val[0];
+ mac[1] = val[0] >> 8;
+ mac[2] = val[0] >> 16;
+ mac[3] = val[0] >> 24;
+ mac[4] = val[1];
+ mac[5] = val[1] >> 8;
+
+ debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
+ __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ return;
+err:
+ printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
+}
--
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[U-Boot] [PATCH v6 10/34] imx: boot_mode: Add FLEXSPI boot entry
From: Peng Fan
i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h
b/arch/arm/include/asm/mach-imx/boot_mode.h
index 8766e9d180..3a483b6afa 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -25,6 +25,7 @@ enum boot_device {
MMC4_BOOT,
NAND_BOOT,
QSPI_BOOT,
+ FLEXSPI_BOOT,
USB_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
--
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[U-Boot] [PATCH v6 16/34] imx8: add boot device detection
From: Peng Fan
Add get_boot_device to detect boot device.
Add print_bootinfo to print the boot device info.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sys_proto.h | 10 +++
arch/arm/mach-imx/imx8/cpu.c | 85 ++
2 files changed, 95 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
new file mode 100644
index 00..f9a3016132
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+
+enum boot_device get_boot_device(void);
+int print_bootinfo(void);
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0b841e291d..90b6ea4211 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -11,8 +11,10 @@
#include
#include
#include
+#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -91,3 +93,86 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+int print_bootinfo(void)
+{
+ enum boot_device bt_dev = get_boot_device();
+
+ puts("Boot: ");
+ switch (bt_dev) {
+ case SD1_BOOT:
+ puts("SD0\n");
+ break;
+ case SD2_BOOT:
+ puts("SD1\n");
+ break;
+ case SD3_BOOT:
+ puts("SD2\n");
+ break;
+ case MMC1_BOOT:
+ puts("MMC0\n");
+ break;
+ case MMC2_BOOT:
+ puts("MMC1\n");
+ break;
+ case MMC3_BOOT:
+ puts("MMC2\n");
+ break;
+ case FLEXSPI_BOOT:
+ puts("FLEXSPI\n");
+ break;
+ case SATA_BOOT:
+ puts("SATA\n");
+ break;
+ case NAND_BOOT:
+ puts("NAND\n");
+ break;
+ case USB_BOOT:
+ puts("USB\n");
+ break;
+ default:
+ printf("Unknown device %u\n", bt_dev);
+ break;
+ }
+
+ return 0;
+}
+
+enum boot_device get_boot_device(void)
+{
+ enum boot_device boot_dev = SD1_BOOT;
+
+ sc_rsrc_t dev_rsrc;
+
+ sc_misc_get_boot_dev(-1, &dev_rsrc);
+
+ switch (dev_rsrc) {
+ case SC_R_SDHC_0:
+ boot_dev = MMC1_BOOT;
+ break;
+ case SC_R_SDHC_1:
+ boot_dev = SD2_BOOT;
+ break;
+ case SC_R_SDHC_2:
+ boot_dev = SD3_BOOT;
+ break;
+ case SC_R_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case SC_R_FSPI_0:
+ boot_dev = FLEXSPI_BOOT;
+ break;
+ case SC_R_SATA_0:
+ boot_dev = SATA_BOOT;
+ break;
+ case SC_R_USB_0:
+ case SC_R_USB_1:
+ case SC_R_USB_2:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
--
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[U-Boot] [PATCH v6 11/34] imx8: add imx-regs header file
From: Peng Fan Add imx-regs header file to include the register base definition Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/imx-regs.h | 46 +++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h new file mode 100644 index 00..af0fb5154b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_REGS_H__ +#define __ASM_ARCH_IMX8_REGS_H__ + +#define LPUART_BASE0x5A06 + +#define GPT1_BASE_ADDR 0x5D14 +#define SCU_LPUART_BASE0x3322 +#define GPIO1_BASE_ADDR0x5D08 +#define GPIO2_BASE_ADDR0x5D09 +#define GPIO3_BASE_ADDR0x5D0A +#define GPIO4_BASE_ADDR0x5D0B +#define GPIO5_BASE_ADDR0x5D0C +#define GPIO6_BASE_ADDR0x5D0D +#define GPIO7_BASE_ADDR0x5D0E +#define GPIO8_BASE_ADDR0x5D0F +#define LPI2C1_BASE_ADDR 0x5A80 +#define LPI2C2_BASE_ADDR 0x5A81 +#define LPI2C3_BASE_ADDR 0x5A82 +#define LPI2C4_BASE_ADDR 0x5A83 +#define LPI2C5_BASE_ADDR 0x5A84 + +#ifdef CONFIG_IMX8QXP +#define LVDS0_PHYCTRL_BASE 0x56221000 +#define LVDS1_PHYCTRL_BASE 0x56241000 +#define MIPI0_SS_BASE 0x5622 +#define MIPI1_SS_BASE 0x5624 +#endif + +#define APBH_DMA_ARB_BASE_ADDR 0x5B81 +#define APBH_DMA_ARB_END_ADDR 0x5B81 +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR + +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +#define PASS_OVER_INFO_ADDR0x0010fe00 + +#define USB_BASE_ADDR 0x5b0d +#define USB_PHY0_BASE_ADDR 0x5b10 + +#endif /* __ASM_ARCH_IMX8_REGS_H__ */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 12/34] imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
From: Peng Fan Include i.MX8QXP pin header when CONFIG_IMX8QXP defined, if no SoC macro defined, report error. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 +++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h new file mode 100644 index 00..dcced1010b --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __ASM_ARCH_IMX8_PINS_H__ +#define __ASM_ARCH_IMX8_PINS_H__ + +#if defined(CONFIG_IMX8QXP) +#include +#else +#error "No pin header" +#endif + +#endif /* __ASM_ARCH_IMX8_PINS_H__ */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 23/34] imx8: add dummy clock
From: Peng Fan
This driver is mostly used to avoid build errors.
We use uclass clk driver for clk related operations.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/clock.h | 27 ++
arch/arm/mach-imx/imx8/clock.c | 21
2 files changed, 48 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8/clock.h
create mode 100644 arch/arm/mach-imx/imx8/clock.c
diff --git a/arch/arm/include/asm/arch-imx8/clock.h
b/arch/arm/include/asm/arch-imx8/clock.h
new file mode 100644
index 00..bea157171f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/clock.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_CLOCK_H__
+#define __ASM_ARCH_IMX8_CLOCK_H__
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_FEC_CLK,
+};
+
+u32 mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c
new file mode 100644
index 00..d747e1332f
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/clock.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
--
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[U-Boot] [PATCH v6 19/34] imx8: add arch_cpu_init arch_cpu_init_dm
From: Peng Fan
Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sys_proto.h | 9
arch/arm/mach-imx/imx8/cpu.c | 53 +-
2 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index f9a3016132..73ffaba7d5 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -6,5 +6,14 @@
#include
#include
+struct pass_over_info_t {
+ u16 barker;
+ u16 len;
+ u32 g_bt_cfg_shadow;
+ u32 card_address_mode;
+ u32 bad_block_count_met;
+ u32 g_ap_mu;
+};
+
enum boot_device get_boot_device(void);
int print_bootinfo(void);
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index f73ce2fde3..d80b4b175d 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -95,6 +95,57 @@ int print_cpuinfo(void)
}
#endif
+#define BT_PASSOVER_TAG0x504F
+struct pass_over_info_t *get_pass_over_info(void)
+{
+ struct pass_over_info_t *p =
+ (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
+
+ if (p->barker != BT_PASSOVER_TAG ||
+ p->len != sizeof(struct pass_over_info_t))
+ return NULL;
+
+ return p;
+}
+
+int arch_cpu_init(void)
+{
+ struct pass_over_info_t *pass_over = get_pass_over_info();
+
+ if (pass_over && pass_over->g_ap_mu == 0) {
+ /*
+* When ap_mu is 0, means the U-Boot booted
+* from first container
+*/
+ sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+ }
+
+ return 0;
+}
+
+int arch_cpu_init_dm(void)
+{
+ struct udevice *devp;
+ int node, ret;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
+ ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu",
+offset_to_ofnode(node), &devp);
+
+ if (ret) {
+ printf("could not find scu %d\n", ret);
+ return ret;
+ }
+
+ ret = device_probe(devp);
+ if (ret) {
+ printf("scu probe failed %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
@@ -252,7 +303,7 @@ phys_size_t get_effective_memsize(void)
if (start > end)
continue;
- /* Find the memory region runs the u-boot */
+ /* Find the memory region runs the U-Boot */
if (start >= PHYS_SDRAM_1 && start <= end1 &&
(start <= CONFIG_SYS_TEXT_BASE &&
end >= CONFIG_SYS_TEXT_BASE)) {
--
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[U-Boot] [PATCH v6 08/34] misc: add i.MX8 misc driver
From: Peng Fan
Add i.MX8 MISC driver to handle the communication between
A35 Core and SCU.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
drivers/misc/Makefile | 1 +
drivers/misc/imx8/Makefile | 3 +
drivers/misc/imx8/scu.c| 266 +
3 files changed, 270 insertions(+)
create mode 100644 drivers/misc/imx8/Makefile
create mode 100644 drivers/misc/imx8/scu.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index cf6587268e..759d2c791b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+obj-$(CONFIG_IMX8) += imx8/
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
diff --git a/drivers/misc/imx8/Makefile b/drivers/misc/imx8/Makefile
new file mode 100644
index 00..3395340d22
--- /dev/null
+++ b/drivers/misc/imx8/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += scu.o
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
new file mode 100644
index 00..0647ddf103
--- /dev/null
+++ b/drivers/misc/imx8/scu.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mu_type {
+ u32 tr[4];
+ u32 rr[4];
+ u32 sr;
+ u32 cr;
+};
+
+struct imx8_scu {
+ struct mu_type *base;
+ struct udevice *clk;
+ struct udevice *pinclk;
+};
+
+#define MU_CR_GIE_MASK 0xF000u
+#define MU_CR_RIE_MASK 0xF00u
+#define MU_CR_GIR_MASK 0xFu
+#define MU_CR_TIE_MASK 0xF0u
+#define MU_CR_F_MASK 0x7u
+#define MU_SR_TE0_MASK BIT(23)
+#define MU_SR_RF0_MASK BIT(27)
+#define MU_TR_COUNT4
+#define MU_RR_COUNT4
+
+static inline void mu_hal_init(struct mu_type *base)
+{
+ /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
+ clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
+MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
+}
+
+static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
+{
+ u32 mask = MU_SR_TE0_MASK >> reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ /* Wait TX register to be empty. */
+ ret = readl_poll_timeout(&base->sr, val, val & mask, 1);
+ if (ret < 0) {
+ printf("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ writel(msg, &base->tr[reg_index]);
+
+ return 0;
+}
+
+static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
+{
+ u32 mask = MU_SR_RF0_MASK >> reg_index;
+ u32 val;
+ int ret;
+
+ assert(reg_index < MU_TR_COUNT);
+
+ /* Wait RX register to be full. */
+ ret = readl_poll_timeout(&base->sr, val, val & mask, 1);
+ if (ret < 0) {
+ printf("%s timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ *msg = readl(&base->rr[reg_index]);
+
+ return 0;
+}
+
+static int sc_ipc_read(struct mu_type *base, void *data)
+{
+ struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
+ int ret;
+ u8 count = 0;
+
+ if (!msg)
+ return -EINVAL;
+
+ /* Read first word */
+ ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
+ if (ret)
+ return ret;
+ count++;
+
+ /* Check size */
+ if (msg->size > SC_RPC_MAX_MSG) {
+ *((u32 *)msg) = 0;
+ return -EINVAL;
+ }
+
+ /* Read remaining words */
+ while (count < msg->size) {
+ ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
+ &msg->DATA.u32[count - 1]);
+ if (ret)
+ return ret;
+ count++;
+ }
+
+ return 0;
+}
+
+static int sc_ipc_write(struct mu_type *base, void *data)
+{
+ struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
+ int ret;
+ u8 count = 0;
+
+ if (!msg)
+ return -EINVAL;
+
+ /* Check size */
+ if (msg->size > SC_RPC_MAX_MSG)
+ return -EINVAL;
+
+ /* Write first word */
+ ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
+ if (ret)
+ return ret;
+ count++;
+
+ /* Write remaining words */
+ while (count < msg->size) {
+ ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
+msg->DATA.u32[count - 1]);
+ if (ret)
+ return ret;
+ count+
[U-Boot] [PATCH v6 13/34] imx: add i.MX8 cpu type
From: Peng Fan Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-imx/cpu.h | 5 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 62df1b9ad2..cf6303c3f5 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,12 +25,14 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8QXP0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX60x60 #define MXC_SOC_MX70x70 #define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_00x10 @@ -41,6 +43,9 @@ #define CHIP_REV_2_50x25 #define CHIP_REV_3_00x30 +#define CHIP_REV_A 0x0 +#define CHIP_REV_B 0x1 + #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 #define BOARD_VER_OFFSET0x8 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index d1d6cbc462..f8890b57da 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -27,6 +27,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8() (is_soc_type(MXC_SOC_IMX8)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -41,6 +42,8 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 18/34] imx8: add mmu and dram related functions
From: Peng Fan
Add mmu memmap, some memory regions are reserved by M4, Arm Trusted
Firmware, so need to get memreg using SCFW API and setup the memmap.
Add dram_init, dram_init_banksize, get_effective_memsize functions,
according to the memreg.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/cpu.c | 284 +++
1 file changed, 284 insertions(+)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0cacaa895c..f73ce2fde3 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -208,3 +209,286 @@ int mmc_get_env_dev(void)
return board_mmc_get_env_dev(devno);
}
#endif
+
+#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
+
+static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
+ sc_faddr_t *addr_end)
+{
+ sc_faddr_t start, end;
+ int ret;
+ bool owned;
+
+ owned = sc_rm_is_memreg_owned(-1, mr);
+ if (owned) {
+ ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
+ if (ret) {
+ printf("Memreg get info failed, %d\n", ret);
+ return -EINVAL;
+ }
+ debug("0x%llx -- 0x%llx\n", start, end);
+ *addr_start = start;
+ *addr_end = end;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ sc_rm_mr_t mr;
+ sc_faddr_t start, end, end1;
+ int err;
+
+ end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
+
+ for (mr = 0; mr < 64; mr++) {
+ err = get_owned_memreg(mr, &start, &end);
+ if (!err) {
+ start = roundup(start, MEMSTART_ALIGNMENT);
+ /* Too small memory region, not use it */
+ if (start > end)
+ continue;
+
+ /* Find the memory region runs the u-boot */
+ if (start >= PHYS_SDRAM_1 && start <= end1 &&
+ (start <= CONFIG_SYS_TEXT_BASE &&
+ end >= CONFIG_SYS_TEXT_BASE)) {
+ if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
+ PHYS_SDRAM_1_SIZE))
+ return (end - PHYS_SDRAM_1 + 1);
+ else
+ return PHYS_SDRAM_1_SIZE;
+ }
+ }
+ }
+
+ return PHYS_SDRAM_1_SIZE;
+}
+
+int dram_init(void)
+{
+ sc_rm_mr_t mr;
+ sc_faddr_t start, end, end1, end2;
+ int err;
+
+ end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
+ end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
+ for (mr = 0; mr < 64; mr++) {
+ err = get_owned_memreg(mr, &start, &end);
+ if (!err) {
+ start = roundup(start, MEMSTART_ALIGNMENT);
+ /* Too small memory region, not use it */
+ if (start > end)
+ continue;
+
+ if (start >= PHYS_SDRAM_1 && start <= end1) {
+ if ((end + 1) <= end1)
+ gd->ram_size += end - start + 1;
+ else
+ gd->ram_size += end1 - start;
+ } else if (start >= PHYS_SDRAM_2 && start <= end2) {
+ if ((end + 1) <= end2)
+ gd->ram_size += end - start + 1;
+ else
+ gd->ram_size += end2 - start;
+ }
+ }
+ }
+
+ /* If error, set to the default value */
+ if (!gd->ram_size) {
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size += PHYS_SDRAM_2_SIZE;
+ }
+ return 0;
+}
+
+static void dram_bank_sort(int current_bank)
+{
+ phys_addr_t start;
+ phys_size_t size;
+
+ while (current_bank > 0) {
+ if (gd->bd->bi_dram[current_bank - 1].start >
+ gd->bd->bi_dram[current_bank].start) {
+ start = gd->bd->bi_dram[current_bank - 1].start;
+ size = gd->bd->bi_dram[current_bank - 1].size;
+
+ gd->bd->bi_dram[current_bank - 1].start =
+ gd->bd->bi_dram[current_bank].start;
+ gd->bd->bi_dram[current_bank - 1].size =
+ gd->bd->bi_dram[current_bank].size;
+
+ gd->bd->bi_dram[current_bank].start = start;
+ gd
[U-Boot] [PATCH v6 09/34] misc: imx8: add scfw api impementation
From: Peng Fan
Add clk/misc/pad/pm/rm scfw api implementaion for different
drivers to invoke. The low level code is using misc_call
to invoke imx8_scu driver.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/sci/sci.h | 30 ++
drivers/misc/imx8/Makefile | 2 +-
drivers/misc/imx8/scu_api.c | 367 +++
3 files changed, 398 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/imx8/scu_api.c
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h
b/arch/arm/include/asm/arch-imx8/sci/sci.h
index d0ff5c5c41..d1621669e2 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -55,4 +55,34 @@ static inline int sc_err_to_linux(sc_err_t err)
return ret;
}
+/* PM API*/
+int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_power_mode_t mode);
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate);
+int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+ sc_bool_t enable, sc_bool_t autog);
+
+/* MISC API */
+int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
+ u32 *val);
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
+void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
+int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
+
+/* RM API */
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
+ sc_faddr_t *addr_end);
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
+
+/* PAD API */
+int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
#endif
diff --git a/drivers/misc/imx8/Makefile b/drivers/misc/imx8/Makefile
index 3395340d22..ee05893cbb 100644
--- a/drivers/misc/imx8/Makefile
+++ b/drivers/misc/imx8/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-y += scu.o
+obj-y += scu_api.o scu.o
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
new file mode 100644
index 00..65080d7544
--- /dev/null
+++ b/drivers/misc/imx8/scu_api.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CLK and PM */
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (u8)PM_FUNC_SET_CLOCK_RATE;
+ RPC_U32(&msg, 0U) = *(u32 *)rate;
+ RPC_U16(&msg, 4U) = (u16)resource;
+ RPC_U8(&msg, 6U) = (u8)clk;
+ RPC_SIZE(&msg) = 3U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret)
+ printf("%s: rate:%u resource:%u: clk:%u res:%d\n",
+ __func__, *rate, resource, clk, RPC_R8(&msg));
+
+ *rate = RPC_U32(&msg, 0U);
+
+ return ret;
+}
+
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+sc_pm_clock_rate_t *rate)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+ int ret;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (u8)PM_FUNC_GET_CLOCK_RATE;
+ RPC_U16(&msg, 0U) = (u16)resource;
+ RPC_U8(&msg, 2U) = (u8)clk;
+ RPC_SIZE(&msg) = 2U;
+
+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+ if (ret) {
+ printf("%s: resource:%d clk:%d: res:%d\n",
+ __func__, resource, clk, RPC_R8(&msg));
+ return ret;
+ }
+
+ if (rate)
+ *rate = RPC_U32(&msg, 0U);
+
+ return 0;
+}
+
+int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+ sc_bool_t enable, sc_bool_t autog)
+{
+ struct udevice *dev = gd->arch.scu_dev;
+ int size = sizeof(struct sc_rpc_msg_s);
+ struct sc_rpc_msg_s msg;
+
[U-Boot] [PATCH v6 15/34] imx8: add basic cpu support
From: Peng Fan
Add basic cpu support, including cpu revision, cpu type,
cpu core detection.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/Makefile | 7 +++
arch/arm/mach-imx/imx8/cpu.c| 93 +
2 files changed, 100 insertions(+)
create mode 100644 arch/arm/mach-imx/imx8/Makefile
create mode 100644 arch/arm/mach-imx/imx8/cpu.c
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
new file mode 100644
index 00..57876139a1
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
new file mode 100644
index 00..0b841e291d
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_cpu_rev(void)
+{
+ u32 id = 0, rev = 0;
+ int ret;
+
+ ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
+ if (ret)
+ return 0;
+
+ rev = (id >> 5) & 0xf;
+ id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
+
+ return (id << 12) | rev;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+const char *get_imx8_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_IMX8QXP:
+ return "8QXP";
+ default:
+ return "??";
+ }
+}
+
+const char *get_imx8_rev(u32 rev)
+{
+ switch (rev) {
+ case CHIP_REV_A:
+ return "A";
+ case CHIP_REV_B:
+ return "B";
+ default:
+ return "?";
+ }
+}
+
+const char *get_core_name(void)
+{
+ if (is_cortex_a35())
+ return "A35";
+ else
+ return "?";
+}
+
+int print_cpuinfo(void)
+{
+ struct udevice *dev;
+ struct clk cpu_clk;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_CPU, 0, &dev);
+ if (ret)
+ return 0;
+
+ ret = clk_get_by_index(dev, 0, &cpu_clk);
+ if (ret) {
+ dev_err(dev, "failed to clk\n");
+ return 0;
+ }
+
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n",
+ get_imx8_type((cpurev & 0xFF000) >> 12),
+ get_imx8_rev((cpurev & 0xFFF)),
+ get_core_name(),
+ clk_get_rate(&cpu_clk) / 100);
+
+ return 0;
+}
+#endif
--
2.17.1
___
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[U-Boot] [PATCH v6 22/34] imx8: add iomux configuration api
From: Peng Fan
Add iomux configuration api.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/iomux.h | 40
arch/arm/mach-imx/imx8/Makefile| 2 +-
arch/arm/mach-imx/imx8/iomux.c | 43 ++
3 files changed, 84 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h
create mode 100644 arch/arm/mach-imx/imx8/iomux.c
diff --git a/arch/arm/include/asm/arch-imx8/iomux.h
b/arch/arm/include/asm/arch-imx8/iomux.h
new file mode 100644
index 00..bedd01bfd8
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/iomux.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_IOMUX_H__
+#define __ASM_ARCH_IMX8_IOMUX_H__
+
+/*
+ * We use 64bits value for iomux settings.
+ * High 32bits are used for padring register value,
+ * low 16bits are used for pin index.
+ */
+typedef u64 iomux_cfg_t;
+
+#define PADRING_IFMUX_EN_SHIFT 31
+#define PADRING_IFMUX_EN_MASK BIT(31)
+#define PADRING_GP_EN_SHIFT30
+#define PADRING_GP_EN_MASK BIT(30)
+#define PADRING_IFMUX_SHIFT27
+#define PADRING_IFMUX_MASK GENMASK(29, 27)
+#define PADRING_CONFIG_SHIFT 25
+#define PADRING_LPCONFIG_SHIFT 23
+#define PADRING_PULL_SHIFT 5
+#define PADRING_DSE_SHIFT 0
+
+#define MUX_PAD_CTRL_SHIFT 32
+#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x << MUX_PAD_CTRL_SHIFT)
+#define MUX_PAD_CTRL(x)((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT)
+#define PIN_ID_MASK((iomux_cfg_t)0x)
+
+/* Valid mux alt0 to alt7 */
+#define MUX_MODE_ALT(x)(((iomux_cfg_t)(x) << MUX_MODE_SHIFT) &
\
+MUX_MODE_MASK)
+
+void imx8_iomux_setup_pad(iomux_cfg_t pad);
+void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count);
+#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 57876139a1..31ad169ccf 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += cpu.o
+obj-y += cpu.o iomux.o
diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c
new file mode 100644
index 00..0ade85fb8f
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/iomux.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx8_iomux_setup_pad(iomux_cfg_t pad)
+{
+ sc_pad_t pin_id = pad & PIN_ID_MASK;
+ int ret;
+
+ u32 val = (u32)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT);
+
+ val |= PADRING_IFMUX_EN_MASK;
+ val |= PADRING_GP_EN_MASK;
+
+ ret = sc_pad_set(-1, pin_id, val);
+ if (ret)
+ printf("sc_pad_set failed!, pin: %u, val: 0x%x\n", pin_id, val);
+
+ debug("iomux: pin %d, val = 0x%x\n", pin_id, val);
+}
+
+/* configures a list of pads within declared with IOMUX_PADS macro */
+void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count)
+{
+ iomux_cfg_t const *p = pad_list;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ imx8_iomux_setup_pad(*p);
+ p++;
+ }
+}
--
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[U-Boot] [PATCH v6 17/34] imx8: implement mmc_get_env_dev
From: Peng Fan
Implement mmc_get_env_dev for i.MX8.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8/cpu.c | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 90b6ea4211..0cacaa895c 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -176,3 +176,35 @@ enum boot_device get_boot_device(void)
return boot_dev;
}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ sc_rsrc_t dev_rsrc;
+ int devno;
+
+ sc_misc_get_boot_dev(-1, &dev_rsrc);
+
+ switch (dev_rsrc) {
+ case SC_R_SDHC_0:
+ devno = 0;
+ break;
+ case SC_R_SDHC_1:
+ devno = 1;
+ break;
+ case SC_R_SDHC_2:
+ devno = 2;
+ break;
+ default:
+ /* If not boot from sd/mmc, use default value */
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
--
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[U-Boot] [PATCH v6 33/34] arm: dts: introduce dtsi for i.MX8QXP
From: Peng Fan
Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P),
so add them there, because i.MX8QXP includes the dtsi of them.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
---
arch/arm/dts/fsl-imx8-ca35.dtsi | 66 +
arch/arm/dts/fsl-imx8dx.dtsi| 499
arch/arm/dts/fsl-imx8dxp.dtsi | 11 +
arch/arm/dts/fsl-imx8qxp.dtsi | 51
4 files changed, 627 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi
create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi
create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi
diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi
new file mode 100644
index 00..28bc32c8b7
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8-ca35.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include
+
+/{
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* We have 1 clusters having 4 Cortex-A35 cores */
+ A35_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ };
+
+ A35_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = ;
+ interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc401>;
+ cpu_off = <0xc402>;
+ cpu_on= <0xc403>;
+ };
+};
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
new file mode 100644
index 00..3b1a2a20e3
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include
+#include "fsl-imx8-ca35.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Freescale i.MX8DX";
+ compatible = "fsl,imx8dx", "fsl,imx8qxp";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ serial0 = &lpuart0;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x 0x8000 0 0x4000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+* reserved-memory layout
+* 0x8800_ ~ 0x8FFF_ is reserved for M4
+* Shouldn't be used at A core and Linux side.
+*
+*/
+ decoder_boot: decoder_boot@0x8400 {
+ no-map;
+ reg = <0 0x8400 0 0x200>;
+ };
+ encoder_boot: encoder_boot@0x8600 {
+ no-map;
+ reg = <0 0x8600 0 0x200>;
+ };
+ rpmsg_reserved: rpmsg@0x9000 {
+ no-map;
+ reg = <0 0x9000 0 0x40>;
+ };
+ decoder_rpc: decoder_rpc@0x9040 {
+ no-map;
+ reg = <0 0x9040 0 0x100>;
+ };
+ encoder_rpc: encoder_rpc@0x9140 {
[U-Boot] [PATCH v6 26/34] power: Add power domain driver for i.MX8
From: Peng Fan
Add the power domain DM driver for i.MX8, that it depends on the DTB
power domain trees to generate the power domain provider devices. Users
need to add power domain trees with property "compatible = "nxp,imx8-pd";"
When power on a PD device, the driver will power on its ancestor PD
devices in power domain tree.
When power off a PD device, the driver will check its child PD devices
first. Only if all child PD devices are off, then power off the current PD
device. Then the driver checks sibling PD devices. If sibling PD devices
are off, then it will power off parent PD device.
There is no counter maintained in this driver, but a state to hold current
on/off state. So the request and free functions are empty.
The power domain implementation in i.MX8 DTB set the "#power-domain-cells"
to 0, so there is no ID binding with each PD device. We don't use "id"
variable in struct power_domain. At the same time, we have to set of_xlate
to empty to bypass standard of_xlate in uclass driver.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/power-domain.h | 15 +
drivers/power/domain/Kconfig | 8 +-
drivers/power/domain/Makefile | 1 +
drivers/power/domain/imx8-power-domain.c | 315 ++
4 files changed, 338 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h
create mode 100644 drivers/power/domain/imx8-power-domain.c
diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h
b/arch/arm/include/asm/arch-imx8/power-domain.h
new file mode 100644
index 00..1396008877
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/power-domain.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
+#define _ASM_ARCH_IMX8_POWER_DOMAIN_H
+
+#include
+
+struct imx8_power_domain_platdata {
+ sc_rsrc_t resource_id;
+};
+
+#endif
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 2c344888ca..a08b4288b4 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -16,6 +16,13 @@ config BCM6328_POWER_DOMAIN
Enable support for manipulating BCM6345 power domains via MMIO
mapped registers.
+config IMX8_POWER_DOMAIN
+ bool "Enable i.MX8 power domain driver"
+depends on ARCH_IMX8
+help
+ Enable support for manipulating NXP i.MX8 on-SoC power domains via
IPC
+ requests to the SCU.
+
config MESON_GX_VPU_POWER_DOMAIN
bool "Enable Amlogic Meson GX VPU power domain driver"
depends on ARCH_MESON
@@ -44,5 +51,4 @@ config TI_SCI_POWER_DOMAIN
help
Generic power domain implementation for TI devices implementing the
TI SCI protocol.
-
endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 6bdaa175e9..23fb1ecede 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
+obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/imx8-power-domain.c
b/drivers/power/domain/imx8-power-domain.c
new file mode 100644
index 00..d51dbaa6c0
--- /dev/null
+++ b/drivers/power/domain/imx8-power-domain.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx8_power_domain_priv {
+ bool state_on;
+};
+
+static int imx8_power_domain_request(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ return 0;
+}
+
+static int imx8_power_domain_free(struct power_domain *power_domain)
+{
+ debug("%s(power_domain=%p)\n", __func__, power_domain);
+
+ return 0;
+}
+
+static int imx8_power_domain_on(struct power_domain *power_domain)
+{
+ struct udevice *dev = power_domain->dev;
+ struct imx8_power_domain_platdata *pdata;
+ struct imx8_power_domain_priv *ppriv;
+ sc_err_t ret;
+ int err;
+
+ struct power_domain parent_domain;
+ struct udevice *parent = dev_get_parent(dev);
+
+ /* Need to power on parent node first */
+ if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
+ parent_domain.dev = parent;
+ err = imx8_power_domain_on(&parent_domain);
+ if (err)
+ return err;
+ }
+
+ pdata = (struct imx8_power_domain_platdata *)dev_get_platdata(dev);
+ ppriv = (struct imx8_
[U-Boot] [PATCH v6 28/34] serial_lpuart: Update lpuart driver to support i.MX8
From: Peng Fan
Add i.MX8 compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also, according to RM, the Receive FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so this definition should change to 0x08
(not 0x40) for i.MX8, otherwise the Receive FIFO is not disabled.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
drivers/serial/serial_lpuart.c | 15 ---
include/fsl_lpuart.h | 2 +-
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 1212b72676..c14a8105c9 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -41,7 +41,11 @@
#define CTRL_RE(1 << 18)
#define FIFO_TXFE 0x80
+#ifdef CONFIG_ARCH_IMX8
+#define FIFO_RXFE 0x08
+#else
#define FIFO_RXFE 0x40
+#endif
#define WATER_TXWATER_OFF 1
#define WATER_RXWATER_OFF 16
@@ -54,7 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum lpuart_devtype {
DEV_VF610 = 1,
DEV_LS1021A,
- DEV_MX7ULP
+ DEV_MX7ULP,
+ DEV_IMX8
};
struct lpuart_serial_platdata {
@@ -325,7 +330,7 @@ static int _lpuart32_serial_init(struct
lpuart_serial_platdata *plat)
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype == DEV_MX7ULP) {
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
@@ -342,7 +347,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int
baudrate)
struct lpuart_serial_platdata *plat = dev->platdata;
if (is_lpuart32(dev)) {
- if (plat->devtype == DEV_MX7ULP)
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
_lpuart32_serial_setbrg_7ulp(plat, baudrate);
else
_lpuart32_serial_setbrg(plat, baudrate);
@@ -427,6 +432,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice
*dev)
plat->devtype = DEV_MX7ULP;
else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
plat->devtype = DEV_VF610;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
+ plat->devtype = DEV_IMX8;
return 0;
}
@@ -444,6 +451,8 @@ static const struct udevice_id lpuart_serial_ids[] = {
{ .compatible = "fsl,imx7ulp-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
{ .compatible = "fsl,vf610-lpuart"},
+ { .compatible = "fsl,imx8qm-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ }
};
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 02ebfefc74..fc517d4b7f 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -4,7 +4,7 @@
*
*/
-#ifdef CONFIG_ARCH_MX7ULP
+#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
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[U-Boot] [PATCH v6 30/34] serial: lpuart: support uclass clk api
From: Peng Fan
Modify most APIs to use udevice as the first parameter, then
it will be easy to get the clk reference by using udevice pointer.
Use uclass api to get lpuart clk when CONFIG_CLK is enabled.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
drivers/serial/serial_lpuart.c | 80 ++
1 file changed, 61 insertions(+), 19 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index b28f7cf68d..cee9e5e231 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -104,6 +105,29 @@ u32 __weak get_lpuart_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
+#if IS_ENABLED(CONFIG_CLK)
+ulong get_lpuart_clk_rate(struct udevice *dev)
+{
+ struct clk per_clk;
+ ulong rate;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+
+ rate = clk_get_rate(&per_clk);
+ if ((long)rate <= 0) {
+ dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
+ return ret;
+ }
+
+ return rate;
+}
+#endif
+
static bool is_lpuart32(struct udevice *dev)
{
struct lpuart_serial_platdata *plat = dev->platdata;
@@ -111,13 +135,19 @@ static bool is_lpuart32(struct udevice *dev)
return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}
-static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
+static void _lpuart_serial_setbrg(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl *base = plat->reg;
- u32 clk = get_lpuart_clk();
+ u32 clk;
u16 sbr;
+ if (IS_ENABLED(CONFIG_CLK))
+ clk = get_lpuart_clk_rate(dev);
+ else
+ clk = get_lpuart_clk();
+
sbr = (u16)(clk / (16 * baudrate));
/* place adjustment later - n/32 BRFA */
@@ -162,8 +192,9 @@ static int _lpuart_serial_tstc(struct
lpuart_serial_platdata *plat)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_init(struct udevice *dev)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
u8 ctrl;
@@ -182,19 +213,25 @@ static int _lpuart_serial_init(struct
lpuart_serial_platdata *plat)
__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
/* provide data bits, parity, stop bit, etc */
- _lpuart_serial_setbrg(plat, gd->baudrate);
+ _lpuart_serial_setbrg(dev, gd->baudrate);
__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
return 0;
}
-static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
- u32 clk = get_lpuart_clk();
+ u32 clk;
+
+ if (IS_ENABLED(CONFIG_CLK))
+ clk = get_lpuart_clk_rate(dev);
+ else
+ clk = get_lpuart_clk();
baud_diff = baudrate;
osr = 0;
@@ -248,13 +285,19 @@ static void _lpuart32_serial_setbrg_7ulp(struct
lpuart_serial_platdata *plat,
out_le32(&base->baud, tmp);
}
-static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_setbrg(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
- u32 clk = get_lpuart_clk();
+ u32 clk;
u32 sbr;
+ if (IS_ENABLED(CONFIG_CLK))
+ clk = get_lpuart_clk_rate(dev);
+ else
+ clk = get_lpuart_clk();
+
sbr = (clk / (16 * baudrate));
/* place adjustment later - n/32 BRFA */
@@ -321,8 +364,9 @@ static int _lpuart32_serial_tstc(struct
lpuart_serial_platdata *plat)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
+static int _lpuart32_serial_init(struct udevice *dev)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
u32 val, tx_fifo_size;
@@ -350,10 +394,10 @@
[U-Boot] [PATCH v6 25/34] pinctrl: Add pinctrl driver for i.MX8
From: Peng Fan
Add pinctrl driver for i.MX8. The pads configuration is controlled
by SCU, so need to ask SCU to configure pads through scfw API.
Add pinctrl-scu to invoke sc_pad_set to configure pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms
which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
drivers/pinctrl/nxp/Kconfig| 18 +++
drivers/pinctrl/nxp/Makefile | 2 +
drivers/pinctrl/nxp/pinctrl-imx.c | 209 -
drivers/pinctrl/nxp/pinctrl-imx.h | 16 +++
drivers/pinctrl/nxp/pinctrl-imx8.c | 40 ++
drivers/pinctrl/nxp/pinctrl-scu.c | 66 +
6 files changed, 258 insertions(+), 93 deletions(-)
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index b668359a0b..799d1d2465 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -1,6 +1,9 @@
config PINCTRL_IMX
bool
+config PINCTRL_IMX_SCU
+ bool
+
config PINCTRL_IMX5
bool "IMX5 pinctrl driver"
depends on ARCH_MX5 && PINCTRL_FULL
@@ -56,3 +59,18 @@ config PINCTRL_IMX7ULP
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
+
+config PINCTRL_IMX8
+ bool "IMX8 pinctrl driver"
+ depends on ARCH_IMX8 && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8 pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX8 SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configures related
+ registers.
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index c763948376..310b3b3a2e 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o
obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
+obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c
b/drivers/pinctrl/nxp/pinctrl-imx.c
index 36e1e8983c..04ea82aba5 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -28,7 +28,9 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct
udevice *config)
dev_dbg(dev, "%s: %s\n", __func__, config->name);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX8_USE_SCU)
+ pin_size = SHARE_IMX8_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = SHARE_FSL_PIN_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -58,112 +60,127 @@ static int imx_pinctrl_set_state(struct udevice *dev,
struct udevice *config)
npins = size / pin_size;
- /*
-* Refer to linux documentation for details:
-* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
-*/
- for (i = 0; i < npins; i++) {
- mux_reg = pin_data[j++];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = pin_data[j++];
- if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
- conf_reg = -1;
- }
+ if (info->flags & IMX8_USE_SCU) {
+ imx_pinctrl_scu_conf_pins(info, pin_data, npins);
+ } else {
+ /*
+* Refer to linux documentation for details:
+* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+*/
+ for (i = 0; i < npins; i++) {
+ mux_reg = pin_data[j++];
- if ((mux_reg == -1) || (conf_reg == -1)) {
- dev_err(dev, "Error mux_reg or conf_reg\n");
- devm_kfree(dev, pin_data);
- return -EINVAL;
- }
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
- input_reg = pin_data[j++];
- mux_mode = pin_data[j++];
- input_val = pin_data[j++];
- config_val = pin_data[j++];
+
[U-Boot] [PATCH v6 34/34] imx: add i.MX8QXP MEK board support
From: Peng Fan
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver.
Added README file.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
Cc: Fabio Estevam
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-imx8qxp-mek.dts | 246 ++
arch/arm/mach-imx/imx8/Kconfig| 13 ++
board/freescale/imx8qxp_mek/Kconfig | 14 ++
board/freescale/imx8qxp_mek/MAINTAINERS | 6 +
board/freescale/imx8qxp_mek/Makefile | 7 +
board/freescale/imx8qxp_mek/README| 72 +++
board/freescale/imx8qxp_mek/imx8qxp_mek.c | 170 +++
board/freescale/mx8mq_evk/README | 81 +++
configs/imx8qxp_mek_defconfig | 51 +
include/configs/imx8qxp_mek.h | 157 ++
11 files changed, 819 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts
create mode 100644 board/freescale/imx8qxp_mek/Kconfig
create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS
create mode 100644 board/freescale/imx8qxp_mek/Makefile
create mode 100644 board/freescale/imx8qxp_mek/README
create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c
create mode 100644 board/freescale/mx8mq_evk/README
create mode 100644 configs/imx8qxp_mek_defconfig
create mode 100644 include/configs/imx8qxp_mek.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8e6f8e99d3..4c9d4b6a09 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -454,6 +454,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
new file mode 100644
index 00..09ea3b4a3a
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+ model = "Freescale i.MX8QXP MEK";
+ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200
earlycon=lpuart32,0x5a06,115200";
+ stdout-path = &lpuart0;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <3480>;
+ enable-active-high;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx8qxp-mek {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0
0x064c
+ SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD
0x000514a0
+ >;
+ };
+
+ pinctrl_ioexp_rst: ioexp-rst-grp {
+ fsl,pins = <
+ SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x0621
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_ENET0_MDC_CONN_ENET0_MDC
0x0648
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO
0x0648
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
0x0648
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
0x0648
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
0x0648
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
0x0648
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
0x0648
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
0x0648
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
0x0648
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
0x0648
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
0x0648
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
0x0648
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
0x0648
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
0x0648
+ >;
+ };
+
+
[U-Boot] [PATCH v6 14/34] armv8: add cpu core helper functions
From: Peng Fan
Add helper functions to identify different armv8 variants.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/armv8/cpu.h | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 arch/arm/include/asm/armv8/cpu.h
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
new file mode 100644
index 00..40d54dc85a
--- /dev/null
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define MIDR_PARTNUM_CORTEX_A350xD04
+#define MIDR_PARTNUM_CORTEX_A530xD03
+#define MIDR_PARTNUM_CORTEX_A720xD08
+#define MIDR_PARTNUM_SHIFT 0x4
+#define MIDR_PARTNUM_MASK (0xFFF << 0x4)
+
+static inline unsigned int read_midr(void)
+{
+ unsigned long val;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (val));
+
+ return val;
+}
+
+#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
+#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
+#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
+MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
--
2.17.1
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[U-Boot] [PATCH v6 32/34] mmc: fsl_esdhc: add uclass clk support
From: Peng Fan
When CONIFG_CLK is enabled, use uclass clk api to handle
the clock.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Jaehoon Chung
Cc: Stefano Babic
---
drivers/mmc/fsl_esdhc.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 220f4f74a8..3cdfa7f5a6 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -121,6 +122,7 @@ struct esdhc_soc_data {
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
+ struct clk per_clk;
unsigned int clock;
unsigned int mode;
unsigned int bus_width;
@@ -1496,10 +1498,26 @@ static int fsl_esdhc_probe(struct udevice *dev)
init_clk_usdhc(dev->seq);
- priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
- if (priv->sdhc_clk <= 0) {
- dev_err(dev, "Unable to get clk for %s\n", dev->name);
- return -EINVAL;
+ if (IS_ENABLED(CONFIG_CLK)) {
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
+
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+ } else {
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
+ }
}
ret = fsl_esdhc_init(priv, plat);
--
2.17.1
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[U-Boot] [PATCH v6 27/34] clk: imx: add clk driver for i.MX8QXP
From: Peng Fan
Add clk driver for i.MX8QXP. This basic version supports clk
enable/disable/get_rate/set_rate operations for I2C, ENET,
SDHC0 and UART clocks.
Signed-off-by: Peng Fan
Signed-off-by: Anatolij Gustschin
Cc: Stefano Babic
---
drivers/clk/Kconfig| 1 +
drivers/clk/Makefile | 1 +
drivers/clk/imx/Kconfig| 6 +
drivers/clk/imx/Makefile | 5 +
drivers/clk/imx/clk-imx8.c | 393 +
5 files changed, 406 insertions(+)
create mode 100644 drivers/clk/imx/Kconfig
create mode 100644 drivers/clk/imx/Makefile
create mode 100644 drivers/clk/imx/clk-imx8.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7853a7a9d3..eadf7f8250 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -100,6 +100,7 @@ config CLK_STM32MP1
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
+source "drivers/clk/imx/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8bc9f520c1..f87c9aec85 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
new file mode 100644
index 00..a6fb58d6cf
--- /dev/null
+++ b/drivers/clk/imx/Kconfig
@@ -0,0 +1,6 @@
+config CLK_IMX8
+ bool "Clock support for i.MX8"
+ depends on ARCH_IMX8
+ select CLK
+ help
+ This enables support clock driver for i.MX8 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
new file mode 100644
index 00..5505ae52e2
--- /dev/null
+++ b/drivers/clk/imx/Makefile
@@ -0,0 +1,5 @@
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
new file mode 100644
index 00..fcb8090d35
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct imx8_clks {
+ ulong id;
+ const char *name;
+};
+
+static struct imx8_clks imx8_clk_names[] = {
+ { IMX8QXP_A35_DIV, "A35_DIV" },
+ { IMX8QXP_I2C0_CLK, "I2C0" },
+ { IMX8QXP_I2C1_CLK, "I2C1" },
+ { IMX8QXP_I2C2_CLK, "I2C2" },
+ { IMX8QXP_I2C3_CLK, "I2C3" },
+ { IMX8QXP_UART0_CLK, "UART0" },
+ { IMX8QXP_UART1_CLK, "UART1" },
+ { IMX8QXP_UART2_CLK, "UART2" },
+ { IMX8QXP_UART3_CLK, "UART3" },
+ { IMX8QXP_SDHC0_CLK, "SDHC0" },
+ { IMX8QXP_SDHC1_CLK, "SDHC1" },
+ { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
+ { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
+ { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
+ { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
+ { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
+ { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
+ { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
+ { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
+};
+
+static ulong imx8_clk_get_rate(struct clk *clk)
+{
+ sc_pm_clk_t pm_clk;
+ ulong rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QXP_A35_DIV:
+ resource = SC_R_A35;
+ pm_clk = SC_PM_CLK_CPU;
+ break;
+ case IMX8QXP_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC0_IPG_CLK:
+ case IMX8QXP_SDHC0_CLK:
+ case IMX8QXP_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC1_IPG_CLK:
+ case IMX8QXP_SDHC1_CLK:
+ case IMX8QXP_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART0_IPG_CLK:
+ case IMX8QXP_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CL
[U-Boot] [PATCH v6 24/34] gpio: mxc_gpio: add support for i.MX8
From: Peng Fan
Add i.MX8 support, there are 8 GPIO banks.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx8/gpio.h | 21 +++
drivers/gpio/mxc_gpio.c | 30 +++
2 files changed, 42 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h
diff --git a/arch/arm/include/asm/arch-imx8/gpio.h
b/arch/arm/include/asm/arch-imx8/gpio.h
new file mode 100644
index 00..24cfde3c29
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_GPIO_H
+#define __ASM_ARCH_IMX8_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr;/* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+/* IMX8 the GPIO index is from 0 not 1 */
+#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31))
+
+#endif /* __ASM_ARCH_IMX8_GPIO_H */
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index d8e72ada19..b820160ae7 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -40,21 +40,27 @@ static unsigned long gpio_ports[] = {
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+ defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+ defined(CONFIG_ARCH_IMX8)
[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+ defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+ defined(CONFIG_ARCH_IMX8)
[4] = GPIO5_BASE_ADDR,
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
[5] = GPIO6_BASE_ADDR,
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
+ defined(CONFIG_ARCH_IMX8)
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
[6] = GPIO7_BASE_ADDR,
#endif
#endif
+#if defined(CONFIG_ARCH_IMX8)
+ [7] = GPIO8_BASE_ADDR,
+#endif
};
static int mxc_gpio_direction(unsigned int gpio,
@@ -347,19 +353,22 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
#ifndef CONFIG_MX8M
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
#endif
+#if defined(CONFIG_ARCH_IMX8)
+ { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
+#endif
};
U_BOOT_DEVICES(mxc_gpios) = {
@@ -368,19 +377,22 @@ U_BOOT_DEVICES(mxc_gpios) = {
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[3] },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[4] },
#ifndef CONFIG_MX8M
{ "gpio_mxc", &mxc_plat[5] },
#endif
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[6] },
#endif
+#if defined(CONFIG_ARCH_IMX8)
+ { "gpio_mxc", &mxc_plat[7] },
+#endif
};
#endif
#endif
--
2.17.1
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[U-Boot] [PATCH v6 31/34] fsl_esdhc: Update usdhc driver to support i.MX8
From: Ye Li
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Jaehoon Chung
---
drivers/mmc/fsl_esdhc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 03c6743ae8..220f4f74a8 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -257,7 +257,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
dma_addr_t addr;
#endif
uint wml_value;
@@ -271,7 +271,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -301,7 +301,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -367,7 +367,7 @@ static void check_and_invalidate_dcache_range
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
- defined(CONFIG_MX8M)
+ defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
--
2.17.1
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[U-Boot] [PATCH v6 29/34] serial: lpuart: Enable RX and TX FIFO
From: Ye Li
Enable the RX and TX FIFO in LPUART driver to avoid the input lost
during U-Boot boot up.
Signed-off-by: Ye Li
Acked-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
---
drivers/serial/serial_lpuart.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index c14a8105c9..b28f7cf68d 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -40,6 +40,12 @@
#define CTRL_TE(1 << 19)
#define CTRL_RE(1 << 18)
+#define FIFO_RXFLUSH BIT(14)
+#define FIFO_TXFLUSH BIT(15)
+#define FIFO_TXSIZE_MASK 0x70
+#define FIFO_TXSIZE_OFF4
+#define FIFO_RXSIZE_MASK 0x7
+#define FIFO_RXSIZE_OFF0
#define FIFO_TXFE 0x80
#ifdef CONFIG_ARCH_IMX8
#define FIFO_RXFE 0x08
@@ -47,7 +53,7 @@
#define FIFO_RXFE 0x40
#endif
-#define WATER_TXWATER_OFF 1
+#define WATER_TXWATER_OFF 0
#define WATER_RXWATER_OFF 16
DECLARE_GLOBAL_DATA_PTR;
@@ -318,15 +324,28 @@ static int _lpuart32_serial_tstc(struct
lpuart_serial_platdata *plat)
static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
{
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
- u32 ctrl;
+ u32 val, tx_fifo_size;
- lpuart_read32(plat->flags, &base->ctrl, &ctrl);
- ctrl &= ~CTRL_RE;
- ctrl &= ~CTRL_TE;
- lpuart_write32(plat->flags, &base->ctrl, ctrl);
+ lpuart_read32(plat->flags, &base->ctrl, &val);
+ val &= ~CTRL_RE;
+ val &= ~CTRL_TE;
+ lpuart_write32(plat->flags, &base->ctrl, val);
lpuart_write32(plat->flags, &base->modir, 0);
- lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+ lpuart_read32(plat->flags, &base->fifo, &val);
+ tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
+ /* Set the TX water to half of FIFO size */
+ if (tx_fifo_size > 1)
+ tx_fifo_size = tx_fifo_size >> 1;
+
+ /* Set RX water to 0, to be triggered by any receive data */
+ lpuart_write32(plat->flags, &base->water,
+ (tx_fifo_size << WATER_TXWATER_OFF));
+
+ /* Enable TX and RX FIFO */
+ val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
+ lpuart_write32(plat->flags, &base->fifo, val);
lpuart_write32(plat->flags, &base->match, 0);
--
2.17.1
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[U-Boot] [PATCH v6 21/34] imx8: cpu: add uclass based CPU driver
print_cpuinfo() in board init code requires uclass CPU driver,
add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO
option is enabled. CPU node in DT will have to include 'clocks'
and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo()
to work as expected. The driver outputs info for i.MX8QXP Rev A
and Rev B CPUs.
Signed-off-by: Anatolij Gustschin
Cc: Stefano Babic
---
arch/arm/include/asm/arch-imx/cpu.h | 5 +-
arch/arm/mach-imx/imx8/cpu.c| 215 ++--
2 files changed, 142 insertions(+), 78 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index cf6303c3f5..2af79659d2 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,6 +25,7 @@
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_MX8MQ 0x82
+#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QXP0x92 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
@@ -43,8 +44,8 @@
#define CHIP_REV_2_50x25
#define CHIP_REV_3_00x30
-#define CHIP_REV_A 0x0
-#define CHIP_REV_B 0x1
+#define CHIP_REV_A 0x0
+#define CHIP_REV_B 0x1
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index da34a94a23..f093f34ca5 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
#include
@@ -19,82 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 get_cpu_rev(void)
-{
- u32 id = 0, rev = 0;
- int ret;
-
- ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
- if (ret)
- return 0;
-
- rev = (id >> 5) & 0xf;
- id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
-
- return (id << 12) | rev;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-const char *get_imx8_type(u32 imxtype)
-{
- switch (imxtype) {
- case MXC_CPU_IMX8QXP:
- return "8QXP";
- default:
- return "??";
- }
-}
-
-const char *get_imx8_rev(u32 rev)
-{
- switch (rev) {
- case CHIP_REV_A:
- return "A";
- case CHIP_REV_B:
- return "B";
- default:
- return "?";
- }
-}
-
-const char *get_core_name(void)
-{
- if (is_cortex_a35())
- return "A35";
- else
- return "?";
-}
-
-int print_cpuinfo(void)
-{
- struct udevice *dev;
- struct clk cpu_clk;
- int ret;
-
- ret = uclass_get_device(UCLASS_CPU, 0, &dev);
- if (ret)
- return 0;
-
- ret = clk_get_by_index(dev, 0, &cpu_clk);
- if (ret) {
- dev_err(dev, "failed to clk\n");
- return 0;
- }
-
- u32 cpurev;
-
- cpurev = get_cpu_rev();
-
- printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n",
- get_imx8_type((cpurev & 0xFF000) >> 12),
- get_imx8_rev((cpurev & 0xFFF)),
- get_core_name(),
- clk_get_rate(&cpu_clk) / 100);
-
- return 0;
-}
-#endif
-
#define BT_PASSOVER_TAG0x504F
struct pass_over_info_t *get_pass_over_info(void)
{
@@ -581,3 +506,141 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
err:
printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
}
+
+#if CONFIG_IS_ENABLED(CPU)
+struct cpu_imx_platdata {
+ const char *name;
+ const char *rev;
+ const char *type;
+ u32 cpurev;
+ u32 freq_mhz;
+};
+
+u32 get_cpu_rev(void)
+{
+ u32 id = 0, rev = 0;
+ int ret;
+
+ ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
+ if (ret)
+ return 0;
+
+ rev = (id >> 5) & 0xf;
+ id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
+
+ return (id << 12) | rev;
+}
+
+const char *get_imx8_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_IMX8QXP:
+ case MXC_CPU_IMX8QXP_A0:
+ return "QXP";
+ default:
+ return "??";
+ }
+}
+
+const char *get_imx8_rev(u32 rev)
+{
+ switch (rev) {
+ case CHIP_REV_A:
+ return "A";
+ case CHIP_REV_B:
+ return "B";
+ default:
+ return "?";
+ }
+}
+
+const char *get_core_name(void)
+{
+ if (is_cortex_a35())
+ return "A35";
+ else if (is_cortex_a53())
+ return "A53";
+ else if (is_cortex_a72())
+ return "A72";
+ else
+ return "?";
+}
+
+int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
+{
+ struct cpu_imx_platdata *plat
Re: [U-Boot] [PATCH 27/41] net: fec: do not access reserved register for i.MX8
Hi Peng, On Mon, 28 May 2018 20:25:12 +0800 Peng Fan peng@nxp.com wrote: > The MIB RAM and FIFO receive start register does not exist on > i.MX8. Accessing these register will cause SERROR. > > Signed-off-by: Peng Fan > Cc: Joe Hershberger > --- > drivers/net/fec_mxc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) This should be merged for v2018.11, so applied to u-boot-staging/ag...@denx.de, thanks! -- Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] net: fec_mxc: fix phy-reset-gpios logic
'phy-reset-gpios' property is optional, don't return error when
it is missing. Read 'phy-reset-duration' property only if
'phy-reset-gpios' exists. The binding defines the duration value
in milliseconds, so use mdelay() for waiting.
Signed-off-by: Anatolij Gustschin
Cc: Joe Hershberger
---
drivers/net/fec_mxc.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d0fdbcb771..5a1a8bc897 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1254,7 +1254,7 @@ static void fec_gpio_reset(struct fec_priv *priv)
debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
dm_gpio_set_value(&priv->phy_reset_gpio, 1);
- udelay(priv->reset_delay);
+ mdelay(priv->reset_delay);
dm_gpio_set_value(&priv->phy_reset_gpio, 0);
}
}
@@ -1352,22 +1352,18 @@ static int fecmxc_ofdata_to_platdata(struct udevice
*dev)
#ifdef CONFIG_DM_GPIO
ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
-&priv->phy_reset_gpio, GPIOD_IS_OUT);
- if (ret == 0) {
- ret = dev_read_u32_array(dev, "phy-reset-duration",
-&priv->reset_delay, 1);
- } else if (ret == -ENOENT) {
- priv->reset_delay = 1000;
- ret = 0;
- }
+ &priv->phy_reset_gpio, GPIOD_IS_OUT);
+ if (ret < 0)
+ return 0; /* property is optional, don't return error! */
+ priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
if (priv->reset_delay > 1000) {
- printf("FEX MXC: gpio reset timeout should be less the 1000\n");
- priv->reset_delay = 1000;
+ /* property value wrong, use default value */
+ priv->reset_delay = 1;
}
#endif
- return ret;
+ return 0;
}
static const struct udevice_id fecmxc_ids[] = {
--
2.17.1
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[U-Boot] [PATCH] net: fec_mxc: add support for i.MX8X
Add compatible property and enable the FEC ipg clock when probing
on i.MX8X. Add specific function for reading FEC clock rate via
clock driver when configuring MII speed register. Allow FEC_MXC
selection for i.MX8.
Signed-off-by: Anatolij Gustschin
Cc: Joe Hershberger
---
drivers/net/Kconfig | 2 +-
drivers/net/fec_mxc.c | 59 ---
drivers/net/fec_mxc.h | 4 +++
3 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f1f0e2d94e..39687431fb 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -176,7 +176,7 @@ config FEC_MXC_MDIO_BASE
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX5 || MX6 || MX7
+ depends on MX5 || MX6 || MX7 || IMX8
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 5a1a8bc897..96fc733116 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -122,6 +122,32 @@ static int fec_mdio_read(struct ethernet_regs *eth,
uint8_t phyaddr,
return val;
}
+static int fec_get_clk_rate(void *udev, int idx)
+{
+#if IS_ENABLED(CONFIG_IMX8)
+ struct fec_priv *fec;
+ struct udevice *dev;
+ int ret;
+
+ dev = udev;
+ if (!dev) {
+ ret = uclass_get_device(UCLASS_ETH, idx, &dev);
+ if (ret < 0) {
+ debug("Can't get FEC udev: %d\n", ret);
+ return ret;
+ }
+ }
+
+ fec = dev_get_priv(dev);
+ if (fec)
+ return fec->clk_rate;
+
+ return -EINVAL;
+#else
+ return imx_get_fecclk();
+#endif
+}
+
static void fec_mii_setspeed(struct ethernet_regs *eth)
{
/*
@@ -139,9 +165,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
* Given that ceil(clkrate / 500) <= 64, the calculation for
* holdtime cannot result in a value greater than 3.
*/
- u32 pclk = imx_get_fecclk();
- u32 speed = DIV_ROUND_UP(pclk, 500);
- u32 hold = DIV_ROUND_UP(pclk, 1) - 1;
+ u32 pclk;
+ u32 speed;
+ u32 hold;
+ int ret;
+
+ ret = fec_get_clk_rate(NULL, 0);
+ if (ret < 0) {
+ printf("Can't find FEC0 clk rate: %d\n", ret);
+ return;
+ }
+ pclk = ret;
+ speed = DIV_ROUND_UP(pclk, 500);
+ hold = DIV_ROUND_UP(pclk, 1) - 1;
+
#ifdef FEC_QUIRK_ENET_MAC
speed--;
#endif
@@ -1268,6 +1305,21 @@ static int fecmxc_probe(struct udevice *dev)
uint32_t start;
int ret;
+ if (IS_ENABLED(CONFIG_IMX8)) {
+ ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+ if (ret < 0) {
+ debug("Can't get FEC ipg clk: %d\n", ret);
+ return ret;
+ }
+ ret = clk_enable(&priv->ipg_clk);
+ if (ret < 0) {
+ debug("Can't enable FEC ipg clk: %d\n", ret);
+ return ret;
+ }
+
+ priv->clk_rate = clk_get_rate(&priv->ipg_clk);
+ }
+
ret = fec_alloc_descs(priv);
if (ret)
return ret;
@@ -1372,6 +1424,7 @@ static const struct udevice_id fecmxc_ids[] = {
{ .compatible = "fsl,imx6sx-fec" },
{ .compatible = "fsl,imx6ul-fec" },
{ .compatible = "fsl,imx53-fec" },
+ { .compatible = "fsl,imx7d-fec" },
{ }
};
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index fd89443205..75ba55b69f 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -16,6 +16,8 @@
#ifndef __FEC_MXC_H
#define __FEC_MXC_H
+#include
+
/* Layout description of the FEC */
struct ethernet_regs {
/* [10:2]addr = 00 */
@@ -257,6 +259,8 @@ struct fec_priv {
#ifdef CONFIG_DM_ETH
u32 interface;
#endif
+ struct clk ipg_clk;
+ u32 clk_rate;
};
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
--
2.17.1
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[U-Boot] [PATCH] gpio: pca953x_gpio: fix DT GPIO flags translation
Commit fb01e07a95 accidentally broke initialisation of GPIO
descriptor flags from device tree: currently the active low
flag from gpio-specifier is always ignored. Fix it.
Signed-off-by: Anatolij Gustschin
Cc: Mario Six
---
drivers/gpio/pca953x_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 535b2f12ea..0bb484498a 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -227,7 +227,7 @@ static int pca953x_xlate(struct udevice *dev, struct
gpio_desc *desc,
struct ofnode_phandle_args *args)
{
desc->offset = args->args[0];
- desc->flags = args->args[1] & (GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
return 0;
}
--
2.17.1
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[U-Boot] [PATCH] gpio: pca953x: Clear the polarity invert register at init
From: Ye Li
The pca953x_gpio driver uses default value of polarity inversion
register. For some devices like PCA9557 and MAX7310, their polarity
inversion register default value is 0xf0. So for high 4 ports, when
reading their values, the values are inverted as the actual level.
This patch clears the polarity inversion register to 0 at init, so
that the port read and write values are aligned.
Signed-off-by: Ye Li
Acked-by: Fugang Duan
Acked-by: Peng Fan
Signed-off-by: Anatolij Gustschin
---
drivers/gpio/pca953x_gpio.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 0bb484498a..341527acc5 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -130,6 +130,25 @@ static int pca953x_read_regs(struct udevice *dev, int reg,
u8 *val)
return ret;
}
+static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int ret = 0;
+
+ if (info->gpio_count <= 8) {
+ ret = dm_i2c_write(dev, reg, val, 1);
+ } else if (info->gpio_count <= 16) {
+ ret = dm_i2c_write(dev, reg << 1, val, info->bank_count);
+ } else if (info->gpio_count == 40) {
+ /* Auto increment */
+ ret = dm_i2c_write(dev, (reg << 3) | 0x80, val,
info->bank_count);
+ } else {
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
static int pca953x_is_output(struct udevice *dev, int offset)
{
struct pca953x_info *info = dev_get_platdata(dev);
@@ -251,6 +270,7 @@ static int pca953x_probe(struct udevice *dev)
int ret;
int size;
const u8 *tmp;
+ u8 val[MAX_BANK];
addr = dev_read_addr(dev);
if (addr == 0)
@@ -296,6 +316,14 @@ static int pca953x_probe(struct udevice *dev)
snprintf(name, sizeof(name), "gpio@%x_", info->addr);
}
+ /* Clear the polarity registers to no invert */
+ memset(val, 0, MAX_BANK);
+ ret = pca953x_write_regs(dev, PCA953X_INVERT, val);
+ if (ret < 0) {
+ dev_err(dev, "Error writing invert register\n");
+ return ret;
+ }
+
str = strdup(name);
if (!str)
return -ENOMEM;
--
2.17.1
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Re: [U-Boot] [PATCH v3 2/5] dm: video: bridge: don't fail to activate bridge if reset or sleep GPIO is missing
On Wed, 17 Oct 2018 22:56:48 -0700
Vasily Khoruzhick wrote:
> Both GPIOs are optional, so we shouldn't fail if any is missing.
> Without this fix reset is not deasserted if sleep GPIO is missing.
>
> Signed-off-by: Vasily Khoruzhick
> Acked-by: Maxime Ripard
> Tested-by: Maxime Ripard
> Cc: Vagrant Cascadian
Reviewed-by: Andre Przywara
Thanks!
Andre.
> ---
> drivers/video/bridge/video-bridge-uclass.c | 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/video/bridge/video-bridge-uclass.c
> b/drivers/video/bridge/video-bridge-uclass.c index
> cd4959cc71..5fecb4cfd5 100644 ---
> a/drivers/video/bridge/video-bridge-uclass.c +++
> b/drivers/video/bridge/video-bridge-uclass.c @@ -106,13 +106,19 @@
> static int video_bridge_pre_probe(struct udevice *dev) int
> video_bridge_set_active(struct udevice *dev, bool active) {
> struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
> - int ret;
> + int ret = 0;
>
> debug("%s: %d\n", __func__, active);
> - ret = dm_gpio_set_value(&uc_priv->sleep, !active);
> - if (ret)
> - return ret;
> - if (active) {
> + if (uc_priv->sleep.dev) {
> + ret = dm_gpio_set_value(&uc_priv->sleep, !active);
> + if (ret)
> + return ret;
> + }
> +
> + if (!active)
> + return 0;
> +
> + if (uc_priv->reset.dev) {
> ret = dm_gpio_set_value(&uc_priv->reset, true);
> if (ret)
> return ret;
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Re: [U-Boot] [PATCH v3 1/5] mmc: sunxi: add support for automatic delay calibration
On Wed, 17 Oct 2018 22:56:47 -0700
Vasily Khoruzhick wrote:
> A64 and H6 support automatic delay calibration and Linux driver uses
> it instead of hardcoded delays. Add support for it to u-boot driver.
>
> Fixes eMMC instability on Pinebook
>
> Signed-off-by: Vasily Khoruzhick
> Acked-by: Maxime Ripard
> Tested-by: Maxime Ripard
> Cc: Vagrant Cascadian
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/include/asm/arch-sunxi/mmc.h | 6 +-
> drivers/mmc/sunxi_mmc.c | 21 -
> 2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
> b/arch/arm/include/asm/arch-sunxi/mmc.h index d98c53faaa..f2deafddd2
> 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -46,7 +46,9 @@ struct sunxi_mmc {
> u32 cbda; /* 0x94 */
> u32 res2[26];
> #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
> - u32 res3[64];
> + u32 res3[17];
> + u32 samp_dl;
> + u32 res4[46];
> #endif
> u32 fifo; /* 0x100 / 0x200 FIFO access
> address */ };
> @@ -130,5 +132,7 @@ struct sunxi_mmc {
> #define SUNXI_MMC_COMMON_CLK_GATE(1 << 16)
> #define SUNXI_MMC_COMMON_RESET (1 << 18)
>
> +#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
> +
> struct mmc *sunxi_mmc_init(int sdc_no);
> #endif /* _SUNXI_MMC_H */
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 39f15eb423..147eb9b4d5 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
> *priv, unsigned int hz) {
> unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
> bool new_mode = false;
> + bool calibrate = false;
> u32 val = 0;
>
> if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) &&
> (priv->mmc_no == 2)) new_mode = true;
>
> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
> + calibrate = true;
> +#endif
> +
> /*
>* The MMC clock has an extra /2 post-divider when operating
> in the new
>* mode.
> @@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
> *priv, unsigned int hz) val = CCM_MMC_CTRL_MODE_SEL_NEW;
> setbits_le32(&priv->reg->ntsr,
> SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif
> - } else {
> + } else if (!calibrate) {
> + /*
> + * Use hardcoded delay values if controller doesn't
> support
> + * calibration
> + */
> val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
> CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
> }
> @@ -228,6 +237,16 @@ static int mmc_config_clock(struct
> sunxi_mmc_priv *priv, struct mmc *mmc) rval &=
> ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr);
>
> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
> + /* A64 supports calibration of delays on MMC controller and
> we
> + * have to set delay of zero before starting calibration.
> + * Allwinner BSP driver sets a delay only in the case of
> + * using HS400 which is not supported by mainline U-Boot or
> + * Linux at the moment
> + */
> + writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
> +#endif
> +
> /* Re-enable Clock */
> rval |= SUNXI_MMC_CLK_ENABLE;
> writel(rval, &priv->reg->clkcr);
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[U-Boot] [PATCH] i2c: imx_lpi2c: fix typo and register base address format
Output the register base address in hex notation.
Signed-off-by: Anatolij Gustschin
---
drivers/i2c/imx_lpi2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index 6c343072fb..4586d4331f 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -105,7 +105,7 @@ static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int
len)
while (len--) {
result = bus_i2c_wait_for_tx_ready(regs);
if (result) {
- debug("i2c: send wait fot tx ready: %d\n", result);
+ debug("i2c: send wait for tx ready: %d\n", result);
return result;
}
writel(*txbuf++, ®s->mtdr);
@@ -482,7 +482,7 @@ static int imx_lpi2c_probe(struct udevice *bus)
if (ret < 0)
return ret;
- debug("i2c : controller bus %d at %lu , speed %d: ",
+ debug("i2c : controller bus %d at 0x%lx , speed %d: ",
bus->seq, i2c_bus->base,
i2c_bus->speed);
--
2.17.1
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Re: [U-Boot] [RFC PATCH v2 2/3] tools: Add a tool to get a list of defconfigs based on filters
On 09/10/2018 18:20, Simon Glass wrote:
Hi Jean-Jacques,
On 3 October 2018 at 07:53, Jean-Jacques Hiblot wrote:
The possible filters are "arch", "vendor", "soc", "cpu" and "arch".
The list of all the defconfigs is read from boards.cfg. If this file
doesn't exist, then tools/genboardscfg.py is called to generate it.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
tools/find_defconfigs.py | 167 +++
1 file changed, 167 insertions(+)
create mode 100755 tools/find_defconfigs.py
This looks good, but I have some style comments below.
Also it seems to do a similar thing to tools/buildman/board.py. Should
we replace that impl with what you have here? It looks more flexible
that what buildman currently provides.
diff --git a/tools/find_defconfigs.py b/tools/find_defconfigs.py
new file mode 100755
index 000..9d68cef
--- /dev/null
+++ b/tools/find_defconfigs.py
@@ -0,0 +1,167 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Author: JJ Hiblot
+#
+
+"""
+Output a list of defconfig matching criteria.
I think you mean defconfig-matching?
+
+The possible criteria are soc, vendor, arch, cpu, board and defconfig name.
+The criteria are expressed as regexp, allowing for complex selection.
+
+How does it work?
+-
+
+This tools uses the boards.cfg file produced by tools/genboardscfg.py
+It reads the file to get a list of all the defconfigs and the information
+about the soc, vendor etc. for each of them.
+Then it walks this list and outputs the defconfigs for which the info match
+the regexp passed to the program.
+
+examples:
+-
+
+1) Get the list of defconfigs for boards built around omap5, omap4 and k3, not
built by TI
+
+$ tools/find_defconfigs.py --soc 'omap[45]|k3' --vendor '(?!ti)'
+kc1_defconfig
+duovero_defconfig
+cl-som-am57x_defconfig
+cm_t54_defconfig
+
+2) Same list but iwth more details on the items that were used as filters
+
+$ tools/find_defconfigs.py --soc 'omap[45]|k3' --vendor '(?!ti)'
--show-details
+kc1_defconfig | omap4 | amazon
+duovero_defconfig | omap4 | gumstix
+cl-som-am57x_defconfig | omap5 | compulab
+cm_t54_defconfig | omap5 | compulab
+
+
+"""
+
+import re
+import os
+import argparse
Please sort these
+
+
+class board:
+
Need a class comment here, also use Board since it is a class name
+def __init__(self, status, arch, cpu, soc,
+ vendor, board, target, options, maintainer):
+self.status = status
+self.arch = arch
+self.cpu = cpu
+self.soc = soc
+self.vendor = vendor
+self.board = board
+self.target = target
+self.defconfig = "{}_defconfig".format(target)
+self.options = options
+self.maintainer = maintainer
+
+def show(self, sep=' | ', props=None):
Function comment (see other tools for style). Need to document args
and any return value.
+if not props:
+print(
+sep.join([self.defconfig,
+ self.vendor,
+ self.arch,
+ self.cpu,
+ self.soc,
+ self.board,
+ self.status,
+ self.maintainer]))
+else:
+print(sep.join([self.defconfig] + [getattr(self, prop) for prop in
props]))
Does this need to import print_function from __future__ for Python 2?
No it doesn't. You can run this program as-is with python2 or python3.
+
+def cleanup(self):
+""" remove the directory in which the cfg files have been built """
Please use comment style from other tools. Same below.
+shutil.rmtree(self.temp_dir)
+
+def match(self, rules):
+""" return True if the board match all the criteria """
+for prop, r in rules:
+val = getattr(self, prop)
+if not val or val == "-":
+return False
+if not r.match(val):
+return False
+return True
+
+
+def get_all_boards():
+""" extract a list of boards from 'boards.cfg' """
+result = []
+if not os.path.isfile("boards.cfg"):
+os.system('tools/genboardscfg.py')
+
+with open('boards.cfg', 'r') as f:
+for l in f.readlines():
+if not l or l[0] == "#":
+continue
+props = l.strip().split(None, 8)
+if not props:
+continue
+if len(props) < 9:
+props.extend(["-"] * (9 - len(props)))
+result.append(board(*props))
+return result
+
+
+def get_default_options():
+return ["board", "soc", "vendor", "arch", "cpu", "target"]
+
+
+def update_parser_with_default_options(parser):
+parser.add_argument('-i', '--ignore-case', action="store_true")
+parser.add_argument("--soc",
+help="regexp to filter on SoC. ex: 'omap[45]' to inspect
omap5 and oma
Re: [U-Boot] [PATCH v2 02/19] dm: i2c: Add dm_i2c_probe_device() to test the presence of a chip
On 12/10/2018 02:00, Simon Glass wrote:
Hi Jean-Jacques,
On 11 October 2018 at 06:01, Jean-Jacques Hiblot wrote:
Hi Simon,
thanks for the reviews.
On 11/10/2018 05:13, Simon Glass wrote:
Hi Jean-Jacques,
On 5 October 2018 at 10:45, Jean-Jacques Hiblot wrote:
In a non-DM environment, it is possible to test the presence of a chip
using i2c_probe(chip_addr).
dm_i2c_probe_device() brings the same functionality with a DM interface.
The intent is to be able to test the presence of a chip for the device
has
been created with i2c_get_chip_for_busnum(bus_num, chip_addr, ...)
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/i2c/i2c-uclass.c | 8
include/i2c.h| 13 +
2 files changed, 21 insertions(+)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index c5a3c4e..ec88168 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -378,6 +378,14 @@ int dm_i2c_probe(struct udevice *bus, uint
chip_addr, uint chip_flags,
return ret;
}
+int dm_i2c_probe_device(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+
+ return i2c_probe_chip(bus, chip->chip_addr, chip->flags);
+}
Why not just probe the device? That should have the same effect.
The device itself is not probed when using i2c_get_chip_for_busnum(). I
could have changed it there but was sure about possible side-effects on all
boards.
The code that uses the non-DM API usually calls I2C_probe() at some point,
this function is the equivalent in the DM world.
So if you change your above function to:
int dm_i2c_probe_device(struct udevice *dev)
{
return device_probe(dev);
If the chip is not present on the bus, it is quite happy to probe the
device anyway.
I have had a harder look at the usage of i2c_get_chip_for_busnum() and
all of the platforms should be ok if this function fails if the chip is
not detected. In fact most of the platform expect it to fail if the chip
is not detected.
So instead of adding a new function, I'll modify
i2c_get_chip_for_busnum() to fail if the device is not detected on the bus.
JJ
}
what happens?
Regards,
Simon
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Re: [U-Boot] [PATCH v3 5/5] sunxi: DT: add support for Pinebook
On 2018-10-17, Vasily Khoruzhick wrote:
> Pinebook is a laptop produced by Pine64, with USB-connected keyboard,
> USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP
> bridge from Analogix.
>
> Signed-off-by: Vasily Khoruzhick
> Acked-by: Maxime Ripard
> Tested-by: Maxime Ripard
> Cc: Vagrant Cascadian
Working great on my pinebook! Thanks!
Depends on the sunxi-pwm fixes recently posted for working LCD backlight
at the u-boot prompt:
https://patchwork.ozlabs.org/project/uboot/list/?series=71167
Tested-by: Vagrant Cascadian
live well,
vagrant
> ---
> arch/arm/dts/Makefile| 1 +
> arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi | 15 +
> arch/arm/dts/sun50i-a64-pinebook.dts | 294 +++
> configs/pinebook_defconfig | 22 ++
> 4 files changed, 332 insertions(+)
> create mode 100644 arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi
> create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts
> create mode 100644 configs/pinebook_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index dfe9335a04..6b8ee81059 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -404,6 +404,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
> sun50i-a64-orangepi-win.dtb \
> sun50i-a64-pine64-plus.dtb \
> sun50i-a64-pine64.dtb \
> + sun50i-a64-pinebook.dtb \
> sun50i-a64-sopine-baseboard.dtb
> dtb-$(CONFIG_MACH_SUN9I) += \
> sun9i-a80-optimus.dtb \
> diff --git a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi
> b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi
> new file mode 100644
> index 00..a99b7171d0
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2018 Vasily Khoruzhick
> + *
> + */
> +
> +/* The ANX6345 eDP-bridge is on r_i2c */
> +&r_i2c {
> + anx6345: edp-bridge@38 {
> + compatible = "analogix,anx6345";
> + reg = <0x38>;
> + reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
> + status = "okay";
> + };
> +};
> diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts
> b/arch/arm/dts/sun50i-a64-pinebook.dts
> new file mode 100644
> index 00..a3b0526ef6
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-a64-pinebook.dts
> @@ -0,0 +1,294 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2017 Icenowy Zheng
> + * Copyright (C) 2018 Vasily Khoruzhick
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "sun50i-a64.dtsi"
> +
> +#include
> +#include
> +#include
> +
> +/ {
> + model = "Pinebook";
> + compatible = "pine64,pinebook", "allwinner,sun50i-a64";
> +
> + aliases {
> + serial0 = &uart0;
> + ethernet0 = &rtl8723cs;
> + };
> +
> + vdd_bl: regulator@0 {
> + compatible = "regulator-fixed";
> + regulator-name = "bl-3v3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
> + enable-active-high;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm 0 5 0>;
> + brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
> + default-brightness-level = <2>;
> + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
> + power-supply = <&vdd_bl>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> +
> + framebuffer-lcd {
> + panel-supply = <®_dc1sw>;
> + dvdd25-supply = <®_dldo2>;
> + dvdd12-supply = <®_fldo1>;
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> +
> + lid_switch {
> + label = "Lid Switch";
> + gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
> + linux,input-type = ;
> + linux,code = ;
> + linux,can-disable;
> + wakeup-source;
> + };
> + };
> +
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> + };
> +};
> +
> +&ehci0 {
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + vmmc-supply = <®_dcdc1>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
> + disable
Re: [U-Boot] [U-Boot, 3/3] pwm: sunxi: choose best prescaler to improve PWM resolution
On 2018-10-16, Vasily Khoruzhick wrote:
> Choose best prescaler to improve PWM resolution. Without this change
> driver chooses first prescaler that gives us period value within
> range, but it could be not the best one.
>
> Signed-off-by: Vasily Khoruzhick
Fixes LCD backlight issues with the pinebook series:
https://patchwork.ozlabs.org/project/uboot/list/?series=71358
Tested-by: Vagrant Cascadian
> ---
> drivers/pwm/sunxi_pwm.c | 32 +++-
> 1 file changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
> index 6284409b4f..8a55e4f461 100644
> --- a/drivers/pwm/sunxi_pwm.c
> +++ b/drivers/pwm/sunxi_pwm.c
> @@ -67,49 +67,55 @@ static int sunxi_pwm_set_config(struct udevice *dev, uint
> channel,
> {
> struct sunxi_pwm_priv *priv = dev_get_priv(dev);
> struct sunxi_pwm *regs = priv->regs;
> - int prescaler;
> - u32 v, period = 0, duty;
> - u64 scaled_freq = 0;
> + int best_prescaler = 0;
> + u32 v, best_period = 0, duty;
> + u64 best_scaled_freq = 0;
> const u32 nsecs_per_sec = 10U;
>
> debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
>
> - for (prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
> + for (int prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
>prescaler++) {
> + u32 period = 0;
> + u64 scaled_freq = 0;
> if (!prescaler_table[prescaler])
> continue;
> scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
> period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
> - if (period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)
> - break;
> + if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) &&
> + best_period < period) {
> + best_period = period;
> + best_scaled_freq = scaled_freq;
> + best_prescaler = prescaler;
> + }
> }
>
> - if (period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
> + if (best_period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
> debug("%s: failed to find prescaler value\n", __func__);
> return -EINVAL;
> }
>
> - duty = lldiv(scaled_freq * duty_ns, nsecs_per_sec);
> + duty = lldiv(best_scaled_freq * duty_ns, nsecs_per_sec);
>
> - if (priv->prescaler != prescaler) {
> + if (priv->prescaler != best_prescaler) {
> /* Mask clock to update prescaler */
> v = readl(®s->ctrl);
> v &= ~SUNXI_PWM_CTRL_CLK_GATE;
> writel(v, ®s->ctrl);
> v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
> - v |= (prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
> + v |= (best_prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
> writel(v, ®s->ctrl);
> v |= SUNXI_PWM_CTRL_CLK_GATE;
> writel(v, ®s->ctrl);
> - priv->prescaler = prescaler;
> + priv->prescaler = best_prescaler;
> }
>
> - writel(SUNXI_PWM_CH0_PERIOD_PRD(period) |
> + writel(SUNXI_PWM_CH0_PERIOD_PRD(best_period) |
> SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period);
>
> debug("%s: prescaler: %d, period: %d, duty: %d\n",
> __func__, priv->prescaler,
> - period, duty);
> + best_period, duty);
>
> return 0;
> }
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[U-Boot] [BUG] H2+/H3 : SPI driver : error: ‘AHB_GATE_OFFSET_SPI0’ undeclared (first use in this function)
Version: u-boot-2018.09 Configuration : orangepi_zero_defconfig In file included from include/wait_bit.h:15:0, from drivers/spi/sun4i_spi.c:26: drivers/spi/sun4i_spi.c: In function 'sun4i_spi_enable_clock': LD drivers/usb/musb-new/built-in.o drivers/spi/sun4i_spi.c:246:38: error: 'AHB_GATE_OFFSET_SPI0' undeclared (first use in this function); did you mean 'AHB_GATE_OFFSET_MMC0'? setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0)); AHB_GATE_OFFSET_SPI0 can be found in: ./arch/arm/include/asm/arch-sunxi/clock_sun4i.h:#define AHB_GATE_OFFSET_SPI0 20 ./arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h:#define AHB_GATE_OFFSET_SPI0 20 ~/uboot/u-boot-2018.09$ grep -a CONFIG_MACH_SUN8I .config # CONFIG_MACH_SUN8I_A23 is not set # CONFIG_MACH_SUN8I_A33 is not set # CONFIG_MACH_SUN8I_A83T is not set CONFIG_MACH_SUN8I_H3=y # CONFIG_MACH_SUN8I_R40 is not set # CONFIG_MACH_SUN8I_V3S is not set CONFIG_MACH_SUN8I=y With arch/arm/include/asm/arch/clock.h #if defined(CONFIG_MACH_SUN8I_A83T) #include #elif defined(CONFIG_MACH_SUN50I_H6) #include #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ defined(CONFIG_MACH_SUN50I) #include #elif defined(CONFIG_MACH_SUN9I) #include #else #include #endif The AHB_GATE_OFFSET_SPI0 should be defined in asm/arch/clock_sun6i.h - Arjan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: rmobile: Drop PRR syscon driver
The PRR syscon driver is available too late for Multi DTB build
of U-Boot. Replace it with simple check whether a platform is
Gen3 or not and produce an address of the PRR.
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/cpu_info-rcar.c | 61 ---
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index ccb7a32ac4..ce9312f9d8 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -11,7 +11,14 @@
#define R8A7796_REV_1_00x5200
#define R8A7796_REV_1_10x5210
-static u32 rmobile_get_prr(void);
+static u32 rmobile_get_prr(void)
+{
+#ifdef CONFIG_RCAR_GEN3
+ return readl(0xFFF00044);
+#else
+ return readl(0xFF44);
+#endif
+}
u32 rmobile_get_cpu_type(void)
{
@@ -37,55 +44,3 @@ u32 rmobile_get_cpu_rev_fraction(void)
else
return prr & 0x000F;
}
-
-#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON)
-static u32 rmobile_get_prr(void)
-{
- /*
-* On RCar/RMobile Gen2 and older systems, the PRR is always
-* located at the address below. On newer systems, the PRR
-* may be located at different address, but that information
-* is obtained from DT. This code will be removed when all
-* of the older systems get converted to DM and OF control.
-*/
- return readl(0xFF44);
-}
-#else
-
-#include
-#include
-#include
-
-struct renesas_prr_priv {
- fdt_addr_t regs;
-};
-
-enum {
- PRR_RCAR,
-};
-
-static u32 rmobile_get_prr(void)
-{
- struct regmap *map;
-
- map = syscon_get_regmap_by_driver_data(PRR_RCAR);
- if (!map) {
- printf("PRR regmap failed!\n");
- hang();
- }
-
- return readl(map->ranges[0].start);
-}
-
-static const struct udevice_id renesas_prr_ids[] = {
- { .compatible = "renesas,prr", .data = PRR_RCAR },
- { }
-};
-
-U_BOOT_DRIVER(renesas_prr) = {
- .name = "renesas_prr",
- .id = UCLASS_SYSCON,
- .of_match = renesas_prr_ids,
- .flags = DM_FLAG_PRE_RELOC,
-};
-#endif
--
2.18.0
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[U-Boot] [PATCH] ARM: dts: rmobile: Build -u-boot variants of DTs
Build the -u-boot variants of the device trees so they can be included in Multi-DTB fitImage, which in turn allows us to build single U-Boot image for multiple boards. Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8e6f8e99d3..0de6234eec 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -455,14 +455,14 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb dtb-$(CONFIG_RCAR_GEN3) += \ - r8a7795-h3ulcb.dtb \ - r8a7795-salvator-x.dtb \ - r8a7796-m3ulcb.dtb \ - r8a7796-salvator-x.dtb \ - r8a77965-salvator-x.dtb \ - r8a77970-eagle.dtb \ - r8a77990-ebisu.dtb \ - r8a77995-draak.dtb + r8a7795-h3ulcb-u-boot.dtb \ + r8a7795-salvator-x-u-boot.dtb \ + r8a7796-m3ulcb-u-boot.dtb \ + r8a7796-salvator-x-u-boot.dtb \ + r8a77965-salvator-x-u-boot.dtb \ + r8a77970-eagle-u-boot.dtb \ + r8a77990-ebisu-u-boot.dtb \ + r8a77995-draak-u-boot.dtb dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] fdt: Fix uncompress_blob() for U-Boot proper
When U-Boot proper is compiled with CONFIG_MULTI_DTB_FIT and tries
to call uncompress_blob(), it fails with -ENOTSUPP. This is because
the full implementation of this function which includes compression
is available only in SPL. In U-Boot proper or if the compression is
not enabled, the blob is not compressed and thus can be passed to
locate_dtb_in_fit() in fdtdec_setup() without any changes. Pass the
blob without any changes if compression is not enabled instead of
failing.
Signed-off-by: Marek Vasut
Cc: Michal Simek
Cc: Tom Rini
---
lib/fdtdec.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index a420ba1885..d28f2cbb1c 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1198,7 +1198,8 @@ static int uncompress_blob(const void *src, ulong sz_src,
void **dstp)
# else
static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
{
- return -ENOTSUPP;
+ *dstp = (void *)src;
+ return 0;
}
# endif
#endif
--
2.18.0
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[U-Boot] [PATCH 1/9] ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3
From: Hiroyuki Yokoyama This patch fixes the write-protect control of CPG. Signed-off-by: Hiroyuki Yokoyama --- board/renesas/draak/draak.c | 4 ++-- board/renesas/salvator-x/salvator-x.c | 4 ++-- board/renesas/ulcb/ulcb.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 852fdda843..e7f0bd7b65 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGWPCR0xE6150904 -#define CPGWPR 0xE615090C +#define CPGWPR 0xE6150900 #define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) @@ -39,8 +39,8 @@ void s_init(void) writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); + writel(0x5A5A, CPGWPR); writel(0xA5A5, CPGWPCR); - writel(0x, CPGWPR); } #define GSX_MSTP112BIT(12) /* 3DG */ diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 00256bc1a3..746403a5c5 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGWPCR0xE6150904 -#define CPGWPR 0xE615090C +#define CPGWPR 0xE6150900 #define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) @@ -40,8 +40,8 @@ void s_init(void) writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); + writel(0x5A5A, CPGWPR); writel(0xA5A5, CPGWPCR); - writel(0x, CPGWPR); } #define GSX_MSTP112BIT(12) /* 3DG */ diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 213e869ebe..dfe8efd3ac 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGWPCR0xE6150904 -#define CPGWPR 0xE615090C +#define CPGWPR 0xE6150900 #define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) @@ -39,8 +39,8 @@ void s_init(void) writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); + writel(0x5A5A, CPGWPR); writel(0xA5A5, CPGWPCR); - writel(0x, CPGWPR); } #define GSX_MSTP112BIT(12) /* 3DG */ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 9/9] ARM: dts: rmobile: r8a77990: Add USB2.0(EHCI) DT nodes on Ebisu
From: Hiroyuki Yokoyama
Add device tree nodes for USB2.0(EHCI) on R-Car E3 Ebisu board.
Signed-off-by: Hiroyuki Yokoyama
---
arch/arm/dts/r8a77990-ebisu.dts | 16 ++
arch/arm/dts/r8a77990.dtsi| 38 +++
include/dt-bindings/power/r8a77990-sysc.h | 20
3 files changed, 74 insertions(+)
create mode 100644 include/dt-bindings/power/r8a77990-sysc.h
diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts
index 8b0d24bd29..5e3c195d4c 100644
--- a/arch/arm/dts/r8a77990-ebisu.dts
+++ b/arch/arm/dts/r8a77990-ebisu.dts
@@ -65,6 +65,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&extal_clk {
clock-frequency = <4800>;
};
@@ -101,6 +105,18 @@
function = "sdhi3";
power-source = <1800>;
};
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-name = "default";
+
+ status = "okay";
};
&sdhi0 {
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 6d2d5e1068..ad20ea14cd 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
/ {
compatible = "renesas,r8a77990";
@@ -165,6 +166,43 @@
resets = <&cpg 906>;
};
+ ohci0: usb@ee08 {
+ compatible = "generic-ohci";
+ reg = <0 0xee08 0 0x100>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ ehci0: usb@ee080100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee080100 0 0x100>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a7790",
+"renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee080200 0 0x700>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
pfc: pin-controller@e606 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe606 0 0x508>;
diff --git a/include/dt-bindings/power/r8a77990-sysc.h
b/include/dt-bindings/power/r8a77990-sysc.h
new file mode 100644
index 00..1409c73a57
--- /dev/null
+++ b/include/dt-bindings/power/r8a77990-sysc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77990_PD_CA53_CPU0 5
+#define R8A77990_PD_CA53_SCU 21
+
+/* Always-on power area */
+#define R8A77990_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
--
2.18.0
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[U-Boot] [PATCH 5/9] ARM: rmobile: salvator-x: Remove GSX clock force supply
From: Hiroyuki Yokoyama
GSX clock force supply code is unnecessary at U-Boot,
because GSX clock control is supported at the kernel driver.
Signed-off-by: Hiroyuki Yokoyama
---
board/renesas/salvator-x/salvator-x.c | 12
1 file changed, 12 deletions(-)
diff --git a/board/renesas/salvator-x/salvator-x.c
b/board/renesas/salvator-x/salvator-x.c
index 296aa90a12..726a236af3 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -31,7 +31,6 @@ void s_init(void)
{
}
-#define GSX_MSTP112BIT(12) /* 3DG */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
@@ -60,20 +59,9 @@ int board_early_init_f(void)
int board_init(void)
{
- u32 cpu_type = rmobile_get_cpu_type();
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x5;
- if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
- /* GSX: force power and clock supply */
- writel(0x001F, SYSC_PWRONCR2);
- while (readl(SYSC_PWRSR2) != 0x03E0)
- mdelay(20);
-
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
- }
-
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
--
2.18.0
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[U-Boot] [PATCH 8/9] ARM: rmobile: Fix module clock controls refer status on Gen3
From: Hiroyuki Yokoyama
When referring to the MSTPSR register, it contains the clock
status of SYS, RT, SECURE, and controlling SMSTPCR using this
value has the problem of being affected by the RT and SECURE
status.This patch changes the reference register to SMSTPCR.
Signed-off-by: Hiroyuki Yokoyama
---
board/renesas/draak/draak.c | 4 ++--
board/renesas/salvator-x/salvator-x.c | 4 ++--
board/renesas/ulcb/ulcb.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 060343dfe4..8f3d3915f7 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
diff --git a/board/renesas/salvator-x/salvator-x.c
b/board/renesas/salvator-x/salvator-x.c
index a1a1531663..8b15267d7b 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index e549a2efac..63550af1f0 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
- mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
@@ -60,7 +60,7 @@ int board_init(void)
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
--
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[U-Boot] [PATCH 7/9] ARM: rmobile: Enable cache command on Gen3
From: Hiroyuki Yokoyama This patch enables the cache command, mostly for convenience of testing. Signed-off-by: Hiroyuki Yokoyama Signed-off-by: Marek Vasut --- arch/arm/mach-rmobile/Kconfig| 1 + configs/r8a7795_salvator-x_defconfig | 1 + include/configs/draak.h | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index ac08d6eb12..d82023acf3 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -12,6 +12,7 @@ config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select ARM64 select PHY + select CMD_CACHE endchoice diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 40712a44c3..87870fc595 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y diff --git a/include/configs/draak.h b/include/configs/draak.h index 5d1da21e99..70c4f166a5 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -33,6 +33,5 @@ #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_CMD_CACHE #endif /* __DRAAK_H */ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/9] ARM: rmobile: Remove console parameter from bootargs on Gen3
From: Hiroyuki Yokoyama This patch removes 'console=' argument, because kernel uses stdout-path as parameter. Signed-off-by: Hiroyuki Yokoyama --- configs/r8a7795_salvator-x_defconfig | 2 +- configs/r8a7795_ulcb_defconfig| 2 +- configs/r8a77965_salvator-x_defconfig | 2 +- configs/r8a7796_salvator-x_defconfig | 2 +- configs/r8a7796_ulcb_defconfig| 2 +- configs/r8a77970_eagle_defconfig | 2 +- configs/r8a77990_ebisu_defconfig | 2 +- configs/r8a77995_draak_defconfig | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index aae38e84a0..40712a44c3 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -8,7 +8,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index c341e1aaac..f1d150b5a0 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -8,7 +8,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig index 567f63977e..72549e2836 100644 --- a/configs/r8a77965_salvator-x_defconfig +++ b/configs/r8a77965_salvator-x_defconfig @@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index e3551a8007..7c39268a43 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 8086261637..ef5c9443f9 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 0cd47c1203..67ef2632a9 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 4f9ebad23d..7363310d52 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200" +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index ca89a12b7b..0f1189b671 100644 --- a/configs/r8a7799
[U-Boot] [PATCH 4/9] ARM: rmobile: Remove Watchdog and CPG settings on Gen3
From: Hiroyuki Yokoyama
This code is unnecessary, because these registers are set by the
initial program loader (IPL).
Signed-off-by: Hiroyuki Yokoyama
---
board/renesas/draak/draak.c | 13 -
board/renesas/salvator-x/salvator-x.c | 13 -
board/renesas/ulcb/ulcb.c | 13 -
3 files changed, 39 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index f9ae74a39d..71fd5001c4 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -26,21 +26,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CPGWPCR0xE6150904
-#define CPGWPR 0xE6150900
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- writel(0x5A5A, CPGWPR);
- writel(0xA5A5, CPGWPCR);
}
#define GSX_MSTP112BIT(12) /* 3DG */
diff --git a/board/renesas/salvator-x/salvator-x.c
b/board/renesas/salvator-x/salvator-x.c
index cb5228a0bd..296aa90a12 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -27,21 +27,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CPGWPCR0xE6150904
-#define CPGWPR 0xE6150900
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- writel(0x5A5A, CPGWPR);
- writel(0xA5A5, CPGWPCR);
}
#define GSX_MSTP112BIT(12) /* 3DG */
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index fca6eae1fb..a7ca274f34 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -26,21 +26,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CPGWPCR0xE6150904
-#define CPGWPR 0xE6150900
-
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
- struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
- /* Watchdog init */
- writel(0xA5A5A500, &rwdt->rwtcsra);
- writel(0xA5A5A500, &swdt->swtcsra);
-
- writel(0x5A5A, CPGWPR);
- writel(0xA5A5, CPGWPCR);
}
#define GSX_MSTP112BIT(12) /* 3DG */
--
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[U-Boot] [PATCH 3/9] ARM: rmobile: Remove TMU0/TMU1 settings on Gen3
From: Hiroyuki Yokoyama
U-Boot uses ARM generic timer, TMU0 and TMU1 are not used, remove them.
Signed-off-by: Hiroyuki Yokoyama
---
board/renesas/draak/draak.c | 5 -
board/renesas/eagle/eagle.c | 5 -
board/renesas/ebisu/ebisu.c | 5 -
board/renesas/salvator-x/salvator-x.c | 5 -
board/renesas/ulcb/ulcb.c | 5 -
5 files changed, 25 deletions(-)
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index e7f0bd7b65..f9ae74a39d 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -44,17 +44,12 @@ void s_init(void)
}
#define GSX_MSTP112BIT(12) /* 3DG */
-#define TMU0_MSTP125 BIT(25) /* secure */
-#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
- /* TMU0,1 *//* which use ? */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
index 9317410071..0e5efea19d 100644
--- a/board/renesas/eagle/eagle.c
+++ b/board/renesas/eagle/eagle.c
@@ -50,17 +50,12 @@ void s_init(void)
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
-#define TMU0_MSTP125 BIT(25) /* secure */
-
int board_early_init_f(void)
{
/* Unlock CPG access */
writel(0xA5A5, CPGWPR);
writel(0x5A5A, CPGWPCR);
- /* TMU0 */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-
return 0;
}
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c
index 248223b444..5d8b79eee3 100644
--- a/board/renesas/ebisu/ebisu.c
+++ b/board/renesas/ebisu/ebisu.c
@@ -30,13 +30,8 @@ void s_init(void)
{
}
-#define TMU0_MSTP125 BIT(25) /* secure */
-
int board_early_init_f(void)
{
- /* TMU0 */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-
return 0;
}
diff --git a/board/renesas/salvator-x/salvator-x.c
b/board/renesas/salvator-x/salvator-x.c
index 746403a5c5..cb5228a0bd 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -45,17 +45,12 @@ void s_init(void)
}
#define GSX_MSTP112BIT(12) /* 3DG */
-#define TMU0_MSTP125 BIT(25) /* secure */
-#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
- /* TMU0,1 *//* which use ? */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index dfe8efd3ac..fca6eae1fb 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -44,17 +44,12 @@ void s_init(void)
}
#define GSX_MSTP112BIT(12) /* 3DG */
-#define TMU0_MSTP125 BIT(25) /* secure */
-#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
- /* TMU0,1 *//* which use ? */
- mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
--
2.18.0
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[U-Boot] [PATCH] cmd: fdt: Fix fdt address information after the movement
From: Hiroyuki Yokoyama
This patch fixes the address information of fdt.
wrong case:
=> fdt addr 0x4800
=> fdt move 0x4800 0x4100 0xa000
=> fdt addr
The address of the fdt is 4800
Active address in this case is 0x4100.
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Marek Vasut
Cc: Hiroyuki Yokoyama
Cc: Nobuhiro Iwamatsu
Cc: Pantelis Antoniou
---
cmd/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 8a19a3fdbf..84be26f4f1 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -202,7 +202,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
fdt_strerror(err));
return 1;
}
- working_fdt = newaddr;
+ set_working_fdt_addr((ulong)newaddr);
#ifdef CONFIG_OF_SYSTEM_SETUP
/* Call the board-specific fixup routine */
} else if (strncmp(argv[1], "sys", 3) == 0) {
--
2.18.0
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[U-Boot] [PATCH 6/9] ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3
From: Hiroyuki Yokoyama Tidy up unused definition related to power control of 3DG. Signed-off-by: Hiroyuki Yokoyama --- board/renesas/draak/draak.c | 6 -- board/renesas/salvator-x/salvator-x.c | 6 -- board/renesas/ulcb/ulcb.c | 6 -- 3 files changed, 18 deletions(-) diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 71fd5001c4..060343dfe4 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -44,12 +44,6 @@ int board_early_init_f(void) return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#defineSYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#defineSYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 726a236af3..a1a1531663 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -44,12 +44,6 @@ int board_early_init_f(void) return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#defineSYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#defineSYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index a7ca274f34..e549a2efac 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -44,12 +44,6 @@ int board_early_init_f(void) return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#defineSYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#defineSYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] usb: ohci: Add OHCI PCI driver
Add small OHCI PCI driver for USB 1.1 OHCI controllers on PCI bus.
This driver matches only on PCI class (serial-ohci) and requires
DM-USB ; any sort of deprecated legacy usage is not supported.
Signed-off-by: Marek Vasut
---
drivers/usb/host/Kconfig| 6
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ohci-pci.c | 55 +
3 files changed, 62 insertions(+)
create mode 100644 drivers/usb/host/ohci-pci.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a213c918bc..045aa0a3f6 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -224,6 +224,12 @@ config USB_OHCI_GENERIC
---help---
Enables support for generic OHCI controller.
+config USB_OHCI_PCI
+ bool "Support for PCI-based OHCI USB controller"
+ depends on DM_USB
+ help
+ Enables support for the PCI-based OHCI controller.
+
endif # USB_OHCI_HCD
config USB_UHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index cb8c315a15..b7c94cadcb 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
+obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o
# echi
obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
new file mode 100644
index 00..dd078f008e
--- /dev/null
+++ b/drivers/usb/host/ohci-pci.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ohci.h"
+
+/* Information about the USB port */
+struct ohci_pci_priv {
+ ohci_t ohci;
+};
+
+static int ohci_pci_probe(struct udevice *dev)
+{
+ struct ohci_regs *regs;
+ u32 cmd;
+
+ regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ if (!regs)
+ return -ENOMEM;
+
+ /* Enable busmaster */
+ dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER;
+ dm_pci_write_config32(dev, PCI_COMMAND, cmd);
+
+ debug("OHCI-PCI init regs %p\n", regs);
+
+ return ohci_register(dev, regs);
+}
+
+U_BOOT_DRIVER(ohci_pci) = {
+ .name = "ohci_pci",
+ .id = UCLASS_USB,
+ .probe = ohci_pci_probe,
+ .remove = ohci_deregister,
+ .ops= &ohci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct ohci_pci_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static struct pci_device_id ohci_pci_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(ohci_pci, ohci_pci_supported);
--
2.18.0
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[U-Boot] [PATCH] mmc: dw_mmc: fix dwmci_data_transfer not filling data buffer
From: Paweł Jarosz
In current version of the driver when data size is low (observed with 2 bytes
or 16 bytes)
like in case when mmc tries to read card capabilities or switch card mode, data
buffer in
function dwmci_data_transfer not being filled.
The reason is that interrupt Receive FIFO Data Request (RXDR) not being fired
but instead
Data Transfer Over (DTO) fires.
This results in card not being properly detected (i.e. SD version 1.0 instead
of 3.0,
buswidth 1 instead 4).
So fix this by checking both interrupts status before reading data.
Signed-off-by: Paweł Jarosz
---
drivers/mmc/dw_mmc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 3b601b0e43..f1736c7abf 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -138,7 +138,8 @@ static int dwmci_data_transfer(struct dwmci_host *host,
struct mmc_data *data)
if (host->fifo_mode && size) {
len = 0;
if (data->flags == MMC_DATA_READ &&
- (mask & DWMCI_INTMSK_RXDR)) {
+ (mask & DWMCI_INTMSK_RXDR ||
+mask & DWMCI_INTMSK_DTO)) {
while (size) {
ret = dwmci_fifo_ready(host,
DWMCI_FIFO_EMPTY,
--
2.17.1
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[U-Boot] socfpga cyclone5 dts
Hi Marek, I was playing with updating the dts files for cyclone5 (and arria5) from current kernel sources, but I found that the kernel as 4 boards that U-Boot doesn't have and U-Boot has 6 boards that the kernel doesn't have. How should I proceed here? Should I copy new boards from the kernel? Should I keep U-Boot-only boards and try to adjust them to changes (if any)? Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] arm: ti: boot: Remove environment partition
Remove "environment" partition and do not read it when booting Android
from eMMC. We don't use this partition anymore, so this is just an
unintentional leftover.
Earlier we were reading dtb file from "environment" partition to feed it
further to kernel. Now we are using dtb from FIT image ("boot" partition
contains boot_fit.img image), which can be seen from this command:
bootm ${loadaddr}#${fdtfile}
where "#" character means we have FIT image in ${loadaddr} RAM address.
Signed-off-by: Sam Protsenko
---
include/environment/ti/boot.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 2893cd4287..560753ae4c 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -35,7 +35,6 @@
"uuid_disk=${uuid_gpt_disk};" \
"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
"name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \
- "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
"name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
@@ -92,8 +91,6 @@
"mmc dev $mmcdev; " \
"mmc rescan; " \
AVB_VERIFY_CHECK \
- "part start mmc ${mmcdev} environment fdt_start; " \
- "part size mmc ${mmcdev} environment fdt_size; " \
"part start mmc ${mmcdev} boot boot_start; " \
"part size mmc ${mmcdev} boot boot_size; " \
"mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
--
2.19.1
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[U-Boot] [PATCH 1/1] efi_loader: fix typos
Fix typos in EFI subsystem comments.
Signed-off-by: Heinrich Schuchardt
---
cmd/bootefi.c| 2 +-
lib/efi_loader/efi_bootmgr.c | 2 +-
lib/efi_loader/efi_console.c | 4 ++--
lib/efi_loader/efi_device_path_to_text.c | 8
lib/efi_loader/efi_gop.c | 11 +++
lib/efi_loader/efi_net.c | 8
6 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 78f126f1c6..3605c3ff96 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -354,7 +354,7 @@ static efi_status_t do_bootefi_exec(void *efi,
/*
* Special case for efi payload not loaded from disk, such as
* 'bootefi hello' or for example payload loaded directly into
-* memory via jtag, etc:
+* memory via JTAG, etc:
*/
if (!device_path && !image_path) {
printf("WARNING: using memory device/image path, this may
confuse some payloads!\n");
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 0c5764db12..2aae12e154 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * EFI utils
+ * EFI boot manager
*
* Copyright (c) 2017 Rob Clark
*/
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 7274d75204..66c33a551d 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -205,7 +205,7 @@ static int query_console_serial(int *rows, int *cols)
/*
* Not all terminals understand CSI [18t for querying the console size.
* We should adhere to escape sequences documented in the console_codes
-* manpage and the ECMA-48 standard.
+* man page and the ECMA-48 standard.
*
* So here we follow a different approach. We position the cursor to the
* bottom right and query its position. Before leaving the function we
@@ -480,7 +480,7 @@ void set_shift_mask(int mod, struct efi_key_state
*key_state)
*
* This gets called when we have already parsed CSI.
*
- * @modifiers: bitmask (shift, alt, ctrl)
+ * @modifiers: bit mask (shift, alt, ctrl)
* @return:the unmodified code
*/
static int analyze_modifiers(struct efi_key_state *key_state)
diff --git a/lib/efi_loader/efi_device_path_to_text.c
b/lib/efi_loader/efi_device_path_to_text.c
index 0082236359..e219f84b28 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -269,9 +269,9 @@ static char *efi_convert_single_device_node_to_text(
* for details.
*
* device_node device node to be converted
- * display_onlytrue if the shorter text represenation shall be
used
+ * display_onlytrue if the shorter text representation shall
be used
* allow_shortcuts true if shortcut forms may be used
- * @return text represenation of the device path
+ * @return text representation of the device path
* NULL if out of memory of device_path is NULL
*/
static uint16_t EFIAPI *efi_convert_device_node_to_text(
@@ -302,9 +302,9 @@ out:
* for details.
*
* device_path device path to be converted
- * display_onlytrue if the shorter text represenation shall be
used
+ * display_onlytrue if the shorter text representation shall
be used
* allow_shortcuts true if shortcut forms may be used
- * @return text represenation of the device path
+ * @return text representation of the device path
* NULL if out of memory of device_path is NULL
*/
static uint16_t EFIAPI *efi_convert_device_path_to_text(
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index fbd5d97de9..d62ce45912 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -243,12 +243,12 @@ static efi_uintn_t gop_get_bpp(struct efi_gop *this)
}
/*
- * Gcc can't optimize our BLT function well, but we need to make sure that
+ * GCC can't optimize our BLT function well, but we need to make sure that
* our 2-dimensional loop gets executed very quickly, otherwise the system
* will feel slow.
*
* By manually putting all obvious branch targets into functions which call
- * our generic blt function with constants, the compiler can successfully
+ * our generic BLT function with constants, the compiler can successfully
* optimize for speed.
*/
static efi_status_t gop_blt_video_fill(struct efi_gop *this,
@@ -452,7 +452,7 @@ efi_status_t efi_gop_register(void)
ret = efi_add_protocol(&gopobj->header, &efi_gop_guid,
&gopobj->ops);
if (ret != EFI_SUCCESS) {
- printf("ERROR: Failure adding gop protocol\n");
+ printf("ERROR: Failure adding GOP protocol\n");
return ret;
}
go
Re: [U-Boot] [PATCH] arm: ti: boot: Remove environment partition
On 10/18/2018 2:47 PM, Sam Protsenko wrote:
Remove "environment" partition and do not read it when booting Android
from eMMC. We don't use this partition anymore, so this is just an
unintentional leftover.
Earlier we were reading dtb file from "environment" partition to feed it
further to kernel. Now we are using dtb from FIT image ("boot" partition
contains boot_fit.img image), which can be seen from this command:
bootm ${loadaddr}#${fdtfile}
where "#" character means we have FIT image in ${loadaddr} RAM address.
Signed-off-by: Sam Protsenko
Acked-by: Praneeth Bajjuri
---
include/environment/ti/boot.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 2893cd4287..560753ae4c 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -35,7 +35,6 @@
"uuid_disk=${uuid_gpt_disk};" \
"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
"name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \
- "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
"name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
@@ -92,8 +91,6 @@
"mmc dev $mmcdev; " \
"mmc rescan; " \
AVB_VERIFY_CHECK \
- "part start mmc ${mmcdev} environment fdt_start; " \
- "part size mmc ${mmcdev} environment fdt_size; " \
"part start mmc ${mmcdev} boot boot_start; " \
"part size mmc ${mmcdev} boot boot_size; " \
"mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
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Re: [U-Boot] socfpga cyclone5 dts
On 10/18/2018 09:28 PM, Simon Goldschmidt wrote: > Hi Marek, Hi, > I was playing with updating the dts files for cyclone5 (and arria5) from > current kernel sources, but I found that the kernel as 4 boards that > U-Boot doesn't have and U-Boot has 6 boards that the kernel doesn't have. Thanks for doing this, really appreciated (even though it probably doesn't look that way most of the time). And yikes, which boards are where , can you list the problematic ones? > How should I proceed here? Should I copy new boards from the kernel? > Should I keep U-Boot-only boards and try to adjust them to changes (if > any)? I'd say sync as much as possible with kernel and the rest, update. I don't think there are any real board specific things which would prevent the update in those DTs missing in the kernel. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] socfpga cyclone5 dts
Marek Vasut schrieb am Do., 18. Okt. 2018, 22:15: > On 10/18/2018 09:28 PM, Simon Goldschmidt wrote: > > Hi Marek, > > Hi, > > > I was playing with updating the dts files for cyclone5 (and arria5) from > > current kernel sources, but I found that the kernel as 4 boards that > > U-Boot doesn't have and U-Boot has 6 boards that the kernel doesn't have. > > Thanks for doing this, really appreciated (even though it probably > doesn't look that way most of the time). > > And yikes, which boards are where , can you list the problematic ones? > > > How should I proceed here? Should I copy new boards from the kernel? > > Should I keep U-Boot-only boards and try to adjust them to changes (if > > any)? > > I'd say sync as much as possible with kernel and the rest, update. I > don't think there are any real board specific things which would prevent > the update in those DTs missing in the kernel. > Ok, I'll just try and prepare a patch that ports the existing boards and mentions the boards not ported from current kernel sources. I don't want to remove boards from U-Boot, so we'll just have to test those not in Linux. Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] socfpga cyclone5 dts
On 10/18/2018 10:20 PM, Simon Goldschmidt wrote: > > > Marek Vasut mailto:marek.va...@gmail.com>> > schrieb am Do., 18. Okt. 2018, 22:15: > > On 10/18/2018 09:28 PM, Simon Goldschmidt wrote: > > Hi Marek, > > Hi, > > > I was playing with updating the dts files for cyclone5 (and > arria5) from > > current kernel sources, but I found that the kernel as 4 boards that > > U-Boot doesn't have and U-Boot has 6 boards that the kernel > doesn't have. > > Thanks for doing this, really appreciated (even though it probably > doesn't look that way most of the time). > > And yikes, which boards are where , can you list the problematic ones? > > > How should I proceed here? Should I copy new boards from the kernel? > > Should I keep U-Boot-only boards and try to adjust them to changes (if > > any)? > > I'd say sync as much as possible with kernel and the rest, update. I > don't think there are any real board specific things which would prevent > the update in those DTs missing in the kernel. > > > Ok, I'll just try and prepare a patch that ports the existing boards and > mentions the boards not ported from current kernel sources. I don't want > to remove boards from U-Boot, so we'll just have to test those not in Linux. Sounds good! -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] pwm: sunxi: fix off-by-one that prevented PWM to use prescaler bypass
On Tue, 16 Oct 2018 21:56:33 -0700 Vasily Khoruzhick anars...@gmail.com wrote: > Fix off-by-one that prevented PWM driver to use prescaler bypass. > Without this change prescaler is always enabled. > > Signed-off-by: Vasily Khoruzhick > --- > drivers/pwm/sunxi_pwm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied whole series to u-boot-staging/ag...@denx.de, thanks! -- Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] efi-next: Kconfig: error: recursive dependency detected!
Hello Alex, in branch efi-next Kconfig has a recursive dependency: $ make qemu_arm64_defconfig drivers/usb/Kconfig:1:error: recursive dependency detected! drivers/usb/Kconfig:1: symbol USB is selected by DISTRO_DEFAULTS Kconfig:89: symbol DISTRO_DEFAULTS depends on USB For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" This recursive dependency does not exist in master HEAD. Bisection points to: distro: Imply USB_STORAGE when USB is available https://lists.denx.de/pipermail/u-boot/2018-October/344774.html Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: Samsung: Add Exynos5422-based Odroid HC2 support
Odroid HC2 board is based on Odroid XU4 board, like the Odroid HC1.
The linux kernel does not provide a hc2 DTB so the hc1 DTB is also used
for the Odroid HC2.
Signed-off-by: Dirk Meul
---
board/samsung/common/exynos5-dt-types.c | 16 +---
board/samsung/common/exynos5-dt.c | 4 ++--
configs/odroid-xu3_defconfig| 2 +-
include/samsung/exynos5-dt-types.h | 2 ++
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/board/samsung/common/exynos5-dt-types.c
b/board/samsung/common/exynos5-dt-types.c
index 4473968db6..7a86e91877 100644
--- a/board/samsung/common/exynos5-dt-types.c
+++ b/board/samsung/common/exynos5-dt-types.c
@@ -24,14 +24,15 @@ static const struct udevice_id board_ids[] = {
};
/**
- * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf):
+ * Odroix XU3/XU4/HC1/HC2 board revisions (from
HC1+_HC2_MAIN_REV0.1_20171017.pdf):
* Rev ADCmax Board
* 0.1 0 XU3 0.1
* 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
* 0.3 1280 XU4 0.1
* 0.4 739 XU4 0.2
* 0.5 1016 XU4+Air0.1 (Passive cooling)
- * 0.6 1308 XU4S 0.1 (HC1)
+ * 0.6 1309 XU4-HC1 0.1
+ * 0.7 1470 XU4-HC1+ 0.1 (HC2)
* Use +1% for ADC value tolerance in the array below, the code loops until
* the measured ADC value is lower than then ADCmax from the array.
*/
@@ -39,7 +40,8 @@ struct odroid_rev_info odroid_info[] = {
{ EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" },
{ EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" },
{ EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" },
- { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" },
+ { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1322, "hc1" },
+ { EXYNOS5_BOARD_ODROID_HC2_REV01, 1, 1484, "hc1" },
{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
};
@@ -144,6 +146,14 @@ bool board_is_odroidhc1(void)
return false;
}
+bool board_is_odroidhc2(void)
+{
+ if (gd->board_type == EXYNOS5_BOARD_ODROID_HC2_REV01)
+ return true;
+
+ return false;
+}
+
bool board_is_generic(void)
{
if (gd->board_type == EXYNOS5_BOARD_GENERIC)
diff --git a/board/samsung/common/exynos5-dt.c
b/board/samsung/common/exynos5-dt.c
index 8c3a9ea564..c183965b92 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -179,7 +179,7 @@ char *get_dfu_alt_system(char *interface, char *devstr)
{
char *info = "Not supported!";
- if (board_is_odroidxu4() || board_is_odroidhc1())
+ if (board_is_odroidxu4() || board_is_odroidhc1() ||
board_is_odroidhc2())
return info;
return env_get("dfu_alt_system");
@@ -192,7 +192,7 @@ char *get_dfu_alt_boot(char *interface, char *devstr)
char *alt_boot;
int dev_num;
- if (board_is_odroidxu4() || board_is_odroidhc1())
+ if (board_is_odroidxu4() || board_is_odroidhc1() ||
board_is_odroidhc2())
return info;
dev_num = simple_strtoul(devstr, NULL, 10);
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 258b9781cc..d5c7cc7129 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E0
CONFIG_ARCH_EXYNOS5=y
-CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1"
+CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=8
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/include/samsung/exynos5-dt-types.h
b/include/samsung/exynos5-dt-types.h
index 8e11af30d1..8fe08fe211 100644
--- a/include/samsung/exynos5-dt-types.h
+++ b/include/samsung/exynos5-dt-types.h
@@ -9,6 +9,7 @@ enum {
EXYNOS5_BOARD_ODROID_XU3_REV02,
EXYNOS5_BOARD_ODROID_XU4_REV01,
EXYNOS5_BOARD_ODROID_HC1_REV01,
+ EXYNOS5_BOARD_ODROID_HC2_REV01,
EXYNOS5_BOARD_ODROID_UNKNOWN,
EXYNOS5_BOARD_COUNT,
@@ -25,5 +26,6 @@ bool board_is_generic(void);
bool board_is_odroidxu3(void);
bool board_is_odroidxu4(void);
bool board_is_odroidhc1(void);
+bool board_is_odroidhc2(void);
#endif
--
2.17.1
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[U-Boot] socfpga cyclone5 dts
Hi Marek, I was playing with updating the dts files for cyclone5 (and arria5) from current kernel sources, but I found that the kernel as 4 boards that U-Boot doesn't have and U-Boot has 6 boards that the kernel doesn't have. How should I proceed here? Should I copy new boards from the kernel? Should I keep U-Boot-only boards and try to adjust them to changes (if any)? Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 30/34] serial: lpuart: support uclass clk api
From: Peng Fan
Modify most APIs to use udevice as the first parameter, then
it will be easy to get the clk reference by using udevice pointer.
Use uclass api to get lpuart clk when CONFIG_CLK is enabled.
Signed-off-by: Peng Fan
Signed-off-by: Anatolij Gustschin
Cc: Stefano Babic
---
Changes in v7:
- fixed build error when CONFIG_CLK not defined
- get_lpuart_clk_rate() can return negative value on error,
check return value and only proceed with register config
when meaningful clock rate returned
drivers/serial/serial_lpuart.c | 95 +++---
1 file changed, 76 insertions(+), 19 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index b28f7cf68d..6106c1f9ec 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -104,6 +105,32 @@ u32 __weak get_lpuart_clk(void)
return CONFIG_SYS_CLK_FREQ;
}
+#if IS_ENABLED(CONFIG_CLK)
+static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
+{
+ struct clk per_clk;
+ ulong rate;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+
+ rate = clk_get_rate(&per_clk);
+ if ((long)rate <= 0) {
+ dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
+ return ret;
+ }
+ *clk = rate;
+ return 0;
+}
+#else
+static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
+{ return -ENOSYS; }
+#endif
+
static bool is_lpuart32(struct udevice *dev)
{
struct lpuart_serial_platdata *plat = dev->platdata;
@@ -111,12 +138,22 @@ static bool is_lpuart32(struct udevice *dev)
return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
}
-static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
+static void _lpuart_serial_setbrg(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl *base = plat->reg;
- u32 clk = get_lpuart_clk();
+ u32 clk;
u16 sbr;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_CLK)) {
+ ret = get_lpuart_clk_rate(dev, &clk);
+ if (ret)
+ return;
+ } else {
+ clk = get_lpuart_clk();
+ }
sbr = (u16)(clk / (16 * baudrate));
@@ -162,8 +199,9 @@ static int _lpuart_serial_tstc(struct
lpuart_serial_platdata *plat)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
+static int _lpuart_serial_init(struct udevice *dev)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
u8 ctrl;
@@ -182,19 +220,29 @@ static int _lpuart_serial_init(struct
lpuart_serial_platdata *plat)
__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
/* provide data bits, parity, stop bit, etc */
- _lpuart_serial_setbrg(plat, gd->baudrate);
+ _lpuart_serial_setbrg(dev, gd->baudrate);
__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
return 0;
}
-static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
- u32 clk = get_lpuart_clk();
+ u32 clk;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_CLK)) {
+ ret = get_lpuart_clk_rate(dev, &clk);
+ if (ret)
+ return;
+ } else {
+ clk = get_lpuart_clk();
+ }
baud_diff = baudrate;
osr = 0;
@@ -248,12 +296,22 @@ static void _lpuart32_serial_setbrg_7ulp(struct
lpuart_serial_platdata *plat,
out_le32(&base->baud, tmp);
}
-static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
+static void _lpuart32_serial_setbrg(struct udevice *dev,
int baudrate)
{
+ struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
struct lpuart_fsl_reg32 *base = plat->reg;
- u32 clk = get_lpuart_clk();
+ u32 clk;
u32 sbr;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_CLK)) {
+ ret = get_lpuart_clk_rate(dev, &clk);
+ if (ret)
+ return;
+ } else {
+ clk = get_lpuart_clk();
+ }
sbr = (clk / (16 * baudrate));
@@ -321,8 +379,9
[U-Boot] [PATCH] mtd: nand: lpc32xx mlc: predefine number of NAND chips to support
Build option CONFIG_SYS_MAX_NAND_CHIPS is used by NXP LPC32xx NAND MLC
driver only, as a preparation for potential removal or replacement of
the option the change predefines CONFIG_SYS_MAX_NAND_CHIPS to 1, same
value is used by the single user Work Microwave Work 92105 board, thus
it will be safe now to remove the option as a board specific one.
Signed-off-by: Vladimir Zapolskiy
---
drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 5d4ffea608d9..79d1489dc72c 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -82,6 +82,10 @@ struct lpc32xx_nand_mlc_registers {
static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
+#if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
+#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#endif
+
#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
/**
--
2.17.1
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[U-Boot] [PATCH] mtd: nand: lpc32xx slc: disable DMA support in SPL builds
Testing and analysis shows that at the moment LPC32xx NAND SLC driver
can not get PL080 DMA backbone support in SPL build, because SPL NAND
loaders operate with subpage (ECC step to be precisely) reads, and
this is not supported in the NAND SLC + DMA + hardware ECC calculation
bundle.
The change removes a cautious build time warning and explicitly
disables DMA flavour of the driver for SPL builds, to reduce the
amound of #ifdef sections the code blocks are minimally reorganized.
Signed-off-by: Vladimir Zapolskiy
---
drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 78 ++---
1 file changed, 32 insertions(+), 46 deletions(-)
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 99f6e15f4e07..8615b112a21f 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -2,13 +2,12 @@
/*
* LPC32xx SLC NAND flash controller driver
*
- * (C) Copyright 2015 Vladimir Zapolskiy
+ * (C) Copyright 2015-2018 Vladimir Zapolskiy
+ * Copyright (c) 2015 Tyco Fire Protection Products.
*
* Hardware ECC support original source code
* Copyright (C) 2008 by NXP Semiconductors
* Author: Kevin Wells
- *
- * Copyright (c) 2015 Tyco Fire Protection Products.
*/
#include
@@ -22,10 +21,6 @@
#include
#include
-#if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD)
-#warning "DMA support in SPL image is not tested"
-#endif
-
struct lpc32xx_nand_slc_regs {
u32 data;
u32 addr;
@@ -78,16 +73,14 @@ struct lpc32xx_nand_slc_regs {
* Note: For large page devices, the default layouts are used. */
static struct nand_ecclayout lpc32xx_nand_oob_16 = {
.eccbytes = 6,
- .eccpos = {10, 11, 12, 13, 14, 15},
+ .eccpos = { 10, 11, 12, 13, 14, 15, },
.oobfree = {
- {.offset = 0,
-. length = 4},
- {.offset = 6,
-. length = 4}
- }
+ { .offset = 0, .length = 4, },
+ { .offset = 6, .length = 4, },
+ }
};
-#if defined(CONFIG_DMA_LPC32XX)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
/*
@@ -165,7 +158,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
}
-#if defined(CONFIG_DMA_LPC32XX)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
/*
* Prepares DMA descriptors for NAND RD/WR operations
* If the size is < 256 Bytes then it is assumed to be
@@ -324,7 +317,6 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const
u8 *buf,
if (unlikely(ret < 0))
BUG();
-
/* Wait for NAND to be ready */
while (!lpc32xx_nand_dev_ready(mtd))
;
@@ -404,46 +396,18 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char
*dat,
return ret2;
}
-#endif
-#if defined(CONFIG_DMA_LPC32XX)
static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
lpc32xx_nand_xfer(mtd, buf, len, 1);
}
-#else
-static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- while (len-- > 0)
- *buf++ = readl(&lpc32xx_nand_slc_regs->data);
-}
-#endif
-static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
-{
- return readl(&lpc32xx_nand_slc_regs->data);
-}
-
-#if defined(CONFIG_DMA_LPC32XX)
static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
int len)
{
lpc32xx_nand_xfer(mtd, buf, len, 0);
}
-#else
-static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int
len)
-{
- while (len-- > 0)
- writel(*buf++, &lpc32xx_nand_slc_regs->data);
-}
-#endif
-
-static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
-{
- writel(byte, &lpc32xx_nand_slc_regs->data);
-}
-#if defined(CONFIG_DMA_LPC32XX)
/* Reuse the logic from "nand_read_page_hwecc()" */
static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip
*chip,
uint8_t *buf, int oob_required, int page)
@@ -511,8 +475,30 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
return 0;
}
+#else
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ while (len-- > 0)
+ *buf++ = readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int
len)
+{
+ while (len-- > 0)
+ writel(*buf++, &lpc32xx_nand_slc_regs->data);
+}
#endif
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+ return readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
+{
+ writel(byte, &lpc32xx_nand_slc_regs->data);
+}
+
/*
* LPC32xx has only one SLC NAND controller, don't utilize
Re: [U-Boot] [PATCH 0/2] arm: lpc32xx: create platform specific Kconfig file
Hi Tom, On 09/17/2018 09:43 PM, Vladimir Zapolskiy wrote: > There is a need to introduce ARCH_LPC32XX build config symbol > to improve selection of build options for drivers, which are > specific to NXP LPC32xx platform only. At the same time the > new Kconfig file and sections can be used to describe common SoC > properties and collect entries of all LPC32xx boards. > > The presented two patches are the initial ones in the series of > LPC32xx device driver changes, which move LPC32xx board specific > options from include/configs/* to build system and board configs. > > Vladimir Zapolskiy (2): > arm: lpc32xx: add CONFIG_ARCH_LPC32XX build option > Makefile: add LPC32xx precondition for building platform images > > Makefile| 2 ++ > arch/arm/Kconfig| 24 > arch/arm/cpu/arm926ejs/lpc32xx/Kconfig | 20 > board/timll/devkit3250/Kconfig | 3 --- > board/work-microwave/work_92105/Kconfig | 3 --- > configs/devkit3250_defconfig| 6 +- > configs/work_92105_defconfig| 11 --- > 7 files changed, 39 insertions(+), 30 deletions(-) > create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/Kconfig > I kindly ask you to apply these 2 patches, because I have 30+ changes in my queue which depend on these ones. I've also added support of NXP LPC18xx/LPC43xx (ARMv7-M) to U-Boot, so it might be desired to add an lpc project to get merges faster. Thank you in advance. -- Best wishes, Vladimir ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Errors when starting sandbox
Hi Joe, On 1 October 2018 at 16:01, Joe Hershberger wrote: > > On Mon, Oct 1, 2018 at 4:27 PM, Simon Glass wrote: > > Hi Joe, > > > > On 1 October 2018 at 15:14, Joe Hershberger wrote: > >> > >> Hi Simon, > >> > >> On Mon, Oct 1, 2018 at 12:32 PM, Simon Glass wrote: > >> > Hi Joe, > >> > > >> > When I start sandbox now I see these errors every time. It is possible > >> > to fix this? > >> > > >> > $ u-boot -D > >> > ... > >> > Warning: host_lo MAC addresses don't match: > >> > Address in ROM is ea:06:97:67:f4:b6 > >> > Address in environment is 00:00:11:22:33:44 > >> > > >> > Warning: host_eth0 MAC addresses don't match: > >> > Address in ROM is ea:06:97:67:f4:b6 > >> > Address in environment is 00:00:11:22:33:45 > >> > > >> > Warning: host_enp0s31f6 using MAC address from ROM > >> > > >> > Warning: host_eth6 MAC addresses don't match: > >> > Address in ROM is ea:06:97:67:f4:b6 > >> > Address in environment is 00:00:11:22:33:46 > >> > > >> > Warning: host_docker_gwbridge using MAC address from ROM > >> > > >> > Warning: host_docker0 MAC addresses don't match: > >> > Address in ROM is ca:07:52:28:25:66 > >> > Address in environment is 00:00:11:22:33:47 > >> > > >> > Warning: host_veth1f6bcd2 using MAC address from ROM > >> > >> These are warnings based on commit b96ced9cdb6 (sandbox: eth-raw: Make > >> random MAC addresses available to eth-raw). Because we don't know the > >> number of interfaces that exist on the given host when we write the > >> sandbox.dts, we override the MAC addresses with random ones. In the > >> normal case (real hardware), we would warn, since the hardware should > >> know its interfaces. > >> > >> Do you have a proposed different approach? I don't like the idea of > >> adding sandbox checks in the core code that prints this warning, and > >> it also doesn't seem like a great idea to add a hook that doesn't warn > >> just for sandbox. > >> > >> I'm happy to work on this, but I didn't address it at the time because > >> I didn't see a clear way to do it that didn't degrade the code in > >> order to remove warnings in sandbox. > > > > Can we make it so that the addresses do actually match in sandbox? > > The issue is that the eth(N)?addr lives in the default env and the > interfaces are discovered by drivers/net/sandbox-raw-bus.c. Currently > we make sure we don't "run out" of addresses defined in the env by > using a randomly generated one instead. Unfortunately, the env is > shared with all modes of sandbox, so while the addresses are not > shared when running sandbox.dts, they are required when running > test.dts. > > Thoughts? > How about a device-tree property that is only present in the test DT, to control the behaviour? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 20/34] imx8: cpu: add function for reading FEC MAC from fuse
Hi Anatolij,
> -Original Message-
> From: Anatolij Gustschin [mailto:ag...@denx.de]
> Sent: 2018年10月18日 20:28
> To: u-boot@lists.denx.de; Peng Fan ; sba...@denx.de
> Subject: [PATCH v6 20/34] imx8: cpu: add function for reading FEC MAC from
> fuse
>
> FEC driver requires imx_get_mac_from_fuse(). Add it in preparation for ENETx
> support.
>
> Signed-off-by: Anatolij Gustschin
> Cc: Stefano Babic
> ---
> arch/arm/mach-imx/imx8/cpu.c | 38
>
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
> index d80b4b175d..da34a94a23 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -543,3 +543,41 @@ u64 get_page_table_size(void)
> return size;
> }
> #endif
> +
> +#define FUSE_MAC0_WORD0 708
> +#define FUSE_MAC0_WORD1 709
> +#define FUSE_MAC1_WORD0 710
> +#define FUSE_MAC1_WORD1 711
> +
> +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) {
> + u32 word[2], val[2] = {};
> + int i, ret;
> +
> + if (dev_id == 0) {
> + word[0] = FUSE_MAC0_WORD0;
> + word[1] = FUSE_MAC0_WORD1;
> + } else {
> + word[0] = FUSE_MAC1_WORD0;
> + word[1] = FUSE_MAC1_WORD1;
> + }
> +
> + for (i = 0; i < 2; i++) {
> + ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
> + if (ret < 0)
> + goto err;
> + }
> +
> + mac[0] = val[0];
> + mac[1] = val[0] >> 8;
> + mac[2] = val[0] >> 16;
> + mac[3] = val[0] >> 24;
> + mac[4] = val[1];
> + mac[5] = val[1] >> 8;
> +
> + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
> + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
> + return;
> +err:
> + printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); }
Reviewed-by: Peng Fan
Thanks,
Peng.
> --
> 2.17.1
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Re: [U-Boot] [PATCH v6 21/34] imx8: cpu: add uclass based CPU driver
Hi Anatolij,
> -Original Message-
> From: Anatolij Gustschin [mailto:ag...@denx.de]
> Sent: 2018年10月18日 20:28
> To: u-boot@lists.denx.de; Peng Fan ; sba...@denx.de
> Subject: [PATCH v6 21/34] imx8: cpu: add uclass based CPU driver
>
> print_cpuinfo() in board init code requires uclass CPU driver, add it to be
> able to
> display CPU info when CONFIG_DISPLAY_CPUINFO option is enabled. CPU node
> in DT will have to include 'clocks'
> and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo() to work as
> expected. The driver outputs info for i.MX8QXP Rev A and Rev B CPUs.
>
> Signed-off-by: Anatolij Gustschin
> Cc: Stefano Babic
> ---
> arch/arm/include/asm/arch-imx/cpu.h | 5 +-
> arch/arm/mach-imx/imx8/cpu.c| 215 ++--
> 2 files changed, 142 insertions(+), 78 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-imx/cpu.h
> b/arch/arm/include/asm/arch-imx/cpu.h
> index cf6303c3f5..2af79659d2 100644
> --- a/arch/arm/include/asm/arch-imx/cpu.h
> +++ b/arch/arm/include/asm/arch-imx/cpu.h
> @@ -25,6 +25,7 @@
> #define MXC_CPU_MX7S 0x71 /* dummy ID */
> #define MXC_CPU_MX7D 0x72
> #define MXC_CPU_MX8MQ0x82
> +#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
> #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
> #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
> #define MXC_CPU_VF6100xF6 /* dummy ID */
> @@ -43,8 +44,8 @@
> #define CHIP_REV_2_50x25
> #define CHIP_REV_3_00x30
>
> -#define CHIP_REV_A 0x0
> -#define CHIP_REV_B 0x1
> +#define CHIP_REV_A 0x0
> +#define CHIP_REV_B 0x1
>
> #define BOARD_REV_1_0 0x0
> #define BOARD_REV_2_0 0x1
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
> index da34a94a23..f093f34ca5 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -5,6 +5,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -19,82 +20,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -u32 get_cpu_rev(void)
> -{
> - u32 id = 0, rev = 0;
> - int ret;
> -
> - ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
> - if (ret)
> - return 0;
> -
> - rev = (id >> 5) & 0xf;
> - id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
> -
> - return (id << 12) | rev;
> -}
> -
> -#ifdef CONFIG_DISPLAY_CPUINFO
> -const char *get_imx8_type(u32 imxtype)
> -{
> - switch (imxtype) {
> - case MXC_CPU_IMX8QXP:
> - return "8QXP";
> - default:
> - return "??";
> - }
> -}
> -
> -const char *get_imx8_rev(u32 rev)
> -{
> - switch (rev) {
> - case CHIP_REV_A:
> - return "A";
> - case CHIP_REV_B:
> - return "B";
> - default:
> - return "?";
> - }
> -}
> -
> -const char *get_core_name(void)
> -{
> - if (is_cortex_a35())
> - return "A35";
> - else
> - return "?";
> -}
> -
> -int print_cpuinfo(void)
> -{
> - struct udevice *dev;
> - struct clk cpu_clk;
> - int ret;
> -
> - ret = uclass_get_device(UCLASS_CPU, 0, &dev);
> - if (ret)
> - return 0;
> -
> - ret = clk_get_by_index(dev, 0, &cpu_clk);
> - if (ret) {
> - dev_err(dev, "failed to clk\n");
> - return 0;
> - }
> -
> - u32 cpurev;
> -
> - cpurev = get_cpu_rev();
> -
> - printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n",
> -get_imx8_type((cpurev & 0xFF000) >> 12),
> -get_imx8_rev((cpurev & 0xFFF)),
> -get_core_name(),
> -clk_get_rate(&cpu_clk) / 100);
> -
> - return 0;
> -}
> -#endif
> -
> #define BT_PASSOVER_TAG 0x504F
> struct pass_over_info_t *get_pass_over_info(void) { @@ -581,3 +506,141
> @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> err:
> printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); }
> +
> +#if CONFIG_IS_ENABLED(CPU)
> +struct cpu_imx_platdata {
> + const char *name;
> + const char *rev;
> + const char *type;
> + u32 cpurev;
> + u32 freq_mhz;
> +};
> +
> +u32 get_cpu_rev(void)
> +{
> + u32 id = 0, rev = 0;
> + int ret;
> +
> + ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
> + if (ret)
> + return 0;
> +
> + rev = (id >> 5) & 0xf;
> + id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
> +
> + return (id << 12) | rev;
> +}
> +
> +const char *get_imx8_type(u32 imxtype)
> +{
> + switch (imxtype) {
> + case MXC_CPU_IMX8QXP:
> + case MXC_CPU_IMX8QXP_A0:
> + return "QXP";
> + default:
> + return "??";
> + }
> +}
> +
> +const char *get_imx8_rev(u32 rev)
> +{
> + switch (rev) {
> + case CHIP_REV_A:
> + return "A";
> + case CHIP_REV_B:
> +
Re: [U-Boot] [PATCH v3 5/9] pinctrl: stm32: Add get_pins_count() ops
On 9 October 2018 at 07:31, Patrice Chotard wrote: > Add get_pins_count ops to obtain the number of pins > owns by a pin-controller. > On STM32 SoCs bindings, each pin-controller owns > several gpio banks. Each GPIO bank can own up to 16 pins. > > To obtain the total pins count, walk through each sub-nodes > (ie GPIO banks) and sum each GPIO banks pins number. For that > in probe() we build a list with each GPIO device reference found. > This list will also be used with future get_pin_muxing and get_pin_name > ops to speed up and optimize walk through all GPIO banks. > > As this code is common to all STM32 SoCs, this code is put > under SPL_BUILD compilation flag to avoid to increase SPL code size > for STM32F7 which is limited to 32Ko. > > Signed-off-by: Patrice Chotard > --- > > Changes in v3: None > Changes in v2: None > > drivers/pinctrl/pinctrl_stm32.c | 94 > ++--- > 1 file changed, 89 insertions(+), 5 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 6/9] pinctrl: stm32: Add get_pin_name() ops
On 9 October 2018 at 07:31, Patrice Chotard wrote: > Add get_pin_name ops to obtain a pin name given a > pin index of a specified pin-controller. > > Signed-off-by: Patrice Chotard > --- > > Changes in v3: None > Changes in v2: None > > drivers/pinctrl/pinctrl_stm32.c | 47 > + > 1 file changed, 47 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] syscon: reset node list syscon_list after relocation
Hi Patrick, On 12 October 2018 at 09:26, Patrick Delaunay wrote: > Reset the list head after the reallocation because the list syscon_list > use allocated pointer and they are no more valid. > This patch avoid issue (crash) when syscon_node_to_regmap() is called > before and after reallocation. > > Signed-off-by: Patrick Delaunay > --- > Hi > > This patch correct a crash see on v2018.11-rc1 with my board stm32mp1 > for the command "reset". > > The crash is a side effect of 2 patches > 1f6ca3f42f6edf143473159297f4c515b1cf36f6 > sysreset: syscon: update regmap access to syscon > > 23471aed5c33e104d6fa64575932577618543bec > board_f: Add reset status printing > > With the first patch the syscon_node_to_regmap() is called > each time that the class sysreset_syscon is probed. > > => in v2018.09 probe is done only when reset is requested > > NB: for stm32mp1, the node rcc_reboot in tagged pre-relocated to > support reset in pre-reloc phases (allow panic). > > With the second patch, U-Boot probes all the sysreset uclass in preloc > phase to allow to print the reset status, and the list is initialized > in board_f / pre-reloc: > > -> print_resetinfo > --> uclass_first_device_err(UCLASS_SYSRESET, &dev); > ---> syscon_reboot_probe() > > syscon_node_to_regmap(node) > -> of_syscon_register() > ---> list_add_tail(&syscon->list, &syscon_list); > > During relocation, the content of syscon_list (static) is updated > but the list use pointers allocated by malloc in pre-reloc phasis > > And when I execute the reset command > -> do_reset() > --> reset_cpu() > ---> sysreset_walk_halt(SYSRESET_COLD); > > loop on device UCLASS_SYSRESET > -> syscon_reboot_probe() > --> syscon_node_to_regmap(node) > ---> list_for_each_entry(entry, &syscon_list, list) We have a similar issue with the timer - we set gd->timer to NULL in initr_dm(). I am not 100% what is going on here, but using pre-reloc devices (i.e. which were set up before relocation) after relocation is bad. We need to avoid that. The syscon_list struct should be in the syscon uclass, i.e. declared as uclass priv data in UCLASS_DRIVER(syscon). We should not have this as free-standard static data. That's not how DM works... So I guess Masahiro's patch needs to be adjusted. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
