On Wed, 17 Oct 2018 22:56:47 -0700
Vasily Khoruzhick <anars...@gmail.com> wrote:
> A64 and H6 support automatic delay calibration and Linux driver uses
> it instead of hardcoded delays. Add support for it to u-boot driver.
>
> Fixes eMMC instability on Pinebook
>
> Signed-off-by: Vasily Khoruzhick <anars...@gmail.com>
> Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
> Tested-by: Maxime Ripard <maxime.rip...@bootlin.com>
> Cc: Vagrant Cascadian <vagr...@debian.org>
Reviewed-by: Andre Przywara <andre.przyw...@arm.com>
Cheers,
Andre
> ---
> arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++-
> drivers/mmc/sunxi_mmc.c | 21 ++++++++++++++++++++-
> 2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
> b/arch/arm/include/asm/arch-sunxi/mmc.h index d98c53faaa..f2deafddd2
> 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -46,7 +46,9 @@ struct sunxi_mmc {
> u32 cbda; /* 0x94 */
> u32 res2[26];
> #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
> - u32 res3[64];
> + u32 res3[17];
> + u32 samp_dl;
> + u32 res4[46];
> #endif
> u32 fifo; /* 0x100 / 0x200 FIFO access
> address */ };
> @@ -130,5 +132,7 @@ struct sunxi_mmc {
> #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
> #define SUNXI_MMC_COMMON_RESET (1 << 18)
>
> +#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
> +
> struct mmc *sunxi_mmc_init(int sdc_no);
> #endif /* _SUNXI_MMC_H */
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 39f15eb423..147eb9b4d5 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
> *priv, unsigned int hz) {
> unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
> bool new_mode = false;
> + bool calibrate = false;
> u32 val = 0;
>
> if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) &&
> (priv->mmc_no == 2)) new_mode = true;
>
> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
> + calibrate = true;
> +#endif
> +
> /*
> * The MMC clock has an extra /2 post-divider when operating
> in the new
> * mode.
> @@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv
> *priv, unsigned int hz) val = CCM_MMC_CTRL_MODE_SEL_NEW;
> setbits_le32(&priv->reg->ntsr,
> SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif
> - } else {
> + } else if (!calibrate) {
> + /*
> + * Use hardcoded delay values if controller doesn't
> support
> + * calibration
> + */
> val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
> CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
> }
> @@ -228,6 +237,16 @@ static int mmc_config_clock(struct
> sunxi_mmc_priv *priv, struct mmc *mmc) rval &=
> ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr);
>
> +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
> + /* A64 supports calibration of delays on MMC controller and
> we
> + * have to set delay of zero before starting calibration.
> + * Allwinner BSP driver sets a delay only in the case of
> + * using HS400 which is not supported by mainline U-Boot or
> + * Linux at the moment
> + */
> + writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
> +#endif
> +
> /* Re-enable Clock */
> rval |= SUNXI_MMC_CLK_ENABLE;
> writel(rval, &priv->reg->clkcr);
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
