[U-Boot] [PATCH 02/14] mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init
This fixes an issue which has been noticed on the Gardena board, with the watchdog enabled, where the watdchdog reset (after a system hang) did result in reporting of 2.9 GiB and a hang after this. With this patch applied the memory controller is correctly reset and initialized again even after a watchdog reset. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/mach-mt7620/lowlevel_init.S | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S index 1a50f160fe..aa707e0de6 100644 --- a/arch/mips/mach-mt7620/lowlevel_init.S +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -108,6 +108,12 @@ CPLL_READY: sw t3, 0(t0) CPLL_DONE: + /* Reset MC */ + lw t2, 0x34(s0) + ori t2, BIT(10) + sw t2, 0x34(s0) + nop + /* * SDR and DDR initialization: delay 200us */ -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/14] mips: mt76xx: Enable SYS_MIPS_CACHE_INIT_RAM_LOAD for cache init
Using CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD should ensure that the cache is initialized correctly (parity etc). Even though some issues are still seen on the linkit and gardena MT7688 platforms, which could be a result of a non-optimal cache configuration / setup. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/mach-mt7620/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig index 13a7bd2cc0..e42d918ba0 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mt7620/Kconfig @@ -13,6 +13,7 @@ choice config SOC_MT7620 bool "MT7620/8" select MIPS_L1_CACHE_SHIFT_5 + select SYS_MIPS_CACHE_INIT_RAM_LOAD help This supports MediaTek MIPS MT7620 family. -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/14] mips: mt76xx: Add GPIO DT nodes to mt7628a.dtsi
Add the GPIO DT nodes to the DTS file.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/dts/mt7628a.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index effb36681f..8da2ca3e4d 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -71,6 +71,38 @@
reg = <0x300 0x100>;
};
+ gpio@600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
+ reg = <0x600 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <6>;
+
+ gpio0: bank@0 {
+ reg = <0>;
+ compatible = "mtk,mt7621-gpio-bank";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: bank@1 {
+ reg = <1>;
+ compatible = "mtk,mt7621-gpio-bank";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: bank@2 {
+ reg = <2>;
+ compatible = "mtk,mt7621-gpio-bank";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x40>;
--
2.19.1
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[U-Boot] [PATCH 08/14] mips: mt76xx: Enable watchdog support
This patch enables and starts the watchdog on the MT7620 platform.
Currently the WD timeout is configured to 60 seconds.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/Kconfig | 1 +
arch/mips/mach-mt7620/cpu.c | 40 +
2 files changed, 41 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0aa23981d4..54a483075f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -79,6 +79,7 @@ config ARCH_MT7620
select DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
+ select ARCH_MISC_INIT if WATCHDOG
select MIPS_TUNE_24KC
select OF_CONTROL
select ROM_EXCEPTION_VECTORS
diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c
index 457f09f32c..87cc973b75 100644
--- a/arch/mips/mach-mt7620/cpu.c
+++ b/arch/mips/mach-mt7620/cpu.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -67,3 +68,42 @@ int print_cpuinfo(void)
return 0;
}
+
+#ifdef CONFIG_WATCHDOG
+static struct udevice *watchdog_dev;
+
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ static ulong next_reset;
+ ulong now;
+
+ if (!watchdog_dev)
+ return;
+
+ now = get_timer(0);
+
+ /* Do not reset the watchdog too often */
+ if (now > next_reset) {
+ next_reset = now + 1000;/* reset every 1000ms */
+ wdt_reset(watchdog_dev);
+ }
+}
+
+int arch_misc_init(void)
+{
+ /* Init watchdog */
+ if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
+ debug("Watchdog: Not found by seq!\n");
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ puts("Watchdog: Not found!\n");
+ return 0;
+ }
+ }
+
+ wdt_start(watchdog_dev, 6, 0); /* 60 seconds */
+ printf("Watchdog: Started\n");
+
+ return 0;
+}
+#endif
--
2.19.1
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[U-Boot] [PATCH 09/14] mips: mt76xx: gardena-smart-gateway: Configure GPIOs (digital vs analog)
Configure digital vs analog GPIOs as needed on this board.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
board/gardena/smart-gateway-mt7688/board.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/gardena/smart-gateway-mt7688/board.c
b/board/gardena/smart-gateway-mt7688/board.c
index 5ff546f505..838dfc205b 100644
--- a/board/gardena/smart-gateway-mt7688/board.c
+++ b/board/gardena/smart-gateway-mt7688/board.c
@@ -4,14 +4,17 @@
*/
#include
-#include
+#include
+
+#define MT76XX_AGPIO_CFG 0x103c
int board_early_init_f(void)
{
- /*
-* Nothing to be done here for this board (no UART setup etc)
-* right now. We might need some pin muxing, so lets keep this
-* function for now.
-*/
+ void __iomem *gpio_mode;
+
+ /* Configure digital vs analog GPIOs */
+ gpio_mode = ioremap_nocache(MT76XX_AGPIO_CFG, 0x100);
+ iowrite32(0x00fe01ff, gpio_mode);
+
return 0;
}
--
2.19.1
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[U-Boot] [PATCH 14/14] mips: mt76xx: linkit-smart-7688: Misc updates to dts/config/defconfig
These misc updates include the following changes:
- Change baudrate from 57600 to 115200
- Enable MIPS_BOOT_CMDLINE_LEGACY
- Enable FIT support
- Enable ethernet support
- Enable SPI support
- Enable GPIO support
- Change max image size from 0x4 to 0x8
A note about the baudrate change:
The original Mediatek U-Boot version used 57600 baud. Lets move to a
more common and faster speed of 115200 baud. And remove the "console="
property from the DT as its not needed.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/dts/linkit-smart-7688.dts | 1 -
configs/linkit-smart-7688-ram_defconfig | 22 +++---
configs/linkit-smart-7688_defconfig | 22 +++---
include/configs/linkit-smart-7688.h | 2 +-
4 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/mips/dts/linkit-smart-7688.dts
b/arch/mips/dts/linkit-smart-7688.dts
index df4bf907c6..c9db136f30 100644
--- a/arch/mips/dts/linkit-smart-7688.dts
+++ b/arch/mips/dts/linkit-smart-7688.dts
@@ -22,7 +22,6 @@
};
chosen {
- bootargs = "console=ttyS0,57600";
stdout-path = &uart2;
};
};
diff --git a/configs/linkit-smart-7688-ram_defconfig
b/configs/linkit-smart-7688-ram_defconfig
index 77cd1c1575..bca7449971 100644
--- a/configs/linkit-smart-7688-ram_defconfig
+++ b/configs/linkit-smart-7688-ram_defconfig
@@ -1,35 +1,38 @@
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x8001
CONFIG_ARCH_MT7620=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+CONFIG_BOARD_LINKIT_SMART_7688=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
-# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
-# CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_CLK=y
-CONFIG_CPU=y
-CONFIG_DM_GPIO=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
@@ -40,12 +43,17 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_FIXED=y
+CONFIG_MT76XX_ETH=y
CONFIG_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-CONFIG_BAUDRATE=57600
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
CONFIG_SYSRESET_SYSCON=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
diff --git a/configs/linkit-smart-7688_defconfig
b/configs/linkit-smart-7688_defconfig
index 62cdda1e0a..4435b06fba 100644
--- a/configs/linkit-smart-7688_defconfig
+++ b/configs/linkit-smart-7688_defconfig
@@ -1,39 +1,42 @@
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9c00
CONFIG_ARCH_MT7620=y
+CONFIG_BOARD_LINKIT_SMART_7688=y
CONFIG_BOOT_ROM=y
CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
-# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
-# CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_CLK=y
-CONFIG_CPU=y
-CONFIG_DM_GPIO=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
@@ -44,12 +47,17 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_FIXED=y
+CONFIG_MT76XX_ETH=y
CONFIG_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-CONFIG_BAUDRATE=57600
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
CONFIG_SYSRESET_SYSCON=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
diff --git a/include/configs/linkit-smart-7688.h
b/include/configs/linkit-smart-7688.h
index 78ef
[U-Boot] [PATCH 01/14] mips: Add in_le32(), out_le32() etc IO accessor functions
in_le32() and out_le32() are needed for the bootcounter support. So lets implement these accessor functions for MIPS as well. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/include/asm/io.h | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 957442effd..a750f6c0e4 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -391,6 +391,27 @@ __BUILDIO(q, u64) #define readq readq #define writeq writeq +/* in_le32(), out_le32() and friends */ +#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le64(a,v) out_arch(q,le64,a,v) +#define out_le32(a,v) out_arch(l,le32,a,v) +#define out_le16(a,v) out_arch(w,le16,a,v) + +#define in_le64(a) in_arch(q,le64,a) +#define in_le32(a) in_arch(l,le32,a) +#define in_le16(a) in_arch(w,le16,a) + +#define out_be32(a,v) out_arch(l,be32,a,v) +#define out_be16(a,v) out_arch(w,be16,a,v) + +#define in_be32(a) in_arch(l,be32,a) +#define in_be16(a) in_arch(w,be16,a) + +#define out_8(a,v) __raw_writeb(v,a) +#define in_8(a)__raw_readb(a) + #define __BUILD_MEMORY_STRING(bwlq, type) \ \ static inline void writes##bwlq(volatile void __iomem *mem,\ -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 12/14] mips: mt76xx: gardena-smart-gateway: Misc updates to dts/config/defconfig
These misc updates include the following changes:
- Change baudrate from 57600 to 115200
- Enable MIPS_BOOT_CMDLINE_LEGACY
- Enable FIT support
- Enable ethernet support
- Enable SPI NOR and NAND support
- Change MTD_UBI_BEB_LIMIT to 22
- Enable MTD Support
- Enable GPIO support
- Enable watchdog support
- Enable bootcounter support
- Enable version variable
- Change max image size from 0x8 to 0xa
- Change SYS_MALLOC_LEN to 16MiB (because of UBI/UBIFS)
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
.../mips/dts/gardena-smart-gateway-mt7688.dts | 1 -
...gardena-smart-gateway-mt7688-ram_defconfig | 36 ++-
.../gardena-smart-gateway-mt7688_defconfig| 36 ++-
.../configs/gardena-smart-gateway-mt7688.h| 4 +--
4 files changed, 58 insertions(+), 19 deletions(-)
diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
index ef8a9612fd..d8d88686bb 100644
--- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
+++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
@@ -81,7 +81,6 @@
};
chosen {
- bootargs = "console=ttyS0,57600";
stdout-path = &uart0;
};
};
diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig
b/configs/gardena-smart-gateway-mt7688-ram_defconfig
index 0e2f158518..5d1a84fb3f 100644
--- a/configs/gardena-smart-gateway-mt7688-ram_defconfig
+++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig
@@ -1,55 +1,75 @@
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x8001
CONFIG_ARCH_MT7620=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
-# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
-# CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(nand)"
CONFIG_CMD_UBI=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xb06c
CONFIG_CLK=y
-CONFIG_CPU=y
-CONFIG_DM_GPIO=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_BEB_LIMIT=22
+CONFIG_PHYLIB=y
+CONFIG_PHY_FIXED=y
+CONFIG_MT76XX_ETH=y
CONFIG_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
-CONFIG_BAUDRATE=57600
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
CONFIG_SYSRESET_SYSCON=y
+CONFIG_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_WDT_MT7621=y
+CONFIG_LZMA=y
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig
b/configs/gardena-smart-gateway-mt7688_defconfig
index 1213227758..7c930f0cd9 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -4,55 +4,75 @@ CONFIG_ARCH_MT7620=y
CONFIG_BOOT_ROM=y
CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
-# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
-# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
-# CONFIG_CMD_NET is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)"
+CONFIG_MTDPARTS_DEF
[U-Boot] [PATCH 13/14] mips: mt76xx: linkit-smart-7688: Use ioremap_nocache to get address
Use the correct function to get the uncached address to access the SoC
registers.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
board/seeed/linkit-smart-7688/board.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/board/seeed/linkit-smart-7688/board.c
b/board/seeed/linkit-smart-7688/board.c
index a28abc00b8..d3d3d50c2c 100644
--- a/board/seeed/linkit-smart-7688/board.c
+++ b/board/seeed/linkit-smart-7688/board.c
@@ -6,12 +6,15 @@
#include
#include
-#define MT76XX_GPIO1_MODE 0xb060
+#define MT76XX_GPIO1_MODE 0x1060
void board_debug_uart_init(void)
{
+ void __iomem *gpio_mode;
+
/* Select UART2 mode instead of GPIO mode (default) */
- clrbits_le32((void __iomem *)MT76XX_GPIO1_MODE, GENMASK(27, 26));
+ gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100);
+ clrbits_le32(gpio_mode, GENMASK(27, 26));
}
int board_early_init_f(void)
--
2.19.1
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[U-Boot] [PATCH 10/14] mips: mt76xx: gardena-smart-gateway: Add LEDs to dts
Add the available LEDs to the DTS file so that they can be used.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
.../mips/dts/gardena-smart-gateway-mt7688.dts | 59 +++
1 file changed, 59 insertions(+)
diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
index ee99c3d17c..ef8a9612fd 100644
--- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts
+++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "mt7628a.dtsi"
+#include
/ {
compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
@@ -21,6 +22,64 @@
reg = <0x0 0x0800>;
};
+ leds {
+ compatible = "gpio-leds";
+
+ power_blue {
+ label = "smartgw:power:blue";
+ gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ power_green {
+ label = "smartgw:power:green";
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ power_red {
+ label = "smartgw:power:red";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_blue {
+ label = "smartgw:radio:blue";
+ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_green {
+ label = "smartgw:radio:green";
+ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_red {
+ label = "smartgw:radio:red";
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_blue {
+ label = "smartgw:internet:blue";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_green {
+ label = "smartgw:internet:green";
+ gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_red {
+ label = "smartgw:internet:red";
+ gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
chosen {
bootargs = "console=ttyS0,57600";
stdout-path = &uart0;
--
2.19.1
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[U-Boot] [PATCH 06/14] mips: mt76xx: Add watchdog DT node to mt7628a.dtsi
Add the watchdog DT node to the DTS file.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/dts/mt7628a.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index 8da2ca3e4d..70e34cfdbc 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -48,6 +48,17 @@
mask = <0x1>;
};
+ watchdog: watchdog@100 {
+ compatible = "ralink,mt7628a-wdt",
"mediatek,mt7621-wdt";
+ reg = <0x100 0x30>;
+
+ resets = <&resetc 8>;
+ reset-names = "wdt";
+
+ interrupt-parent = <&intc>;
+ interrupts = <24>;
+ };
+
intc: interrupt-controller@200 {
compatible = "ralink,rt2880-intc";
reg = <0x200 0x100>;
--
2.19.1
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[U-Boot] [PATCH 11/14] mips: mt76xx: gardena-smart-gateway: Add board_late_init() to set LED def state
This is needed to set the LEDs automatically to a default state, as
configured in the dts.
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
---
arch/mips/mach-mt7620/Kconfig | 1 +
board/gardena/smart-gateway-mt7688/board.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig
index e42d918ba0..6f6952afd0 100644
--- a/arch/mips/mach-mt7620/Kconfig
+++ b/arch/mips/mach-mt7620/Kconfig
@@ -25,6 +25,7 @@ choice
config BOARD_GARDENA_SMART_GATEWAY_MT7688
bool "Gardena Smart Gateway"
depends on SOC_MT7620
+ select BOARD_LATE_INIT
select SUPPORTS_BOOT_RAM
help
Gardena Smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
diff --git a/board/gardena/smart-gateway-mt7688/board.c
b/board/gardena/smart-gateway-mt7688/board.c
index 838dfc205b..3a1838e44a 100644
--- a/board/gardena/smart-gateway-mt7688/board.c
+++ b/board/gardena/smart-gateway-mt7688/board.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#define MT76XX_AGPIO_CFG 0x103c
@@ -18,3 +19,11 @@ int board_early_init_f(void)
return 0;
}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
--
2.19.1
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[U-Boot] [PATCH 07/14] mips: mt76xx: Kconfig: Add ethernet and GPIO support
Imply DM_ETH and DM_GPIO for ARCH_MT7620, as this platform now supports ethernet and GPIO as well. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- arch/mips/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 071dea04ec..0aa23981d4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -74,6 +74,8 @@ config ARCH_MT7620 imply CMD_DM select DISPLAY_CPUINFO select DM + imply DM_ETH + imply DM_GPIO select DM_SERIAL imply DM_SPI imply DM_SPI_FLASH -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: socfpga: fix SPL booting from fpga OnChip RAM
On Tue, Oct 9, 2018 at 4:49 AM Marek Vasut wrote:
>
> On 10/08/2018 08:26 PM, Simon Goldschmidt wrote:
> > This patch prevents disabling the FPGA bridges when
> > SPL or U-Boot is executed from FPGA onchip RAM.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > Changes in v2:
> > - use less ifdefs and more C code for address checks
> > (but this gives a checkpatch warning because of comparing two
> > upper case constants)
> > - changed comments
> >
> > This patch depends on:
> > - CONFIG_SPL_TEXT_BASE needs to be set to 0xC000
> > ideally this is done by moving SPL_TEXT_BASE to Kconfig:
> > https://patchwork.ozlabs.org/patch/976918/
> > ---
> > arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 1 +
> > arch/arm/mach-socfpga/misc_gen5.c | 13 -
> > arch/arm/mach-socfpga/spl_gen5.c | 10 +++---
> > 3 files changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > index bb9e3faa29..2725e9fcc3 100644
> > --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
> > @@ -6,6 +6,7 @@
> > #ifndef _SOCFPGA_BASE_ADDRS_H_
> > #define _SOCFPGA_BASE_ADDRS_H_
> >
> > +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc000
> > #define SOCFPGA_STM_ADDRESS 0xfc00
> > #define SOCFPGA_DAP_ADDRESS 0xff00
> > #define SOCFPGA_EMAC0_ADDRESS0xff70
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c
> > b/arch/arm/mach-socfpga/misc_gen5.c
> > index 429c3d6cd5..b35636b590 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -177,6 +177,8 @@ static void socfpga_nic301_slave_ns(void)
> >
> > void socfpga_sdram_remap_zero(void)
> > {
> > + u32 remap;
> > +
> > socfpga_nic301_slave_ns();
> >
> > /*
> > @@ -187,7 +189,16 @@ void socfpga_sdram_remap_zero(void)
> > setbits_le32(&scu_regs->sacr, 0xfff);
> >
> > /* Configure the L2 controller to make SDRAM start at 0 */
> > - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
> > + remap = 0x1; /* remap.mpuzero */
> > + if (CONFIG_SYS_TEXT_BASE >= SOCFPGA_FPGA_SLAVES_ADDRESS &&
> > + CONFIG_SYS_TEXT_BASE < SOCFPGA_STM_ADDRESS)
>
> We can detect where we're executing from at runtime, right ?
Sure, we can either read the 'pc' reg (are there predefined functions for this
in the U-Boot sources?) or take the address of this function. Which one do
you prefer?
Simon
> > + remap |= 0x8; /* remap.hps2fpga: keep fpga bridge enabled */
> > +#ifdef CONFIG_SPL_BUILD
> > + if (CONFIG_SPL_TEXT_BASE == SOCFPGA_FPGA_SLAVES_ADDRESS)
> > + remap |= 0x8; /* remap.hps2fpga: keep fpga bridge enabled */
> > +#endif
> > + writel(remap, &nic301_regs->remap);
> > +
> > writel(0x1, &pl310->pl310_addr_filter_start);
> > }
> >
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> > b/arch/arm/mach-socfpga/spl_gen5.c
> > index be318cc0d9..5c3995be13 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -92,8 +92,11 @@ void board_init_f(ulong dummy)
> >
> > /* Put everything into reset but L4WD0. */
> > socfpga_per_reset_all();
> > - /* Put FPGA bridges into reset too. */
> > - socfpga_bridges_reset(1);
> > +
> > + if (CONFIG_SPL_TEXT_BASE != SOCFPGA_FPGA_SLAVES_ADDRESS) {
> > + /* Put FPGA bridges into reset (unless booting from FPGA). */
> > + socfpga_bridges_reset(1);
> > + }
> >
> > socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> > socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> > @@ -163,5 +166,6 @@ void board_init_f(ulong dummy)
> > hang();
> > }
> >
> > - socfpga_bridges_reset(1);
> > + if (CONFIG_SPL_TEXT_BASE != SOCFPGA_FPGA_SLAVES_ADDRESS)
> > + socfpga_bridges_reset(1);
> > }
> >
>
>
> --
> Best regards,
> Marek Vasut
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[U-Boot] [PATCH] cmd: kgdb: Enable kgdb only for PPC
Only PPC supports this option that's why there should be proper dependency setup via Kconfig. Signed-off-by: Michal Simek --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 7ed3c9c3b30b..d66f710ad0f8 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1811,6 +1811,7 @@ config CMD_IRQ config CMD_KGDB bool "kgdb - Allow debugging of U-Boot with gdb" + depends on PPC help This enables a 'kgdb' command which allows gdb to connect to U-Boot over a serial link for debugging purposes. This allows -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] imx: mx7: fix potential overflow in imx_ddr_size()
From: Marcel Ziswiler The imx_ddr_size() function may overflow as it is possible to kind of over provision the DDR controller. Fix this by capping it to 2 GB which is the maximum allowed size as per reference manual. Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam --- Changes in v2: Added Fabio's reviewed-by. arch/arm/mach-imx/mx7/ddr.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index f19aeb8042..9713835bf2 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -196,5 +196,9 @@ unsigned int imx_ddr_size(void) if (field_val <= 29) bits++; + /* cap to max 2 GB */ + if (bits > 31) + bits = 31; + return 1 << bits; } -- 2.14.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] colibri_imx7: prime get_ram_size() using imx_ddr_size()
From: Fabio Estevam
Rather than passing a hardcoded maxsize to the generic get_ram_size()
function use the i.MX 7 specific imx_ddr_size() function, which extracts
the memory size at runtime by reading the DDR controller registers.
This is a purely cosmetic change as the generic get_ram_size() function
already took care of properly automatically detecting 256MB, 512MB or 1GB
modules.
Signed-off-by: Fabio Estevam
Signed-off-by: Marcel Ziswiler
Reviewed-by: Fabio Estevam
Acked-by: Stefan Agner
---
Changes in v2:
- Added Fabio's and Stefan's acked- resp. reviewed-bys.
board/toradex/colibri_imx7/colibri_imx7.c | 2 +-
include/configs/colibri_imx7.h| 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c
b/board/toradex/colibri_imx7/colibri_imx7.c
index 2b7591eb00..a4c99626b4 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
return 0;
}
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index ff6bd678cf..02849ba35f 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -14,7 +14,6 @@
#include "mx7_common.h"
/*#define CONFIG_DBG_MONITOR*/
-#define PHYS_SDRAM_SIZESZ_1G
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
--
2.14.4
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Re: [U-Boot] [PATCH 02/11] efi_loader: Initial HII protocols
On Fri, Oct 05, 2018 at 03:06:52PM +0200, Alexander Graf wrote: > On 10/05/2018 11:49 AM, Leif Lindholm wrote: > >On Fri, Oct 05, 2018 at 05:52:09PM +0900, AKASHI, Takahiro wrote: > 2. If a platform includes a configuration infrastructure, then the > EFI_HII_DATABASE_PROTOCOL, EFI_HII_STRING_PROTOCOL, > EFI_HII_CONFIG_ROUTING_PROTOCOL, and EFI_HII_CONFIG_ACCESS_PROTOCOL are > required. > >>>Do you think efi implementation on u-boot also wants those protocols? > >>>(Apparently, config access protocol can be optional for shell unless > >>>we want driver configuration?) > >>One more question: > >>Does u-boot support any kind of "UEFI driver"? > >>If yes, is there any good example? > >>If no, do you expect that it should be supported? > >I don't think full-on option ROMs with configuration menus are > >something we care about for EBBR-style implementations. > >What could be useful is things like shim - a simple driver installing > >a protocol that lets other applications running at boot-time access > >it. But I think that is already (mostly?) supported. > > That works, iPXE also works. But neither use HII from what I'm aware of. After all, do both of you say that we neither have to have Config Routing nor Config Access Protocol for now? > >If someone at a later date decides that they want to support option > >ROMs, basically using U-Boot for an SBBR implementation, that will > >come with additional work required for the menu support. And should be > >possible to configure out at build time for users who don't want it. > > Yeah, IMHO for HII we can treat it as a Shell.efi only wart we have to live > with, but implement as little as we can get away with. Do you have any specific idea about what is really missing in Leif's/Rob's HII patch? (My original question.) -Takahiro Akashi > > Alex > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] ZYNQ ZC706 Board
Hi sir, i am using ZYNQ ZC706 Board and i have downloaded u-boot(2016.7),uImage,root file system files from wiki.xilinx.com website downloaded and properly working all the things. But i am doing manually downloaded u-boot from github and ELDK-5.5.3 version taken export PATH=/opt/eldk-5.5.3/armv7a-hf/sysroots/i686-eldk-linux/usr/bin:/opt/eldk-5.5.3/armv7a-hf/sysroots/i686-eldk-linux/usr/bin/arm-linux-gnueabi:$PATH export ARCH=arm export CROSS_COMPILE=arm-linux-gnueabi- source /opt/eldk-5.5.3/armv7a-hf/environment-setup-* cd /home/ram/Desktop/arm/u-boot-2016.07/ make distclean make zynq_zc706_defconfig make all those above things used created u-boot.bin file but in serial monitor nothing displaying its problem with u-boot version (but both are same versions) or ELDK-5.5.3 is not creating properly -- Thanks & Regards, RamaChandra PC +918892147159. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] nand: atmel: Initialize pmecc smu with correct size
Hi Bin,
Bin Meng wrote on Mon, 8 Oct 2018 02:27:44 -0700:
> Currently in pmecc_get_sigma(), the code tries to clear the memory
> pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'.
> Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu)
> does not generate correct size to be cleared.
>
> In fact, GCC 8.1.0 reports a warning against it:
>
> error: division 'sizeof (int16_t * {aka short int *}) / sizeof (int16_t
> {aka short int})' does not compute the number of array elements
> [-Werror=sizeof-pointer-div]
>
> Fix it by using the correct size.
>
> Signed-off-by: Bin Meng
> ---
>
It's curious that the code of this driver differs a lot from its Linux
cousin. Anyway this looks fine by me. Maybe a Fixes tag would be
great.
Reviewed-by: Miquel Raynal
Thanks,
Miquèl
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Re: [U-Boot] [PATCH 2/2] pci: Change the first CFG read to Vendor ID in enumeration
Hi Simon and Bin, Do I need to send the standalone patch 1/2 in version 2? Thanks, Zhiqiang > -Original Message- > From: s...@google.com On Behalf Of Simon Glass > Sent: 2018年10月9日 11:41 > To: Bin Meng > Cc: Z.q. Hou ; U-Boot Mailing List > ; Christian Gmeiner ; > Tuomas Tynkkynen ; Bernhard Messerklinger > ; Masahiro Yamada > ; Mingkai Hu ; > M.h. Lian > Subject: Re: [PATCH 2/2] pci: Change the first CFG read to Vendor ID in > enumeration > > Hi Bin, > > On 8 October 2018 at 02:54, Bin Meng wrote: > > On Mon, Oct 8, 2018 at 4:36 PM Zhiqiang Hou > wrote: > >> > >> From: Hou Zhiqiang > >> > >> As the PCIe specification recommend reading the Vendor ID register to > >> determine if a Function is present, read the Vendor ID of a > >> non-existent Function must not result in system error, so we'd better > >> make the first CFG read to Vendor ID instead of Header Type register > >> in the PCIe enumeration. > >> > >> Signed-off-by: Hou Zhiqiang > >> --- > >> drivers/pci/pci.c | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > > > > Simon, do we need fix the non-DM version or adding new "capability" to > > the non-DM drivers? I guess the answer is no and we should set some > > deadline for PCI DM conversion too? > > We should not fix or add new features to non-DM PCI. No one should be using > it at this point. > > I agree about the deadline. Do you want to send a patch? > > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms
> -Original Message- > From: York Sun > Sent: Monday, October 8, 2018 10:11 PM > To: Rajesh Bhagat ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha > Subject: Re: [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms > > On 10/07/2018 03:21 AM, Rajesh Bhagat wrote: > > Includes changes in u-boot framework to support TF-A for NXP Chassis 2 > > platforms. A new defconfig is added namely ls*_ram_defconfig which will > > be used for all boot sources when TF-A is used. > > > > Tested on LS1043A, LS1046A and LS1012A platforms. > > > > Changes in v2: > > - Patch subject and description changes > > - Removed extra CONFIG_TFABOOT flag usage > > - Merged board specific TFA boot support patches > > - Checked compilation using buildman tool for each commit > > Please check again. I see compiling warning on ls2080aqds_nand > ls1046aqds_nand ls1043aqds_nand ls1043ardb_nand ls2080ardb_nand after > patch #2, seems to be fix by patch #4. You may squash these two patches. > Will take care in next version, will check for other warnings too. Regards, Rajesh Bhagat > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 21/33] armv8: ls1046ardb: Add TFABOOT support
> -Original Message- > From: York Sun > Sent: Monday, October 8, 2018 8:35 PM > To: Rajesh Bhagat ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Pankit Garg > > Subject: Re: [PATCH v2 21/33] armv8: ls1046ardb: Add TFABOOT support > > On 10/07/2018 03:22 AM, Rajesh Bhagat wrote: > > TFABOOT support includes: > > - ls1046ardb_tfa_defconfig to be loaded by trusted firmware > > - environment address and size changes for TFABOOT > > - FMAN address changes for TFABOOT > > - define BOOTCOMMAND for TFABOOT > > > > Signed-off-by: York Sun > > Signed-off-by: Pankit Garg > > Signed-off-by: Rajesh Bhagat > > --- > > Change in v2: > > - Merged ls1046ardb TFA boot support patches > > - Removed extra CONFIG_TFABOOT flag usage > > > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++-- > > board/freescale/ls1046ardb/ddr.c | 12 ++ > > configs/ls1046ardb_tfa_defconfig | 49 +++ > > include/configs/ls1046a_common.h | 12 ++ > > include/configs/ls1046ardb.h | 15 +++ > > 6 files changed, 101 insertions(+), 3 deletions(-) create mode > > 100644 configs/ls1046ardb_tfa_defconfig > Hi York, Thanks for the review. > Separate changes to add TFABOOT and put it into a standalone patch. > Leave the rest in this patch, and squash with patch #22. > Will take care in next version. > Do the same squash for every board, i.e. to keep on patch per board. > This reduces the total number of compiling tests. > Will take care in next version. > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/33] move data structure out of cpu.h
> -Original Message- > From: York Sun > Sent: Monday, October 8, 2018 8:08 PM > To: Rajesh Bhagat ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha > Subject: Re: [PATCH v2 01/33] move data structure out of cpu.h > > On 10/07/2018 03:21 AM, Rajesh Bhagat wrote: > > From: York Sun > > > > Move static definitions to cpu.c file, as it doesn't allow the cpu.h > > file to be included in multiple c files. > > > > Signed-off-by: York Sun > > --- > > Change in v2: None > > > > Rajesh, > > Did you send your patch set twice? I received two copies. The first one has > Message-Id: <20181007095929.17876-2-rajesh.bha...@nxp.com>, sent on > 7 Oct 2018 15:28:57 +0530. The second one has Message-Id: > <20181007102131.19159-2-rajesh.bha...@nxp.com>, sent on 7 Oct 2018 > 15:50:59 +0530. You also sent two copies of your v1 patch. Please do not send > more than one. If some error happened and you have to send them again, > make sure you put "resend" in the subject to be easily identified. > Hi York, I faced some issue in sending patch, will prefix the subject with RESEND in case same issue occurs next time. Regards, Rajesh Bhagat > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 10/33] armv8: layerscape: remove EL3 specific erratas for TFABOOT
> -Original Message- > From: York Sun > Sent: Monday, October 8, 2018 8:19 PM > To: Rajesh Bhagat ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha > Subject: Re: [PATCH v2 10/33] armv8: layerscape: remove EL3 specific erratas > for TFABOOT > > On 10/07/2018 03:21 AM, Rajesh Bhagat wrote: > > Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. > > > > ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, > SYS_FSL_ERRATUM_A008511, > > SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, > > SYS_FSL_ERRATUM_A009803 SYS_FSL_ERRATUM_A009942, > > SYS_FSL_ERRATUM_A010165 > > > > Signed-off-by: Rajesh Bhagat > > --- > > Change in v2: None > > > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 > > +++ > > 1 file changed, 12 insertions(+), 12 deletions(-) > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > index f2111fadc0..1b84da5f66 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > @@ -1,7 +1,7 @@ > > config ARCH_LS1012A > > bool > > select ARMV8_SET_SMPEN > > - select ARM_ERRATA_855873 > > + select ARM_ERRATA_855873 if !TFABOOT > > select FSL_LSCH2 > > select SYS_FSL_SRDS_1 > > select SYS_HAS_SERDES > > @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A > > bool > > select ARMV8_SET_SMPEN > > - select ARM_ERRATA_855873 > > + select ARM_ERRATA_855873 if !TFABOOT > > This seems to be an error of reordering the patches. TFABOOT has not beed > added at this point. > Will take care in next version. > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] arm: spl: Fix SPL falcon mode boot on MMC with ext partition
If the kernel is on an ext partition, we cannot load it because spl_boot_mode() return MMCSD_MODE_RAW instead of MMCSD_MODE_FS. Signed-off-by: Fabien Lahoudere --- arch/arm/mach-imx/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index a20b30d154..4da028a6e7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -162,7 +162,7 @@ u32 spl_boot_mode(const u32 boot_device) /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: -#if defined(CONFIG_SPL_FAT_SUPPORT) +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) return MMCSD_MODE_FS; #elif defined(CONFIG_SUPPORT_EMMC_BOOT) return MMCSD_MODE_EMMCBOOT; -- 2.11.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert "fdt: fdtdec_setup_memory_banksize() use livetree"
Hi Michal On 10/08/2018 08:28 AM, Michal Simek wrote: > On 6.10.2018 15:33, Patrice CHOTARD wrote: >> Hi >> >> I got same issue on STM32F746 > > Will be good to convert this to more formal line to have a record in git > commit. commit c35a7d375ec8f0a8ee343ae4868be3242172632e breaks also the SPL on STM32F746-disco board. Thanks Patrice > > Thanks, > Michal > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] bootefi selftest on qemu-x86_64
Hi Heinrich, Did you ever get 'bootefi selftest' pass on qemu-x86_64? I got: => bootefi selftest WARNING: booting without device tree lib/efi_selftest/efi_selftest.c(242): ERROR: Cannot open loaded image protocol Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 9/9] pinctrl: sandbox: Add get_pin_muxing ops support
Hi Eugen
On 10/01/2018 03:26 PM, Eugen Hristev wrote:
>
>
> On 01.10.2018 14:59, Patrice Chotard wrote:
>> Add get_pin_mux ops support to display the pin muxing
>> description of the sandbox_pins[]
>>
>> Signed-off-by: Patrice Chotard
>> ---
>>
>> Changes in v2: None
>>
>> drivers/pinctrl/pinctrl-sandbox.c | 15 +++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/pinctrl/pinctrl-sandbox.c
>> b/drivers/pinctrl/pinctrl-sandbox.c
>> index 755ac08bdf72..5c92acbff8e0 100644
>> --- a/drivers/pinctrl/pinctrl-sandbox.c
>> +++ b/drivers/pinctrl/pinctrl-sandbox.c
>> @@ -17,6 +17,14 @@ static const char * const sandbox_pins[] = {
>> "W1"
>> };
>> +static const char * const sandbox_pins_muxing[] = {
>> + "I2C SCL",
>> + "I2C SDA",
>> + "Uart TX",
>> + "Uart RX",
>> + "Onwire gpio",
>
> You have a typo here, its "Onewire", but can name it "1-wire gpio" as it
> fits the most used naming.
Ok
Thanks
Patrice
>
>> +};
>> +
>> static const char * const sandbox_groups[] = {
>> "i2c",
>> "serial_a",
>> @@ -56,6 +64,12 @@ static const char *sandbox_get_pin_name(struct
>> udevice *dev, unsigned selector)
>> return sandbox_pins[selector];
>> }
>> +static const char *sandbox_get_pin_muxing(struct udevice *dev,
>> + unsigned int selector)
>> +{
>> + return sandbox_pins_muxing[selector];
>> +}
>> +
>> static int sandbox_get_groups_count(struct udevice *dev)
>> {
>> return ARRAY_SIZE(sandbox_groups);
>> @@ -123,6 +137,7 @@ static int sandbox_pinconf_group_set(struct
>> udevice *dev,
>> const struct pinctrl_ops sandbox_pinctrl_ops = {
>> .get_pins_count = sandbox_get_pins_count,
>> .get_pin_name = sandbox_get_pin_name,
>> + .get_pin_muxing = sandbox_get_pin_muxing,
>> .get_groups_count = sandbox_get_groups_count,
>> .get_group_name = sandbox_get_group_name,
>> .get_functions_count = sandbox_get_functions_count,
>>
___
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[U-Boot] [PATCH] iot_dk: Disable networking support
There's no Ethernet controller on the board so no point in having networking support. This also saves us 5.5 kB of precious memory. | # bloat-o-meter u-boot.net u-boot.no_net_regex | tail -1 | Total: Before=127892, After=122334, chg -4.35% Signed-off-by: Alexey Brodkin --- configs/iot_devkit_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig index 1f0f9c3256..84b99c93c0 100644 --- a/configs/iot_devkit_defconfig +++ b/configs/iot_devkit_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_PROMPT="IoTDK# " # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -# CONFIG_CMD_NET is not set CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y @@ -25,6 +24,7 @@ CONFIG_DEFAULT_DEVICE_TREE="iot_devkit" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +# CONFIG_NET is not set CONFIG_DM=y CONFIG_MMC=y CONFIG_MMC_DW=y -- 2.16.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms
Includes changes in u-boot framework to support TF-A for NXP Chassis 2 platforms. A new defconfig is added namely ls*_tfa_defconfig which will be used for all boot sources when TF-A is used. Tested on LS1043A, LS1046A and LS1012A platforms. Changes in v3: - Changed order of TFABOOT dependent patches - Merged secureboot TFA boot support patches - Merged nand env patches to remove warning Changes in v2: - Patch subject and description changes - Removed extra CONFIG_TFABOOT flag usage - Merged board specific TFA boot support patches - Checked compilation using buildman tool for each commit Pankit Garg (5): armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 drivers: ifc: dynamic chipselect mapping support armv8: fsl-layerscape: bootcmd identification for TFABOOT armv8: sec_firmware: return job ring status as true in TFABOOT armv8: fsl-layerscape: add support of MC framework for TFA Rajesh Bhagat (19): env: allow flash and nand env driver to compile together env: sf: define API to override sf environment address driver/ifc: replace __ilog2 with LOG2 macro armv8: layerscape: Add TFABOOT support armv8: fsl-layerscape: identify boot source from PORSR register armv8: layerscape: remove EL3 specific erratas for TFABOOT armv8: layerscape: add SMC calls for DDR size and bank info armv8: layerscape: skip OCRAM init for TFABOOT armv8: sec_firmware: change el2_to_aarch32 SMC ID net: fm: add TFABOOT support drivers: qe: add TFABOOT support armv8: ls1046ardb: Add TFABOOT support armv8: ls1046aqds: Add TFABOOT support armv8: ls1043ardb: Add TFABOOT support armv8: ls1043aqds: Add TFABOOT support armv8: ls1012ardb: Add TFABOOT support armv8: ls1012aqds: Add TFABOOT support Revert "env_mmc: add mmc_get_env_addr() prototype" configs: update TFABOOT defconfigs for SD boot support Vinitha V Pillai (1): armv8: ls1012a: fix secure boot compilation York Sun (3): move data structure out of cpu.h armv8: layerscape: Enable routing SError exception armv8: fsl-layerscape: Update parsing boot source arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 31 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 613 +- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 12 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 128 arch/arm/cpu/armv8/sec_firmware.c | 4 + arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 - .../asm/arch-fsl-layerscape/immap_lsch2.h | 20 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 49 ++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 22 + board/freescale/ls1012aqds/Kconfig| 10 + board/freescale/ls1012aqds/ls1012aqds.c | 23 +- board/freescale/ls1012ardb/Kconfig| 4 + board/freescale/ls1012ardb/ls1012ardb.c | 16 +- board/freescale/ls1043aqds/ddr.c | 11 + board/freescale/ls1043aqds/ls1043aqds.c | 147 - board/freescale/ls1043ardb/ddr.c | 14 + board/freescale/ls1043ardb/ls1043ardb.c | 110 board/freescale/ls1046aqds/ddr.c | 11 + board/freescale/ls1046aqds/ls1046aqds.c | 148 - board/freescale/ls1046ardb/ddr.c | 12 + configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 65 ++ configs/ls1012aqds_tfa_defconfig | 62 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 63 ++ configs/ls1012ardb_tfa_defconfig | 56 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 58 ++ configs/ls1043aqds_tfa_defconfig | 55 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 51 ++ configs/ls1043ardb_tfa_defconfig | 50 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 58 ++ configs/ls1046aqds_tfa_defconfig | 58 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 52 ++ configs/ls1046ardb_tfa_defconfig | 50 ++ drivers/misc/fsl_ifc.c| 488 ++ drivers/net/fm/fm.c | 102 ++- drivers/qe/qe.c | 81 +++ env/flash.c | 4 +- env/nand.c| 6 +- env/sf.c | 9 +- include/configs/B4860QDS.h| 2 +- include/configs/T102xQDS.h| 2 +- include/configs/T1040QDS.h| 2 +- include/configs/T208xQDS.h| 2 +- include/configs/T4240QDS.h| 2 +- include/configs/T4240RDB.h| 2 +- include/configs/ls1012a_common.h | 16 +- include/configs/ls1012aqds.h | 1 + include/configs/ls1012ardb.h | 6 + include/configs/ls1043a_common.h
[U-Boot] [PATCH v3 01/28] move data structure out of cpu.h
From: York Sun
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 +
.../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 --
2 files changed, 297 insertions(+), 300 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 052e0708d4..bae50f68d8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,303 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+ CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+ CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+ CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+ CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+ CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+ CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+ CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
+ CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+ CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+ CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+ CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+ CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
+};
+
+#define EARLY_PGTABLE_SIZE 0x5000
+static struct mm_region early_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#ifdef CONFIG_FSL_IFC
+ /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_F
[U-Boot] [PATCH v3 03/28] env: sf: define API to override sf environment address
Defines env_sf_get_env_addr API to override sf environment address,
required to support multiple environment.
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
env/sf.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index 494510533a..df22fd520b 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -297,10 +297,17 @@ out:
}
#endif
+#ifdef CONFIG_ENV_ADDR
+__weak void *env_sf_get_env_addr(void)
+{
+ return (void *)CONFIG_ENV_ADDR;
+}
+#endif
+
#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
static int env_sf_init(void)
{
- env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR);
+ env_t *env_ptr = (env_t *)env_sf_get_env_addr();
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
gd->env_addr= (ulong)&(env_ptr->data);
--
2.17.1
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[U-Boot] [PATCH v3 02/28] env: allow flash and nand env driver to compile together
Define env_ptr as static in flash and nand env driver to allow these to compile together. Signed-off-by: Rajesh Bhagat --- Change in v3: - Merged env nand specific patches to remove compilation warning Change in v2: None env/flash.c | 4 ++-- env/nand.c| 6 ++ include/environment.h | 1 - 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/env/flash.c b/env/flash.c index 32236c716e..33b199f05b 100644 --- a/env/flash.c +++ b/env/flash.c @@ -45,13 +45,13 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifdef ENV_IS_EMBEDDED -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; #else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; +static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; #endif /* ENV_IS_EMBEDDED */ diff --git a/env/nand.c b/env/nand.c index 3698e68957..29eda66fad 100644 --- a/env/nand.c +++ b/env/nand.c @@ -40,11 +40,9 @@ #endif #if defined(ENV_IS_EMBEDDED) -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) -env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; -#else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr; +static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; #endif /* ENV_IS_EMBEDDED */ DECLARE_GLOBAL_DATA_PTR; diff --git a/include/environment.h b/include/environment.h index 5e90f157e8..7da1291d5b 100644 --- a/include/environment.h +++ b/include/environment.h @@ -157,7 +157,6 @@ extern env_t environment; #endif /* ENV_IS_EMBEDDED */ extern const unsigned char default_environment[]; -extern env_t *env_ptr; #if defined(CONFIG_NEEDS_MANUAL_RELOC) extern void env_reloc(void); -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 07/28] drivers: ifc: dynamic chipselect mapping support
From: Pankit Garg
IFC driver changes to implement the chipselect mappings at run time.
Defines init_early_memctl_regs and init_final_memctl_regs with
chipselect dynamic mapping for nor and nand boot.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
drivers/misc/fsl_ifc.c | 488 +
include/fsl_ifc.h | 17 ++
2 files changed, 369 insertions(+), 136 deletions(-)
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index 7d66c3cf76..2e3b43356e 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -7,185 +7,401 @@
#include
#include
-void print_ifc_regs(void)
-{
- int i, j;
-
- printf("IFC Controller Registers\n");
- for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
- printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
- i, get_ifc_cspr(i), i, get_ifc_amask(i),
- i, get_ifc_csor(i));
- for (j = 0; j < 4; j++)
- printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
- }
-}
-
-void init_early_memctl_regs(void)
-{
+struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+{
+ "cs0",
#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
- set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
- set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
- set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
- set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
-
-#ifndef CONFIG_A003399_NOR_WORKAROUND
+ CONFIG_SYS_CSPR0,
#ifdef CONFIG_SYS_CSPR0_EXT
- set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
-#endif
+ CONFIG_SYS_CSPR0_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK0
+ CONFIG_SYS_AMASK0,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR0,
+ {
+ CONFIG_SYS_CS0_FTIM0,
+ CONFIG_SYS_CS0_FTIM1,
+ CONFIG_SYS_CS0_FTIM2,
+ CONFIG_SYS_CS0_FTIM3,
+ },
#ifdef CONFIG_SYS_CSOR0_EXT
- set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+ CONFIG_SYS_CSOR0_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_CSPR0_FINAL
+ CONFIG_SYS_CSPR0_FINAL,
+#else
+ 0,
#endif
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
- set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#ifdef CONFIG_SYS_AMASK0_FINAL
+ CONFIG_SYS_AMASK0_FINAL,
+#else
+ 0,
#endif
#endif
+ },
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
+ {
+ "cs1",
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+ CONFIG_SYS_CSPR1,
#ifdef CONFIG_SYS_CSPR1_EXT
- set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
-#endif
+ CONFIG_SYS_CSPR1_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK1
+ CONFIG_SYS_AMASK1,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR1,
+ {
+ CONFIG_SYS_CS1_FTIM0,
+ CONFIG_SYS_CS1_FTIM1,
+ CONFIG_SYS_CS1_FTIM2,
+ CONFIG_SYS_CS1_FTIM3,
+ },
#ifdef CONFIG_SYS_CSOR1_EXT
- set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+ CONFIG_SYS_CSOR1_EXT,
+#else
+ 0,
#endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
- set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
- set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
- set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
- set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
-
- set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+#ifdef CONFIG_SYS_CSPR1_FINAL
+ CONFIG_SYS_CSPR1_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK1_FINAL
+ CONFIG_SYS_AMASK1_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
#endif
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
+ {
+ "cs2",
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+ CONFIG_SYS_CSPR2,
#ifdef CONFIG_SYS_CSPR2_EXT
- set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
-#endif
+ CONFIG_SYS_CSPR2_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK2
+ CONFIG_SYS_AMASK2,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR2,
+ {
+ CONFIG_SYS_CS2_FTIM0,
+ CONFIG_SYS_CS2_FTIM1,
+ CONFIG_SYS_CS2_FTIM2,
+ CONFIG_SYS_CS2_FTIM3,
+ },
#ifdef CONFIG_SYS_CSOR2_EXT
-
[U-Boot] [PATCH v3 06/28] armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
From: Pankit Garg Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bae50f68d8..6304825180 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -371,7 +371,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el(); /* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 04/28] driver/ifc: replace __ilog2 with LOG2 macro
Replaces __ilog2 function call with LOG2 macro, required to use macros in global variables. Also, corrects the value passed in LOG2 for some PowerPC platforms. Minimum value that can be configured is is 64K for IFC IP. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat --- Change in v3: None Change in v2: None include/configs/B4860QDS.h | 2 +- include/configs/T102xQDS.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T4240QDS.h | 2 +- include/configs/T4240RDB.h | 2 +- include/fsl_ifc.h | 10 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c37864c139..be7ee8e433 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -286,7 +286,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 191616b8b0..a8d64998f2 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -299,7 +299,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 25615be40e..6a91071162 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -225,7 +225,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 7d9354b360..8d358c9285 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -275,7 +275,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index f85881fc3c..0b469b1477 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -201,7 +201,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9d8834a3be..27bd145b52 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -470,7 +470,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0de8..17697c7341 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0x #define IFC_AMASK_SHIFT16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x0700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n)((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#def
[U-Boot] [PATCH v3 13/28] armv8: layerscape: skip OCRAM init for TFABOOT
OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 11b5fb2ec3..cbc9112eb1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -304,7 +304,8 @@ ENTRY(lowlevel_init) 100: #endif -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_TFABOOT) && \ + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) bl fsl_ocram_init #endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 10/28] armv8: layerscape: remove EL3 specific erratas for TFABOOT
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803 SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9092757d1f..1872c66dcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -62,17 +62,17 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 05/28] armv8: layerscape: Enable routing SError exception
From: York Sun In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index ef3987ea84..11b5fb2ec3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f/* skip if not in EL3 */ 1: -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 15/28] armv8: sec_firmware: change el2_to_aarch32 SMC ID
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 1c0f963e18..af1b2da072 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -68,7 +68,7 @@ ENTRY(armv8_el2_to_aarch32) mov x3, x2 mov x2, x1 mov x1, x4 - ldr x0, =0xc000ff04 + ldr x0, =0xc200ff17 smc #0 ret ENDPROC(armv8_el2_to_aarch32) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 08/28] armv8: layerscape: Add TFABOOT support
Adds TFABOOT support config option and add generic code to enable
execution from DDR.
Signed-off-by: York Sun
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Seperated TFABOOT generic code
- Moved before dependency patches
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f2111fadc0..9092757d1f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex
use
pins, select it when the pins are assigned to USB.
+
+config TFABOOT
+ bool "Support for booting from TFA"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via TFA.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6304825180..3e084eddfa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -88,7 +88,8 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -139,7 +140,8 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -1236,7 +1238,8 @@ void update_early_mmu_table(void)
__weak int dram_init(void)
{
fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+ defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 09/28] armv8: fsl-layerscape: identify boot source from PORSR register
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.
Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 190 ++
.../asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++
.../asm/arch-fsl-layerscape/immap_lsch3.h | 49 +
.../arm/include/asm/arch-fsl-layerscape/soc.h | 17 ++
4 files changed, 276 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3e084eddfa..5f56897ab0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -31,6 +31,10 @@
#include
#include
+#ifdef CONFIG_TFABOOT
+#include
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static struct cpu_type cpu_type_list[] = {
@@ -581,7 +585,193 @@ void enable_caches(void)
icache_enable();
dcache_enable();
}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+#ifdef CONFIG_TFABOOT
+enum boot_src __get_boot_src(u32 porsr1)
+{
+ enum boot_src src = BOOT_SOURCE_RESERVED;
+ uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
+#if !defined(CONFIG_FSL_LSCH3_2)
+ uint32_t val;
+#endif
+ debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
+
+#if defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_FSL_LSCH3_2)
+ switch (rcw_src) {
+ case RCW_SRC_SDHC1_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_SDHC2_VAL:
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ case RCW_SRC_FLEXSPI_NAND2K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_FLEXSPI_NAND4K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_RESERVED_1_VAL:
+ src = BOOT_SOURCE_RESERVED;
+ break;
+ case RCW_SRC_FLEXSPI_NOR_24B:
+ src = BOOT_SOURCE_XSPI_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+#else
+ val = rcw_src & RCW_SRC_TYPE_MASK;
+ if (val == RCW_SRC_NOR_VAL) {
+ val = rcw_src & NOR_TYPE_MASK;
+
+ switch (val) {
+ case NOR_16B_VAL:
+ case NOR_32B_VAL:
+ src = BOOT_SOURCE_IFC_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ } else {
+ /* RCW SRC Serial Flash */
+ val = rcw_src & RCW_SRC_SERIAL_MASK;
+ switch (val) {
+ case RCW_SRC_QSPI_VAL:
+ /* RCW SRC Serial NOR (QSPI) */
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case RCW_SRC_SD_CARD_VAL:
+ /* RCW SRC SD Card */
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_EMMC_VAL:
+ /* RCW SRC EMMC */
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ /* RCW SRC I2C1 Extended */
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+#endif
+#elif defined(CONFIG_FSL_LSCH2)
+ /* RCW SRC NAND */
+ val = rcw_src & RCW_SRC_NAND_MASK;
+ if (val == RCW_SRC_NAND_VAL) {
+ val = rcw_src & NAND_RESERVED_MASK;
+ if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+ src = BOOT_SOURCE_IFC_NAND;
+ }
+ } else {
+ /* RCW SRC NOR */
+ val = rcw_src & RCW_SRC_NOR_MASK;
+ if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+ src = BOOT_SOURCE_IFC_NOR;
+ } else {
+ switch (rcw_src) {
+ case QSPI_VAL1:
+ case QSPI_VAL2:
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case SD_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+ }
#endif
+ debug("%s: src 0x%x\n", __func__, src);
+ return src;
+}
+
+enum boot_src get_boot_src(void)
+{
+ u32 porsr1;
+
+#if defined(CONFIG_FSL_LSCH3)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ por
[U-Boot] [PATCH v3 25/28] armv8: ls1012aqds: Add TFABOOT support
TFABOOT support includes:
- ls1012aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat
Signed-off-by: Vinitha V Pillai
Signed-off-by: Pankit Garg
---
Change in v3:
- Added ls1012aqds_tfa_SECURE_BOOT_defconfig
Change in v2:
- Merged ls1012aqds TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1012aqds/ls1012aqds.c | 17 -
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 65
configs/ls1012aqds_tfa_defconfig | 62 +++
3 files changed, 141 insertions(+), 3 deletions(-)
create mode 100644 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/ls1012aqds_tfa_defconfig
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c
b/board/freescale/ls1012aqds/ls1012aqds.c
index 7102237756..1187bd130e 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -55,6 +55,16 @@ int checkboard(void)
return 0;
}
+#ifdef CONFIG_TFABOOT
+int dram_init(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+#else
int dram_init(void)
{
static const struct fsl_mmdc_info mparam = {
@@ -74,7 +84,6 @@ int dram_init(void)
};
mmdc_init(&mparam);
-
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
@@ -83,6 +92,7 @@ int dram_init(void)
return 0;
}
+#endif
int board_early_init_f(void)
{
@@ -110,8 +120,9 @@ int board_init(void)
/* Set CCI-400 control override register to enable barrier
* transaction */
- out_le32(&cci->ctrl_ord,
-CCI400_CTRLORD_EN_BARRIER);
+ if (current_el() == 3)
+ out_le32(&cci->ctrl_ord,
+CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 00..8087825bec
--- /dev/null
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_SYS_TEXT_BASE=0x8200
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_TFABOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500 quiet lpj=25"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_FSL_PFE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
new file mode 100644
index 00..39805ccf9e
--- /dev/null
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+CONFIG_SYS_TEXT_BASE=0x8200
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500 quiet lpj=25"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+
[U-Boot] [PATCH v3 24/28] armv8: ls1012ardb: Add TFABOOT support
TFABOOT support includes:
- ls1012ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat
Signed-off-by: Vinitha V Pillai
Signed-off-by: Pankit Garg
---
Change in v3:
- Added ls1012ardb_tfa_SECURE_BOOT_defconfig
Change in v2:
- Merged ls1012ardb TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1012ardb/ls1012ardb.c | 16 -
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 62
configs/ls1012ardb_tfa_defconfig | 56 ++
include/configs/ls1012a_common.h | 16 -
include/configs/ls1012ardb.h | 6 ++
5 files changed, 154 insertions(+), 2 deletions(-)
create mode 100644 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/ls1012ardb_tfa_defconfig
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c
b/board/freescale/ls1012ardb/ls1012ardb.c
index 888f8500d4..f648a9040b 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -87,8 +87,19 @@ int checkboard(void)
return 0;
}
+#ifdef CONFIG_TFABOOT
int dram_init(void)
{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+#else
+int dram_init(void)
+{
+#ifndef CONFIG_TFABOOT
static const struct fsl_mmdc_info mparam = {
0x0518, /* mdctl */
0x00030035, /* mdpdc */
@@ -106,6 +117,7 @@ int dram_init(void)
};
mmdc_init(&mparam);
+#endif
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
@@ -115,6 +127,7 @@ int dram_init(void)
return 0;
}
+#endif
int board_early_init_f(void)
@@ -132,7 +145,8 @@ int board_init(void)
* Set CCI-400 control override register to enable barrier
* transaction
*/
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ if (current_el() == 3)
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 00..1161ae8d0f
--- /dev/null
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+CONFIG_SYS_TEXT_BASE=0x8200
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_TFABOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500 quiet lpj=25"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
new file mode 100644
index 00..e594bd6b21
--- /dev/null
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+CONFIG_SYS_TEXT_BASE=0x8200
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c050
[U-Boot] [PATCH v3 20/28] armv8: ls1046ardb: Add TFABOOT support
TFABOOT support includes:
- ls1046ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: York Sun
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Removed TFABOOT generic code
- Added ls1046ardb_tfa_SECURE_BOOT_defconfig
Change in v2:
- Merged ls1046ardb TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1046ardb/ddr.c | 12 +
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 52
configs/ls1046ardb_tfa_defconfig | 49 ++
include/configs/ls1046a_common.h | 12 +
include/configs/ls1046ardb.h | 15 ++
5 files changed, 140 insertions(+)
create mode 100644 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/ls1046ardb_tfa_defconfig
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index 82b1b1d9ea..321222d68d 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -97,6 +97,17 @@ found:
popts->cpo_sample = 0x61;
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@@ -117,3 +128,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
new file mode 100644
index 00..8102d13d7d
--- /dev/null
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_SYS_TEXT_BASE=0x8200
+CONFIG_SECURE_BOOT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_TFABOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500
mtdparts=155.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=155.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_USB=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_RSA=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
new file mode 100644
index 00..5bc80ed24e
--- /dev/null
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_SYS_TEXT_BASE=0x8200
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500
mtdparts=155.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=155.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HC
[U-Boot] [PATCH v3 14/28] armv8: fsl-layerscape: Update parsing boot source
From: York Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 26 ---
.../arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ca5329f25c..2e3494bee4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1)
}
}
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
+ src = BOOT_SOURCE_QSPI_NOR;
+
debug("%s: src 0x%x\n", __func__, src);
return src;
}
enum boot_src get_boot_src(void)
{
- u32 porsr1;
+ struct pt_regs regs;
+ u32 porsr1 = 0;
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
-
- porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#endif
+
+ if (current_el() == 2) {
+ regs.regs[0] = SIP_SVC_RCW;
- porsr1 = in_be32(&gur->porsr1);
+ smc_call(®s);
+ if (!regs.regs[0])
+ porsr1 = regs.regs[1];
+ }
+
+ if (current_el() == 3 || !porsr1) {
+#ifdef CONFIG_FSL_LSCH3
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ porsr1 = in_be32(&gur->porsr1);
#endif
+ }
+
debug("%s: porsr1 0x%x\n", __func__, porsr1);
return __get_boot_src(porsr1);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index ef228b6443..daa1c70b3a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -56,6 +56,7 @@ struct cpu_type {
#ifdef CONFIG_TFABOOT
#define SMC_DRAM_BANK_INFO (0xC200FF12)
+#define SIP_SVC_RCW0xC200FF18
phys_size_t tfa_get_dram_size(void);
--
2.17.1
___
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[U-Boot] [PATCH v3 18/28] drivers: qe: add TFABOOT support
Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2:
- Removed extra CONFIG_TFABOOT flag usage
drivers/qe/qe.c | 81 +
1 file changed, 81 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7010bbc230..daefb5aa07 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -17,9 +17,17 @@
#include
#endif
+#ifdef CONFIG_TFABOOT
+#include
+/* required to include IFC and QSPI base address */
+#include
+#include
+#include
+#else
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
#include
#endif
+#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
@@ -170,6 +178,33 @@ void qe_put_snum(u8 snum)
}
}
+#ifdef CONFIG_TFABOOT
+void qe_init(uint qe_base)
+{
+ enum boot_src src = get_boot_src();
+
+ /* Init the QE IMMR base */
+ qe_immr = (qe_map_t *)qe_base;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ /*
+* Upload microcode to IRAM for those SOCs
+* which do not have ROM in QE.
+*/
+ qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE));
+
+ /* enable the microcode in IRAM */
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ }
+
+ gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+ gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
+
+ qe_sdma_init();
+ qe_snums_init();
+}
+#else
void qe_init(uint qe_base)
{
/* Init the QE IMMR base */
@@ -192,8 +227,53 @@ void qe_init(uint qe_base)
qe_snums_init();
}
#endif
+#endif
#ifdef CONFIG_U_QE
+#ifdef CONFIG_TFABOOT
+void u_qe_init(void)
+{
+ enum boot_src src = get_boot_src();
+
+ qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
+
+ void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
CONFIG_SYS_FSL_IFC_BASE);
+ }
+ if (src == BOOT_SOURCE_QSPI_NOR) {
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
CONFIG_SYS_FSL_QSPI_BASE);
+ }
+ if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+ if (mmc_initialize(gd->bd)) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return;
+ }
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ free(addr);
+ printf("\nMMC cannot find device for ucode\n");
+ } else {
+ printf("\nMMC read: dev # %u, block # %u,\
+ count %u ...\n", dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+ cnt, addr);
+ }
+ }
+ if (!u_qe_upload_firmware(addr))
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ if (src == BOOT_SOURCE_SD_MMC)
+ free(addr);
+}
+#else
void u_qe_init(void)
{
qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
@@ -229,6 +309,7 @@ void u_qe_init(void)
#endif
}
#endif
+#endif
#ifdef CONFIG_U_QE
void u_qe_resume(void)
--
2.17.1
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[U-Boot] [PATCH v3 22/28] armv8: ls1043ardb: Add TFABOOT support
TFABOOT support includes:
- ls1043ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN and QE address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Added ls1046ardb_tfa_SECURE_BOOT_defconfig
Change in v2:
- Merged ls1046ardb TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1043ardb/ddr.c | 14 +++
board/freescale/ls1043ardb/ls1043ardb.c | 110 +++
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 51 +
configs/ls1043ardb_tfa_defconfig | 49 +
include/configs/ls1043a_common.h | 27 -
include/configs/ls1043ardb.h | 29 +
6 files changed, 279 insertions(+), 1 deletion(-)
create mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/ls1043ardb_tfa_defconfig
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 7bc0f568ff..784e482f32 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -205,6 +205,19 @@ phys_size_t fixed_sdram(void)
}
#endif
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+ gd->ram_size = fsl_ddr_sdram_size();
+#else
+ gd->ram_size = 0x8000;
+#endif
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@@ -236,3 +249,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/freescale/ls1043ardb/ls1043ardb.c
index f31f0ec515..fbd9a2691b 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -27,6 +27,104 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nor",
+ CONFIG_SYS_NOR_CSPR,
+ CONFIG_SYS_NOR_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+
+ },
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "cpld",
+ CONFIG_SYS_CPLD_CSPR,
+ CONFIG_SYS_CPLD_CSPR_EXT,
+ CONFIG_SYS_CPLD_AMASK,
+ CONFIG_SYS_CPLD_CSOR,
+ {
+ CONFIG_SYS_CPLD_FTIM0,
+ CONFIG_SYS_CPLD_FTIM1,
+ CONFIG_SYS_CPLD_FTIM2,
+ CONFIG_SYS_CPLD_FTIM3
+ },
+ }
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "nor",
+ CONFIG_SYS_NOR_CSPR,
+ CONFIG_SYS_NOR_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ },
+ {
+ "cpld",
+ CONFIG_SYS_CPLD_CSPR,
+ CONFIG_SYS_CPLD_CSPR_EXT,
+ CONFIG_SYS_CPLD_AMASK,
+ CONFIG_SYS_CPLD_CSOR,
+ {
+ CONFIG_SYS_CPLD_FTIM0,
+ CONFIG_SYS_CPLD_FTIM1,
+ CONFIG_SYS_CPLD_FTIM2,
+ CONFIG_SYS_CPLD_FTIM3
+ },
+ }
+};
+
+void ifc_cfg_boot_i
[U-Boot] [PATCH v3 17/28] net: fm: add TFABOOT support
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2:
- Removed extra CONFIG_TFABOOT flag usage
drivers/net/fm/fm.c | 102 ++--
1 file changed, 98 insertions(+), 4 deletions(-)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index c5cf188f05..768d4a9241 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -11,13 +11,13 @@
#include "fm.h"
#include /* For struct qe_firmware */
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include
-#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
#include
-#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
#include
-#endif
+/* required to include IFC and QSPI base address */
+#include
+#include
+#include
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
@@ -347,6 +347,99 @@ static void fm_init_qmi(struct fm_qmi_common *qmi)
}
/* Init common part of FM, index is fm num# like fm as above */
+#ifdef CONFIG_TFABOOT
+int fm_init_common(int index, struct ccsr_fman *reg)
+{
+ int rc;
+ void *addr = NULL;
+ enum boot_src src = get_boot_src();
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE);
+ } else if (src == BOOT_SOURCE_IFC_NAND) {
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+ rc = nand_read(get_nand_dev_by_index(0),
+ (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+ &fw_length, (u_char *)addr);
+ if (rc == -EUCLEAN) {
+ printf("NAND read of FMAN firmware at offset 0x%x\
+ failed %d\n", CONFIG_SYS_FMAN_FW_ADDR, rc);
+ }
+ } else if (src == BOOT_SOURCE_QSPI_NOR) {
+ struct spi_flash *ucode_flash;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ int ret = 0;
+
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ /* speed and mode will be read from DT */
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+ ucode_flash = dev_get_uclass_priv(new);
+#else
+ ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+ CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ,
+ CONFIG_ENV_SPI_MODE);
+#endif
+ if (!ucode_flash)
+ printf("SF: probe for ucode failed\n");
+ else {
+ ret = spi_flash_read(ucode_flash,
+CONFIG_SYS_FMAN_FW_ADDR +
+CONFIG_SYS_FSL_QSPI_BASE,
+CONFIG_SYS_QE_FMAN_FW_LENGTH,
+addr);
+ if (ret)
+ printf("SF: read for ucode failed\n");
+ spi_flash_free(ucode_flash);
+ }
+ } else if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc)
+ printf("\nMMC cannot find device for ucode\n");
+ else {
+ printf("\nMMC read: dev # %u, block # %u, count %u \
+ ...\n", dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+ cnt, addr);
+ }
+ } else
+ addr = NULL;
+
+ /* Upload the Fman microcode if it's present */
+ rc = fman_upload_firmware(index, ®->fm_imem, addr);
+ if (rc)
+ return rc;
+ env_set_addr("fman_ucode", addr);
+
+ fm_init_muram(index, ®->muram);
+ fm_init_qmi(®->fm_qmi_common);
+ fm_init_fpm(®->fm_fpm);
+
+ /* clear DMA status */
+ setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
+
+ /* set DMA mode */
+ setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
+
+ return fm_init_bmi(index, ®->fm_bmi_common);
+}
+#else
int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
@@ -429,3 +522,4 @@ int fm_init_common(int index, struct ccsr_fman *reg)
return fm_init_bmi(index,
[U-Boot] [PATCH v3 19/28] armv8: fsl-layerscape: add support of MC framework for TFA
From: Pankit Garg
Add support of MC framework for TFA
Make MC framework independent of boot source.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b68d99c765..0092a22394 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -747,6 +747,54 @@ int fsl_setenv_bootcmd(void)
}
return 0;
}
+
+int fsl_setenv_mcinitcmd(void)
+{
+ int ret = 0;
+ enum boot_src src = get_boot_src();
+
+ switch (src) {
+#ifdef IFC_MC_INIT_CMD
+ case BOOT_SOURCE_IFC_NAND:
+ case BOOT_SOURCE_IFC_NOR:
+ ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
+ break;
+#endif
+#ifdef QSPI_MC_INIT_CMD
+ case BOOT_SOURCE_QSPI_NAND:
+ case BOOT_SOURCE_QSPI_NOR:
+ ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
+ break;
+#endif
+#ifdef XSPI_MC_INIT_CMD
+ case BOOT_SOURCE_XSPI_NAND:
+ case BOOT_SOURCE_XSPI_NOR:
+ ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
+ break;
+#endif
+#ifdef SD_MC_INIT_CMD
+ case BOOT_SOURCE_SD_MMC:
+ ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
+ break;
+#endif
+#ifdef SD2_MC_INIT_CMD
+ case BOOT_SOURCE_SD_MMC2:
+ ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
+ break;
+#endif
+ default:
+#ifdef QSPI_MC_INIT_CMD
+ ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
+#endif
+ break;
+ }
+
+ if (ret) {
+ printf("Failed to set mcinitcmd: ret = %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
@@ -758,9 +806,11 @@ int board_late_init(void)
#ifdef CONFIG_TFABOOT
/*
* check if gd->env_addr is default_environment; then setenv bootcmd
+* and mcinitcmd.
*/
if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
fsl_setenv_bootcmd();
+ fsl_setenv_mcinitcmd();
}
#endif
#ifdef CONFIG_QSPI_AHB_INIT
--
2.17.1
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[U-Boot] [PATCH v3 12/28] armv8: layerscape: add SMC calls for DDR size and bank info
Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 4 +
2 files changed, 88 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6c1b1ffec8..ca5329f25c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1230,12 +1230,96 @@ phys_size_t get_effective_memsize(void)
return ea_size;
}
+#ifdef CONFIG_TFABOOT
+phys_size_t tfa_get_dram_size(void)
+{
+ struct pt_regs regs;
+ phys_size_t dram_size = 0;
+
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = -1;
+
+ smc_call(®s);
+ if (regs.regs[0])
+ return 0;
+
+ dram_size = regs.regs[1];
+ return dram_size;
+}
+
+static int tfa_dram_init_banksize(void)
+{
+ int i = 0, ret = 0;
+ struct pt_regs regs;
+ phys_size_t dram_size = tfa_get_dram_size();
+
+ debug("dram_size %llx\n", dram_size);
+
+ if (!dram_size)
+ return -EINVAL;
+
+ do {
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = i;
+
+ smc_call(®s);
+ if (regs.regs[0]) {
+ ret = -EINVAL;
+ break;
+ }
+
+ debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
+ regs.regs[2]);
+ gd->bd->bi_dram[i].start = regs.regs[1];
+ gd->bd->bi_dram[i].size = regs.regs[2];
+
+ dram_size -= gd->bd->bi_dram[i].size;
+
+ i++;
+ } while (dram_size);
+
+ if (i > 0)
+ ret = 0;
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+ /* Assign memory for MC */
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bd->bi_dram[2].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[2].start +
+ gd->bd->bi_dram[2].size -
+ board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ } else
+#endif
+ {
+ if (gd->bd->bi_dram[1].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[1].start +
+ gd->bd->bi_dram[1].size -
+ board_reserve_ram_top(gd->bd->bi_dram[1].size);
+ } else if (gd->bd->bi_dram[0].size >
+ board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size -
+ board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ }
+ }
+#endif /* CONFIG_FSL_MC_ENET */
+
+ return ret;
+}
+#endif
+
int dram_init_banksize(void)
{
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
phys_size_t dp_ddr_size;
#endif
+#ifdef CONFIG_TFABOOT
+ if (!tfa_dram_init_banksize())
+ return 0;
+#endif
/*
* gd->ram_size has the total size of DDR memory, less reserved secure
* memory. The DDR extends from low region to high region(s) presuming
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index d327c7ba1f..ef228b6443 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -55,6 +55,10 @@ struct cpu_type {
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#ifdef CONFIG_TFABOOT
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+phys_size_t tfa_get_dram_size(void);
+
enum boot_src {
BOOT_SOURCE_RESERVED = 0,
BOOT_SOURCE_IFC_NOR,
--
2.17.1
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[U-Boot] [PATCH v3 16/28] armv8: sec_firmware: return job ring status as true in TFABOOT
From: Pankit Garg
Returns job ring status as true in TFABOOT, as one job ring is always
reserved.
Signed-off-by: Ruchika Gupta
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/sec_firmware.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/sec_firmware.c
b/arch/arm/cpu/armv8/sec_firmware.c
index a13c92e246..8dc0ac9266 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void)
*/
bool sec_firmware_support_hwrng(void)
{
+#ifdef CONFIG_TFABOOT
+ /* return true as TFA has one job ring reserved */
+ return true;
+#endif
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
return true;
}
--
2.17.1
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[U-Boot] [PATCH v3 11/28] armv8: fsl-layerscape: bootcmd identification for TFABOOT
From: Pankit Garg
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3:
- Merged secure boot bootcmd changes
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 78 +
2 files changed, 92 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 5f56897ab0..6c1b1ffec8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,9 @@
#ifdef CONFIG_TFABOOT
#include
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include
+#endif
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -741,6 +744,14 @@ enum env_location env_get_location(enum env_operation op,
int prio)
if (prio)
return ENVL_UNKNOWN;
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* Check Boot Mode
+* If Boot Mode is Secure, return ENVL_NOWHERE
+*/
+ if (fsl_check_boot_mode_secure() == 1)
+ goto done;
+#endif
+
switch (src) {
case BOOT_SOURCE_IFC_NOR:
env_loc = ENVL_FLASH;
@@ -768,6 +779,9 @@ enum env_location env_get_location(enum env_operation op,
int prio)
break;
}
+#ifdef CONFIG_CHAIN_OF_TRUST
+done:
+#endif
return env_loc;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 54fb0745f9..b68d99c765 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -24,6 +24,10 @@
#include
#endif
#include
+#ifdef CONFIG_TFABOOT
+#include
+DECLARE_GLOBAL_DATA_PTR;
+#endif
bool soc_has_dp_ddr(void)
{
@@ -679,12 +683,86 @@ int qspi_ahb_init(void)
}
#endif
+#ifdef CONFIG_TFABOOT
+#define MAX_BOOTCMD_SIZE 256
+
+int fsl_setenv_bootcmd(void)
+{
+ int ret;
+ enum boot_src src = get_boot_src();
+ char bootcmd_str[MAX_BOOTCMD_SIZE];
+
+ switch (src) {
+#ifdef IFC_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NOR:
+ sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NOR:
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NOR:
+ sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef IFC_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NAND:
+ sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NAND:
+ sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NAND:
+ sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC:
+ sprintf(bootcmd_str, SD_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD2_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC2:
+ sprintf(bootcmd_str, SD2_BOOTCOMMAND);
+ break;
+#endif
+ default:
+#ifdef QSPI_NOR_BOOTCOMMAND
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+#endif
+ break;
+ }
+
+ ret = env_set("bootcmd", bootcmd_str);
+ if (ret) {
+ printf("Failed to set bootcmd: ret = %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
+#ifdef CONFIG_TFABOOT
+ /*
+* check if gd->env_addr is default_environment; then setenv bootcmd
+*/
+ if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
+ fsl_setenv_bootcmd();
+ }
+#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
#endif
--
2.17.1
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[U-Boot] [PATCH v3 23/28] armv8: ls1043aqds: Add TFABOOT support
TFABOOT support includes:
- ls1043aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Added ls1043aqds_tfa_SECURE_BOOT_defconfig
Change in v2:
- Merged ls1043aqds TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1043aqds/ddr.c | 11 ++
board/freescale/ls1043aqds/ls1043aqds.c | 147 ++-
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 58
configs/ls1043aqds_tfa_defconfig | 54 +++
include/configs/ls1043aqds.h | 50 ++-
5 files changed, 317 insertions(+), 3 deletions(-)
create mode 100644 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/ls1043aqds_tfa_defconfig
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index efc441a917..d29a3ad797 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -108,6 +108,16 @@ found:
#endif
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@@ -131,3 +141,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
b/board/freescale/ls1043aqds/ls1043aqds.c
index 44cc509b53..45f006dab7 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -46,8 +47,135 @@ enum {
#define CFG_UART_MUX_SHIFT 1
#define CFG_LPUART_EN 0x1
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nor0",
+ CONFIG_SYS_NOR0_CSPR,
+ CONFIG_SYS_NOR0_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+
+ },
+ {
+ "nor1",
+ CONFIG_SYS_NOR1_CSPR,
+ CONFIG_SYS_NOR1_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ },
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "fpga",
+ CONFIG_SYS_FPGA_CSPR,
+ CONFIG_SYS_FPGA_CSPR_EXT,
+ CONFIG_SYS_FPGA_AMASK,
+ CONFIG_SYS_FPGA_CSOR,
+ {
+ CONFIG_SYS_FPGA_FTIM0,
+ CONFIG_SYS_FPGA_FTIM1,
+ CONFIG_SYS_FPGA_FTIM2,
+ CONFIG_SYS_FPGA_FTIM3
+ },
+ }
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "nor0",
+ CONFIG_SYS_NOR0_CSPR,
+ CONFIG_SYS_NOR0_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ },
+ {
+ "nor1",
+ CONFIG_SYS_NOR1_CSPR,
+ CONFIG_SYS_NOR1_
[U-Boot] [PATCH v3 26/28] armv8: ls1012a: fix secure boot compilation
From: Vinitha V Pillai Includes environment.h file in ls1012aqds.c Also, enables pfe validation in ls1012ardb. Signed-off-by: Vinitha V Pillai --- Change in v3: None Change in v2: None board/freescale/ls1012aqds/Kconfig | 10 ++ board/freescale/ls1012aqds/ls1012aqds.c | 6 ++ board/freescale/ls1012ardb/Kconfig | 4 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 + include/configs/ls1012aqds.h | 1 + 5 files changed, 22 insertions(+) diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index b702fb2740..8844557aae 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -16,6 +16,12 @@ config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x4040 +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x4068 +endif + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy @@ -33,6 +39,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a0 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x4070 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x0380 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 1187bd130e..a862fe6a93 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -18,12 +18,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" @@ -132,6 +134,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 4cd66bd548..51efd0fa37 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -33,6 +33,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a0 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x4070 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x0380 diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 1161ae8d0f..3754931702 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -44,6 +44,7 @@ CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_FSL_PFE=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index c5bdea6798..c76bfdc8f8 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -117,4 +117,5 @@ #define CONFIG_SYS_MEMTEST_START 0x8000 #define CONFIG_SYS_MEMTEST_END 0x9fff +#include #endif /* __LS1012AQDS_H__ */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 43/45] video: at91: Adjust vidconsole_position_cursor() to use char pos
On 09.10.2018 06:40, Simon Glass wrote:
> Hi Eugen,
>
> On 2 October 2018 at 01:37, Eugen Hristev wrote:
>>
>>
>>
>> On 01.10.2018 23:22, Anatolij Gustschin wrote:
>>>
>>> Hi Simon,
>>>
>>> On Mon, 1 Oct 2018 12:22:47 -0600
>>> Simon Glass s...@chromium.org wrote:
>>>
At present this function uses pixels but it seems more useful for it to
position in terms of characters on the screen. This also matches the
comment to the function. Update this.
Unfortunately there is one user of this function (at91). Have a crack at
fixing this, since I cannot test it.
>>
>>
>> Hello Simon,
>>
>> I will gladly test this for you on at91 board,
>> but I am having some issues applying your patch series:
>>
>> Applying: binman: Move to three-digit test-file numbers
>> error: patch failed: tools/binman/entry_test.py:25
>> error: tools/binman/entry_test.py: patch does not apply
>> error: patch failed: tools/binman/ftest.py:712
>> error: tools/binman/ftest.py: patch does not apply
>> Patch failed at 0026 binman: Move to three-digit test-file numbers
>>
>> Do you have them in some public tree I can pull from ?
>
> Yes you can try u-boot-dm/testing
>
>>
>> Also, any specific tests you would like except just checking the video
>> console ?
>
> It looks like this code runs when the board boots up, so just starting
> it should be enough.
I made a build on your branch and tested it on at91 sama5d2_xplained
board, and the logo and text appears on the display.
Tested-by: Eugen Hristev
Let me know if you want me to do more tests.
Eugen
>
> Thanks,
> Simon
>
>
>>
>> Eugen
>>
>>
Signed-off-by: Simon Glass
>>>
>>>
>>> Reviewed-by: Anatolij Gustschin
>>>
---
board/atmel/common/video_display.c | 5 -
drivers/video/vidconsole-uclass.c | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/atmel/common/video_display.c
b/board/atmel/common/video_display.c
index 7dd7b85556e..e02cb00f866 100644
--- a/board/atmel/common/video_display.c
+++ b/board/atmel/common/video_display.c
@@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
int at91_video_show_board_info(void)
{
+ struct vidconsole_priv *priv;
ulong dram_size, nand_size;
int i;
u32 len = 0;
@@ -63,7 +64,9 @@ int at91_video_show_board_info(void)
if (ret)
return ret;
- vidconsole_position_cursor(con, 0, logo_info.logo_height);
+ priv = dev_get_uclass_priv(con);
+ vidconsole_position_cursor(con, 0, (logo_info.logo_height +
+ con->y_charsize - 1) / con->y_charsize);
>>>
>>>
>>> Shouldn't it be priv->y_charsize? 'con' is struct udevice * and doesn't
>>> have y_charsize.
>>>
>>>
>>> --
>>> Anatolij
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>>>
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[U-Boot] [PATCH v3 21/28] armv8: ls1046aqds: Add TFABOOT support
TFABOOT support includes:
- ls1046aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg
Signed-off-by: Vinitha V Pillai
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Added ls1046aqds_tfa_SECURE_BOOT_defconfig
Change in v2:
- Merged ls1046aqds TFA boot support patches
- Removed extra CONFIG_TFABOOT flag usage
board/freescale/ls1046aqds/ddr.c | 11 ++
board/freescale/ls1046aqds/ls1046aqds.c | 148 ++-
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 58
configs/ls1046aqds_tfa_defconfig | 57 +++
include/configs/ls1046aqds.h | 59 +++-
5 files changed, 330 insertions(+), 3 deletions(-)
create mode 100644 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/ls1046aqds_tfa_defconfig
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index 08f7610e69..45b1f373a7 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -92,6 +92,16 @@ found:
popts->cpo_sample = 0x70;
}
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
+#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@@ -116,3 +126,4 @@ int fsl_initdram(void)
return 0;
}
+#endif
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c
b/board/freescale/ls1046aqds/ls1046aqds.c
index 0da82381af..b71c1746bb 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -32,12 +33,140 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nor0",
+ CONFIG_SYS_NOR0_CSPR,
+ CONFIG_SYS_NOR0_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+
+ },
+ {
+ "nor1",
+ CONFIG_SYS_NOR1_CSPR,
+ CONFIG_SYS_NOR1_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ },
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "fpga",
+ CONFIG_SYS_FPGA_CSPR,
+ CONFIG_SYS_FPGA_CSPR_EXT,
+ CONFIG_SYS_FPGA_AMASK,
+ CONFIG_SYS_FPGA_CSOR,
+ {
+ CONFIG_SYS_FPGA_FTIM0,
+ CONFIG_SYS_FPGA_FTIM1,
+ CONFIG_SYS_FPGA_FTIM2,
+ CONFIG_SYS_FPGA_FTIM3
+ },
+ }
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+ {
+ "nand",
+ CONFIG_SYS_NAND_CSPR,
+ CONFIG_SYS_NAND_CSPR_EXT,
+ CONFIG_SYS_NAND_AMASK,
+ CONFIG_SYS_NAND_CSOR,
+ {
+ CONFIG_SYS_NAND_FTIM0,
+ CONFIG_SYS_NAND_FTIM1,
+ CONFIG_SYS_NAND_FTIM2,
+ CONFIG_SYS_NAND_FTIM3
+ },
+ },
+ {
+ "nor0",
+ CONFIG_SYS_NOR0_CSPR,
+ CONFIG_SYS_NOR0_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+ {
+ CONFIG_SYS_NOR_FTIM0,
+ CONFIG_SYS_NOR_FTIM1,
+ CONFIG_SYS_NOR_FTIM2,
+ CONFIG_SYS_NOR_FTIM3
+ },
+ },
+ {
+ "nor1",
+ CONFIG_SYS_NOR1_CSPR,
+ CONFIG_SYS_NOR1_CSPR_EXT,
+ CONFIG_SYS_NOR_AMASK,
+ CONFIG_SYS_NOR_CSOR,
+
Re: [U-Boot] [PATCH] Revert "fdt: fdtdec_setup_memory_banksize() use livetree"
Hi Patrice, On 9.10.2018 11:15, Patrice CHOTARD wrote: > Hi Michal > > On 10/08/2018 08:28 AM, Michal Simek wrote: >> On 6.10.2018 15:33, Patrice CHOTARD wrote: >>> Hi >>> >>> I got same issue on STM32F746 >> >> Will be good to convert this to more formal line to have a record in git >> commit. > > commit c35a7d375ec8f0a8ee343ae4868be3242172632e breaks also the SPL on > STM32F746-disco board. I meant something like Tested-by: <> [for STM32F746] M ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/6] MSCC: add support for VCoreIII SoCs
Hi Daniel,
I am bout to send a new version of the series, but befor I am going to
answer to the pending point I didn't already address in my email 10 days
ago.
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> Hi Gregory,
>
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> These families of SoCs are found in the Microsemi Switches solution.
>>
>> Currently the support for two families support is added:
>> - Ocelot (VSC7513, VSC7514) already supported in Linux
>> - Luton (Luton10: VSC7423, VSC7424, VSC7428 and Luton26: VSC7425,
>>VSC7426, VSC7426, VSC7427, VSC7429)
[...]
>> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
>> libs-y += $(machdirs)
>> diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
>> new file mode 100644
>> index 00..20148bfe15
>> --- /dev/null
>> +++ b/arch/mips/mach-mscc/Kconfig
>> @@ -0,0 +1,101 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +if ARCH_MSCC
>> +
>> +config SYS_DCACHE_SIZE
>> +default 32768
>> +
>> +config SYS_DCACHE_LINE_SIZE
>> +default 32
>> +
>> +config SYS_ICACHE_SIZE
>> +default 32768
>> +
>> +config SYS_ICACHE_LINE_SIZE
>> +default 32
>> +
>> +endif
>
> from the code below I assume you have a MIPS24k core? If so you should
> use the automatic cache size detection
Eventually I managed to use the automatic cache size detection.
>> +void vcoreiii_tlb_init(void)
>> +{
>> +register int tlbix = 0;
>> +
>> +init_tlb();
>> +
>> +/* 0x7000 size 32M (0x0200) */
>> +create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#ifdef CONFIG_SOC_LUTON
>> +create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#endif
>> +/* 0x4000 - 0x43ff - NON-CACHED! */
>> +/* Flash CS0-3, each 16M = 64M total (16 x 4 below ) */
>> +create_tlb(tlbix++, MSCC_FLASH_TO,SZ_16M, MMU_REGIO_RO,
>> MMU_REGIO_RO);
>> +create_tlb(tlbix++, MSCC_FLASH_TO+SZ_32M, SZ_16M, MMU_REGIO_RO,
>> MMU_REGIO_RO);
>> +
>> +/* 0x2000 - up */
>> +#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
>> +create_tlb(tlbix++, MSCC_DDR_TO,SZ_64M, MMU_REGIO_RW,
>> MMU_REGIO_INVAL);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
>> +create_tlb(tlbix++, MSCC_DDR_TO,SZ_64M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW,
>> MMU_REGIO_INVAL);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#else /* 1024M */
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_512M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#endif
>
> can't you leave that to the kernel? U-Boot is only running in kernel
> mode and doesn't need MMU mappings.
Actually, U-Boot doesn't need MMU mappings, and without this chunk of
code U-Boot is running without any problem, but unlike most of the MIPS
based SoCs, the IO register address are not in KSEG0. The mainline linux
kernel built in legacy mode needs to access some of the registers very
early in the boot and make the assumption that the bootloader already
configured them, so we have to match this expectation.
So in code I only keep the tlb entry for MSCC_IO_ORIGIN1_OFFSET and
MSCC_IO_ORIGIN1_OFFSET (where the Io registers are) and I added a
comment to explain it.
>> +}
>> +
>> +int mach_cpu_init(void)
>> +{
>> +/* Speed up NOR flash access */
>> +#ifdef CONFIG_SOC_LUTON
>> +writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
>> +#else
>> +writel(
>> +#endif
>> + ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
>> + ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
>> +
>> +/* Disable all IRQs - map to destination map 0 */
>> +writel(0, REG_CFG(ICPU_INTR_ENA));
>> +#ifdef CONFIG_SOC_OCELOT
>> +writel(~0, REG_CFG(ICPU_DST_INTR_MAP(0)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(1)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(2)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(3)));
>> +#else
>> +writel(ICPU_INTR_IRQ0_ENA_IRQ0_ENA, REG_CFG(ICPU_INTR_IRQ0_ENA));
>> +#endif
>
> do you really need to disable interrupts after a cold or warm boot?
It was a workaround for an issue in a legacy kernel that is now fixed so
indeed can remove it.
[...]
>> +
>> +static inline void init_tlb(void)
>> +{
>> +register int i, max;
>> +
>> +max = get_tlb_count();
>> +for(i = 0; i < max; i++)
>> +create_tlb(i, i * SZ_1M, SZ_4K, MMU_REGIO_INVAL, MMU_REGIO_INVAL);
>> +}
>
> again can't you leave the setup of MMU mappings to the kernel?
I removed this part
[...]
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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Re: [U-Boot] [PATCH 3/6] MSCC: add board support for the VCoreIII based evaluation boards
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
[...]
>> diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
>> new file mode 100644
>> index 00..0804f5081d
>> --- /dev/null
>> +++ b/board/mscc/ocelot/Kconfig
>> @@ -0,0 +1,24 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +config SYS_VENDOR
>> +default "mscc"
>> +
>> +if SOC_OCELOT
>> +
>> +config SYS_BOARD
>> +default "ocelot"
>> +
>> +config SYS_CONFIG_NAME
>> +default "ocelot"
>> +
>> +endif
>> +
>> +if SOC_LUTON
>> +
>> +config SYS_BOARD
>> +default "luton"
>> +
>> +config SYS_CONFIG_NAME
>> +default "luton"
>> +
>
> this is already defined in board/mscc/luton/Kconfig
I removed it
>
>> +endif
>> diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile
>> new file mode 100644
>> index 00..f6a665ca83
>> --- /dev/null
>> +++ b/board/mscc/ocelot/Makefile
>> @@ -0,0 +1,5 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +obj-$(CONFIG_SOC_OCELOT):= ocelot.o
>> +obj-y += ../common/board.o
>> +
>> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
>> new file mode 100644
>> index 00..971fa93d07
>> --- /dev/null
>> +++ b/board/mscc/ocelot/ocelot.c
>> @@ -0,0 +1,38 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Microsemi Corporation
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +void external_cs_manage(struct udevice *dev, bool enable)
>> +{
>> +u32 cs = spi_chip_select(dev);
>> +/* IF_SI0_OWNER, select the owner of the SI interface
>> + * Encoding: 0: SI Slave
>> + * 1: SI Boot Master
>> + * 2: SI Master Controller
>> + */
>
> style issues like indentation and multi-line comments
I fixed it
Gregory
>
>> +if (!enable) {
>> +writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
>> + ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
>> + REG_CFG(ICPU_SW_MODE));
>> +writel((readl(REG_CFG(ICPU_GENERAL_CTRL))
>> +& ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
>> + ICPU_GENERAL_CTRL_IF_SI_OWNER(2),
>> + REG_CFG(ICPU_GENERAL_CTRL));
>> +} else {
>> +writel(0, REG_CFG(ICPU_SW_MODE));
>> +writel((readl(REG_CFG(ICPU_GENERAL_CTRL)) &
>> +~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
>> + ICPU_GENERAL_CTRL_IF_SI_OWNER(1),
>> + REG_CFG(ICPU_GENERAL_CTRL));
>> +}
>> +}
>>
>
> --
> - Daniel
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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[U-Boot] [PATCH] ARM: dts: rmobile: Reinstate missing CPLD on ULCB
The CPLD is used to reset the ULCB and it was removed
during DT sync with Linux 4.17. Reinstate it.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/ulcb.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
index bff00d8c18..4b00db8970 100644
--- a/arch/arm/dts/ulcb.dtsi
+++ b/arch/arm/dts/ulcb.dtsi
@@ -24,6 +24,15 @@
stdout-path = "serial0:115200n8";
};
+ cpld {
+ compatible = "renesas,ulcb-cpld";
+ status = "okay";
+ gpio-sck = <&gpio6 8 0>;
+ gpio-mosi = <&gpio6 7 0>;
+ gpio-miso = <&gpio6 10 0>;
+ gpio-sstbz = <&gpio2 3 0>;
+ };
+
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
--
2.18.0
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Re: [U-Boot] [PATCH 3/6] MSCC: add board support for the VCoreIII based evaluation boards
Hi Marek,
On jeu., sept. 27 2018, Marek Vasut wrote:
> On 09/25/2018 03:01 PM, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> board/mscc/common/board.c | 29 +
>> board/mscc/luton/Kconfig | 14 ++
>> board/mscc/luton/Makefile | 4
>> board/mscc/luton/luton.c | 14 ++
>> board/mscc/ocelot/Kconfig | 24
>> board/mscc/ocelot/Makefile | 5 +
>> board/mscc/ocelot/ocelot.c | 38 ++
>> 7 files changed, 128 insertions(+)
>> create mode 100644 board/mscc/common/board.c
>> create mode 100644 board/mscc/luton/Kconfig
>> create mode 100644 board/mscc/luton/Makefile
>> create mode 100644 board/mscc/luton/luton.c
>> create mode 100644 board/mscc/ocelot/Kconfig
>> create mode 100644 board/mscc/ocelot/Makefile
>> create mode 100644 board/mscc/ocelot/ocelot.c
>>
>> diff --git a/board/mscc/common/board.c b/board/mscc/common/board.c
>> new file mode 100644
>> index 00..86e7bf3353
>> --- /dev/null
>> +++ b/board/mscc/common/board.c
>> @@ -0,0 +1,29 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Microsemi Corporation
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_early_init_r(void)
>> +{
>> +u32 ctrl;
>> +
>> +/* Prepare SPI controller to be used in master mode */
>> +writel(0, REG_CFG(ICPU_SW_MODE));
>> +ctrl = readl(REG_CFG(ICPU_GENERAL_CTRL));
>> +
>> +writel((ctrl & ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
>> + ICPU_GENERAL_CTRL_IF_SI_OWNER(2),
>> + REG_CFG(ICPU_GENERAL_CTRL));
>
> This can be replaced by one of the clrsetbits stuff.
I used the clrsetbits family everywhere it was possible now.
>
> [...]
>
>> +++ b/board/mscc/luton/luton.c
>> @@ -0,0 +1,14 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Microsemi Corporation
>> + */
>> +
>> +#include
>> +#include
>> +
>> +void board_debug_uart_init(void)
>> +{
>> +/* too early for the pinctrl driver, so configure the UART pins here */
>> +writel(BIT(30)|BIT(31), REG_GCB((0x68+8*4)));
>> +writel(~(BIT(30)|BIT(31)), REG_GCB((0x68+9*4)));
>
> Can this ad-hoc random address be replaced by a macro ?
Done!
Gregory
>
> [...]
>
> --
> Best regards,
> Marek Vasut
--
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Embedded Linux and Kernel engineering
http://bootlin.com
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Re: [U-Boot] [PATCH 4/6] MSCC: add device tree for Ocelot and Luton (boards and SoCs)
Hi Daniel, On mer., sept. 26 2018, Daniel Schwierzeck wrote: > On 25.09.2018 15:01, Gregory CLEMENT wrote: >> Adding device tree for Ocelot SoC (extract from Linux) and the 2 >> evaluation boards using this SoC: PCB120 and PCB132. >> >> Adding device tree for Luton SoC (not yet in Linux) and the evaluation >> boards using this SoC: PCB91. >> >> Signed-off-by: Gregory CLEMENT >> --- >> arch/mips/dts/luton_pcb091.dts | 36 >> arch/mips/dts/mscc,luton.dtsi | 87 +++ >> arch/mips/dts/mscc,ocelot.dtsi | 132 + >> arch/mips/dts/mscc,ocelot_pcb.dtsi | 37 >> arch/mips/dts/ocelot_pcb120.dts| 12 +++ >> arch/mips/dts/ocelot_pcb123.dts| 12 +++ >> 6 files changed, 316 insertions(+) >> create mode 100644 arch/mips/dts/luton_pcb091.dts >> create mode 100644 arch/mips/dts/mscc,luton.dtsi >> create mode 100644 arch/mips/dts/mscc,ocelot.dtsi >> create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi >> create mode 100644 arch/mips/dts/ocelot_pcb120.dts >> create mode 100644 arch/mips/dts/ocelot_pcb123.dts > > should be added along with the board code. Also please try to add Ocelot > and Luton boards in separate patches. Done Gregory -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] mmc: tmio: Pass full address to tmio_sd_addr_is_dmaable()
Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
so we don't have to apply casts throughout the code.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
---
drivers/mmc/tmio-common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index b311b80be8..6b21941991 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -372,8 +372,10 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct
mmc_data *data)
}
/* check if the address is DMA'able */
-static bool tmio_sd_addr_is_dmaable(unsigned long addr)
+static bool tmio_sd_addr_is_dmaable(const char *src)
{
+ uintptr_t addr = (uintptr_t)src;
+
if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
return false;
@@ -486,7 +488,7 @@ int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd
*cmd,
if (data) {
/* use DMA if the HW supports it and the buffer is aligned */
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
- tmio_sd_addr_is_dmaable((long)data->src))
+ tmio_sd_addr_is_dmaable(data->src))
ret = tmio_sd_dma_xfer(dev, data);
else
ret = tmio_sd_pio_xfer(dev, data);
--
2.18.0
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Re: [U-Boot] [PATCH 5/6] MSCC: add configuration for Ocelot and Luton based boards
Hi Daniel, On mer., sept. 26 2018, Daniel Schwierzeck wrote: > On 25.09.2018 15:01, Gregory CLEMENT wrote: >> Add common configuration header for the VCore III SoCs (currently Ocelot >> and Luton), but also the defconfig for the evaluation boards of these >> SoCs. >> >> Signed-off-by: Gregory CLEMENT >> --- >> configs/mscc_luton_defconfig | 66 + >> configs/mscc_ocelot_defconfig| 57 ++ >> configs/mscc_ocelot_pcb120_defconfig | 56 ++ >> include/configs/vcoreiii.h | 72 >> 4 files changed, 251 insertions(+) >> create mode 100644 configs/mscc_luton_defconfig >> create mode 100644 configs/mscc_ocelot_defconfig >> create mode 100644 configs/mscc_ocelot_pcb120_defconfig >> create mode 100644 include/configs/vcoreiii.h > > should also be added along with the board code Done too Gregory -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] mmc: tmio: Limit DMA to 32bit on R-Car Gen3
The internal DMAC on Gen3 is 32bit only, limit the DMA address range to 32bit. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/tmio-common.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 6b21941991..138de59470 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -379,6 +379,12 @@ static bool tmio_sd_addr_is_dmaable(const char *src) if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN)) return false; +#if defined(CONFIG_RCAR_GEN3) + /* Gen3 DMA has 32bit limit */ + if (addr >> 32) + return false; +#endif + #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ defined(CONFIG_SPL_BUILD) /* -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] MIPS: bootm: Add support for Vcore III linux kernel
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line is expected to be a single string
>> passed in argv[1]. An other expectation is that the arguments are located
>> in the cached address space.
>>
>> However, like yamon, they expect that rd_start and rd_size was passed by
>> the bootloader in the command line of the kernel, and besides that it
>> also wait for the root=/dev/ram0.
>
> Can't you use existing boot interfaces? The preferred way would be to
> pass a device-tree blob to the kernel and let U-Boot fill the bootargs
> in that DTB. I wonder why the linux-mips guys let you add another boot
> interface. Or do you simply want to boot some legacy or propietary
> kernels?
Actually we support the dtb way, but the legacy kernel still neeeds this
see:
https://elixir.bootlin.com/linux/v4.19-rc7/source/arch/mips/generic/board-ocelot.c#L38
Gregory
>
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> arch/mips/lib/bootm.c | 62 +--
>> 1 file changed, 42 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
>> index deca5189e3..417f5ce452 100644
>> --- a/arch/mips/lib/bootm.c
>> +++ b/arch/mips/lib/bootm.c
>> @@ -44,22 +44,38 @@ void arch_lmb_reserve(struct lmb *lmb)
>> lmb_reserve(lmb, sp, gd->ram_top - sp);
>> }
>>
>> -static void linux_cmdline_init(void)
>> +static void linux_cmdline_init(int vcoreiii)
>> {
>> +if (!vcoreiii) {
>> +linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +} else {
>> +/*
>> + * Vcore III linux kernels expect arguments in the cached
>> + * address space. They also expect the command line being a
>> + * single string in the first argument
>> + */
>> +linux_argv = (char **)(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +linux_argv[1] = linux_argp;
>> +}
>> linux_argc = 1;
>> -linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> linux_argv[0] = 0;
>> -linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> }
>>
>> -static void linux_cmdline_set(const char *value, size_t len)
>> +static void linux_cmdline_set(const char *value, size_t len, int vcoreiii)
>> {
>> -linux_argv[linux_argc] = linux_argp;
>> memcpy(linux_argp, value, len);
>> -linux_argp[len] = 0;
>> -
>> +if (!vcoreiii) {
>> +linux_argv[linux_argc] = linux_argp;
>> +linux_argp[len] = 0;
>> +linux_argc++;
>> +} else {
>> +linux_argp[len] = ' ';
>> +linux_argp[len + 1] = 0;
>> +linux_argc = 2;
>> +}
>> linux_argp += len + 1;
>> -linux_argc++;
>> }
>>
>> static void linux_cmdline_dump(void)
>> @@ -73,12 +89,10 @@ static void linux_cmdline_dump(void)
>> debug(" arg %03d: %s\n", i, linux_argv[i]);
>> }
>>
>> -static void linux_cmdline_legacy(bootm_headers_t *images)
>> +static void linux_cmdline_legacy(bootm_headers_t *images, int vcoreiii)
>> {
>> const char *bootargs, *next, *quote;
>> -
>> -linux_cmdline_init();
>> -
>> +linux_cmdline_init(vcoreiii);
>> bootargs = env_get("bootargs");
>> if (!bootargs)
>> return;
>> @@ -104,7 +118,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> if (!next)
>> next = bootargs + strlen(bootargs);
>>
>> -linux_cmdline_set(bootargs, next - bootargs);
>> +linux_cmdline_set(bootargs, next - bootargs, vcoreiii);
>>
>> if (*next)
>> next++;
>> @@ -113,7 +127,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> }
>> }
>>
>> -static void linux_cmdline_append(bootm_headers_t *images)
>> +static void linux_cmdline_append(bootm_headers_t *images, int vcoreiii)
>> {
>> char buf[24];
>> ulong mem, rd_start, rd_size;
>> @@ -121,7 +135,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
>> /* append mem */
>> mem = gd->ram_size >> 20;
>> sprintf(buf, "mem=%luM", mem);
>> -linux_cmdline_set(buf, strlen(buf));
>> +linux_cmdline_set(buf, strlen(buf), vcoreiii);
>>
>> /* append rd_start and rd_size */
>> rd_start = images->initrd_start;
>> @@ -129,9 +143,13 @@ static void linux_cmdline_append(bootm_headers_t
>> *images)
>>
>> if (rd_size) {
>> sprintf(buf, "rd_start=0x%08lX", rd_start);
>> -linux_cmdline_set(buf, strlen(buf));
>> +linux_cmdline_set(buf, strlen(buf), vcoreiii);
>> sprintf(buf, "rd_size=0x%lX", rd_size);
>> -
Re: [U-Boot] [PATCH v1 00/19] DM_I2C_COMPAT removal for all ti platforms
On Mon, Oct 8, 2018 at 4:36 AM Jean-Jacques Hiblot wrote: > > > > On 06/10/2018 03:22, Adam Ford wrote: > > On Thu, Oct 4, 2018 at 8:48 AM Jean-Jacques Hiblot wrote: > >> This series remove the usage of the DM_I2C_COMPAT option for all the ti > >> platforms. It also takes this opportunity to not disable DM_I2C in the SPL. > >> > >> There are a couples of issues to fix: > >> - CMD_EEPROM does not support the DM API. Fixed by removing this option > >>when DM_I2C is used without DM_I2C_COMPAT > >> - i2c_get_chip_for_busnum() does not work when OF_CONTROL is not used > >>(as is the case with am33xx SPL). > >> - The I2C driver do not support DM_I2C without OF_CONTROL. > >> - Most of the PMIC drivers do not support the I2C DM API. > >> - Board detection is done prior DM initialization. Fixed by moving it after > >>DM is initialized. That move breaks the DRA7 platforms (The fixes for > >>that are at the last 5 patches this series) > >> > >> When all this is taken care of DM_I2C_COMPAT can be removed and DM_I2C > >> enabled in the SPL. > >> > >> This has been tested with the following boards: > >> - am437x SK > >> - am335x SK > >> - am335x beaglebone (both DM and non-DM config) > >> - dra76 evm > >> - am572 evm > >> - k2g evm > >> > >> > >> > > The whole series applied and > > > > Tested-by: Adam Ford #omap3_logic > Thanks for testing > but I guess you meant that for v2 not v1 ? Sorry. I did intend that for the V2 patch. Thanks for doing that. I had started on it for the twl4030, but your implemention was a little cleaner than what I was doing. adam > JJ > > > > adam > >> Andreas Dannenberg (1): > >>ti: common: board_detect: Allow DM I2C without CONFIG_DM_I2C_COMPAT > >> > >> Jean-Jacques Hiblot (17): > >>cmd: Kconfig: Do not include EEPROM if DM_I2C is used without > >> DM_I2C_COMPAT > >>dm: i2c: Add dm_i2c_probe_device() to test the presence of a chip > >>dm: device: Allow using uclass_find_device_by_seq() without OF_CONTROL > >>configs: am335x: am57x: dra7x: Enable CONFIG_SPL_DM_SEQ_ALIAS > >>i2c: omap24xx_i2c: Use platdata to probe the device > >>am335x: Register the I2C controllers if DM_I2C is used. > >>dts: am43x: omap5: Add node for I2C in SPL > >>omap: detect the board after DM is available > >>power: make most tps drivers and the twl4030 driver compatible with > >> DM_I2C > >>configs: am335x_pdu001: Explicitly enable CONFIG_I2C_COMPAT > >>ti: remove usage of DM_I2C_COMPAT and don't disable DM_I2C in SPL > >>am57xx: remove non-DM I2C code > >>configs: dra7xx-evm: increase the size of the malloc's pool before > >> relocation > >>lib: fdtdec: Add function re-setup the fdt more effeciently > >>drivers: core: Add the option SPL_DM_DEVICE_REMOVE to the Kconfig > >>drivers: core: nullify gd->dm_root after dm_uninit() > >>dra7: Allow selecting a new dtb after board detection. > >> > >> Vignesh R (1): > >>i2c: omap24xx_i2c: Move away from SoC specific headers for reg offset > >> > >> arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 4 + > >> arch/arm/dts/omap5-u-boot.dtsi | 4 + > >> arch/arm/include/asm/arch-am33xx/i2c.h | 47 +-- > >> arch/arm/include/asm/arch-omap3/i2c.h| 47 --- > >> arch/arm/include/asm/arch-omap4/i2c.h| 45 --- > >> arch/arm/include/asm/arch-omap5/i2c.h| 45 --- > >> arch/arm/include/asm/omap_i2c.h | 24 ++ > >> arch/arm/mach-keystone/ddr3_spd.c| 7 + > >> arch/arm/mach-omap2/am33xx/board.c | 24 +- > >> arch/arm/mach-omap2/am33xx/clk_synthesizer.c | 56 +++- > >> arch/arm/mach-omap2/clocks-common.c | 2 + > >> arch/arm/mach-omap2/hwinit-common.c | 23 +- > >> board/ti/am335x/board.c | 17 +- > >> board/ti/am335x/mux.c| 14 + > >> board/ti/am43xx/board.c | 35 +- > >> board/ti/am57xx/board.c | 25 +- > >> board/ti/common/board_detect.c | 110 +++ > >> board/ti/ks2_evm/board_k2g.c | 11 + > >> cmd/Kconfig | 1 + > >> configs/am335x_pdu001_defconfig | 2 + > >> configs/am57xx_evm_defconfig | 1 + > >> configs/am57xx_hs_evm_defconfig | 1 + > >> configs/dra7xx_evm_defconfig | 4 +- > >> configs/dra7xx_hs_evm_defconfig | 1 + > >> configs/omap3_logic_defconfig| 1 + > >> drivers/core/Kconfig | 12 +- > >> drivers/core/device.c| 10 +- > >> drivers/core/root.c | 1 + > >> drivers/core/uclass.c| 24 ++ > >> drivers/i2c/i2c-uclass.c | 8 + > >> drivers/i2c/omap24xx_i2c.c | 467 > >> ++- > >> drivers/power/palmas.c
[U-Boot] [PATCH] QSPI flash driver compatibility fixes for mx6ull
Avoid "SF: Timeout!" messages and generally speed up QSPI flash
operations on mx6ull EVK by adding a QSPI sequence for reading
"flag status register" as required for some (ST/Micron) NOR
flash devices by the DM spi-flash driver.
Enable QSPI clock in EVK specific board_init function, as per
other Freescale EVKs.
Tested on mcimx6ull EVK, U303 populated with a Micron MT25QL256ABA
(ID reads as 'n25q256').
Cc: Peng Fan
Cc: Jagan Teki
Signed-off-by: Neil Stainton
---
arch/arm/dts/imx6ull-14x14-evk.dts| 2 +-
board/freescale/mx6ullevk/mx6ullevk.c | 15 +++
drivers/mtd/spi/spi_flash.c | 4 ++--
drivers/spi/fsl_qspi.c| 24 +++-
4 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts
b/arch/arm/dts/imx6ull-14x14-evk.dts
index 8a1b67d..7cb6d16 100644
--- a/arch/arm/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/dts/imx6ull-14x14-evk.dts
@@ -454,10 +454,10 @@
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
- /* compatible = "micron,n25q256a"; */
compatible = "spi-flash";
spi-max-frequency = <2900>;
spi-nor,ddr-quad-read-dummy = <6>;
+ memory-map = <0x6000 0x0200>;
reg = <0>;
};
};
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c
b/board/freescale/mx6ullevk/mx6ullevk.c
index ad83f36..46d61bc 100644
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -58,11 +58,26 @@ int board_early_init_f(void)
return 0;
}
+#ifdef CONFIG_FSL_QSPI
+static int board_qspi_init(void)
+{
+ /* Set the clock */
+ enable_qspi_clk(0);
+
+ return 0;
+}
+#endif /* !defined(CONFIG_FSL_QSPI) */
+
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_FSL_QSPI
+ /* Set the clock */
+ board_qspi_init();
+#endif
+
return 0;
}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index c159124..c817772 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -360,7 +360,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash,
u32 offset, size_t len)
}
#ifdef CONFIG_SPI_FLASH_BAR
- ret = clean_bar(flash);
+ clean_bar(flash);
#endif
return ret;
@@ -422,7 +422,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash,
u32 offset,
}
#ifdef CONFIG_SPI_FLASH_BAR
- ret = clean_bar(flash);
+ clean_bar(flash);
#endif
return ret;
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1598c4f..07c3ade 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -47,10 +47,12 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#define SEQID_WRAR 13
#define SEQID_RDAR 14
+#define SEQID_RDFSR15
/* QSPI CMD */
#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
#define QSPI_CMD_RDSR 0x05/* Read status register */
+#define QSPI_CMD_RDFSR 0x70/* Read flag status register */
#define QSPI_CMD_WREN 0x06/* Write enable */
#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
#define QSPI_CMD_BE_4K 0x20/* 4K erase */
@@ -230,6 +232,15 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
+ /* Read Flag Status */
+ lut_base = SEQID_RDFSR * 4;
+ qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDFSR) |
+ PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
+ PAD1(LUT_PAD1) | INSTR1(LUT_READ));
+ qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0);
+ qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0);
+ qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0);
+
/* Erase a sector */
lut_base = SEQID_SE * 4;
#ifdef CONFIG_SPI_FLASH_BAR
@@ -698,7 +709,7 @@ static void qspi_op_write(struct fsl_qspi_priv
*priv, u8 *txbuf, u32 len)
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
-static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
+static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32
len, u8 seqid)
{
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg, reg, data;
@@ -712,7 +723,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv,
void *rxbuf, u32 len)
qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base);
qspi_write32(priv->flags, ®s->ipcr,
-(SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
+(seqid << QSPI_IPCR_SEQID_SHIFT) | 0);
while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
;
@@ -815,10 +826,13 @@ int qspi_xfer(struct
Re: [U-Boot] [PATCH 00/22] spl: Add features for passing info from SPL to U-Boot proper
Hi Kever, On 7 October 2018 at 20:30, Kever Yang wrote: > > Hi Simon, > > > On 09/27/2018 05:54 AM, Simon Glass wrote: > > At present we have no standard way of passing information from SPL to > > U-Boot. Such information may be the size of DRAM banks or some information > > about the reset state of the machine,for example. > > > > This series first adds a bloblist, which allows a list of 'blobs' to be > > created, each with a tag so that subsystems can store data and retrieve it > > later. Then it adds the SPL 'handoff' information, which uses bloblist. > > It's great to see this patch set, because Rockchip U-Boot is also > implementing this > kind of feature recently, my plan was send it upstream after we run in a > good result. > We have some discussion in our team, and we chose ATAGs instead of a new > format of data structure at last, fdt is another candidate, but we think > it is too > complicated for those TINY sram SoCs. > The information we need to passing including: > - DRAM size from TPL/SPL; OK, this is supported in this series. > - boot device from bootrom which can be read only in TPL/SPL; That would need to be added. You could add it in arch/arm/include/handoff.h behind an #ifdef CONFIG_ROCKCHIP guard, perhaps? > - DRAM reserved space in TRUST(ATF, OP-TEE), which means we need to modify; > - other info which may help U-Boot, for example, we may able to skip > MMC/SD init > if we can get enough info for controller setting; Same with the above. I suppose we could create a new bloblist tag if needed. Regards, Simon > > Thanks, > - Kever > > Various minor sandbox enhancements are provided to make this easier, or to > > support testing. > > > > > > Simon Glass (22): > > log: Correct definition of log_msg_ret() > > spl: Add support for logging in SPL and TPL > > Add core support for a bloblist to convey data from SPL > > spl: Set up the bloblist in SPL > > bloblist: Locate bloblist in U-Boot > > test: Add a simple test for bloblist > > Add bloblist documentation > > spl: Support hash, input, pch, pci, rtc, tpm in SPL > > spl: Add a define for SPL_TPL_PROMPT > > spl: Make SPL_DISABLE_BANNER_PRINT a positive option > > spl: Add a comment to spl_set_bd() > > spl: Print a message if we are unable to load an image > > sandbox: Add a memory map to the sandbox README > > test/py: Add a way to pass flags to sandbox > > sandbox: Add an option to display of-platdata in SPL > > sandbox: Add a new 'sb' command > > sandbox: Allow puts() output before global_data is set up > > sandbox: Refactor code to create os_jump_to_file() > > sandbox: Use malloc() and free() from os layer > > sandbox: Filter arguments when starting U-Boot > > sandbox: Boot in U-Boot through the standard call > > spl: Add support for passing handoff info to U-Boot proper > > > > arch/Kconfig | 1 + > > arch/powerpc/include/asm/spl.h | 3 - > > arch/sandbox/cpu/eth-raw-os.c | 9 +- > > arch/sandbox/cpu/os.c | 115 +- > > arch/sandbox/cpu/spl.c | 31 +++- > > arch/sandbox/cpu/start.c | 19 +++ > > arch/sandbox/cpu/u-boot-spl.lds| 2 +- > > arch/sandbox/include/asm/handoff.h | 18 +++ > > arch/sandbox/include/asm/state.h | 8 + > > board/sandbox/README.sandbox | 14 +- > > cmd/Makefile | 1 + > > cmd/host.c | 5 - > > cmd/sb.c | 65 > > common/Kconfig | 84 +- > > common/Makefile| 5 +- > > common/bloblist.c | 239 + > > common/board_f.c | 47 ++ > > common/console.c | 7 + > > common/init/Makefile | 1 + > > common/init/handoff.c | 47 ++ > > common/spl/Kconfig | 95 +++- > > common/spl/spl.c | 142 + > > configs/sandbox_spl_defconfig | 1 + > > doc/README.bloblist| 82 ++ > > drivers/Makefile | 11 +- > > include/asm-generic/global_data.h | 7 + > > include/bloblist.h | 194 +++ > > include/handoff.h | 36 + > > include/log.h | 10 +- > > include/spl.h | 41 + > > include/test/suites.h | 1 + > > test/Makefile | 1 + > > test/bloblist.c| 187 ++ > > test/cmd_ut.c | 3 + > > test/py/tests/test_handoff.py | 14 ++ > > test/py/tests/test_ofplatdata.py | 31 +++- > > test/py/u_boot_console_base.py | 2 +- > > test/py/u_boot_console_sandbox.py | 18 ++- > > test/run | 2 +- > > 39 files changed, 1497 insertions(+), 102 deletions(-) > > create mode 100644 arch/sandbox/inclu
Re: [U-Boot] [PATCH] travis: Add sandbox/clang-7 support
On Mon, Oct 08, 2018 at 09:40:51PM -0600, Simon Glass wrote: > Hi Tom, > > On 7 October 2018 at 12:20, Tom Rini wrote: > > > > To make testing with clang support easier, add sandbox/clang-7 > > combination to our testing matrix. To facilitate this, switch to using > > the "sources" method that the travis.yml file supports to list > > additional repositories and add the official one for llvm-7. Due to > > buildman not supporting using clang at this time add logic to manually > > build a single sandbox configuration in the expected output directory so > > that we can still invoke all of our tests. > > > > Cc: Simon Glass > > Signed-off-by: Tom Rini > > --- > > .travis.yml | 27 --- > > 1 file changed, 20 insertions(+), 7 deletions(-) > > Reviewed-by: Simon Glass > > What prevents buildman supporting clang? Well, I couldn't convince buildman to accept "/usr/bin/clang-7" as the full and entire path to the toolchain to use. Ideas? Thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert "fdt: fdtdec_setup_memory_banksize() use livetree"
Hi Michal
On 10/04/2018 09:24 AM, Michal Simek wrote:
> This reverts commit c35a7d375ec8f0a8ee343ae4868be3242172632e.
> This commit is breaking SPL on zc706.
>
> Signed-off-by: Michal Simek
> ---
>
> lib/fdtdec.c | 44 +++-
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 74196ce7f9f7..bf5e0f6a57c0 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -15,7 +15,6 @@
> #include
> #include
> #include
> -#include
> #include
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -1182,34 +1181,41 @@ int fdtdec_setup_mem_size_base(void)
>
> #if defined(CONFIG_NR_DRAM_BANKS)
>
> -static ofnode get_next_memory_node(ofnode mem)
> +static int get_next_memory_node(const void *blob, int mem)
> {
> do {
> - mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
> - } while (ofnode_valid(mem) && !ofnode_is_available(mem));
> + mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
> + "device_type", "memory", 7);
> + } while (!fdtdec_get_is_enabled(blob, mem));
>
> return mem;
> }
>
> int fdtdec_setup_memory_banksize(void)
> {
> - int bank, reg = 0;
> - struct resource res;
> - ofnode mem;
> + int bank, ret, mem, reg = 0;
> + struct fdt_resource res;
>
> - mem = get_next_memory_node(ofnode_null());
> - if (!ofnode_valid(mem))
> - goto missing_node;
> + mem = get_next_memory_node(gd->fdt_blob, -1);
> + if (mem < 0) {
> + debug("%s: Missing /memory node\n", __func__);
> + return -EINVAL;
> + }
>
> for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> - while (ofnode_read_resource(mem, reg++, &res)) {
> + ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
> + if (ret == -FDT_ERR_NOTFOUND) {
> reg = 0;
> - mem = get_next_memory_node(mem);
> - if (!ofnode_valid(mem)) {
> - if (bank)
> - return 0;
> - goto missing_node;
> - }
> + mem = get_next_memory_node(gd->fdt_blob, mem);
> + if (mem == -FDT_ERR_NOTFOUND)
> + break;
> +
> + ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++,
> &res);
> + if (ret == -FDT_ERR_NOTFOUND)
> + break;
> + }
> + if (ret != 0) {
> + return -EINVAL;
> }
>
> gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
> @@ -1223,10 +1229,6 @@ int fdtdec_setup_memory_banksize(void)
> }
>
> return 0;
> -
> -missing_node:
> - debug("%s: Missing /memory node\n", __func__);
> - return -EINVAL;
> }
> #endif
>
>
Tested-by: Patrice Chotard [on STM32F746-disco]
Patrice
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[U-Boot] [PATCH v2 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c | 10 --
arch/mips/include/asm/mipsregs.h | 11 +++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
}
#endif
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
int arch_cpu_init(void)
{
mips_cache_probe();
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..930562ebb2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & 0x3ff;
}
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
2.19.1
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[U-Boot] [PATCH v2 2/7] MIPS: Allow to prefetch and lock instructions into cache
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 3161875441..98b67ccc8e 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void
*addr)
#endif
}
+#define MIPS32_WHICH_ICACHE0x0
+#define MIPS32_FETCH_AND_LOCK 0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+ int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+ for (i = 0; i < lines; i++) {
+ asm volatile (" cache %0, %1(%2)"
+ : /* No Output */
+ : "I" ICACHE_LOAD_LOCK,
+ "n" (i * ARCH_DMA_MINALIGN),
+ "r" (func)
+ : /* No Clobbers */);
+ }
+}
#endif /* !__ASSEMBLY__ */
/*
--
2.19.1
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[U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches
Hello, For the record this the second version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III. We found them on various advanced switches product. The support for Ocelot already have been submit to Linux, but not yet the Luton support. Since the v1 many changes had been done: - a big clean-up for indentation and some style issue - usage of the clrsetbits family functions where it was possible - split the patches for Ocelot and Luton - add a new patch to introduce the icache_lock function which was in the mscc directory in the first version - remove more unused define in the platform header files - use the automatic cache size detection instead of hard coding it - reduce the tlb init to only two entries for the IO as needed by the kernel - remove the interrupt disabling - fix the ddr init for luton Gregory CLEMENT (7): MIPS: move create_tlb() in an proper header: mipsregs.h MIPS: Allow to prefetch and lock instructions into cache MSCC: add support for Ocelot SoCs MSCC: add support for Luton SoCs MSCC: add board support for the Ocelots based evaluation boards MSCC: add board support for the Luton based evaluation board MIPS: bootm: Add support for Vcore III linux kernel arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/cpu/cpu.c | 10 - arch/mips/dts/luton_pcb091.dts| 36 + arch/mips/dts/mscc,luton.dtsi | 87 ++ arch/mips/dts/mscc,ocelot.dtsi| 132 +++ arch/mips/dts/mscc,ocelot_pcb.dtsi| 33 + arch/mips/dts/ocelot_pcb120.dts | 12 + arch/mips/dts/ocelot_pcb123.dts | 12 + arch/mips/include/asm/cacheops.h | 19 + arch/mips/include/asm/mipsregs.h | 11 + arch/mips/lib/bootm.c | 77 +- arch/mips/mach-mscc/Kconfig | 86 ++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 55 ++ arch/mips/mach-mscc/dram.c| 63 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 31 + arch/mips/mach-mscc/include/mach/ddr.h| 786 ++ .../mips/mach-mscc/include/mach/luton/luton.h | 37 + .../include/mach/luton/luton_devcpu_gcb.h | 14 + .../include/mach/luton/luton_icpu_cfg.h | 245 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 ++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 30 + arch/mips/mach-mscc/lowlevel_init_luton.S | 62 ++ arch/mips/mach-mscc/reset.c | 36 + board/mscc/luton/Kconfig | 14 + board/mscc/luton/Makefile | 3 + board/mscc/luton/luton.c | 28 + board/mscc/ocelot/Kconfig | 14 + board/mscc/ocelot/Makefile| 4 + board/mscc/ocelot/ocelot.c| 48 ++ configs/mscc_luton_defconfig | 66 ++ configs/mscc_ocelot_defconfig | 57 ++ configs/mscc_ocelot_pcb120_defconfig | 56 ++ include/configs/vcoreiii.h| 77 ++ 39 files changed, 2660 insertions(+), 30 deletions(-) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mips/dts/ocelot_pcb120.dts create mode 100644 arch/mips/dts/ocelot_pcb123.dts create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S create mode 100644 arch/mips/mach-mscc/reset.c create mode 100644 board/mscc/luton/Kconfig create mode 100644 board/mscc/luton/Makefile create
[U-Boot] [PATCH v2 4/7] MSCC: add support for Luton SoCs
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 13 +
arch/mips/mach-mscc/dram.c| 2 +
arch/mips/mach-mscc/include/mach/common.h | 4 +
arch/mips/mach-mscc/include/mach/ddr.h| 114 +++-
.../mips/mach-mscc/include/mach/luton/luton.h | 37 +++
.../include/mach/luton/luton_devcpu_gcb.h | 14 +
.../include/mach/luton/luton_icpu_cfg.h | 245 ++
arch/mips/mach-mscc/lowlevel_init.S | 7 +
arch/mips/mach-mscc/lowlevel_init_luton.S | 62 +
11 files changed, 508 insertions(+), 4 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 7f1b270207..a8cace0e79 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -21,6 +21,12 @@ config SOC_OCELOT
help
This supports MSCC Ocelot family of SOCs.
+config SOC_LUTON
+ bool
+ select SOC_VCOREIII
+ help
+ This supports MSCC Luton family of SOCs.
+
config SYS_CONFIG_NAME
default "vcoreiii"
@@ -41,6 +47,13 @@ config TARGET_OCELOT_PCB123
When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
ocelot_pcb123
+config TARGET_LUTON_PCB091
+ bool "MSCC PCB091 Reference Board"
+ select SOC_LUTON
+ select MSCC_BITBANG_SPI_GPIO
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ luton_pcb091
endchoice
choice
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index d14ec33838..6c60f26ca4 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -3,3 +3,4 @@
CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 0c8f7933cd..562b2cf5f9 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -31,12 +31,25 @@ void vcoreiii_tlb_init(void)
*/
create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
MMU_REGIO_RW);
+#ifdef CONFIG_SOC_LUTON
+ create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
+ MMU_REGIO_RW);
+#endif
}
int mach_cpu_init(void)
{
/* Speed up NOR flash access */
+#ifdef CONFIG_SOC_LUTON
+ writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
+ ICPU_PI_MST_CFG_CLK_DIV(4), REG_CFG(ICPU_PI_MST_CFG));
+
+ writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+ ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+ ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+#else
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+#endif
return 0;
}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index b82961f773..5ee141ab77 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -23,7 +23,9 @@ int vcoreiii_ddr_init(void)
hal_vcoreiii_wait_memctl();
if (hal_vcoreiii_init_dqs() != 0 ||
hal_vcoreiii_train_bytelane(0) != 0
+#ifdef CONFIG_SOC_OCELOT
|| hal_vcoreiii_train_bytelane(1) != 0
+#endif
)
hal_vcoreiii_ddr_failed();
}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 41887097f9..4ba1f7974c 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -13,6 +13,10 @@
#include
#include
#include
+#elif defined(CONFIG_SOC_LUTON)
+#include
+#include
+#include
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index c089af8e33..51ea65b573 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -586,6 +586,99 @@ static inline int dram_check(void)
}
return 0;
}
+#else /* Luton */
+
+static inline void sleep_100ns(u32 val)
+{
+}
+
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_RST);
+ setbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_MEM_RST_FORCE);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+}
+
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+ regi
[U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT --- arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/mach-mscc/Kconfig | 69 ++ arch/mips/mach-mscc/Makefile | 5 + arch/mips/mach-mscc/cpu.c | 42 ++ arch/mips/mach-mscc/dram.c| 61 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 27 + arch/mips/mach-mscc/include/mach/ddr.h| 680 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 23 + arch/mips/mach-mscc/reset.c | 36 + 15 files changed, 1386 insertions(+) create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/reset.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 071dea04ec..da479f2172 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -59,6 +59,11 @@ config ARCH_ATH79 select OF_CONTROL imply CMD_DM +config ARCH_MSCC + bool "Support MSCC VCore-III" + select OF_CONTROL + select DM + config ARCH_BMIPS bool "Support BMIPS SoCs" select CLK @@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mt7620/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 802244a06e..124e93fa26 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MT7620) += mt7620 +machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig new file mode 100644 index 00..7f1b270207 --- /dev/null +++ b/arch/mips/mach-mscc/Kconfig @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +menu "MSCC VCore-III platforms" + depends on ARCH_MSCC + +config SOC_VCOREIII + select MIPS_TUNE_24KC + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + bool + +config SYS_SOC + default "mscc" + +config SOC_OCELOT + bool + select SOC_VCOREIII + help + This supports MSCC Ocelot family of SOCs. + +config SYS_CONFIG_NAME + default "vcoreiii" + +choice + prompt "Board select" + +config TARGET_OCELOT_PCB120 + bool "MSCC PCB120 Reference Board (aka VSC5635EV)" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb120 + +config TARGET_OCELOT_PCB123 + bool "MSCC PCB123 Reference Board (aka VSC7514EV))" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb123 + +endchoice + +choice + prompt "DDR type" + +config DDRTYPE_H5TQ4G63MFR + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)" + +config DDRTYPE_MT41K256M16 + bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)" + +config DDRTYPE_H5TQ1G63BFA + bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)" + +config DDRTYPE_MT41J128M16HA + bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)" + +config DDRTYPE_MT41K128M16JT + bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)" + +config DDRTYPE_MT47H128M8HQ + bool "Micron MT47H128M8-3 (1Gbit, DDR-533@CL4 @ 4.80ns 16Mbisx8x8)" + +endchoice + +endmenu diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile new file mode 100644 index 00..d14ec33838 --- /dev/null +++ b/arch/
[U-Boot] [PATCH v2 6/7] MSCC: add board support for the Luton based evaluation board
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/luton_pcb091.dts | 36 ++
arch/mips/dts/mscc,luton.dtsi | 87 ++
arch/mips/mach-mscc/Kconfig| 2 +
board/mscc/luton/Kconfig | 14 ++
board/mscc/luton/Makefile | 3 ++
board/mscc/luton/luton.c | 28 +++
configs/mscc_luton_defconfig | 66 ++
7 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb091.dts
create mode 100644 arch/mips/dts/mscc,luton.dtsi
create mode 100644 board/mscc/luton/Kconfig
create mode 100644 board/mscc/luton/Makefile
create mode 100644 board/mscc/luton/luton.c
create mode 100644 configs/mscc_luton_defconfig
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 00..b5e0df8d04
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+spi-max-frequency = <1800>; /* input clock */
+reg = <0>; /* CS0 */
+ };
+};
+
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 00..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x1020>;
+
+ uart0: serial@1010 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+
+ compatible = "ns16550a";
+ reg = <0x1010 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 32>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+
+ gpio_spi_bitbang: gpio@1064 {
+ compatible = "mscc,spi-bitbang-gpio";
+ reg = <0x1064 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+
+ spi0: spi-bitbang {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <&gpio_spi_bitbang 6 0>;
+ gpio-miso = <&gpio_spi_bitbang 0 0>;
+ gpio-mosi = <&gpio_spi_bitbang 5 0>;
+ cs-gpios = <&gpio_spi_bitbang 1 0>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index fc806fc1f3..0e35b77c9d 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -81,4 +81,6 @@ endchoice
source "board/mscc/ocelot/Kconfig"
+source "board/mscc/luton/Kconfig"
+
endmenu
diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig
new file mode 100644
index 00..e1199
[U-Boot] [PATCH v2 5/7] MSCC: add board support for the Ocelots based evaluation boards
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 132 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 33 +++
arch/mips/dts/ocelot_pcb120.dts | 12 +++
arch/mips/dts/ocelot_pcb123.dts | 12 +++
arch/mips/mach-mscc/Kconfig | 2 +
board/mscc/ocelot/Kconfig| 14 +++
board/mscc/ocelot/Makefile | 4 +
board/mscc/ocelot/ocelot.c | 48 ++
configs/mscc_ocelot_defconfig| 57
configs/mscc_ocelot_pcb120_defconfig | 56
include/configs/vcoreiii.h | 77
11 files changed, 447 insertions(+)
create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
create mode 100644 arch/mips/dts/ocelot_pcb120.dts
create mode 100644 arch/mips/dts/ocelot_pcb123.dts
create mode 100644 board/mscc/ocelot/Kconfig
create mode 100644 board/mscc/ocelot/Makefile
create mode 100644 board/mscc/ocelot/ocelot.c
create mode 100644 configs/mscc_ocelot_defconfig
create mode 100644 configs/mscc_ocelot_pcb120_defconfig
create mode 100644 include/configs/vcoreiii.h
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
new file mode 100644
index 00..81afdffd4b
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7000 0x200>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ spi0: spi-master@101000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x101000 0x40>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ spi-max-frequency = <1800>; /* input clock */
+ clocks = <&ahb_clk>;
+
+ status = "disabled";
+ };
+
+ reset@1070008 {
+ compatible = "mscc
[U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel
The kernels built for the Vcore III linux kernel have different
expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 77 ---
1 file changed, 57 insertions(+), 20 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca5189e3..803d5e1de3 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
#defineLINUX_MAX_ENVS 256
#defineLINUX_MAX_ARGS 256
+enum legacy_boot_type {
+ LEGACY_BOOT_YAML,
+ LEGACY_BOOT_VCORE,
+};
+
static int linux_argc;
static char **linux_argv;
static char *linux_argp;
@@ -44,22 +49,46 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, gd->ram_top - sp);
}
-static void linux_cmdline_init(void)
+static void linux_cmdline_init(enum legacy_boot_type boot_type)
{
+ switch (boot_type) {
+ /*
+* Vcore III linux kernels expect arguments in the cached
+* address space. They also expect the command line being a
+* single string in the first argument
+*/
+ case LEGACY_BOOT_VCORE:
+ linux_argv = (char **)(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ linux_argv[1] = linux_argp;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fallthrough */
+ default:
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ }
linux_argc = 1;
- linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
linux_argv[0] = 0;
- linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
}
-static void linux_cmdline_set(const char *value, size_t len)
+static void linux_cmdline_set(const char *value, size_t len,
+ enum legacy_boot_type boot_type)
{
- linux_argv[linux_argc] = linux_argp;
memcpy(linux_argp, value, len);
- linux_argp[len] = 0;
-
+ switch (boot_type) {
+ case LEGACY_BOOT_VCORE:
+ linux_argv[linux_argc] = linux_argp;
+ linux_argp[len] = 0;
+ linux_argc++;
+ case LEGACY_BOOT_YAML:
+ /* fallthrough */
+ default:
+ linux_argp[len] = ' ';
+ linux_argp[len + 1] = 0;
+ linux_argc = 2;
+ }
linux_argp += len + 1;
- linux_argc++;
}
static void linux_cmdline_dump(void)
@@ -73,12 +102,11 @@ static void linux_cmdline_dump(void)
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void linux_cmdline_legacy(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
const char *bootargs, *next, *quote;
-
- linux_cmdline_init();
-
+ linux_cmdline_init(boot_type);
bootargs = env_get("bootargs");
if (!bootargs)
return;
@@ -104,7 +132,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
if (!next)
next = bootargs + strlen(bootargs);
- linux_cmdline_set(bootargs, next - bootargs);
+ linux_cmdline_set(bootargs, next - bootargs, boot_type);
if (*next)
next++;
@@ -113,7 +141,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
}
}
-static void linux_cmdline_append(bootm_headers_t *images)
+static void linux_cmdline_append(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
char buf[24];
ulong mem, rd_start, rd_size;
@@ -121,7 +150,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
/* append mem */
mem = gd->ram_size >> 20;
sprintf(buf, "mem=%luM", mem);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
/* append rd_start and rd_size */
rd_start = images->initrd_start;
@@ -129,9 +158,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
if (rd_size) {
sprintf(buf, "rd_start=0x%08lX", rd_start);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
sprintf(buf, "rd_size=0x%lX", rd_size);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(
[U-Boot] [PATCH v2] pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- use clrbits and setbits from MIPS
- use const and static when needed
- fix style
- use dev_remap_addr
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mscc/Kconfig | 22 +++
drivers/pinctrl/mscc/Makefile | 5 +
drivers/pinctrl/mscc/mscc-common.c| 236 ++
drivers/pinctrl/mscc/mscc-common.h| 51 ++
drivers/pinctrl/mscc/pinctrl-luton.c | 172 +++
drivers/pinctrl/mscc/pinctrl-ocelot.c | 188
8 files changed, 676 insertions(+)
create mode 100644 drivers/pinctrl/mscc/Kconfig
create mode 100644 drivers/pinctrl/mscc/Makefile
create mode 100644 drivers/pinctrl/mscc/mscc-common.c
create mode 100644 drivers/pinctrl/mscc/mscc-common.h
create mode 100644 drivers/pinctrl/mscc/pinctrl-luton.c
create mode 100644 drivers/pinctrl/mscc/pinctrl-ocelot.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8daba6..cc82f91579 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -305,6 +305,7 @@ source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/broadcom/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d163..2461dba293 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-y += mscc/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
new file mode 100644
index 00..cfc6c06076
--- /dev/null
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config PINCTRL_MSCC
+ bool
+
+config PINCTRL_MSCC_OCELOT
+ depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi ocelot family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi ocelot SoCs.
+
+config PINCTRL_MSCC_LUTON
+ depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi luton family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi luton SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
new file mode 100644
index 00..941f418ff9
--- /dev/null
+++ b/drivers/pinctrl/mscc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_PINCTRL_MSCC) += mscc-common.o
+obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
diff --git a/drivers/pinctrl/mscc/mscc-common.c
b/drivers/pinctrl/mscc/mscc-common.c
new file mode 100644
index 00..db98fc30f3
--- /dev/null
+++ b/drivers/pinctrl/mscc/mscc-common.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mscc-common.h"
+
+#define MSCC_GPIO_OUT_SET 0x0
+#define MSCC_GPIO_OUT_CLR 0x4
+#define MSCC_GPIO_OUT 0x8
+#define MSCC_GPIO_IN 0xc
+#define MSCC_GPIO_OE 0x10
+#define MSCC_GPIO_INTR 0x14
+#define MSCC_GPIO_INTR_ENA 0x18
+#define MSCC_GPIO_INTR_IDENT 0x1c
+#define MSCC_GPIO_ALT0 0x20
+#define MSCC_GPIO_ALT1 0x24
+
+static int mscc_get_functions_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_func;
+}
+
+static const char *mscc_get_function_name(struct udevice *dev,
+ unsigned int function)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->function_names[function];
+}
+
+static int mscc_pin_function_idx(unsigned int pin, unsigned int function,
+
[U-Boot] [PATCH v2] gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- use const and static when needed
- fix style
- use dev_remap_addr
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/gpio-mscc-bitbang-spi.c | 122 +++
3 files changed, 130 insertions(+)
create mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 5cd8b34400..947a59cce3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,6 +99,13 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
+config MSCC_BITBANG_SPI_GPIO
+ bool "Microsemi bitbang spi GPIO driver"
+ depends on DM_GPIO && SOC_VCOREIII
+ help
+ Support controlling the GPIO used for SPI bitbang by software. Can
+ be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f186120684..2085dd3cba 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
+obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c
b/drivers/gpio/gpio-mscc-bitbang-spi.c
new file mode 100644
index 00..b675f9052c
--- /dev/null
+++ b/drivers/gpio/gpio-mscc-bitbang-spi.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+enum {
+ SDI,
+ CS0,
+ CS1,
+ CS2,
+ CS3,
+ SDO,
+ SCK
+};
+
+static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
+
+#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
+#define SW_SPI_CS0_OE BIT(1)
+#define SW_SPI_SDO_OE BIT(9)
+#define SW_SPI_SCK_OE BIT(11)
+#define SW_PIN_CTRL_MODE BIT(13)
+
+struct mscc_bb_spi_gpio {
+ void __iomem *regs;
+ u32 cache_val;
+};
+
+static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+
+ if (val)
+ gpio->cache_val |= BIT(pinmap[oft]);
+ else
+ gpio->cache_val &= ~BIT(pinmap[oft]);
+
+ writel(gpio->cache_val, gpio->regs);
+
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
+int val)
+{
+ if (oft == 0) {
+ pr_err("SW_SPI_DSI can't be used as output\n");
+ return -ENOTSUPP;
+ }
+
+ mscc_bb_spi_gpio_set(dev, oft, val);
+
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+ u32 val = readl(gpio->regs);
+
+ return !!(val & BIT(pinmap[oft]));
+}
+
+static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
+ .direction_output = mscc_bb_spi_gpio_direction_output,
+ .direction_input= mscc_bb_spi_gpio_direction_input,
+ .set_value = mscc_bb_spi_gpio_set,
+ .get_value = mscc_bb_spi_gpio_get,
+};
+
+static int mscc_bb_spi_gpio_probe(struct udevice *dev)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ gpio->regs = dev_remap_addr(dev);
+ if (!gpio->regs)
+ return -EINVAL;
+
+ uc_priv->bank_name = dev->name;
+ uc_priv->gpio_count = ARRAY_SIZE(pinmap);
+ /*
+* Enable software mode to control the SPI pin, enables the
+* output mode for most of the pin and initialize the cache
+* value in the same time
+*/
+
+ gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
+ SW_SPI_CS0_OE;
+ writel(gpio->cache_val, gpio->regs);
+
+ return 0;
+}
+
+static const struct udevice_id mscc_bb_spi_gpi
Re: [U-Boot] [PATCH] DW SPI: Allow to overload the management of the external CS
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:17, Gregory CLEMENT wrote:
>> On some platforms, as the Ocelot ones, when wanting to control the CS
>> through software, it is not possible to do it through the GPIO
>> controller. Indeed, this signal is managed through a dedicated range of
>> registers inside the SoC..
>
> and why did you add a spi-bitbang-gpio driver?
Because the DW SPI is not available on Luton, so for Luton we can only
use a spi-bitbang-gpio driver which is very slow.
Gregory
>
>>
>> By declaring the external_cs_manage function as weak, it is possible to
>> manage the CS at platform level and then using the appropriate registers.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> drivers/spi/designware_spi.c | 8 +++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
>> index d8b73ea326..fe6e753bff 100644
>> --- a/drivers/spi/designware_spi.c
>> +++ b/drivers/spi/designware_spi.c
>> @@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
>> return 0;
>> }
>>
>> -static void external_cs_manage(struct udevice *dev, bool on)
>> +/*
>> + * We define external_cs_manage function as 'weak' as some targets
>> + * (like OCELOT) don't control the external CS pin using a GPIO
>> + * controller. These SoCs use specific registers to controll by
>> + * software the SPI pins (and especially the CS).
>> + */
>> +__weak void external_cs_manage(struct udevice *dev, bool on)
>> {
>> #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
>> struct dw_spi_priv *priv = dev_get_priv(dev->parent);
>>
>
> --
> - Daniel
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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[U-Boot] [PATCH v2] DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2
- Fix ocelot name
drivers/spi/designware_spi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index d8b73ea326..1f47ea24c8 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
return 0;
}
-static void external_cs_manage(struct udevice *dev, bool on)
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like MSCC Ocelot) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to control by
+ * software the SPI pins (and especially the CS).
+ */
+__weak void external_cs_manage(struct udevice *dev, bool on)
{
#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
struct dw_spi_priv *priv = dev_get_priv(dev->parent);
--
2.19.1
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Re: [U-Boot] [PATCH 1/2] mmc: tmio: Pass full address to tmio_sd_addr_is_dmaable()
Hi Marek,
On Tue, Oct 9, 2018 at 8:26 PM Marek Vasut wrote:
>
> Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
This statement sounds like
the current code is passing the pointer address only partially.
Is it right?
> so we don't have to apply casts throughout the code.
I do not understand this either
since I see a cast in your code too.
In the previous code, the caller casts src->address
when it passes it to tmio_sd_addr_is_dmaable().
In the new code, 'src' is casted
in tmio_sd_addr_is_dmaable().
To me, you just moved the location of casting.
What is the difference (i.e. benefit)?
If you want to change this code, I am fine.
But, I'd like to know the reason.
At least, I am so confused with your commit description.
> Signed-off-by: Marek Vasut
> Cc: Masahiro Yamada
> ---
> drivers/mmc/tmio-common.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
> index b311b80be8..6b21941991 100644
> --- a/drivers/mmc/tmio-common.c
> +++ b/drivers/mmc/tmio-common.c
> @@ -372,8 +372,10 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct
> mmc_data *data)
> }
>
> /* check if the address is DMA'able */
> -static bool tmio_sd_addr_is_dmaable(unsigned long addr)
> +static bool tmio_sd_addr_is_dmaable(const char *src)
> {
> + uintptr_t addr = (uintptr_t)src;
> +
> if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
> return false;
>
> @@ -486,7 +488,7 @@ int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd
> *cmd,
> if (data) {
> /* use DMA if the HW supports it and the buffer is aligned */
> if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
> - tmio_sd_addr_is_dmaable((long)data->src))
> + tmio_sd_addr_is_dmaable(data->src))
> ret = tmio_sd_dma_xfer(dev, data);
> else
> ret = tmio_sd_pio_xfer(dev, data);
> --
> 2.18.0
>
> ___
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> https://lists.denx.de/listinfo/u-boot
--
Best Regards
Masahiro Yamada
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[U-Boot] [RESEND PATCH v3 00/26] TF-A Boot support for NXP Chassis 2 platforms
Includes changes in u-boot framework to support TF-A for NXP Chassis 2 platforms. A new defconfig is added namely ls*_tfa_defconfig which will be used for all boot sources when TF-A is used. Tested on LS1043A, LS1046A and LS1012A platforms. Changes in v3: - Changed order of TFABOOT dependent patches - Merged secureboot TFA boot support patches - Merged nand env patches to remove warning Changes in v2: - Patch subject and description changes - Removed extra CONFIG_TFABOOT flag usage - Merged board specific TFA boot support patches - Checked compilation using buildman tool for each commit Pankit Garg (5): armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 drivers: ifc: dynamic chipselect mapping support armv8: fsl-layerscape: bootcmd identification for TFABOOT armv8: sec_firmware: return job ring status as true in TFABOOT armv8: fsl-layerscape: add support of MC framework for TFA Rajesh Bhagat (17): env: allow flash and nand env driver to compile together env: sf: define API to override sf environment address driver/ifc: replace __ilog2 with LOG2 macro armv8: layerscape: Add TFABOOT support armv8: fsl-layerscape: identify boot source from PORSR register armv8: layerscape: remove EL3 specific erratas for TFABOOT armv8: layerscape: add SMC calls for DDR size and bank info armv8: layerscape: skip OCRAM init for TFABOOT armv8: sec_firmware: change el2_to_aarch32 SMC ID net: fm: add TFABOOT support drivers: qe: add TFABOOT support armv8: ls1046ardb: Add TFABOOT support armv8: ls1046aqds: Add TFABOOT support armv8: ls1043ardb: Add TFABOOT support armv8: ls1043aqds: Add TFABOOT support armv8: ls1012ardb: Add TFABOOT support armv8: ls1012aqds: Add TFABOOT support Vinitha V Pillai (1): armv8: ls1012a: fix secure boot compilation York Sun (3): move data structure out of cpu.h armv8: layerscape: Enable routing SError exception armv8: fsl-layerscape: Update parsing boot source arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 31 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 613 +- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 12 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 128 arch/arm/cpu/armv8/sec_firmware.c | 4 + arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 - .../asm/arch-fsl-layerscape/immap_lsch2.h | 20 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 49 ++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 22 + board/freescale/ls1012aqds/Kconfig| 10 + board/freescale/ls1012aqds/ls1012aqds.c | 23 +- board/freescale/ls1012ardb/Kconfig| 4 + board/freescale/ls1012ardb/ls1012ardb.c | 16 +- board/freescale/ls1043aqds/ddr.c | 11 + board/freescale/ls1043aqds/ls1043aqds.c | 147 - board/freescale/ls1043ardb/ddr.c | 14 + board/freescale/ls1043ardb/ls1043ardb.c | 110 board/freescale/ls1046aqds/ddr.c | 11 + board/freescale/ls1046aqds/ls1046aqds.c | 148 - board/freescale/ls1046ardb/ddr.c | 12 + configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 65 ++ configs/ls1012aqds_tfa_defconfig | 62 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 63 ++ configs/ls1012ardb_tfa_defconfig | 56 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 58 ++ configs/ls1043aqds_tfa_defconfig | 54 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 51 ++ configs/ls1043ardb_tfa_defconfig | 49 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 58 ++ configs/ls1046aqds_tfa_defconfig | 57 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 52 ++ configs/ls1046ardb_tfa_defconfig | 49 ++ drivers/misc/fsl_ifc.c| 488 ++ drivers/net/fm/fm.c | 102 ++- drivers/qe/qe.c | 81 +++ env/flash.c | 4 +- env/nand.c| 6 +- env/sf.c | 9 +- include/configs/B4860QDS.h| 2 +- include/configs/T102xQDS.h| 2 +- include/configs/T1040QDS.h| 2 +- include/configs/T208xQDS.h| 2 +- include/configs/T4240QDS.h| 2 +- include/configs/T4240RDB.h| 2 +- include/configs/ls1012a_common.h | 16 +- include/configs/ls1012aqds.h | 1 + include/configs/ls1012ardb.h | 6 + include/configs/ls1043a_common.h | 27 +- include/configs/ls1043aqds.h | 50 +- include/configs/ls1043ardb.h
[U-Boot] [RESEND PATCH v3 01/26] move data structure out of cpu.h
From: York Sun
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 297 +
.../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 --
2 files changed, 297 insertions(+), 300 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 052e0708d4..bae50f68d8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,303 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+ CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+ CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+ CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+ CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+ CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+ CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+ CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
+ CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+ CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+ CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+ CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+ CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
+};
+
+#define EARLY_PGTABLE_SIZE 0x5000
+static struct mm_region early_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#ifdef CONFIG_FSL_IFC
+ /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ SYS_FSL_OCRAM_SPACE_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_F
[U-Boot] [RESEND PATCH v3 02/26] env: allow flash and nand env driver to compile together
Define env_ptr as static in flash and nand env driver to allow these to compile together. Signed-off-by: Rajesh Bhagat --- Change in v3: - Merged env nand specific patches to remove compilation warning Change in v2: None env/flash.c | 4 ++-- env/nand.c| 6 ++ include/environment.h | 1 - 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/env/flash.c b/env/flash.c index 32236c716e..33b199f05b 100644 --- a/env/flash.c +++ b/env/flash.c @@ -45,13 +45,13 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifdef ENV_IS_EMBEDDED -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; #else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; +static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; #endif /* ENV_IS_EMBEDDED */ diff --git a/env/nand.c b/env/nand.c index 3698e68957..29eda66fad 100644 --- a/env/nand.c +++ b/env/nand.c @@ -40,11 +40,9 @@ #endif #if defined(ENV_IS_EMBEDDED) -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) -env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; -#else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr; +static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; #endif /* ENV_IS_EMBEDDED */ DECLARE_GLOBAL_DATA_PTR; diff --git a/include/environment.h b/include/environment.h index 5e90f157e8..7da1291d5b 100644 --- a/include/environment.h +++ b/include/environment.h @@ -157,7 +157,6 @@ extern env_t environment; #endif /* ENV_IS_EMBEDDED */ extern const unsigned char default_environment[]; -extern env_t *env_ptr; #if defined(CONFIG_NEEDS_MANUAL_RELOC) extern void env_reloc(void); -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RESEND PATCH v3 03/26] env: sf: define API to override sf environment address
Defines env_sf_get_env_addr API to override sf environment address,
required to support multiple environment.
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
env/sf.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index 494510533a..df22fd520b 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -297,10 +297,17 @@ out:
}
#endif
+#ifdef CONFIG_ENV_ADDR
+__weak void *env_sf_get_env_addr(void)
+{
+ return (void *)CONFIG_ENV_ADDR;
+}
+#endif
+
#if defined(INITENV) && defined(CONFIG_ENV_ADDR)
static int env_sf_init(void)
{
- env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR);
+ env_t *env_ptr = (env_t *)env_sf_get_env_addr();
if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
gd->env_addr= (ulong)&(env_ptr->data);
--
2.17.1
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[U-Boot] [RESEND PATCH v3 06/26] armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
From: Pankit Garg Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta Signed-off-by: Pankit Garg --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bae50f68d8..6304825180 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -371,7 +371,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el(); /* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RESEND PATCH v3 14/26] armv8: fsl-layerscape: Update parsing boot source
From: York Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.
Signed-off-by: York Sun
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 26 ---
.../arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ca5329f25c..2e3494bee4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1)
}
}
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
+ src = BOOT_SOURCE_QSPI_NOR;
+
debug("%s: src 0x%x\n", __func__, src);
return src;
}
enum boot_src get_boot_src(void)
{
- u32 porsr1;
+ struct pt_regs regs;
+ u32 porsr1 = 0;
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
-
- porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#endif
+
+ if (current_el() == 2) {
+ regs.regs[0] = SIP_SVC_RCW;
- porsr1 = in_be32(&gur->porsr1);
+ smc_call(®s);
+ if (!regs.regs[0])
+ porsr1 = regs.regs[1];
+ }
+
+ if (current_el() == 3 || !porsr1) {
+#ifdef CONFIG_FSL_LSCH3
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ porsr1 = in_be32(&gur->porsr1);
#endif
+ }
+
debug("%s: porsr1 0x%x\n", __func__, porsr1);
return __get_boot_src(porsr1);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index ef228b6443..daa1c70b3a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -56,6 +56,7 @@ struct cpu_type {
#ifdef CONFIG_TFABOOT
#define SMC_DRAM_BANK_INFO (0xC200FF12)
+#define SIP_SVC_RCW0xC200FF18
phys_size_t tfa_get_dram_size(void);
--
2.17.1
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[U-Boot] [RESEND PATCH v3 05/26] armv8: layerscape: Enable routing SError exception
From: York Sun In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index ef3987ea84..11b5fb2ec3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f/* skip if not in EL3 */ 1: -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RESEND PATCH v3 04/26] driver/ifc: replace __ilog2 with LOG2 macro
Replaces __ilog2 function call with LOG2 macro, required to use macros in global variables. Also, corrects the value passed in LOG2 for some PowerPC platforms. Minimum value that can be configured is is 64K for IFC IP. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat --- Change in v3: None Change in v2: None include/configs/B4860QDS.h | 2 +- include/configs/T102xQDS.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T4240QDS.h | 2 +- include/configs/T4240RDB.h | 2 +- include/fsl_ifc.h | 10 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c37864c139..be7ee8e433 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -286,7 +286,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 8a38c5e19c..e4a14792a2 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -299,7 +299,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index e890860b7e..0498d7891b 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -225,7 +225,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 7d9354b360..8d358c9285 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -275,7 +275,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index f85881fc3c..0b469b1477 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -201,7 +201,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9d8834a3be..27bd145b52 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -470,7 +470,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0de8..17697c7341 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0x #define IFC_AMASK_SHIFT16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x0700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n)((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#def
[U-Boot] [RESEND PATCH v3 08/26] armv8: layerscape: Add TFABOOT support
Adds TFABOOT support config option and add generic code to enable
execution from DDR.
Signed-off-by: York Sun
Signed-off-by: Rajesh Bhagat
---
Change in v3:
- Seperated TFABOOT generic code
- Moved before dependency patches
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f2111fadc0..9092757d1f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex
use
pins, select it when the pins are assigned to USB.
+
+config TFABOOT
+ bool "Support for booting from TFA"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via TFA.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6304825180..3e084eddfa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -88,7 +88,8 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -139,7 +140,8 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -1236,7 +1238,8 @@ void update_early_mmu_table(void)
__weak int dram_init(void)
{
fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+ defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
--
2.17.1
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[U-Boot] [RESEND PATCH v3 26/26] armv8: ls1012a: fix secure boot compilation
From: Vinitha V Pillai Includes environment.h file in ls1012aqds.c Also, enables pfe validation in ls1012ardb. Signed-off-by: Vinitha V Pillai --- Change in v3: None Change in v2: None board/freescale/ls1012aqds/Kconfig | 10 ++ board/freescale/ls1012aqds/ls1012aqds.c | 6 ++ board/freescale/ls1012ardb/Kconfig | 4 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 + include/configs/ls1012aqds.h | 1 + 5 files changed, 22 insertions(+) diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index b702fb2740..8844557aae 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -16,6 +16,12 @@ config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x4040 +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x4068 +endif + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy @@ -33,6 +39,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a0 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x4070 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x0380 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 1187bd130e..a862fe6a93 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -18,12 +18,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" @@ -132,6 +134,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 4cd66bd548..51efd0fa37 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -33,6 +33,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a0 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x4070 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x0380 diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 1161ae8d0f..3754931702 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -44,6 +44,7 @@ CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_FSL_PFE=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index c5bdea6798..c76bfdc8f8 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -117,4 +117,5 @@ #define CONFIG_SYS_MEMTEST_START 0x8000 #define CONFIG_SYS_MEMTEST_END 0x9fff +#include #endif /* __LS1012AQDS_H__ */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RESEND PATCH v3 10/26] armv8: layerscape: remove EL3 specific erratas for TFABOOT
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803 SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat --- Change in v3: None Change in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9092757d1f..1872c66dcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -62,17 +62,17 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RESEND PATCH v3 11/26] armv8: fsl-layerscape: bootcmd identification for TFABOOT
From: Pankit Garg
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3:
- Merged secure boot bootcmd changes
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 78 +
2 files changed, 92 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 5f56897ab0..6c1b1ffec8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,9 @@
#ifdef CONFIG_TFABOOT
#include
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include
+#endif
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -741,6 +744,14 @@ enum env_location env_get_location(enum env_operation op,
int prio)
if (prio)
return ENVL_UNKNOWN;
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* Check Boot Mode
+* If Boot Mode is Secure, return ENVL_NOWHERE
+*/
+ if (fsl_check_boot_mode_secure() == 1)
+ goto done;
+#endif
+
switch (src) {
case BOOT_SOURCE_IFC_NOR:
env_loc = ENVL_FLASH;
@@ -768,6 +779,9 @@ enum env_location env_get_location(enum env_operation op,
int prio)
break;
}
+#ifdef CONFIG_CHAIN_OF_TRUST
+done:
+#endif
return env_loc;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3f15cb08ff..d6c336548f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -24,6 +24,10 @@
#include
#endif
#include
+#ifdef CONFIG_TFABOOT
+#include
+DECLARE_GLOBAL_DATA_PTR;
+#endif
bool soc_has_dp_ddr(void)
{
@@ -679,12 +683,86 @@ int qspi_ahb_init(void)
}
#endif
+#ifdef CONFIG_TFABOOT
+#define MAX_BOOTCMD_SIZE 256
+
+int fsl_setenv_bootcmd(void)
+{
+ int ret;
+ enum boot_src src = get_boot_src();
+ char bootcmd_str[MAX_BOOTCMD_SIZE];
+
+ switch (src) {
+#ifdef IFC_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NOR:
+ sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NOR:
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NOR:
+ sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef IFC_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NAND:
+ sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NAND:
+ sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NAND:
+ sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC:
+ sprintf(bootcmd_str, SD_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD2_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC2:
+ sprintf(bootcmd_str, SD2_BOOTCOMMAND);
+ break;
+#endif
+ default:
+#ifdef QSPI_NOR_BOOTCOMMAND
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+#endif
+ break;
+ }
+
+ ret = env_set("bootcmd", bootcmd_str);
+ if (ret) {
+ printf("Failed to set bootcmd: ret = %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
+#ifdef CONFIG_TFABOOT
+ /*
+* check if gd->env_addr is default_environment; then setenv bootcmd
+*/
+ if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
+ fsl_setenv_bootcmd();
+ }
+#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
#endif
--
2.17.1
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[U-Boot] [RESEND PATCH v3 09/26] armv8: fsl-layerscape: identify boot source from PORSR register
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.
Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 190 ++
.../asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++
.../asm/arch-fsl-layerscape/immap_lsch3.h | 49 +
.../arm/include/asm/arch-fsl-layerscape/soc.h | 17 ++
4 files changed, 276 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3e084eddfa..5f56897ab0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -31,6 +31,10 @@
#include
#include
+#ifdef CONFIG_TFABOOT
+#include
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static struct cpu_type cpu_type_list[] = {
@@ -581,7 +585,193 @@ void enable_caches(void)
icache_enable();
dcache_enable();
}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+#ifdef CONFIG_TFABOOT
+enum boot_src __get_boot_src(u32 porsr1)
+{
+ enum boot_src src = BOOT_SOURCE_RESERVED;
+ uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
+#if !defined(CONFIG_FSL_LSCH3_2)
+ uint32_t val;
+#endif
+ debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
+
+#if defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_FSL_LSCH3_2)
+ switch (rcw_src) {
+ case RCW_SRC_SDHC1_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_SDHC2_VAL:
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ case RCW_SRC_FLEXSPI_NAND2K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_FLEXSPI_NAND4K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_RESERVED_1_VAL:
+ src = BOOT_SOURCE_RESERVED;
+ break;
+ case RCW_SRC_FLEXSPI_NOR_24B:
+ src = BOOT_SOURCE_XSPI_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+#else
+ val = rcw_src & RCW_SRC_TYPE_MASK;
+ if (val == RCW_SRC_NOR_VAL) {
+ val = rcw_src & NOR_TYPE_MASK;
+
+ switch (val) {
+ case NOR_16B_VAL:
+ case NOR_32B_VAL:
+ src = BOOT_SOURCE_IFC_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ } else {
+ /* RCW SRC Serial Flash */
+ val = rcw_src & RCW_SRC_SERIAL_MASK;
+ switch (val) {
+ case RCW_SRC_QSPI_VAL:
+ /* RCW SRC Serial NOR (QSPI) */
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case RCW_SRC_SD_CARD_VAL:
+ /* RCW SRC SD Card */
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_EMMC_VAL:
+ /* RCW SRC EMMC */
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ /* RCW SRC I2C1 Extended */
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+#endif
+#elif defined(CONFIG_FSL_LSCH2)
+ /* RCW SRC NAND */
+ val = rcw_src & RCW_SRC_NAND_MASK;
+ if (val == RCW_SRC_NAND_VAL) {
+ val = rcw_src & NAND_RESERVED_MASK;
+ if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+ src = BOOT_SOURCE_IFC_NAND;
+ }
+ } else {
+ /* RCW SRC NOR */
+ val = rcw_src & RCW_SRC_NOR_MASK;
+ if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+ src = BOOT_SOURCE_IFC_NOR;
+ } else {
+ switch (rcw_src) {
+ case QSPI_VAL1:
+ case QSPI_VAL2:
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case SD_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+ }
#endif
+ debug("%s: src 0x%x\n", __func__, src);
+ return src;
+}
+
+enum boot_src get_boot_src(void)
+{
+ u32 porsr1;
+
+#if defined(CONFIG_FSL_LSCH3)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ por
[U-Boot] [RESEND PATCH v3 12/26] armv8: layerscape: add SMC calls for DDR size and bank info
Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
---
Change in v3: None
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 84 +++
.../arm/include/asm/arch-fsl-layerscape/soc.h | 4 +
2 files changed, 88 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6c1b1ffec8..ca5329f25c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1230,12 +1230,96 @@ phys_size_t get_effective_memsize(void)
return ea_size;
}
+#ifdef CONFIG_TFABOOT
+phys_size_t tfa_get_dram_size(void)
+{
+ struct pt_regs regs;
+ phys_size_t dram_size = 0;
+
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = -1;
+
+ smc_call(®s);
+ if (regs.regs[0])
+ return 0;
+
+ dram_size = regs.regs[1];
+ return dram_size;
+}
+
+static int tfa_dram_init_banksize(void)
+{
+ int i = 0, ret = 0;
+ struct pt_regs regs;
+ phys_size_t dram_size = tfa_get_dram_size();
+
+ debug("dram_size %llx\n", dram_size);
+
+ if (!dram_size)
+ return -EINVAL;
+
+ do {
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = i;
+
+ smc_call(®s);
+ if (regs.regs[0]) {
+ ret = -EINVAL;
+ break;
+ }
+
+ debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
+ regs.regs[2]);
+ gd->bd->bi_dram[i].start = regs.regs[1];
+ gd->bd->bi_dram[i].size = regs.regs[2];
+
+ dram_size -= gd->bd->bi_dram[i].size;
+
+ i++;
+ } while (dram_size);
+
+ if (i > 0)
+ ret = 0;
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+ /* Assign memory for MC */
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bd->bi_dram[2].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[2].start +
+ gd->bd->bi_dram[2].size -
+ board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ } else
+#endif
+ {
+ if (gd->bd->bi_dram[1].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[1].start +
+ gd->bd->bi_dram[1].size -
+ board_reserve_ram_top(gd->bd->bi_dram[1].size);
+ } else if (gd->bd->bi_dram[0].size >
+ board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size -
+ board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ }
+ }
+#endif /* CONFIG_FSL_MC_ENET */
+
+ return ret;
+}
+#endif
+
int dram_init_banksize(void)
{
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
phys_size_t dp_ddr_size;
#endif
+#ifdef CONFIG_TFABOOT
+ if (!tfa_dram_init_banksize())
+ return 0;
+#endif
/*
* gd->ram_size has the total size of DDR memory, less reserved secure
* memory. The DDR extends from low region to high region(s) presuming
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index d327c7ba1f..ef228b6443 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -55,6 +55,10 @@ struct cpu_type {
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#ifdef CONFIG_TFABOOT
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+phys_size_t tfa_get_dram_size(void);
+
enum boot_src {
BOOT_SOURCE_RESERVED = 0,
BOOT_SOURCE_IFC_NOR,
--
2.17.1
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