[U-Boot] [PATCH] misc: Makefile: Add condition on build i2c_eeprom

[Wenyou Yang]

The i2c_eeprom isn't always necessary when building for SPL,
add the condition on build i2c_eeprom.

Signed-off-by: Wenyou Yang 
---

 drivers/misc/Makefile | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 10265c8fb4..ccc84c38fc 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,7 +20,13 @@ obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
 endif
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
+ifdef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_SPL_I2C_SUPPORT),)
+obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
+endif
+else
 obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
+endif
 obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
-- 
2.13.0

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[U-Boot] [PATCH v3 0/3] board: atmel: Set the ethernet mac address from eeprom

[Wenyou Yang]

Create board/$(VENDOR)/common folder to accommodate the common code
for the boards from atmel. Now put the code to set the ethernet mac
address here, using the function to set the ethernet mac address
on sama5d2 and sama5d4 Xplained boards.

Changes in v3:
 - remove CONFIG_SPL_I2C_SUPPORT=y from the default configuration files.
 - rebase on [PATCH] misc: Makefile: Add condition on build i2c_eeprom.
https://lists.denx.de/pipermail/u-boot/2017-August/300783.html

Changes in v2:
 - Add a new patch to create board/$(VENDOR)/common folder to
   accommodate the common code and put the code to set the ethernet
   mac address from eeprom here.
 - Use the i2c_eeprom driver to read the mac address, instead of
   the dm i2c API directly.

Wenyou Yang (3):
  board: atmel: Create board/$(VENDOR)/common folder
  board: sama5d2_xplained: Replace code to set mac address
  board: sama5d4_xplained: Set mac address from eeprom

 arch/arm/dts/at91-sama5d2_xplained.dts  |  5 +++
 arch/arm/dts/at91-sama5d4_xplained.dts  |  5 +++
 arch/arm/mach-at91/include/mach/at91_common.h   |  2 ++
 board/atmel/common/Makefile | 11 ++
 board/atmel/common/board.c  | 12 +++
 board/atmel/common/mac_eeprom.c | 36 +++
 board/atmel/sama5d2_xplained/sama5d2_xplained.c | 47 +++--
 board/atmel/sama5d4_xplained/sama5d4_xplained.c | 12 +++
 configs/sama5d2_xplained_mmc_defconfig  |  1 +
 configs/sama5d2_xplained_spiflash_defconfig |  1 +
 configs/sama5d4_xplained_mmc_defconfig  |  3 ++
 configs/sama5d4_xplained_nandflash_defconfig|  3 ++
 configs/sama5d4_xplained_spiflash_defconfig |  3 ++
 include/configs/sama5d2_xplained.h  |  4 ---
 include/configs/sama5d4_xplained.h  |  2 ++
 15 files changed, 100 insertions(+), 47 deletions(-)
 create mode 100644 board/atmel/common/Makefile
 create mode 100644 board/atmel/common/board.c
 create mode 100644 board/atmel/common/mac_eeprom.c

-- 
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[U-Boot] [PATCH v3 2/3] board: sama5d2_xplained: Replace code to set mac address

[Wenyou Yang]

Replace the code to set the ethernet mac address with the code from
the common folder.

Signed-off-by: Wenyou Yang 
---

Changes in v3: None
Changes in v2: None

 arch/arm/dts/at91-sama5d2_xplained.dts  |  5 +++
 board/atmel/sama5d2_xplained/sama5d2_xplained.c | 47 +++--
 configs/sama5d2_xplained_mmc_defconfig  |  1 +
 configs/sama5d2_xplained_spiflash_defconfig |  1 +
 include/configs/sama5d2_xplained.h  |  4 ---
 5 files changed, 11 insertions(+), 47 deletions(-)

diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts 
b/arch/arm/dts/at91-sama5d2_xplained.dts
index 3e624f142c..b00aaa2c79 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -102,6 +102,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
+
+   i2c_eeprom: i2c_eeprom@5c {
+   compatible = "atmel,24mac402";
+   reg = <0x5c>;
+   };
};
 
pioA: gpio@fc038000 {
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c 
b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 48f45b35ce..fce931d95f 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -8,8 +8,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -161,51 +159,14 @@ int dram_init(void)
return 0;
 }
 
-#ifdef CONFIG_CMD_I2C
-static int set_ethaddr_from_eeprom(void)
-{
-   const int ETH_ADDR_LEN = 6;
-   unsigned char ethaddr[ETH_ADDR_LEN];
-   const char *ETHADDR_NAME = "ethaddr";
-   struct udevice *bus, *dev;
-
-   if (getenv(ETHADDR_NAME))
-   return 0;
-
-   if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
-   printf("Cannot find I2C bus 1\n");
-   return -1;
-   }
-
-   if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
-   printf("Failed to probe I2C chip\n");
-   return -1;
-   }
-
-   if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
-   printf("Failed to read ethernet address from EEPROM\n");
-   return -1;
-   }
-
-   if (!is_valid_ethaddr(ethaddr)) {
-   printf("The ethernet address read from EEPROM is not valid!\n");
-   return -1;
-   }
-
-   return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
-}
-#else
-static int set_ethaddr_from_eeprom(void)
-{
-   return 0;
-}
-#endif
+#define AT24MAC_MAC_OFFSET 0x9a
 
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r(void)
 {
-   set_ethaddr_from_eeprom();
-
+#ifdef CONFIG_I2C_EEPROM
+   at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
return 0;
 }
 #endif
diff --git a/configs/sama5d2_xplained_mmc_defconfig 
b/configs/sama5d2_xplained_mmc_defconfig
index e9a65ccb9d..3667ddfd14 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -49,6 +49,7 @@ CONFIG_DM_GPIO=y
 CONFIG_ATMEL_PIO4=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ATMEL=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig 
b/configs/sama5d2_xplained_spiflash_defconfig
index 8b9c0ccd2a..343c96b92a 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -47,6 +47,7 @@ CONFIG_DM_GPIO=y
 CONFIG_ATMEL_PIO4=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ATMEL=y
diff --git a/include/configs/sama5d2_xplained.h 
b/include/configs/sama5d2_xplained.h
index 42fb1e11d0..bcddd5b0fe 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -38,10 +38,6 @@
 /* NAND flash */
 #undef CONFIG_CMD_NAND
 
-/* I2C */
-#define AT24MAC_ADDR   0x5c
-#define AT24MAC_REG0x9a
-
 /* LCD */
 
 #ifdef CONFIG_LCD
-- 
2.13.0

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[U-Boot] [PATCH v3 1/3] board: atmel: Create board/$(VENDOR)/common folder

[Wenyou Yang]

Create board/$(VENDOR)/common folder to accommodate the common code
shared by other atmel boards, now put the code to set ethernet mac
address from eeprom, which uses the i2c eeprom driver.

Signed-off-by: Wenyou Yang 
---

Changes in v3: None
Changes in v2: None

 arch/arm/mach-at91/include/mach/at91_common.h |  2 ++
 board/atmel/common/Makefile   | 11 
 board/atmel/common/board.c| 12 +
 board/atmel/common/mac_eeprom.c   | 36 +++
 4 files changed, 61 insertions(+)
 create mode 100644 board/atmel/common/Makefile
 create mode 100644 board/atmel/common/board.c
 create mode 100644 board/atmel/common/mac_eeprom.c

diff --git a/arch/arm/mach-at91/include/mach/at91_common.h 
b/arch/arm/mach-at91/include/mach/at91_common.h
index 0742ffc56f..a95fe41610 100644
--- a/arch/arm/mach-at91/include/mach/at91_common.h
+++ b/arch/arm/mach-at91/include/mach/at91_common.h
@@ -36,4 +36,6 @@ void matrix_init(void);
 void redirect_int_from_saic_to_aic(void);
 void configure_2nd_sram_as_l2_cache(void);
 
+int at91_set_ethaddr(int offset);
+
 #endif /* AT91_COMMON_H */
diff --git a/board/atmel/common/Makefile b/board/atmel/common/Makefile
new file mode 100644
index 00..6d9c6850b5
--- /dev/null
+++ b/board/atmel/common/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017 Microchip
+#Wenyou Yang 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
+endif
diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c
new file mode 100644
index 00..7e326d925b
--- /dev/null
+++ b/board/atmel/common/board.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2017 Microchip
+ *   Wenyou Yang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+void dummy(void)
+{
+}
diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c
new file mode 100644
index 00..cdb786249c
--- /dev/null
+++ b/board/atmel/common/mac_eeprom.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 Microchip
+ *   Wenyou Yang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int at91_set_ethaddr(int offset)
+{
+   const int ETH_ADDR_LEN = 6;
+   unsigned char ethaddr[ETH_ADDR_LEN];
+   const char *ETHADDR_NAME = "ethaddr";
+   struct udevice *dev;
+   int ret;
+
+   if (getenv(ETHADDR_NAME))
+   return 0;
+
+   ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+   if (ret)
+   return ret;
+
+   ret = i2c_eeprom_read(dev, offset, ethaddr, 6);
+   if (ret)
+   return ret;
+
+   if (is_valid_ethaddr(ethaddr))
+   eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
+
+   return 0;
+}
-- 
2.13.0

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[U-Boot] [PATCH v3 3/3] board: sama5d4_xplained: Set mac address from eeprom

[Wenyou Yang]

Add the code to set the ethernet mac address from eeprom by using
the common code from the common folder.

Signed-off-by: Wenyou Yang 
configs: sama5d4_xplained: remove CONFIG_SPL_I2C_SUPPORT

---

Changes in v3:
 - remove CONFIG_SPL_I2C_SUPPORT=y from the default configuration files.
 - rebase on [PATCH] misc: Makefile: Add condition on build i2c_eeprom.
https://lists.denx.de/pipermail/u-boot/2017-August/300783.html

Changes in v2:
 - Add a new patch to create board/$(VENDOR)/common folder to
   accommodate the common code and put the code to set the ethernet
   mac address from eeprom here.
 - Use the i2c_eeprom driver to read the mac address, instead of
   the dm i2c API directly.

 arch/arm/dts/at91-sama5d4_xplained.dts  |  5 +
 board/atmel/sama5d4_xplained/sama5d4_xplained.c | 12 
 configs/sama5d4_xplained_mmc_defconfig  |  3 +++
 configs/sama5d4_xplained_nandflash_defconfig|  3 +++
 configs/sama5d4_xplained_spiflash_defconfig |  3 +++
 include/configs/sama5d4_xplained.h  |  2 ++
 6 files changed, 28 insertions(+)

diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts 
b/arch/arm/dts/at91-sama5d4_xplained.dts
index ca6aff28e5..0592b31b91 100644
--- a/arch/arm/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/dts/at91-sama5d4_xplained.dts
@@ -88,6 +88,11 @@
 
i2c0: i2c@f8014000 {
status = "okay";
+
+   i2c_eeprom: i2c_eeprom@5c {
+   compatible = "atmel,24mac402";
+   reg = <0x5c>;
+   };
};
 
macb0: ethernet@f802 {
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c 
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 854afcb622..248a31b8c4 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -192,6 +192,18 @@ int board_early_init_f(void)
 }
 #endif
 
+#define AT24MAC_MAC_OFFSET 0x9a
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+   at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* adress of boot parameters */
diff --git a/configs/sama5d4_xplained_mmc_defconfig 
b/configs/sama5d4_xplained_mmc_defconfig
index 094e5e1c2d..08e50feabe 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -44,6 +44,9 @@ CONFIG_AT91_UTMI=y
 CONFIG_AT91_H32MX=y
 CONFIG_DM_GPIO=y
 CONFIG_AT91_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig 
b/configs/sama5d4_xplained_nandflash_defconfig
index a096aa929c..0f43160aa4 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -41,6 +41,9 @@ CONFIG_AT91_UTMI=y
 CONFIG_AT91_H32MX=y
 CONFIG_DM_GPIO=y
 CONFIG_AT91_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig 
b/configs/sama5d4_xplained_spiflash_defconfig
index bd884b73c8..780d476001 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -43,6 +43,9 @@ CONFIG_AT91_UTMI=y
 CONFIG_AT91_H32MX=y
 CONFIG_DM_GPIO=y
 CONFIG_AT91_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/include/configs/sama5d4_xplained.h 
b/include/configs/sama5d4_xplained.h
index f1cf65f42c..67a8574940 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -12,6 +12,8 @@
 
 #include "at91-sama5_common.h"
 
+#define CONFIG_MISC_INIT_R
+
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_SYS_SDRAM_BASE   ATMEL_BASE_DDRCS
-- 
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[U-Boot] [PATCH] timer: Add Atmel PIT timer driver

[Wenyou Yang]

Add Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang 
---

 arch/arm/mach-at91/arm926ejs/Makefile |  2 +
 arch/arm/mach-at91/armv7/Makefile |  2 +
 drivers/timer/Kconfig |  8 
 drivers/timer/Makefile|  1 +
 drivers/timer/atmel_pit_timer.c   | 90 +++
 5 files changed, 103 insertions(+)
 create mode 100644 drivers/timer/atmel_pit_timer.c

diff --git a/arch/arm/mach-at91/arm926ejs/Makefile 
b/arch/arm/mach-at91/arm926ejs/Makefile
index 624ccd7c2f..dc935fd9e5 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -22,7 +22,9 @@ obj-y += cache.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y  += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y  += timer.o
+endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y  += lowlevel_init.o
diff --git a/arch/arm/mach-at91/armv7/Makefile 
b/arch/arm/mach-at91/armv7/Makefile
index 9538bc1fad..1ede4cb10a 100644
--- a/arch/arm/mach-at91/armv7/Makefile
+++ b/arch/arm/mach-at91/armv7/Makefile
@@ -14,4 +14,6 @@ obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y += timer.o
+endif
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 17e7dfe245..92c19495d6 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -26,6 +26,14 @@ config ALTERA_TIMER
  Select this to enable a timer for Altera devices. Please find
  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ATMEL_PIT_TIMER
+   bool "Atmel periodic interval timer support"
+   depends on TIMER
+   help
+ Select this to enable a periodic interval timer for Atmel devices,
+ it is designed to offer maximum accuracy and efficient management,
+ even for systems with long response time.
+
 config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index ced7bd66bd..7db04fcdf8 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_STI_TIMER)   += sti-timer.o
 obj-$(CONFIG_ARC_TIMER)+= arc_timer.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
new file mode 100644
index 00..999717b91f
--- /dev/null
+++ b/drivers/timer/atmel_pit_timer.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ *   Wenyou.Yang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define AT91_PIT_VALUE 0xf
+#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
+
+struct atmel_pit_regs {
+   u32 mode;
+   u32 status;
+   u32 value;
+   u32 value_image;
+};
+
+struct atmel_pit_platdata {
+   struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+   struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+   struct atmel_pit_regs *const regs = plat->regs;
+   u32 val = readl(®s->value_image);
+
+   *count = timer_conv_64(val);
+
+   return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+   struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+   struct atmel_pit_regs *const regs = plat->regs;
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct clk clk;
+   ulong clk_rate;
+   int ret;
+
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (ret)
+   return -EINVAL;
+
+   clk_rate = clk_get_rate(&clk);
+   if (!clk_rate)
+   return -EINVAL;
+
+   uc_priv->clock_rate = clk_rate / 16;
+
+   writel(AT91_PIT_VALUE | AT91_PIT_PITEN, ®s->mode);
+
+   return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+   struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+   plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+   return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+   .get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+   { .compatible = "atmel,at91sam9260-pit" },
+   { }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+   .name   = "atmel_pit",
+   .id = UCLASS_TIMER,
+   .of_match = atmel_pit_ids,
+   .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+   .probe  = atmel_pit_probe,
+   .ops= &atmel_pit_ops,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.13.0

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Re: [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its

[Dr. Philipp Tomsich]

Kever,

We use a fork of the ATF repository and have the M3 firmware completely 
factored out and have changed parts of the SRAM setup.
In other words: there will be two separate .bin files created that need to be 
loaded to two separate locations.
Please refer to our board’s README for the steps to get it set up and booted.

Note that there will be a structural update to our ATF in the next couple of 
weeks that is expected to change things around quite a bit.

Regards,
Philipp.

> On 02 Aug 2017, at 05:10, Kever Yang  wrote:
> 
> Hi Philipp,
> 
>rk3399 atf has 3 parts, sram.data, sram.text, pmu_fw for m0, and now the 
> ATF project output
> 
> with all 3 section in one bl31.elf, I use to abstract them into 3 separate 
> bin file and package them
> 
> with fit.
> 
>Could you share some more detail about how you use the ATF in puma-rk3399? 
> You only have
> 
> two section in its description. How many steps do you need for rk3399 to get 
> uboot, atf and the image
> 
> can be flash to eMMC?
> 
> Thanks,
> - Kever
> On 07/29/2017 03:22 AM, Philipp Tomsich wrote:
>> The ITS file generated warnings due to @ designations in the naming
>> which cause DTC to complain as follows:
>>   Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but 
>> no reg property
>>   Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no 
>> reg property
>>   Warning (unit_address_vs_reg): Node /images/pmu@1 has a unit name, but no 
>> reg property
>>   Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no 
>> reg property
>>   Warning (unit_address_vs_reg): Node /configurations/conf@1 has a unit 
>> name, but no reg property
>> 
>> This removes the @ part from the names, as we only have a single
>> image for each payload aspect (and only a single configuration) anyway.
>> 
>> Signed-off-by: Philipp Tomsich 
>> 
>> Reviewed-by: Simon Glass 
>> ---
>> 
>> Changes in v3: None
>> Changes in v2: None
>> 
>>  board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +-
>>  1 file changed, 9 insertions(+), 9 deletions(-)
>> 
>> diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its 
>> b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
>> index f93c251..0519fad 100644
>> --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
>> +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
>> @@ -13,7 +13,7 @@
>>  #address-cells = <1>;
>>  images {
>> -uboot@1 {
>> +uboot {
>>  description = "U-Boot (64-bit)";
>>  data = /incbin/("../../../u-boot-nodtb.bin");
>>  type = "standalone";
>> @@ -21,7 +21,7 @@
>>  compression = "none";
>>  load = <0x0020>;
>>  };
>> -atf@1 {
>> +atf {
>>  description = "ARM Trusted Firmware";
>>  data = /incbin/("../../../bl31.bin");
>>  type = "firmware";
>> @@ -30,14 +30,14 @@
>>  load = <0x1000>;
>>  entry = <0x1000>;
>>  };
>> -pmu@1 {
>> +pmu {
>>  description = "Cortex-M0 firmware";
>>  data = /incbin/("../../../rk3399m0.bin");
>>  type = "pmu-firmware";
>>  compression = "none";
>>  load = <0xff8c>;
>>  };
>> -fdt@1 {
>> +fdt {
>>  description = "RK3399-Q7 (Puma) flat device-tree";
>>  data = /incbin/("../../../u-boot.dtb");
>>  type = "flat_dt";
>> @@ -46,12 +46,12 @@
>>  };
>>  configurations {
>> -default = "conf@1";
>> -conf@1 {
>> +default = "conf";
>> +conf {
>>  description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
>> -firmware = "uboot@1";
>> -loadables = "atf@1";
>> -fdt = "fdt@1";
>> +firmware = "uboot";
>> +loadables = "atf";
>> +fdt = "fdt";
>>  };
>>  };
>>  };
> 
> 

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Re: [U-Boot] [PATCH] imx6: fix SDn_CMD mux mode bitfield arguments

[Stefano Babic]

Hi Anatolji,

On 01/08/2017 15:14, Anatolij Gustschin wrote:
> For ALT0 function mux mode should be 0, not 16.
> 
> Signed-off-by: Anatolij Gustschin 
> ---
>  arch/arm/include/asm/arch-mx6/mx6q_pins.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h 
> b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
> index a8456a2..3dbdb0c 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
> @@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 
> 0x, 0, 0)
>  MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,0x069C, 0x02B4, 1, 0x, 0, 0)
>  MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,0x069C, 0x02B4, 1, 0x0928, 5, 0)
>  MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,   0x069C, 0x02B4, 5, 0x, 0, 0)
> -MX6_PAD_DECL(SD3_CMD__SD3_CMD,   0x06A0, 0x02B8, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD3_CMD__SD3_CMD,   0x06A0, 0x02B8, 0, 0x, 0, 0)
>  MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,   0x06A0, 0x02B8, 1, 0x, 0, 0)
>  MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,   0x06A0, 0x02B8, 1, 0x0924, 2, 0)
>  MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,   0x06A0, 0x02B8, 2, 0x, 0, 0)
> @@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 
> 0x0878, 1, 0)
>  MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,  0x06D8, 0x02F0, 3, 0x, 0, 0)
>  MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,  0x06D8, 0x02F0, 5, 0x, 0, 0)
>  MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1,  0x06D8, 0x02F0, 6, 0x, 0, 0)
> -MX6_PAD_DECL(SD4_CMD__SD4_CMD,   0x06DC, 0x02F4, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD4_CMD__SD4_CMD,   0x06DC, 0x02F4, 0, 0x, 0, 0)
>  MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x, 0, 0)
>  MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x, 0, 0)
>  MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0)
> @@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,0x072C, 0x0344, 
> 3, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_DAT3__WDOG2_B,  0x072C, 0x0344, 4, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,   0x072C, 0x0344, 5, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,0x072C, 0x0344, 6, 0x, 0, 0)
> -MX6_PAD_DECL(SD1_CMD__SD1_CMD,   0x0730, 0x0348, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD1_CMD__SD1_CMD,   0x0730, 0x0348, 0, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI,   0x0730, 0x0348, 1, 0x0830, 0, 0)
>  MX6_PAD_DECL(SD1_CMD__PWM4_OUT,  0x0730, 0x0348, 2, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,  0x0730, 0x0348, 3, 0x, 0, 0)
> @@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK,  0x073C, 0x0354, 
> 1, 0x0828, 1, 0)
>  MX6_PAD_DECL(SD2_CLK__KEY_COL5,  0x073C, 0x0354, 2, 0x08E8, 3, 0)
>  MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0)
>  MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,0x073C, 0x0354, 5, 0x, 0, 0)
> -MX6_PAD_DECL(SD2_CMD__SD2_CMD,   0x0740, 0x0358, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD2_CMD__SD2_CMD,   0x0740, 0x0358, 0, 0x, 0, 0)
>  MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI,   0x0740, 0x0358, 1, 0x0830, 1, 0)
>  MX6_PAD_DECL(SD2_CMD__KEY_ROW5,  0x0740, 0x0358, 2, 0x08F4, 2, 0)
>  MX6_PAD_DECL(SD2_CMD__AUD4_RXC,  0x0740, 0x0358, 3, 0x07BC, 1, 0)
> 

The MUX mode is not changed, but 16 means that the SION bit is set. This
forces the MUX to ALT0. I have no idea why the SION bit is set for SD,
but we have already had some cases with ENET (and GIPOs require to set
SION as well). In any case, if SION must be set, it should be not done
with the value (16), but with the macro IOMUX_CONFIG_SION.

I agree there is no reason why SION must be set.

Acked-by : Stefano Babic 

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] efi_loader: make pool allocations cacheline aligned

[Rob Clark]

On Tue, Aug 1, 2017 at 9:10 PM, Heinrich Schuchardt
 wrote:
> On 08/01/2017 10:00 PM, Rob Clark wrote:
>> This avoids printf() spam about file reads (such as loading an image)
>> into unaligned buffers (and the associated memcpy()).  And generally
>> seems like a good idea.
>>
>> Signed-off-by: Rob Clark 
>> ---
>>  lib/efi_loader/efi_memory.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
>> index 9e079f1fa3..2ba8d8b42b 100644
>> --- a/lib/efi_loader/efi_memory.c
>> +++ b/lib/efi_loader/efi_memory.c
>> @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
>>   */
>>  struct efi_pool_allocation {
>>   u64 num_pages;
>> - char data[];
>> + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
>>  };
>>
>>  /*
>> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
>> long size,
>>  {
>>   efi_status_t r;
>>   efi_physical_addr_t t;
>> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>> + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct efi_pool_allocation),
>> +  EFI_PAGE_SIZE);
>>
>>   if (size == 0) {
>>   *buffer = NULL;
>>
> NAK
>
> With DIV_ROUND_UP you introduce a 64bit division. Depending on the
> architecture this is only available via stdlib which is not available in
> U-Boot.

The divisor is a constant power of two so compiler should turn this into a shift

> Please, use
> + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
> as in the original line.
>

This was actually incorrect (missing a "- 1"), which is why I decided
to stop open-coding DIV_ROUND_UP().

BR,
-R
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Re: [U-Boot] [PATCH] vsprintf.c: add wide string (%ls) support

[Rob Clark]

On Tue, Aug 1, 2017 at 10:22 PM, Heinrich Schuchardt  wrote:
> On 07/31/2017 02:42 PM, Rob Clark wrote:
>> This is convenient for efi_loader which deals a lot with utf16.
>>
>> Signed-off-by: Rob Clark 
>> ---
>>  lib/vsprintf.c | 39 +--
>>  1 file changed, 37 insertions(+), 2 deletions(-)
>>
>> diff --git a/lib/vsprintf.c b/lib/vsprintf.c
>> index 874a2951f7..84e157ecb1 100644
>> --- a/lib/vsprintf.c
>> +++ b/lib/vsprintf.c
>> @@ -270,6 +270,35 @@ static char *string(char *buf, char *end, char *s, int 
>> field_width,
>>   return buf;
>>  }
>>
>> +static size_t strnlen16(const u16* s, size_t count)
>> +{
>> + const u16 *sc;
>> +
>> + for (sc = s; count-- && *sc; ++sc)
>> + /* nothing */;
>> + return sc - s;
>> +}
>> +
>> +static char *string16(char *buf, char *end, u16 *s, int field_width,
>> + int precision, int flags)
>> +{
>> + int len, i;
>> +
>> + if (s == NULL)
>> + s = L"";
>
> The L notation creates a wchar_t string. The width of wchar_t depends on
> gcc compiler flag -fshort-wchar.
>
> vsprintf.c is not compiled with -fshort-wchar. So change this to
>
> const u16 null[] = { '<', 'N', 'U', 'L', 'L', '>', 0};
> s = null;

oh, I have another patch that adds -fshort-wchar globally.. which I
probably should have split out and sent with this.

The problem is we cannot mix objects using short-wchar and ones that
don't without a compiler warning.  Travis would complain a lot more
but I guess BOOTEFI_HELLO is not normally enabled.

With addition of efi_bootmgr.c we really want to be able to use
L"string" to be u16.. and I don't think u-boot has any good reason to
use 32b wchar.

But maybe for this code I should use wchar_t instead of u16.

BR,
-R

>> +
>> + len = strnlen16(s, precision);
>> +
>> + if (!(flags & LEFT))
>> + while (len < field_width--)
>> + ADDCH(buf, ' ');
>> + for (i = 0; i < len; ++i)
>> + ADDCH(buf, *s++);
>> + while (len < field_width--)
>> + ADDCH(buf, ' ');
>> + return buf;
>> +}
>> +
>>  #ifdef CONFIG_CMD_NET
>>  static const char hex_asc[] = "0123456789abcdef";
>>  #define hex_asc_lo(x)hex_asc[((x) & 0x0f)]
>> @@ -528,8 +557,14 @@ repeat:
>>   continue;
>>
>>   case 's':
>> - str = string(str, end, va_arg(args, char *),
>> -  field_width, precision, flags);
>> + if (qualifier == 'l') {
>
> According to ISO 9899:1999 %ls is used to indicate a wchar_t string,
> which may be u32 * or u16 * depending on GCC flag -fshort-wchar.
>
> Wouldn't it make sense to use some other notation, e.g. %S, to indicate
> that we explicitly mean u16 *?
>
> Please, add a comment into the code indicating why we need u16 * support
> referring to the UEFI spec.
>
> Best regards
>
> Heinrich
>
>> + str = string16(str, end, va_arg(args, u16 *),
>> +field_width, precision, flags);
>> +
>> + } else {
>> + str = string(str, end, va_arg(args, char *),
>> +  field_width, precision, flags);
>> + }
>>   continue;
>>
>>   case 'p':
>>
>
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Re: [U-Boot] [PATCH] imx-common: spl: return boot mode for asked MMC device in spl_boot_mode()

[Stefano Babic]

Hi anatolji,

On 01/08/2017 15:23, Anatolij Gustschin wrote:
> Boards may extend or re-define the boot list in their board_boot_order()
> function by modifying spl_boot_list. E.g. a board might boot SPL from a
> slow SPI NOR flash and then load the U-Boot from an eMMC or SD-card.
> Or it might use additional MMC boot device in spl_boot_list for cases
> when the image in SPI NOR flash is not found, so it could fall back to
> eMMC, SD-card or another boot device.
> 
> Getting the MMC boot mode in spl_mmc will fail when we are trying to
> boot from an MMC device in the spl_boot_list and the original board
> boot mode (as returned by spl_boot_device()) is not an MMC boot mode.
> Fix it by checking the asked MMC boot device from the spl_boot_mode()
> argument.
> 
> Signed-off-by: Anatolij Gustschin 
> ---
>  arch/arm/mach-imx/spl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> index 75698c4..cbb9dd5 100644
> --- a/arch/arm/mach-imx/spl.c
> +++ b/arch/arm/mach-imx/spl.c
> @@ -84,7 +84,7 @@ u32 spl_boot_device(void)
>  /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
>  u32 spl_boot_mode(const u32 boot_device)
>  {
> - switch (spl_boot_device()) {
> + switch (boot_device) {
>   /* for MMC return either RAW or FAT mode */
>   case BOOT_DEVICE_MMC1:
>   case BOOT_DEVICE_MMC2:
> 

Nevertheless it seems difficult to be consistent. Let's start with the
case where a on-board device (SPI or eMMC) does not boot, and the way to
save the board is to boot from an external board. And SPL on the onboard
flash is damaged, but not u-boot.img. Anyway, we want that the board
boots with its consistent status, that is with the pair SPL+u-boot.img.
In the example I tracked, both from the SD card. This is consistent
using spl_boot_device, because it does not try to boot from a different
device as the one where SPL was loaded.

Best regards,
Stefano

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Re: [U-Boot] [PATCH 1/8] armv8: Add workaround for USB erratum A-009008

[Ran Wang]

Hello Sir,
May I know the review result for this patch set? Thank you.
BR
Ran

> -Original Message-
> From: Ran Wang [mailto:ran.wan...@nxp.com]
> Sent: Monday, July 10, 2017 10:24 AM
> To: Albert Aribaud ; York Sun ;
> Suresh Gupta 
> Cc: Simon Glass ; Sriram Dash ;
> Rajesh Bhagat ; Andy Tang ;
> Shengzhou Liu ; Priyanka Jain
> ; Prabhakar Kushwaha
> ; open list ; Ran Wang
> 
> Subject: [PATCH 1/8] armv8: Add workaround for USB erratum A-009008
> 
> USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with
> the default value at many corners, particularly at a high temperature
> 
> Optimal eye at TXREFTUNE value to 1001 is observed, change set the same
> value.
> 
> Signed-off-by: Ran Wang 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  7 ++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25
> ++
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6
> ++  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>  4 files changed, 39 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index d8b285d..eebfcfe 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -22,6 +22,7 @@ config ARCH_LS1043A
>   select SYS_FSL_ERRATUM_A009942
>   select SYS_FSL_ERRATUM_A010315
>   select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
>   select SYS_FSL_HAS_DDR3
>   select SYS_FSL_HAS_DDR4
>   select ARCH_EARLY_INIT_R
> @@ -42,6 +43,7 @@ config ARCH_LS1046A
>   select SYS_FSL_ERRATUM_A009942
>   select SYS_FSL_ERRATUM_A010165
>   select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
>   select SYS_FSL_HAS_DDR4
>   select SYS_FSL_SRDS_2
>   select ARCH_EARLY_INIT_R
> @@ -77,6 +79,7 @@ config ARCH_LS2080A
>   select SYS_FSL_ERRATUM_A009942
>   select SYS_FSL_ERRATUM_A010165
>   select SYS_FSL_ERRATUM_A009203
> + select SYS_FSL_ERRATUM_A009008
>   select ARCH_EARLY_INIT_R
>   select BOARD_EARLY_INIT_F
> 
> @@ -220,6 +223,10 @@ config SYS_FSL_ERRATUM_A010315  config
> SYS_FSL_ERRATUM_A010539
>   bool "Workaround for PIN MUX erratum A010539"
> 
> +config SYS_FSL_ERRATUM_A009008
> + bool "Workaround for USB PHY erratum A009008"
> +
> +
>  config MAX_CPUS
>   int "Maximum number of CPUs permitted for Layerscape"
>   default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 0943e83..a91f85e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -52,6 +52,29 @@ bool soc_has_aiop(void)
>   return false;
>  }
> 
> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4,
> val|(USB_TXVREFTUNE << 6));
> + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4,
> val|(USB_TXVREFTUNE << 6));
> + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4,
> val|(USB_TXVREFTUNE <<
> +6)); #elif defined(CONFIG_ARCH_LS2080A)
> + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE <<
> 6));
> +#endif #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
> +
>  #if defined(CONFIG_FSL_LSCH3)
>  /*
>   * This erratum requires setting a value to eddrtqcr1 to @@ -198,6 +221,7 @@
> void fsl_lsch3_early_init_f(void)  #endif
>   erratum_a008514();
>   erratum_a008336();
> + erratum_a009008();
>  #ifdef CONFIG_CHAIN_OF_TRUST
>   /* In case of Secure Boot, the IBR configures the SMMU
>   * to allow only Secure transactions.
> @@ -473,6 +497,7 @@ void fsl_lsch2_early_init_f(void)
>   erratum_a009929();
>   erratum_a009660();
>   erratum_a010539();
> + erratum_a009008();
>  }
>  #endif
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 8ad199f..62d7046 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -337,6 +337,12 @@ struct ccsr_gur {
>  #define SCFG_USBPWRFAULT_USB2_SHIFT  2
>  #define SCFG_USBPWRFAULT_USB1_SHIFT  0
> 
> +#define SCFG_BASE0x0157
> +#define SCFG_USB3PRM1CR_USB1 0x070
> +#define SCFG_USB3PRM1CR_USB2 0x07C
> +#define SCFG_USB3PRM1CR_USB3 0x088
> 

Re: [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module

[Stefano Babic]

On 07/07/2017 12:40, Ben Whitten wrote:
> This board is based on the Atmel 9x5 eval board.
> Supporting the following features:
>  - Boot from NAND Flash
>  - Ethernet
>  - FIT
>  - SPL
> 

Patch is assigned to me. However, this is Atmel, now orphaned. I haven't
work with AT-91 since a very long time, so I cannot say more about
patches, but it is a pity if the patches will be lost. Tom, should I
merge them even if they are not i.MX related ? Or do you pick them
yourself ?

Regards,
Stefano

> Signed-off-by: Ben Whitten 
> Signed-off-by: Dan Kephart 
> ---
>  arch/arm/mach-at91/Kconfig |   6 +
>  arch/arm/mach-at91/include/mach/gpio.h |   2 +
>  board/laird/wb45n/Kconfig  |  12 ++
>  board/laird/wb45n/MAINTAINERS  |   6 +
>  board/laird/wb45n/Makefile |   6 +
>  board/laird/wb45n/wb45n.c  | 199 
> +
>  configs/wb45n_defconfig|  27 +
>  include/configs/wb45n.h| 163 +++
>  8 files changed, 421 insertions(+)
>  create mode 100644 board/laird/wb45n/Kconfig
>  create mode 100644 board/laird/wb45n/MAINTAINERS
>  create mode 100644 board/laird/wb45n/Makefile
>  create mode 100644 board/laird/wb45n/wb45n.c
>  create mode 100644 configs/wb45n_defconfig
>  create mode 100644 include/configs/wb45n.h
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 99b88d1..e4d9690 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -164,6 +164,11 @@ config TARGET_VINCO
>   select CPU_V7
>   select SUPPORT_SPL
>  
> +config TARGET_WB45N
> + bool "Support Laird WB45N"
> + select CPU_ARM926EJS
> + select SUPPORT_SPL
> +
>  endchoice
>  
>  config SYS_SOC
> @@ -197,5 +202,6 @@ source "board/ronetix/pm9g45/Kconfig"
>  source "board/siemens/corvus/Kconfig"
>  source "board/siemens/taurus/Kconfig"
>  source "board/siemens/smartweb/Kconfig"
> +source "board/laird/wb45n/Kconfig"
>  
>  endif
> diff --git a/arch/arm/mach-at91/include/mach/gpio.h 
> b/arch/arm/mach-at91/include/mach/gpio.h
> index df0f719..e206316 100644
> --- a/arch/arm/mach-at91/include/mach/gpio.h
> +++ b/arch/arm/mach-at91/include/mach/gpio.h
> @@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin)
>   at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
>  #define at91_set_B_periph(x, y) \
>   at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
> +#define at91_set_gpio_deglitch(x, y) \
> + at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)
>  #define at91_set_gpio_output(x, y) \
>   at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
>  #define at91_set_gpio_input(x, y) \
> diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig
> new file mode 100644
> index 000..2a67337
> --- /dev/null
> +++ b/board/laird/wb45n/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_WB45N
> +
> +config SYS_BOARD
> + default "wb45n"
> +
> +config SYS_VENDOR
> + default "laird"
> +
> +config SYS_CONFIG_NAME
> + default "wb45n"
> +
> +endif
> diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS
> new file mode 100644
> index 000..60bb563
> --- /dev/null
> +++ b/board/laird/wb45n/MAINTAINERS
> @@ -0,0 +1,6 @@
> +WB45N CPU MODULE
> +M:   Ben Whitten 
> +S:   Maintained
> +F:   board/laird/wb45n/
> +F:   include/configs/wb45n.h
> +F:   configs/wb45n_defconfig
> diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile
> new file mode 100644
> index 000..fc645dd
> --- /dev/null
> +++ b/board/laird/wb45n/Makefile
> @@ -0,0 +1,6 @@
> +#
> +#
> +# SPDX-License-Identifier:   GPL-2.0+
> +#
> +
> +obj-y += wb45n.o
> diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c
> new file mode 100644
> index 000..5914071
> --- /dev/null
> +++ b/board/laird/wb45n/wb45n.c
> @@ -0,0 +1,199 @@
> +/*
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* - 
> */
> +/*
> + * Miscelaneous platform dependent initialisations
> + */
> +static void wb45n_nand_hw_init(void)
> +{
> + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
> + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
> + unsigned long csa;
> +
> + csa = readl(&matrix->ebicsa);
> + /* Enable CS3 */
> + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
> + /* NAND flash on D0 */
> + csa &= ~AT91_MATRIX_NFD0_ON_D16;
> + writel(csa, &matrix->ebicsa);
> +
> + /* Configure SMC CS3 for NAND/SmartMedia */
> + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
> +AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
> +&smc->cs[3].setup);
> + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
>

Re: [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation

[Andy Yan]

Hi Philipp:


On 2017年07月29日 03:22, Philipp Tomsich wrote:

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
  - DDR3
  - 32-bit configuration (i.e. fully populated)
  - dual-rank (i.e. no auto-detection of ranks)
  - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v3:
- correctly states the location of the driver in the commit message

Changes in v2: None

  arch/arm/include/asm/arch-rockchip/ddr_rk3368.h| 187 
  arch/arm/include/asm/arch-rockchip/grf_rk3368.h|   3 +
  arch/arm/mach-rockchip/rk3368/Makefile |   1 -
  arch/arm/mach-rockchip/rk3368/sdram_rk3368.c   |  60 --
  .../clock/rockchip,rk3368-dmc.txt  |  67 ++
  drivers/ram/Makefile   |   2 +
  drivers/ram/rockchip/Makefile  |   7 +
  drivers/ram/rockchip/dmc-rk3368.c  | 990 +
  include/dt-bindings/memory/rk3368-dmc.h|  30 +
  9 files changed, 1286 insertions(+), 61 deletions(-)
  create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
  delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
  create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
  create mode 100644 drivers/ram/rockchip/Makefile
  create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
  create mode 100644 include/dt-bindings/memory/rk3368-dmc.h

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
new file mode 100644
index 000..4e2b233
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+   u32 scfg;
+   u32 sctl;
+   u32 stat;
+   u32 intrstat;
+   u32 reserved0[12];
+   u32 mcmd;
+   u32 powctl;
+   u32 powstat;
+   u32 cmdtstat;
+   u32 cmdtstaten;
+   u32 reserved1[3];
+   u32 mrrcfg0;
+   u32 mrrstat0;
+   u32 mrrstat1;
+   u32 reserved2[4];
+   u32 mcfg1;
+   u32 mcfg;
+   u32 ppcfg;
+   u32 mstat;
+   u32 lpddr2zqcfg;
+   u32 reserved3;
+   u32 dtupdes;
+   u32 dtuna;
+   u32 dtune;
+   u32 dtuprd0;
+   u32 dtuprd1;
+   u32 dtuprd2;
+   u32 dtuprd3;
+   u32 dtuawdt;
+   u32 reserved4[3];
+   u32 togcnt1u;
+   u32 tinit;
+   u32 trsth;
+   u32 togcnt100n;
+   u32 trefi;
+   u32 tmrd;
+   u32 trfc;
+   u32 trp;
+   u32 trtw;
+   u32 tal;
+   u32 tcl;
+   u32 tcwl;
+   u32 tras;
+   u32 trc;
+   u32 trcd;
+   u32 trrd;
+   u32 trtp;
+   u32 twr;
+   u32 twtr;
+   u32 texsr;
+   u32 txp;
+   u32 txpdll;
+   u32 tzqcs;
+   u32 tzqcsi;
+   u32 tdqs;
+   u32 tcksre;
+   u32 tcksrx;
+   u32 tcke;
+   u32 tmod;
+   u32 trstl;
+   u32 tzqcl;
+   u32 tmrr;
+   u32 tckesr;
+   u32 t

Hi Philipp:


On 2017年07月29日 03:22, Philipp Tomsich wrote:

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
  - DDR3
  - 32-bit configuration (i.e. fully populated)
  - dual-rank (i.e. no auto-detection of ranks)
  - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR

[U-Boot] [PATCH 1/1] imx: imx6ull: correct get_cpu_speed_grade_hz on 696MHz SoCs

[Sébastien Szymanski]

Return the correct value when the speed grade is 696MHz.
This makes U-Boot to print the correct value at boot:

U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 12:02:26 +0200)

CPU:   Freescale i.MX6ULL rev1.0 696 MHz (running at 396 MHz)

instead of

U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 11:47:51 +0200)

CPU:   Freescale i.MX6ULL rev1.0 69 MHz (running at 396 MHz)
Signed-off-by: Sébastien Szymanski 
---
 arch/arm/mach-imx/mx6/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index af31673..7607456 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void)
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 52800;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
-   return 6960;
+   return 69600;
else
return 0;
}
-- 
2.7.3

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Re: [U-Boot] [PATCH 1/1] imx: imx6ull: correct get_cpu_speed_grade_hz on 696MHz SoCs

[Stefano Babic]

On 02/08/2017 12:15, Sébastien Szymanski wrote:
> Return the correct value when the speed grade is 696MHz.
> This makes U-Boot to print the correct value at boot:
> 
> U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 12:02:26 +0200)
> 
> CPU:   Freescale i.MX6ULL rev1.0 696 MHz (running at 396 MHz)
> 
> instead of
> 
> U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 11:47:51 +0200)
> 
> CPU:   Freescale i.MX6ULL rev1.0 69 MHz (running at 396 MHz)
> Signed-off-by: Sébastien Szymanski 
> ---
>  arch/arm/mach-imx/mx6/soc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index af31673..7607456 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void)
>   if (val == OCOTP_CFG3_SPEED_528MHZ)
>   return 52800;
>   else if (val == OCOTP_CFG3_SPEED_696MHZ)
> - return 6960;
> + return 69600;
>   else
>   return 0;
>   }
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic


-- 
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Re: [U-Boot] [PATCH 1/5] arm: socfpga: Add checking function on searching boot device

[Chee, Tien Fong]

On Isn, 2017-07-31 at 12:53 +0200, Marek Vasut wrote:
> On 07/31/2017 12:50 PM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Function for checking boot device type, which is required for
> > locating
> > flash where U-boot image, FPGA design are stored.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  arch/arm/mach-socfpga/include/mach/misc.h |   19
> > +++
> >  arch/arm/mach-socfpga/misc_arria10.c  |   22
> > ++
> >  2 files changed, 41 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
> > b/arch/arm/mach-socfpga/include/mach/misc.h
> > index 0b65783..b219aac 100644
> > --- a/arch/arm/mach-socfpga/include/mach/misc.h
> > +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> > @@ -14,6 +14,24 @@ struct bsel {
> >     const char  *name;
> >  };
> >  
> > +enum {
> > +   BOOT_DEVICE_RAM,
> > +   BOOT_DEVICE_MMC1,
> > +   BOOT_DEVICE_MMC2,
> > +   BOOT_DEVICE_MMC2_2,
> > +   BOOT_DEVICE_NAND,
> > +   BOOT_DEVICE_ONENAND,
> > +   BOOT_DEVICE_NOR,
> > +   BOOT_DEVICE_UART,
> > +   BOOT_DEVICE_SPI,
> > +   BOOT_DEVICE_USB,
> > +   BOOT_DEVICE_SATA,
> > +   BOOT_DEVICE_I2C,
> > +   BOOT_DEVICE_BOARD,
> > +   BOOT_DEVICE_DFU,
> > +   BOOT_DEVICE_NONE
> Why do you have so many bootdevices here if half of them aren't
> supported/used ?
> 
Okay, i will reduce it, i refered this from spl.h
> > 
> > +};
> > +
> >  extern struct bsel bsel_str[];
> >  
> >  #ifdef CONFIG_FPGA
> > @@ -26,6 +44,7 @@ static inline void socfpga_fpga_add(void) {}
> >  unsigned int dedicated_uart_com_port(const void *blob);
> >  unsigned int shared_uart_com_port(const void *blob);
> >  unsigned int uart_com_port(const void *blob);
> > +u32 boot_device(void);
> >  #endif
> >  
> >  #endif /* _MISC_H_ */
> > diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-
> > socfpga/misc_arria10.c
> > index 9d751f6..069a0a6 100644
> > --- a/arch/arm/mach-socfpga/misc_arria10.c
> > +++ b/arch/arm/mach-socfpga/misc_arria10.c
> > @@ -235,6 +235,28 @@ unsigned int uart_com_port(const void *blob)
> >     return shared_uart_com_port(blob);
> >  }
> >  
> > +u32 boot_device(void)
> > +{
> > +   const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > +
> > +   switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> This looks very similar to what is on Gen5 ?
> 
I refered from  function spl_boot_device in spl.c . I copied the
function here, because U-boot also need it.
> > 
> > +   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> > +   return BOOT_DEVICE_RAM;
> > +   case 0x2:   /* NAND Flash (1.8V) */
> > +   case 0x3:   /* NAND Flash (3.0V) */
> > +   return BOOT_DEVICE_NAND;
> > +   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
> > +   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
> > +   return BOOT_DEVICE_MMC1;
> > +   case 0x6:   /* QSPI Flash (1.8V) */
> > +   case 0x7:   /* QSPI Flash (3.0V) */
> > +   return BOOT_DEVICE_SPI;
> > +   default:
> > +   printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > +   hang();
> > +   }
> > +}
> > +
> >  /*
> >   * Print CPU information
> >   */
> > 
> 
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Re: [U-Boot] [PATCH 3/5] configs: socfpga: Add config for RBF loading from FAT fs

[Chee, Tien Fong]

On Isn, 2017-07-31 at 12:54 +0200, Marek Vasut wrote:
> On 07/31/2017 12:50 PM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > This config enable the mechanism for loading RBF file from FAT fs
> > into
> > FPGA manager.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  arch/arm/mach-socfpga/Kconfig |7 +++
> >  1 files changed, 7 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> > socfpga/Kconfig
> > index 45e5379..3fbac20 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -33,6 +33,13 @@ config
> > SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
> >  config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
> >     default 0xa2
> >  
> > +config RBF_SDMMC_FAT_SUPPORT
> NAK, Xilinx already has some support for loading FPGA from FS, so
> improve on that.
> 
thanks for the advice. I will take a look.
> > 
> > +   bool "Support FPGA program with FAT RBF"
> > +   default y if SPL_FAT_SUPPORT
> > +   help
> > +   Enable support for programming FPGA with RAW
> > binary file
> > +   (periph rbf + core rbf) loading from FAT
> > partition.
> > +
> >  config TARGET_SOCFPGA_ARRIA5
> >     bool
> >     select TARGET_SOCFPGA_GEN5
> > 
> 
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Re: [U-Boot] [PATCH] imx6: fix SDn_CMD mux mode bitfield arguments

[Anatolij Gustschin]

Hi Stefano,

On Wed, 2 Aug 2017 11:24:22 +0200
Stefano Babic sba...@denx.de wrote:
...
> > -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x, 0, 0)
> > +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0, 0x, 0, 0)
...
> 
> The MUX mode is not changed, but 16 means that the SION bit is set. This
> forces the MUX to ALT0. I have no idea why the SION bit is set for SD,
> but we have already had some cases with ENET (and GIPOs require to set
> SION as well). In any case, if SION must be set, it should be not done
> with the value (16), but with the macro IOMUX_CONFIG_SION.

SD_CMD is bi-directional and SION setting seems to be intended here.
OK, I'll resubmit with IOMUX_CONFIG_SION to make it clear.

Thanks,

Anatolij
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[U-Boot] [PATCH v2 1/1] add support for Raspberry Pi Zero W

[Dmitry Korunov]

The Raspberry Pi Zero W extends the Pi Zero family and it's also
based on a BCM2835 SoC. Like the Pi Zero, it has 512MB RAM,
Mini HDMI and USB On-The-Go ports. Both Pi's hasn't got Ethernet,
but Pi Zero W has built in wireless LAN 802.11 b/g/n.

Signed-off-by: Dmitry Korunov 
---
Changes for v2:
   - removed surplus spaces
   - added the board description

 arch/arm/dts/bcm2835-rpi-zero-w.dts| 33 +
 arch/arm/dts/bcm283x-rpi-usb-host.dtsi |  3 +++
 arch/arm/mach-bcm283x/Kconfig  | 16 
 board/raspberrypi/rpi/rpi.c|  5 +
 configs/rpi_0_w_defconfig  | 28 
 include/configs/rpi.h  |  2 +-
 6 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/bcm2835-rpi-zero-w.dts
 create mode 100644 arch/arm/dts/bcm283x-rpi-usb-host.dtsi
 create mode 100644 configs/rpi_0_w_defconfig

diff --git a/arch/arm/dts/bcm2835-rpi-zero-w.dts 
b/arch/arm/dts/bcm2835-rpi-zero-w.dts
new file mode 100644
index 000..067cb31
--- /dev/null
+++ b/arch/arm/dts/bcm2835-rpi-zero-w.dts
@@ -0,0 +1,33 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+   compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+   model = "Raspberry Pi Zero W";
+
+   leds {
+   act {
+   gpios = <&gpio 47 0>;
+   };
+   };
+};
+
+&gpio {
+   pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
+
+   /* I2S interface */
+   i2s_alt0: i2s_alt0 {
+   brcm,pins = <18 19 20 21>;
+   brcm,function = ;
+   };
+};
+
+&uart1 {
+   status = "okay";
+};
+
+&hdmi {
+   hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/bcm283x-rpi-usb-host.dtsi 
b/arch/arm/dts/bcm283x-rpi-usb-host.dtsi
new file mode 100644
index 000..73f4ece
--- /dev/null
+++ b/arch/arm/dts/bcm283x-rpi-usb-host.dtsi
@@ -0,0 +1,3 @@
+&usb {
+   dr_mode = "host";
+};
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 69f7a46..a78239d 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -44,6 +44,22 @@ config TARGET_RPI
  This option creates a build targetting the ARM1176 ISA.
select BCM2835
 
+config TARGET_RPI_0_W
+   bool "Raspberry Pi Zero W"
+   help
+ Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
+ the RPi Zero model W.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi Zero W. To enable the UART console, the following
+ non-default option must be present in config.txt: enable_uart=1.
+ This is required for U-Boot to operate correctly, even if you only
+ care about the HDMI/usbkbd console.
+
+ This option creates a build targetting the ARMv7/AArch32 ISA.
+   select BCM2835
+
 config TARGET_RPI_2
bool "Raspberry Pi 2"
help
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index d3c6ba5..63998d7 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -105,6 +105,11 @@ static const struct rpi_model rpi_models_new_scheme[] = {
DTB_DIR "bcm2835-rpi-zero.dtb",
false,
},
+   [0xC] = {
+   "Zero W",
+   DTB_DIR "bcm2835-rpi-zero-w.dtb",
+   false,
+   },
 };
 
 static const struct rpi_model rpi_models_old_scheme[] = {
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
new file mode 100644
index 000..092f378
--- /dev/null
+++ b/configs/rpi_0_w_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_0_W=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_DM_ETH=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index c545f99..46295c7 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -79,7 +79,7 @@
 #endif
 
 /* Console UART */
-#ifdef CONFIG_BCM2837
+#if defined (CONFIG_BCM2837) || defined(CONFIG_TARGET_RPI_0_W)
 #define CONFIG_BCM283X_MU_SERIAL
 #else
 #define CONFIG_PL01X_SERIAL
-- 
2.7.4

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Re: [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation

[Dr. Philipp Tomsich]

Andy,

The functionality of the new driver should be equivalent for the non-TPL case.
All the code from the original driver is still present in the new driver for 
non-TPL
(see rk3368_dmc_probe).

Seeing that -19 is -ENODEV, I suspect that something went wrong in the DM
binding/probing: did you set 'status = “okay”’ for the DMC?

Regards,
Phil.

> On 02 Aug 2017, at 12:06, Andy Yan  wrote:
> 
> Hi Philipp:
> 
> 
> On 2017年07月29日 03:22, Philipp Tomsich wrote:
>> This adds a DRAM controller driver for the RK3368 and places it in
>> drivers/ram/rockchip (where the other DM-enabled DRAM controller
>> drivers for rockchip devices should also be moved eventually).
>> 
>> At this stage, only the following feature-set is supported:
>>  - DDR3
>>  - 32-bit configuration (i.e. fully populated)
>>  - dual-rank (i.e. no auto-detection of ranks)
>>  - DDR3-1600K speed-bin
>> 
>> This driver expects to run from a TPL stage that will later return to
>> the RK3368 BROM.  It communicates with later stages through the
>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>> init code).
>> 
>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>> timings are calculated within the driver based on a target frequency
>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>> time).
>> 
>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>> register for controlling the operation of its (single-channel) DRAM
>> controller in the GRF block.  This provides for selecting DDR3, mobile
>> DDR modes, and control low-power operation.
>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>> definition (at offset 0x600).
>> 
>> Signed-off-by: Philipp Tomsich 
>> 
>> Reviewed-by: Simon Glass 
>> ---
>> 
>> Changes in v3:
>> - correctly states the location of the driver in the commit message
>> 
>> Changes in v2: None
>> 
>>  arch/arm/include/asm/arch-rockchip/ddr_rk3368.h| 187 
>>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h|   3 +
>>  arch/arm/mach-rockchip/rk3368/Makefile |   1 -
>>  arch/arm/mach-rockchip/rk3368/sdram_rk3368.c   |  60 --
>>  .../clock/rockchip,rk3368-dmc.txt  |  67 ++
>>  drivers/ram/Makefile   |   2 +
>>  drivers/ram/rockchip/Makefile  |   7 +
>>  drivers/ram/rockchip/dmc-rk3368.c  | 990 
>> +
>>  include/dt-bindings/memory/rk3368-dmc.h|  30 +
>>  9 files changed, 1286 insertions(+), 61 deletions(-)
>>  create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>  delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>  create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>  create mode 100644 drivers/ram/rockchip/Makefile
>>  create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>>  create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>> 
>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h 
>> b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> new file mode 100644
>> index 000..4e2b233
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> @@ -0,0 +1,187 @@
>> +/*
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef __ASM_ARCH_DDR_RK3368_H__
>> +#define __ASM_ARCH_DDR_RK3368_H__
>> +
>> +/*
>> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
>> + * in a few details. Most notably, it has an additional field to track
>> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
>> + */
>> +struct rk3368_ddr_pctl {
>> +u32 scfg;
>> +u32 sctl;
>> +u32 stat;
>> +u32 intrstat;
>> +u32 reserved0[12];
>> +u32 mcmd;
>> +u32 powctl;
>> +u32 powstat;
>> +u32 cmdtstat;
>> +u32 cmdtstaten;
>> +u32 reserved1[3];
>> +u32 mrrcfg0;
>> +u32 mrrstat0;
>> +u32 mrrstat1;
>> +u32 reserved2[4];
>> +u32 mcfg1;
>> +u32 mcfg;
>> +u32 ppcfg;
>> +u32 mstat;
>> +u32 lpddr2zqcfg;
>> +u32 reserved3;
>> +u32 dtupdes;
>> +u32 dtuna;
>> +u32 dtune;
>> +u32 dtuprd0;
>> +u32 dtuprd1;
>> +u32 dtuprd2;
>> +u32 dtuprd3;
>> +u32 dtuawdt;
>> +u32 reserved4[3];
>> +u32 togcnt1u;
>> +u32 tinit;
>> +u32 trsth;
>> +u32 togcnt100n;
>> +u32 trefi;
>> +u32 tmrd;
>> +u32 trfc;
>> +u32 trp;
>> +u32 trtw;
>> +u32 tal;
>> +u32 tcl;
>> +u32 tcwl;
>> +u32 tras;
>> +u32 trc;
>> +u32 trcd;
>> +u32 trrd;
>> +u32 trtp;
>> +u32 twr;
>> +u32 twtr;
>> +u32 texsr;
>> +u32 txp;
>> +u32 txpdll;
>> +u32 tzqcs;
>> +u32 tzqcsi;
>> +u32 tdqs;
>> +u32 tcksre;
>> +u32 tcksrx;
>> +u32 tcke;
>> +u32 tmod;
>> +u32 trstl;
>> +u32 tzqcl;
>> +u32 tmrr;
>> +u32 tckesr;
>> +u32 t
>> 
>> Hi Philipp:
>> 
>> 
>> On 2017年07月2

Re: [U-Boot] [RFC PATCH 0/6] rockchip: rk3368: remove secure timer usage and use DM timer

[Dr. Philipp Tomsich]

Kever,

This patchset does not force the use of the DM timer for any chipsets/boards.
It is essentially opt-in and (for now—i.e. until we enable it for the RK3399) 
it is
enabled for the RK3368 only.

Note that this does not currently target any ARMv7 devices, as it is meant to
decouple the ARMv8 generic timer startup (i.e. starting the stimer) from U-Boot.

Regards,
Philipp.

> On 02 Aug 2017, at 07:05, Kever Yang  wrote:
> 
> Hi Philipp, Simon,
> 
>I still think we should have a option to no involve so much framework 
> thing in
> 
> very early boot stage like TPL/SPL, for those chipset with very little sram 
> onchip.
> 
> Andy send some patches for rk3036 recently, because it get out of memory in 
> SPL
> 
> and not able to boot. Most of people do not notice this but please leave a 
> option for
> 
> those devices. The timer init should always happen very early like SPL/TPL, 
> and I don't
> 
> think the DM is a must for it.
> 
> 
> Thanks,
> - Kever
> On 07/29/2017 12:31 AM, Philipp Tomsich wrote:
>> Trying to answer Simon's question whether the address of the secure
>> timer (for initialising stimer1 and starting up the ARMv8 generic
>> timer) can be obtained from the DTS, here's a series that tries to
>> give an answer.
>> 
>> To summarise this answer in plain English:
>> - The answer to the original question is: "no, but..."
>> - The "but" is what's implemented here: we don't need the ARMv8
>>   generic timer ticking in U-Boot, so we won't have to initialise it
>>   at all (this removing the need to obtain the address for stimer1).
>> - We also have a "however": the size of the TPL binary increases by
>>   approx. 800 bytes, as we need the DM timer support.
>> 
>> This series is based on-top-of my RK3368 enablement series.
>> 
>> If we go ahead with merging this, then I'll have to add support for
>> the RK3399 as well...
>> 
>> 
>> Philipp Tomsich (6):
>>   timer: add OF_PLATDATA support for timer-uclass
>>   dm: timer: normalise SPL and TPL support
>>   rockchip: timer: add device-model timer driver for RK3368 (and
>> similar)
>>   dts: rk3368: make timer0 accessible for SPL and TPL
>>   rockchip: lion-rk3368: defconfig: enable DM timer for all stages
>>   rockchip: rk3368: remove setup of secure timer from TPL/SPL
>> 
>>  arch/arm/cpu/armv8/Makefile   |   2 +
>>  arch/arm/dts/rk3368-lion-u-boot.dtsi  |   2 +-
>>  arch/arm/dts/rk3368.dtsi  |   2 +-
>>  arch/arm/mach-rockchip/rk3368-board-spl.c |  20 --
>>  arch/arm/mach-rockchip/rk3368-board-tpl.c |  19 --
>>  common/spl/Kconfig|   8 ---
>>  configs/chromebook_link64_defconfig   |   2 +-
>>  configs/lion-rk3368_defconfig |   4 ++
>>  configs/qemu-x86_64_defconfig |   2 +-
>>  drivers/Makefile  |   3 +-
>>  drivers/timer/Kconfig |  25 +++
>>  drivers/timer/Makefile|   3 +-
>>  drivers/timer/rockchip_timer.c| 105 
>> ++
>>  drivers/timer/timer-uclass.c  |   6 +-
>>  14 files changed, 148 insertions(+), 55 deletions(-)
>>  create mode 100644 drivers/timer/rockchip_timer.c
>> 
> 
> 

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[U-Boot] [GIT PULL] Xilinx fixes for v2017.09

[Michal Simek]

Hi Tom,

here are changes I have collected in my tree.
I have added also a patch which make reserve_mmu as weak function which
was reviewed by Simon. We need to for mini u-boot configurations which
will be sent later.
Travis is not showing any problem with this branch too.

Thanks,
Michal


 The following changes since commit
6364a5d4bd55beeedc11171419acd0bdff17a599:

   Prepare v2017.09-rc1 (2017-07-31 20:37:25 -0400)

 are available in the git repository at:

   git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2017.09

 for you to fetch changes up to df1cd46fb84922735e1c12f54b7202b0268dcddd:

   arm64: zynqmp: avoid out of buffer access (2017-08-02 09:11:52 +0200)

 
 Xilinx changes for v2017.09

 Zynq:
 - Add Z-Turn board support

 fpga:
 - Remove intermediate buffer from code

 Zynqmp:
 - dts cleanup
 - change psu_init handling
 - Add options to get silicon version
 - Fix time handling
 - Map OCM/TCM via MMU
 - Add new clock driver

 
 Alexander Graf (3):
   zynq: Add EFI runtime sections to linker script
   zynq: Enable distro boot
   zynq: Add Z-Turn board

 Heinrich Schuchardt (1):
   arm64: zynqmp: avoid out of buffer access

 Michal Simek (7):
   arm: zynq: Label whole PL part as fpga_full region
   clk: zynqmp: Remove unused macros/variables
   arm64: zynqmp: Call psu_init from board_early_init_f
   arm64: zynqmp: Add Kconfig option for adding psu_init to binary
   arm64: zynqmp: Fix SVD mask for getting chip ID
   arm64: zynqmp: Do not setup time if already setup
   arm64: zynqmp: Move dts zcu102 to zcu102-revA

 Siva Durga Prasad Paladugu (11):
   common: board_f: Make reserve_mmu a weak function
   clk: zynqmp: Add support for CCF driver
   clk: zynqmp: Dont panic incase of mmio write/read failures
   fpga: xilinx: Avoid using local intermediate buffer
   arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU
   arm64: zynqmp: Define a way to intialize TCM
   arm64: zynqmp: Remove ifdef around zynqmp mmio read and write
rotuines
   arm64: zynqmp: Dont write to system timestamp generator
   arm64: zynqmp: Modify chip_id routine to get either idcode or version
   arm64: zynqmp: Make chip_id a global routine()
   arm64: zynqmp: Make chip_id routine to handle based on el.

  arch/arm/cpu/armv8/zynqmp/Kconfig
 |  11 ++
  arch/arm/cpu/armv8/zynqmp/cpu.c
 |  71 -
  arch/arm/cpu/armv8/zynqmp/mp.c
 |  15 +++
  arch/arm/cpu/armv8/zynqmp/spl.c
 |   2 +-
  arch/arm/dts/Makefile
 |   3 +-
  arch/arm/dts/zynq-7000.dtsi
 |   8 ++
  arch/arm/dts/zynq-zturn-myir.dts
 | 161 +
  arch/arm/dts/{zynqmp-zcu102.dts => zynqmp-zcu102-revA.dts}
 |   2 +-
  arch/arm/dts/zynqmp-zcu102-revB.dts
 |   2 +-
  arch/arm/include/asm/arch-zynqmp/hardware.h
 |  12 +--
  arch/arm/include/asm/arch-zynqmp/sys_proto.h
 |  23 +
  arch/arm/mach-zynq/u-boot.lds
 |  29 ++
  board/xilinx/zynqmp/Makefile
 |   6 +-
  board/xilinx/zynqmp/zynqmp.c
 |  92 +++--
  common/board_f.c
 |   2 +-
  configs/{xilinx_zynqmp_zcu102_defconfig =>
xilinx_zynqmp_zcu102_revA_defconfig} |   2 +-
  configs/zynq_z_turn_defconfig
 |  59 +++
  drivers/clk/clk_zynqmp.c
 | 692
++---
  drivers/fpga/xilinx.c
 |  26 ++---
  include/common.h
 |   1 +
  include/configs/zynq-common.h
 |  55 +-
  include/zynqmppl.h
 |   2 +-
  22 files changed, 1038 insertions(+), 238 deletions(-)
  create mode 100644 arch/arm/dts/zynq-zturn-myir.dts
  rename arch/arm/dts/{zynqmp-zcu102.dts => zynqmp-zcu102-revA.dts} (99%)
  rename configs/{xilinx_zynqmp_zcu102_defconfig =>
xilinx_zynqmp_zcu102_revA_defconfig} (97%)
  create mode 100644 configs/zynq_z_turn_defconfig
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Re: [U-Boot] [RFC PATCH 3/6] rockchip: timer: add device-model timer driver for RK3368 (and similar)

[Dr. Philipp Tomsich]

> On 01 Aug 2017, at 11:48, Simon Glass  wrote:
> 
> On 28 July 2017 at 10:31, Philipp Tomsich
>  wrote:
>> This adds a device-model driver for the timer block in the RK3368 (and
>> similar devices that share the same timer block, such as the RK3288) for
>> the down-counting (i.e. non-secure) timers.
>> 
>> This allows us to configure U-Boot for the RK3368 in such a way that
>> we can run with the secure timer inaccessible or uninitialised (note
>> that the ARMv8 generic timer does not count, if the secure timer is
>> not enabled).
>> 
>> Signed-off-by: Philipp Tomsich 
>> ---
>> 
>> drivers/timer/Kconfig  |   7 +++
>> drivers/timer/Makefile |   1 +
>> drivers/timer/rockchip_timer.c | 105 
>> +
>> 3 files changed, 113 insertions(+)
>> create mode 100644 drivers/timer/rockchip_timer.c
> 
> Reviewed-by: Simon Glass 
> 
> See a few comments below.
> 
>> 
>> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
>> index fb5af4d..5dea404 100644
>> --- a/drivers/timer/Kconfig
>> +++ b/drivers/timer/Kconfig
>> @@ -104,4 +104,11 @@ config AE3XX_TIMER
>>help
>>  Select this to enable a timer for AE3XX devices.
>> 
>> +config ROCKCHIP_TIMER
>> +bool "Rockchip timer support"
>> +   depends on TIMER
>> +   help
>> + Select this to enable support for the timer block found on
> 
> I'm not so keen on the word 'block'. Maybe it should be 'IP block'? Or
> perhaps don't mention block at all and say that this is the timer.
> 
>> + Rockchip devices.
>> +
>> endmenu
>> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
>> index d16ea53..fa7ce7c 100644
>> --- a/drivers/timer/Makefile
>> +++ b/drivers/timer/Makefile
>> @@ -14,3 +14,4 @@ obj-$(CONFIG_STI_TIMER)   += sti-timer.o
>> obj-$(CONFIG_ARC_TIMER)+= arc_timer.o
>> obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
>> obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
>> +obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
>> diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
>> new file mode 100644
>> index 000..bffb630
>> --- /dev/null
>> +++ b/drivers/timer/rockchip_timer.c
>> @@ -0,0 +1,105 @@
>> +/*
>> + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#define DEBUG
> 
> Can we drop this?
> 
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +struct rockchip_timer_plat {
>> +   struct dtd_rockchip_rk3368_timer dtd;
>> +};
>> +#endif
>> +
>> +/* Driver private data. Contains timer id. Could be either 0 or 1. */
>> +struct rockchip_timer_priv {
>> +   struct rk_timer *timer;
>> +};
>> +
>> +static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
>> +{
>> +   struct rockchip_timer_priv *priv = dev_get_priv(dev);
>> +   uint64_t timebase_h, timebase_l;
>> +   uint64_t cntr;
>> +
>> +   timebase_l = readl(&priv->timer->timer_curr_value0);
>> +   timebase_h = readl(&priv->timer->timer_curr_value1);
>> +
>> +   /* timers are down-counting */
>> +   cntr = timebase_h << 32 | timebase_l;
>> +   *count = 0xull - cntr;
>> +   return 0;
>> +}
>> +
>> +static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
>> +{
>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> +   struct rockchip_timer_priv *priv = dev_get_priv(dev);
>> +
>> +   priv->timer = (struct rk_timer *)devfdt_get_addr(dev);
>> +#endif
>> +
>> +   return 0;
>> +}
>> +
>> +static int rockchip_timer_start(struct udevice *dev)
>> +{
>> +   struct rockchip_timer_priv *priv = dev_get_priv(dev);
>> +
>> +   writel(0, &priv->timer->timer_ctrl_reg);
>> +   writel(0x, &priv->timer->timer_load_count0);
>> +   writel(0x, &priv->timer->timer_load_count1);
>> +   writel(1, &priv->timer->timer_ctrl_reg);
>> +
>> +   return 0;
>> +}
>> +
>> +static int rockchip_timer_probe(struct udevice *dev)
>> +{
>> +   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
>> +   const u32 MHz = 100;
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +   struct rockchip_timer_priv *priv = dev_get_priv(dev);
>> +   struct rockchip_timer_plat *plat = dev_get_platdata(dev);
>> +
>> +   priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
>> +#endif
>> +   uc_priv->clock_rate = 24 * MHz;
> 
> If it is not enabled, doesn't this come from the DT?

Unfortunately not, as the DTS neither defines a parent-clk nor a 
clock-frequency.
This should indeed not be here — I’ll add a change that fixes the DTS.

Thanks for highlighting this!

>> +
>> +   return rockchip_timer_start(dev);
>> +}
>> +
>> +static const struct timer_ops rockchip_timer_ops = {
>> +   .get_count = rockchip_timer_get_count,
>> +};
>> +
>> +static const struct udevice_id r

Re: [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation

[Andy Yan]

Hi Philipp:


On 2017年08月02日 18:59, Dr. Philipp Tomsich wrote:

Andy,

The functionality of the new driver should be equivalent for the non-TPL case.
All the code from the original driver is still present in the new driver for 
non-TPL
(see rk3368_dmc_probe).


Yes,  it's so good that the new rk3368 dmc driver also has this 
function.


I also need to add a xxx-u-boot.dtsi for the other rk3368 based boards.


Seeing that -19 is -ENODEV, I suspect that something went wrong in the DM
binding/probing: did you set 'status = “okay”’ for the DMC?

Regards,
Phil.


On 02 Aug 2017, at 12:06, Andy Yan  wrote:

Hi Philipp:


On 2017年07月29日 03:22, Philipp Tomsich wrote:

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
  - DDR3
  - 32-bit configuration (i.e. fully populated)
  - dual-rank (i.e. no auto-detection of ranks)
  - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v3:
- correctly states the location of the driver in the commit message

Changes in v2: None

  arch/arm/include/asm/arch-rockchip/ddr_rk3368.h| 187 
  arch/arm/include/asm/arch-rockchip/grf_rk3368.h|   3 +
  arch/arm/mach-rockchip/rk3368/Makefile |   1 -
  arch/arm/mach-rockchip/rk3368/sdram_rk3368.c   |  60 --
  .../clock/rockchip,rk3368-dmc.txt  |  67 ++
  drivers/ram/Makefile   |   2 +
  drivers/ram/rockchip/Makefile  |   7 +
  drivers/ram/rockchip/dmc-rk3368.c  | 990 +
  include/dt-bindings/memory/rk3368-dmc.h|  30 +
  9 files changed, 1286 insertions(+), 61 deletions(-)
  create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
  delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
  create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
  create mode 100644 drivers/ram/rockchip/Makefile
  create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
  create mode 100644 include/dt-bindings/memory/rk3368-dmc.h

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
new file mode 100644
index 000..4e2b233
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+   u32 scfg;
+   u32 sctl;
+   u32 stat;
+   u32 intrstat;
+   u32 reserved0[12];
+   u32 mcmd;
+   u32 powctl;
+   u32 powstat;
+   u32 cmdtstat;
+   u32 cmdtstaten;
+   u32 reserved1[3];
+   u32 mrrcfg0;
+   u32 mrrstat0;
+   u32 mrrstat1;
+   u32 reserved2[4];
+   u32 mcfg1;
+   u32 mcfg;
+   u32 ppcfg;
+   u32 mstat;
+   u32 lpddr2zqcfg;
+   u32 reserved3;
+   u32 dtupdes;
+   u32 dtuna;
+   u32 dtune;
+   u32 dtuprd0;
+   u32 dtuprd1;
+   u32 dtuprd2;
+   u32 dtuprd3;
+   u32 dtuawdt;
+   u32 reserved4[3];
+   u32 togcnt1u;
+   u32 tinit;
+   u32 trsth;
+   u32 togcnt100n;
+   u32 trefi;
+   u32 tmrd;
+   u32 trfc;
+   u32 trp;
+   u32 trtw;
+   u32 tal;
+   u32 tcl;
+   u32 tcwl;
+   u32 tras;
+   u32 trc;
+   u32 trcd;
+   u32 trrd;
+   u32 trtp;
+   u32 twr;
+   u32 twtr;
+   u32 texsr;
+   u32 txp;
+   u32 txpdll;
+   u32 tzqcs;
+   u32 tzqcsi;
+   u32 tdqs;
+   u32 tcksre;
+   u32 tcksrx;
+   u32 tcke;
+   u32 tmod;
+   u32 trstl;
+   u32 tzqcl;
+   u32 tmrr;
+   u32 tckesr;
+   u32 t

Hi Philipp:


On 2017年07月29日 03:22,

Re: [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368

[Andy Yan]

Hi Philipp:

2017-07-29 3:22 GMT+08:00 Philipp Tomsich <
philipp.toms...@theobroma-systems.com>:

> With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
> supported from Kconfig for the RK3368.  As this is primarily tested on
> the RK3368-uQ7, we'll leave it to board's individual defconfig to
> enable.
>
> Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
> during the early boot-up, as we turn on TPL and SPL.
>
> Signed-off-by: Philipp Tomsich 
>
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/arm/mach-rockchip/Kconfig | 7 +++
>  1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/
> Kconfig
> index 8a89b51..8406e33 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -67,6 +67,13 @@ config ROCKCHIP_RK3328
>  config ROCKCHIP_RK3368
> bool "Support Rockchip RK3368"
> select ARM64
> +   select SUPPORT_SPL
> +   select SUPPORT_TPL
> +   select SPL_SEPARATE_BSS
> +   select SPL_SERIAL_SUPPORT
> +   select TPL_SERIAL_SUPPORT
>


 These should depends on TPL/SPL, or we will get compile warnings like
bellow on non-SPL/TPL boards(px5 evb):
 (ROCKCHIP_RK3368 && ROCKCHIP_RK3399 && X86_RUN_64BIT) selects
SPL_SEPARATE_BSS which has unmet direct dependencies (SPL)

+   select ENABLE_ARM_SOC_BOOT0_HOOK
> +   select DEBUG_UART_BOARD_INIT
> select SYS_NS16550
> help
>   The Rockchip RK3368 is a ARM-based SoC with a octa-core
> (organised
> --
> 2.1.4
>
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Re: [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368

[Dr. Philipp Tomsich]

Looks like SPL_SEPARATE_BSS is special.

Guess, I’ll need to figure out how to best deal with that one (or fall back to 
defining it via defconfig until we can enable TPL/SPL for all RK3368 board).
I wonder how an implies would behave here...

> On 02 Aug 2017, at 14:47, Andy Yan  wrote:
> 
> Hi Philipp:
> 
> 2017-07-29 3:22 GMT+08:00 Philipp Tomsich 
>  >:
> With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
> supported from Kconfig for the RK3368.  As this is primarily tested on
> the RK3368-uQ7, we'll leave it to board's individual defconfig to
> enable.
> 
> Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
> during the early boot-up, as we turn on TPL and SPL.
> 
> Signed-off-by: Philipp Tomsich  >
> 
> Reviewed-by: Simon Glass mailto:s...@chromium.org>>
> ---
> 
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/mach-rockchip/Kconfig | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 8a89b51..8406e33 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -67,6 +67,13 @@ config ROCKCHIP_RK3328
>  config ROCKCHIP_RK3368
> bool "Support Rockchip RK3368"
> select ARM64
> +   select SUPPORT_SPL
> +   select SUPPORT_TPL
> +   select SPL_SEPARATE_BSS
> +   select SPL_SERIAL_SUPPORT
> +   select TPL_SERIAL_SUPPORT
> 
> 
>  These should depends on TPL/SPL, or we will get compile warnings like bellow 
> on non-SPL/TPL boards(px5 evb):
>  (ROCKCHIP_RK3368 && ROCKCHIP_RK3399 && X86_RUN_64BIT) selects 
> SPL_SEPARATE_BSS which has unmet direct dependencies (SPL)
> 
> +   select ENABLE_ARM_SOC_BOOT0_HOOK
> +   select DEBUG_UART_BOARD_INIT
> select SYS_NS16550
> help
>   The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
> --
> 2.1.4
> 
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Re: [U-Boot] [PATCH 1/1] imx: imx6ull: correct get_cpu_speed_grade_hz on 696MHz SoCs

[Sébastien Szymanski]

Hi,

On 08/02/2017 12:11 PM, Stefano Babic wrote:
> On 02/08/2017 12:15, Sébastien Szymanski wrote:
>> Return the correct value when the speed grade is 696MHz.
>> This makes U-Boot to print the correct value at boot:
>>
>> U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 12:02:26 +0200)
>>
>> CPU:   Freescale i.MX6ULL rev1.0 696 MHz (running at 396 MHz)
>>
>> instead of
>>
>> U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 11:47:51 +0200)
>>
>> CPU:   Freescale i.MX6ULL rev1.0 69 MHz (running at 396 MHz)
>> Signed-off-by: Sébastien Szymanski 
>> ---
>>  arch/arm/mach-imx/mx6/soc.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
>> index af31673..7607456 100644
>> --- a/arch/arm/mach-imx/mx6/soc.c
>> +++ b/arch/arm/mach-imx/mx6/soc.c
>> @@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void)
>>  if (val == OCOTP_CFG3_SPEED_528MHZ)
>>  return 52800;
>>  else if (val == OCOTP_CFG3_SPEED_696MHZ)
>> -return 6960;
>> +return 69600;
>>  else
>>  return 0;
>>  }
>>
> 
> Reviewed-by: Stefano Babic 
> 

Thanks. However, I've just noticed this is only true for i.MX6UL.
i.MX6ULL has different speed grading.

Should I resend my patch and fix the commit log?

Best regards,

> Best regards,
> Stefano Babic
> 
> 


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Re: [U-Boot] [PATCH 1/1] lcd: avoid possible NULL dereference

[Dr. Philipp Tomsich]

> On 30 Jul 2017, at 21:59, Heinrich Schuchardt  wrote:
> 
> Do not dereference bmp before the check if it is NULL.
> 
> The problem was indicated by cppcheck.
> 
> Signed-off-by: Heinrich Schuchardt 

Reviewed-by: Philipp Tomsich 

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Re: [U-Boot] [PATCH 1/1] imx: imx6ull: correct get_cpu_speed_grade_hz on 696MHz SoCs

[Stefano Babic]

On 02/08/2017 15:09, Sébastien Szymanski wrote:
> Hi,
> 
> On 08/02/2017 12:11 PM, Stefano Babic wrote:
>> On 02/08/2017 12:15, Sébastien Szymanski wrote:
>>> Return the correct value when the speed grade is 696MHz.
>>> This makes U-Boot to print the correct value at boot:
>>>
>>> U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 12:02:26 +0200)
>>>
>>> CPU:   Freescale i.MX6ULL rev1.0 696 MHz (running at 396 MHz)
>>>
>>> instead of
>>>
>>> U-Boot 2017.09-rc1-dirty (Aug 02 2017 - 11:47:51 +0200)
>>>
>>> CPU:   Freescale i.MX6ULL rev1.0 69 MHz (running at 396 MHz)
>>> Signed-off-by: Sébastien Szymanski 
>>> ---
>>>  arch/arm/mach-imx/mx6/soc.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
>>> index af31673..7607456 100644
>>> --- a/arch/arm/mach-imx/mx6/soc.c
>>> +++ b/arch/arm/mach-imx/mx6/soc.c
>>> @@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void)
>>> if (val == OCOTP_CFG3_SPEED_528MHZ)
>>> return 52800;
>>> else if (val == OCOTP_CFG3_SPEED_696MHZ)
>>> -   return 6960;
>>> +   return 69600;
>>> else
>>> return 0;
>>> }
>>>
>>
>> Reviewed-by: Stefano Babic 
>>
> 
> Thanks. However, I've just noticed this is only true for i.MX6UL.
> i.MX6ULL has different speed grading.>
> Should I resend my patch and fix the commit log?

Yes, thanks for noting thius. I have not yet merged the patch and I
appreciate if this is fixed, too. Please send a V2.

Best regards,
Stefano Babic

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[U-Boot] [PATCH 1/3] rockchip: add u-boot specific dts for rk3368 based boards

[Andy Yan]

Device drivers like debug serial, dmc should be enabled before
relocation, so add u-boot.dtsi files to contain devices that
should be marked as dm-pre-reloc.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/rk3368-geekbox-u-boot.dtsi | 35 +
 arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 35 +
 arch/arm/dts/rk3368-sheep-u-boot.dtsi   | 35 +
 3 files changed, 105 insertions(+)
 create mode 100644 arch/arm/dts/rk3368-geekbox-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3368-sheep-u-boot.dtsi

diff --git a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi 
b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi
new file mode 100644
index 000..7cf4a36
--- /dev/null
+++ b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+   X11
+ */
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+   u-boot,dm-pre-reloc;
+};
+
+&dmc {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+&pmugrf {
+   u-boot,dm-pre-reloc;
+};
+
+&cru {
+   u-boot,dm-pre-reloc;
+};
+
+&grf {
+   u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+   u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
new file mode 100644
index 000..633dfe1
--- /dev/null
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+   X11
+ */
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+   u-boot,dm-pre-reloc;
+};
+
+&dmc {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+&pmugrf {
+   u-boot,dm-pre-reloc;
+};
+
+&cru {
+   u-boot,dm-pre-reloc;
+};
+
+&grf {
+   u-boot,dm-pre-reloc;
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/rk3368-sheep-u-boot.dtsi 
b/arch/arm/dts/rk3368-sheep-u-boot.dtsi
new file mode 100644
index 000..7cf4a36
--- /dev/null
+++ b/arch/arm/dts/rk3368-sheep-u-boot.dtsi
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+   X11
+ */
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+   u-boot,dm-pre-reloc;
+};
+
+&dmc {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+&pmugrf {
+   u-boot,dm-pre-reloc;
+};
+
+&cru {
+   u-boot,dm-pre-reloc;
+};
+
+&grf {
+   u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+   u-boot,dm-pre-reloc;
+};
+
-- 
2.7.4


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[U-Boot] [PATCH 2/3] rockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards

[Andy Yan]

The default 1kb pre-reloc malloc pool is not enough for dm
core to enable the dm-pre-reloc device drivers.

Signed-off-by: Andy Yan 
---

 configs/evb-px5_defconfig  | 1 +
 configs/geekbox_defconfig  | 1 +
 configs/sheep-rk3368_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index dae5094..72e492f 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_ROCKCHIP_RK3368=y
 CONFIG_TARGET_EVB_PX5=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index a1944b4..0fd89d2 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_ROCKCHIP_RK3368=y
 CONFIG_TARGET_GEEKBOX=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index be00fad..da6b93a 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_ROCKCHIP_RK3368=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
 CONFIG_DEBUG_UART=y
-- 
2.7.4


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[U-Boot] [PATCH 3/3] rockchip: remove the hard coded uart iomux setting for px5 evb

[Andy Yan]

As the debug uart is marked as dm-pre-reloc, the pinctrl driver
will handle the correct iomux setting.

Signed-off-by: Andy Yan 
---

 board/rockchip/evb_px5/evb-px5.c | 24 
 1 file changed, 24 deletions(-)

diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
index 6dca1fc..6a47642 100644
--- a/board/rockchip/evb_px5/evb-px5.c
+++ b/board/rockchip/evb_px5/evb-px5.c
@@ -4,30 +4,6 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 #include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mach_cpu_init(void)
-{
-   struct rk3368_pmu_grf *pmugrf;
-   int node;
-
-   node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 
"rockchip,rk3368-pmugrf");
-   pmugrf = (struct rk3368_pmu_grf *)fdtdec_get_addr(gd->fdt_blob, node, 
"reg");
-
-   rk_clrsetreg(&pmugrf->gpio0d_iomux,
-GPIO0D0_MASK | GPIO0D1_MASK |
-GPIO0D2_MASK | GPIO0D3_MASK,
-GPIO0D0_GPIO << GPIO0D0_SHIFT |
-GPIO0D1_GPIO << GPIO0D1_SHIFT |
-GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
-GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
-   return 0;
-}
 
 int board_init(void)
 {
-- 
2.7.4


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Re: [U-Boot] [PATCH 2/3] rockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards

[Dr. Philipp Tomsich]

> On 02 Aug 2017, at 15:10, Andy Yan  wrote:
> 
> The default 1kb pre-reloc malloc pool is not enough for dm
> core to enable the dm-pre-reloc device drivers.
> 
> Signed-off-by: Andy Yan 
> —

Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 

See comment below.

> 
> configs/evb-px5_defconfig  | 1 +
> configs/geekbox_defconfig  | 1 +
> configs/sheep-rk3368_defconfig | 1 +
> 3 files changed, 3 insertions(+)
> 
> diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
> index dae5094..72e492f 100644
> --- a/configs/evb-px5_defconfig
> +++ b/configs/evb-px5_defconfig
> @@ -1,5 +1,6 @@
> CONFIG_ARM=y
> CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_MALLOC_F_LEN=0x1000

We even increased this to 0x2000 for TPL/SPL on the lion-board (i.e. 
RK3368-uQ7).
Should we just make 0x2000 the default for RK3368 (in Kconfig) and reduce the 
noise in defconfig?

> CONFIG_ROCKCHIP_RK3368=y
> CONFIG_TARGET_EVB_PX5=y
> CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
> diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
> index a1944b4..0fd89d2 100644
> --- a/configs/geekbox_defconfig
> +++ b/configs/geekbox_defconfig
> @@ -1,5 +1,6 @@
> CONFIG_ARM=y
> CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_MALLOC_F_LEN=0x1000
> CONFIG_ROCKCHIP_RK3368=y
> CONFIG_TARGET_GEEKBOX=y
> CONFIG_DEFAULT_DEVICE_TREE="rk3368-geekbox"
> diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
> index be00fad..da6b93a 100644
> --- a/configs/sheep-rk3368_defconfig
> +++ b/configs/sheep-rk3368_defconfig
> @@ -1,5 +1,6 @@
> CONFIG_ARM=y
> CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_MALLOC_F_LEN=0x1000
> CONFIG_ROCKCHIP_RK3368=y
> CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
> CONFIG_DEBUG_UART=y
> -- 
> 2.7.4
> 
> 

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Re: [U-Boot] [PATCH 3/3] rockchip: remove the hard coded uart iomux setting for px5 evb

[Dr. Philipp Tomsich]

> On 02 Aug 2017, at 15:10, Andy Yan  wrote:
> 
> As the debug uart is marked as dm-pre-reloc, the pinctrl driver
> will handle the correct iomux setting.
> 
> Signed-off-by: Andy Yan 
> —

Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [PATCH 2/3] rockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards

[Andreas Färber]

Am 02.08.2017 um 15:25 schrieb Dr. Philipp Tomsich:
> 
>> On 02 Aug 2017, at 15:10, Andy Yan  wrote:
>>
>> The default 1kb pre-reloc malloc pool is not enough for dm
>> core to enable the dm-pre-reloc device drivers.
>>
>> Signed-off-by: Andy Yan 
>> —
> 
> Acked-by: Philipp Tomsich 
> Reviewed-by: Philipp Tomsich 
> 
> See comment below.
> 
>>
>> configs/evb-px5_defconfig  | 1 +
>> configs/geekbox_defconfig  | 1 +
>> configs/sheep-rk3368_defconfig | 1 +
>> 3 files changed, 3 insertions(+)
>>
>> diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
>> index dae5094..72e492f 100644
>> --- a/configs/evb-px5_defconfig
>> +++ b/configs/evb-px5_defconfig
>> @@ -1,5 +1,6 @@
>> CONFIG_ARM=y
>> CONFIG_ARCH_ROCKCHIP=y
>> +CONFIG_SYS_MALLOC_F_LEN=0x1000
> 
> We even increased this to 0x2000 for TPL/SPL on the lion-board (i.e. 
> RK3368-uQ7).
> Should we just make 0x2000 the default for RK3368 (in Kconfig) and reduce the 
> noise in defconfig?

Is there any downside to it? If not, I'd say yes.

Regards,
Andreas

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Re: [U-Boot] Please pull u-boot-x86

[Tom Rini]

On Tue, Aug 01, 2017 at 08:24:50PM +0800, Bin Meng wrote:

> Hi Tom,
> 
> The following changes since commit 6364a5d4bd55beeedc11171419acd0bdff17a599:
> 
>   Prepare v2017.09-rc1 (2017-07-31 20:37:25 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-x86.git
> 
> for you to fetch changes up to 24357dfd2aec4118b9178d8bf639fb8fc02e1859:
> 
>   x86: Switch all boards to use DM SCSI (2017-08-01 20:17:02 +0800)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [GIT PULL V2] Please pull u-boot-mmc master

[Tom Rini]

On Tue, Aug 01, 2017 at 02:52:47PM +0900, Jaehoon Chung wrote:

> Dear Tom,
> 
> Could you pull these patches into u-boot/master?
> (Have tested the buildman.)
> 
> Changelog on V2:
> - Drop the Jean-Jacques's patches. After fixing it, will apply.
> 
> The following changes since commit 6364a5d4bd55beeedc11171419acd0bdff17a599:
> 
>   Prepare v2017.09-rc1 (2017-07-31 20:37:25 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mmc.git master
> 
> for you to fetch changes up to 5c970013a661c630ab28ddc3dd6766fe6bf83ece:
> 
>   regulator: palmas: disable bypass when the LDO is enabled (2017-08-01 
> 11:58:01 +0900)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH] imx6: use SION macro in SDn_CMD mux mode bitfield arguments

[Anatolij Gustschin]

Select SION by appropriate macro instead of constant.

Signed-off-by: Anatolij Gustschin 
---
 arch/arm/include/asm/arch-mx6/mx6q_pins.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index a8456a2..41f7240 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,   0x069C, 0x02B4, 0, 
0x, 0, 0)
 MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,  0x069C, 0x02B4, 1, 0x, 0, 0)
 MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,  0x069C, 0x02B4, 1, 0x0928, 5, 0)
 MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x, 0, 0)
-MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 
0x, 0, 0)
 MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x, 0, 0)
 MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0)
 MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x, 0, 0)
@@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,   0x06D8, 0x02F0, 2, 
0x0878, 1, 0)
 MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,0x06D8, 0x02F0, 3, 0x, 0, 0)
 MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,0x06D8, 0x02F0, 5, 0x, 0, 0)
 MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1,0x06D8, 0x02F0, 6, 0x, 0, 0)
-MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 
0x, 0, 0)
 MX6_PAD_DECL(SD4_CMD__NAND_RE_B,   0x06DC, 0x02F4, 1, 0x, 0, 0)
 MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,   0x06DC, 0x02F4, 2, 0x, 0, 0)
 MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,   0x06DC, 0x02F4, 2, 0x0930, 2, 0)
@@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,  0x072C, 0x0344, 3, 
0x, 0, 0)
 MX6_PAD_DECL(SD1_DAT3__WDOG2_B,0x072C, 0x0344, 4, 0x, 0, 0)
 MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x, 0, 0)
 MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,  0x072C, 0x0344, 6, 0x, 0, 0)
-MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 
0x, 0, 0)
 MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0)
 MX6_PAD_DECL(SD1_CMD__PWM4_OUT,0x0730, 0x0348, 2, 0x, 0, 0)
 MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,0x0730, 0x0348, 3, 0x, 0, 0)
@@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK,0x073C, 0x0354, 
1, 0x0828, 1, 0)
 MX6_PAD_DECL(SD2_CLK__KEY_COL5,0x073C, 0x0354, 2, 0x08E8, 3, 0)
 MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,   0x073C, 0x0354, 3, 0x07C0, 1, 0)
 MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,  0x073C, 0x0354, 5, 0x, 0, 0)
-MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 
0x, 0, 0)
 MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0)
 MX6_PAD_DECL(SD2_CMD__KEY_ROW5,0x0740, 0x0358, 2, 0x08F4, 2, 0)
 MX6_PAD_DECL(SD2_CMD__AUD4_RXC,0x0740, 0x0358, 3, 0x07BC, 1, 0)
-- 
1.9.1

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Re: [U-Boot] [PATCH] imx6: use SION macro in SDn_CMD mux mode bitfield arguments

[Stefano Babic]

On 02/08/2017 15:56, Anatolij Gustschin wrote:
> Select SION by appropriate macro instead of constant.
> 
> Signed-off-by: Anatolij Gustschin 
> ---
>  arch/arm/include/asm/arch-mx6/mx6q_pins.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h 
> b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
> index a8456a2..41f7240 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
> @@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 
> 0x, 0, 0)
>  MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,0x069C, 0x02B4, 1, 0x, 0, 0)
>  MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,0x069C, 0x02B4, 1, 0x0928, 5, 0)
>  MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,   0x069C, 0x02B4, 5, 0x, 0, 0)
> -MX6_PAD_DECL(SD3_CMD__SD3_CMD,   0x06A0, 0x02B8, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD3_CMD__SD3_CMD,   0x06A0, 0x02B8, 0 | 
> IOMUX_CONFIG_SION, 0x, 0, 0)
>  MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,   0x06A0, 0x02B8, 1, 0x, 0, 0)
>  MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,   0x06A0, 0x02B8, 1, 0x0924, 2, 0)
>  MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,   0x06A0, 0x02B8, 2, 0x, 0, 0)
> @@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 
> 0x0878, 1, 0)
>  MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,  0x06D8, 0x02F0, 3, 0x, 0, 0)
>  MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,  0x06D8, 0x02F0, 5, 0x, 0, 0)
>  MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1,  0x06D8, 0x02F0, 6, 0x, 0, 0)
> -MX6_PAD_DECL(SD4_CMD__SD4_CMD,   0x06DC, 0x02F4, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD4_CMD__SD4_CMD,   0x06DC, 0x02F4, 0 | 
> IOMUX_CONFIG_SION, 0x, 0, 0)
>  MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x, 0, 0)
>  MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x, 0, 0)
>  MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0)
> @@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,0x072C, 0x0344, 
> 3, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_DAT3__WDOG2_B,  0x072C, 0x0344, 4, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,   0x072C, 0x0344, 5, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,0x072C, 0x0344, 6, 0x, 0, 0)
> -MX6_PAD_DECL(SD1_CMD__SD1_CMD,   0x0730, 0x0348, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD1_CMD__SD1_CMD,   0x0730, 0x0348, 0 | 
> IOMUX_CONFIG_SION, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI,   0x0730, 0x0348, 1, 0x0830, 0, 0)
>  MX6_PAD_DECL(SD1_CMD__PWM4_OUT,  0x0730, 0x0348, 2, 0x, 0, 0)
>  MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,  0x0730, 0x0348, 3, 0x, 0, 0)
> @@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK,  0x073C, 0x0354, 
> 1, 0x0828, 1, 0)
>  MX6_PAD_DECL(SD2_CLK__KEY_COL5,  0x073C, 0x0354, 2, 0x08E8, 3, 0)
>  MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0)
>  MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,0x073C, 0x0354, 5, 0x, 0, 0)
> -MX6_PAD_DECL(SD2_CMD__SD2_CMD,   0x0740, 0x0358, 16, 0x, 0, 0)
> +MX6_PAD_DECL(SD2_CMD__SD2_CMD,   0x0740, 0x0358, 0 | 
> IOMUX_CONFIG_SION, 0x, 0, 0)
>  MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI,   0x0740, 0x0358, 1, 0x0830, 1, 0)
>  MX6_PAD_DECL(SD2_CMD__KEY_ROW5,  0x0740, 0x0358, 2, 0x08F4, 2, 0)
>  MX6_PAD_DECL(SD2_CMD__AUD4_RXC,  0x0740, 0x0358, 3, 0x07BC, 1, 0)
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic

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[U-Boot] [PATCH] imx6: clock: correct comment for PLL_VIDEO

[Anatolij Gustschin]

This appear to be a copy-paste error, clean it up.

Signed-off-by: Anatolij Gustschin 
---
 arch/arm/mach-imx/mx6/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 1f2739e..0e019c4 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -19,7 +19,7 @@ enum pll_clocks {
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET,   /* ENET PLL */
PLL_AUDIO,  /* AUDIO PLL */
-   PLL_VIDEO,  /* AUDIO PLL */
+   PLL_VIDEO,  /* VIDEO PLL */
 };
 
 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-- 
1.9.1

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Re: [U-Boot] [PATCH] imx6: clock: correct comment for PLL_VIDEO

[Stefano Babic]

On 02/08/2017 16:05, Anatolij Gustschin wrote:
> This appear to be a copy-paste error, clean it up.
> 
> Signed-off-by: Anatolij Gustschin 
> ---
>  arch/arm/mach-imx/mx6/clock.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
> index 1f2739e..0e019c4 100644
> --- a/arch/arm/mach-imx/mx6/clock.c
> +++ b/arch/arm/mach-imx/mx6/clock.c
> @@ -19,7 +19,7 @@ enum pll_clocks {
>   PLL_USBOTG, /* OTG USB PLL */
>   PLL_ENET,   /* ENET PLL */
>   PLL_AUDIO,  /* AUDIO PLL */
> - PLL_VIDEO,  /* AUDIO PLL */
> + PLL_VIDEO,  /* VIDEO PLL */
>  };
>  
>  struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 1/2] Move PHYLIB to Kconfig

[Joe Hershberger]

On Tue, Aug 1, 2017 at 7:19 PM, Alexandru Gagniuc  wrote:
> Signed-off-by: Alexandru Gagniuc 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 2/2] Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig

[Joe Hershberger]

On Tue, Aug 1, 2017 at 7:20 PM, Alexandru Gagniuc  wrote:
> Signed-off-by: Alexandru Gagniuc 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module

[Tom Rini]

On Wed, Aug 02, 2017 at 11:58:42AM +0200, Stefano Babic wrote:
> On 07/07/2017 12:40, Ben Whitten wrote:
> > This board is based on the Atmel 9x5 eval board.
> > Supporting the following features:
> >  - Boot from NAND Flash
> >  - Ethernet
> >  - FIT
> >  - SPL
> > 
> 
> Patch is assigned to me. However, this is Atmel, now orphaned. I haven't
> work with AT-91 since a very long time, so I cannot say more about
> patches, but it is a pity if the patches will be lost. Tom, should I
> merge them even if they are not i.MX related ? Or do you pick them
> yourself ?

Ah, sorry, I saw laird, had the WiFi modules they do for i.MX series
platforms in mind and went "oh, must be an i.MX system".  Please toss
them back to me, thanks!

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[U-Boot] [PATCH v2 1/2] imx: imx6ul: correct get_cpu_speed_grade_hz on 696MHz SoCs

[Sébastien Szymanski]

Return the correct value when the speed grade is 696MHz.

Signed-off-by: Sébastien Szymanski 
---
Changes v1 -> v2:
 - Only true on i.MX6UL so adapt the subject and commit log accordingly.
---
 arch/arm/mach-imx/mx6/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index af31673..7607456 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -130,7 +130,7 @@ u32 get_cpu_speed_grade_hz(void)
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 52800;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
-   return 6960;
+   return 69600;
else
return 0;
}
-- 
2.7.3

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[U-Boot] [PATCH 2/2] imx: imx6ull: correct get_cpu_speed_grade_hz

[Sébastien Szymanski]

i.MX6ULL has different speed grades than i.MX6UL.

Signed-off-by: Sébastien Szymanski 
---
Notice that the i.MX6ULL RM says:
2b'00: 800MHz; 2b'01: 850MHz; 2b'10: 1GHz; 2b'11: 1.2Ghz;
which seems incorrect. The commit [1] confirmed it, but I cannot find any
996MHz i.MX6ULL on the NXP website. According to [2], there are only 3 i.MX6ULL
versions: 528, 792 and 900MHz.

[1] 
http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/commit/arch/arm/mach-imx/mach-imx6ul.c?h=imx_4.1.15_2.0.0_ga&id=e8b9e8acb5ee44f48e048d744ccae4b6b02ef6a6
[2] http://www.nxp.com/docs/en/data-sheet/IMX6ULLIEC.pdf
---
 arch/arm/mach-imx/mx6/soc.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 7607456..c15b9cb 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -114,6 +114,12 @@ u32 get_cpu_rev(void)
 #define OCOTP_CFG3_SPEED_528MHZ 1
 #define OCOTP_CFG3_SPEED_696MHZ 2
 
+/*
+ * For i.MX6ULL
+ */
+#define OCOTP_CFG3_SPEED_792MHZ 2
+#define OCOTP_CFG3_SPEED_900MHZ 3
+
 u32 get_cpu_speed_grade_hz(void)
 {
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -126,7 +132,7 @@ u32 get_cpu_speed_grade_hz(void)
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
 
-   if (is_mx6ul() || is_mx6ull()) {
+   if (is_mx6ul()) {
if (val == OCOTP_CFG3_SPEED_528MHZ)
return 52800;
else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -135,6 +141,17 @@ u32 get_cpu_speed_grade_hz(void)
return 0;
}
 
+   if (is_mx6ull()) {
+   if (val == OCOTP_CFG3_SPEED_528MHZ)
+   return 52800;
+   else if (val == OCOTP_CFG3_SPEED_792MHZ)
+   return 79200;
+   else if (val == OCOTP_CFG3_SPEED_900MHZ)
+   return 9;
+   else
+   return 0;
+   }
+
switch (val) {
/* Valid for IMX6DQ */
case OCOTP_CFG3_SPEED_1P2GHZ:
-- 
2.7.3

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Re: [U-Boot] [PATCH 1/8] armv8: Add workaround for USB erratum A-009008

[York Sun]

On 08/02/2017 02:55 AM, Ran Wang wrote:
> Hello Sir,
>  May I know the review result for this patch set? Thank you.
> BR
> Ran

Ran,

I have seen three versions from Suresh, one version from Yinbo, and one 
version from you. Neither you or Yinbo updated the version number, or 
included change log. You have Suresh's signature on 7 of the 8 patches. 
So I am guessing you are resending the patches based on my comment to 
Yingbo's patch set. Without any information, I am treating them as new 
patches and will review them in the order I receive them.

York
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Re: [U-Boot] [PATCH] efi_loader: make pool allocations cacheline aligned

[Brüns , Stefan]

On Mittwoch, 2. August 2017 11:28:37 CEST Rob Clark wrote:
> On Tue, Aug 1, 2017 at 9:10 PM, Heinrich Schuchardt
[...]
> >> 
> >> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type,
> >> unsigned long size,>> 
> >>  {
> >>  
> >>   efi_status_t r;
> >>   efi_physical_addr_t t;
> >> 
> >> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >>
> >> EFI_PAGE_SHIFT; + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct
> >> efi_pool_allocation), +  EFI_PAGE_SIZE);
> >> 
> >>   if (size == 0) {
> >>   
> >>   *buffer = NULL;
> > 
> > NAK
> > 
> > With DIV_ROUND_UP you introduce a 64bit division. Depending on the
> > architecture this is only available via stdlib which is not available in
> > U-Boot.
> 
> The divisor is a constant power of two so compiler should turn this into a
> shift
> > Please, use
> > + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
> > as in the original line.
> 
> This was actually incorrect (missing a "- 1"), which is why I decided
> to stop open-coding DIV_ROUND_UP().

EFI_PAGE_MASK == EFI_PAGE_SIZE - 1

Kind regards,

Stefan
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Re: [U-Boot] [PATCH] misc: Makefile: Add condition on build i2c_eeprom

[Tom Rini]

On Wed, Aug 02, 2017 at 03:47:58PM +0800, Wenyou Yang wrote:

> The i2c_eeprom isn't always necessary when building for SPL,
> add the condition on build i2c_eeprom.
> 
> Signed-off-by: Wenyou Yang 
> ---
> 
>  drivers/misc/Makefile | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 10265c8fb4..ccc84c38fc 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -20,7 +20,13 @@ obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
>  endif
>  obj-$(CONFIG_FSL_IIM) += fsl_iim.o
>  obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
> +ifdef CONFIG_SPL_BUILD
> +ifneq ($(CONFIG_SPL_I2C_SUPPORT),)
> +obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
> +endif
> +else
>  obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
> +endif
>  obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
>  obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
>  obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o

What's wrong with building this when not required?  Build failure?  If
so, we should add SPL_I2C_EEPROM and then the above becomes
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
or so.  Thanks!

-- 
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Re: [U-Boot] [PATCH] imx-common: spl: return boot mode for asked MMC device in spl_boot_mode()

[Anatolij Gustschin]

Hi Stefano,

On Wed, 2 Aug 2017 11:54:24 +0200
Stefano Babic sba...@denx.de wrote:
...
> > +++ b/arch/arm/mach-imx/spl.c
> > @@ -84,7 +84,7 @@ u32 spl_boot_device(void)
> >  /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
> >  u32 spl_boot_mode(const u32 boot_device)
> >  {
> > -   switch (spl_boot_device()) {
> > +   switch (boot_device) {
> > /* for MMC return either RAW or FAT mode */
> > case BOOT_DEVICE_MMC1:
> > case BOOT_DEVICE_MMC2:
> >   
> 
> Nevertheless it seems difficult to be consistent. Let's start with the
> case where a on-board device (SPI or eMMC) does not boot, and the way to
> save the board is to boot from an external board. And SPL on the onboard
> flash is damaged, but not u-boot.img. Anyway, we want that the board
> boots with its consistent status, that is with the pair SPL+u-boot.img.
> In the example I tracked, both from the SD card. This is consistent
> using spl_boot_device, because it does not try to boot from a different
> device as the one where SPL was loaded.

thanks for explanation, I'll have to find another way then, or
will maintain this patch out of tree.

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Re: [U-Boot] [PATCH] efi_loader: make pool allocations cacheline aligned

[Rob Clark]

On Wed, Aug 2, 2017 at 11:24 AM, Brüns, Stefan
 wrote:
> On Mittwoch, 2. August 2017 11:28:37 CEST Rob Clark wrote:
>> On Tue, Aug 1, 2017 at 9:10 PM, Heinrich Schuchardt
> [...]
>> >>
>> >> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type,
>> >> unsigned long size,>>
>> >>  {
>> >>
>> >>   efi_status_t r;
>> >>   efi_physical_addr_t t;
>> >>
>> >> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >>
>> >> EFI_PAGE_SHIFT; + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct
>> >> efi_pool_allocation), +  EFI_PAGE_SIZE);
>> >>
>> >>   if (size == 0) {
>> >>
>> >>   *buffer = NULL;
>> >
>> > NAK
>> >
>> > With DIV_ROUND_UP you introduce a 64bit division. Depending on the
>> > architecture this is only available via stdlib which is not available in
>> > U-Boot.
>>
>> The divisor is a constant power of two so compiler should turn this into a
>> shift
>> > Please, use
>> > + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>> > as in the original line.
>>
>> This was actually incorrect (missing a "- 1"), which is why I decided
>> to stop open-coding DIV_ROUND_UP().
>
> EFI_PAGE_MASK == EFI_PAGE_SIZE - 1
>

Oh, you're right, I was reading that as PAGE_SIZE, not PAGE_MASK.  All
the more reason we should use DIV_ROUND_UP().

BR,
-R
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[U-Boot] [PATCH] mx6sabresd: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values

[Breno Lima]

The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima 
---
 board/freescale/mx6sabresd/mx6sabresd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index e416042..5329c3b 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -755,8 +755,8 @@ static void gpr_init(void)
writel(0xF0CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-   writel(0x007F007F, &iomux->gpr[6]);
-   writel(0x007F007F, &iomux->gpr[7]);
+   writel(0x77177717, &iomux->gpr[6]);
+   writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
-- 
2.7.4

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Re: [U-Boot] [PATCH] vsprintf.c: add wide string (%ls) support

[Heinrich Schuchardt]

On 08/02/2017 11:38 AM, Rob Clark wrote:
> On Tue, Aug 1, 2017 at 10:22 PM, Heinrich Schuchardt  
> wrote:
>> On 07/31/2017 02:42 PM, Rob Clark wrote:
>>> This is convenient for efi_loader which deals a lot with utf16.
>>>
>>> Signed-off-by: Rob Clark 
>>> ---
>>>  lib/vsprintf.c | 39 +--
>>>  1 file changed, 37 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/lib/vsprintf.c b/lib/vsprintf.c
>>> index 874a2951f7..84e157ecb1 100644
>>> --- a/lib/vsprintf.c
>>> +++ b/lib/vsprintf.c
>>> @@ -270,6 +270,35 @@ static char *string(char *buf, char *end, char *s, int 
>>> field_width,
>>>   return buf;
>>>  }
>>>
>>> +static size_t strnlen16(const u16* s, size_t count)
>>> +{
>>> + const u16 *sc;
>>> +
>>> + for (sc = s; count-- && *sc; ++sc)
>>> + /* nothing */;
>>> + return sc - s;
>>> +}
>>> +
>>> +static char *string16(char *buf, char *end, u16 *s, int field_width,
>>> + int precision, int flags)
>>> +{
>>> + int len, i;
>>> +
>>> + if (s == NULL)
>>> + s = L"";
>>
>> The L notation creates a wchar_t string. The width of wchar_t depends on
>> gcc compiler flag -fshort-wchar.
>>
>> vsprintf.c is not compiled with -fshort-wchar. So change this to
>>
>> const u16 null[] = { '<', 'N', 'U', 'L', 'L', '>', 0};
>> s = null;
> 
> oh, I have another patch that adds -fshort-wchar globally.. which I
> probably should have split out and sent with this.
> 
> The problem is we cannot mix objects using short-wchar and ones that
> don't without a compiler warning.  Travis would complain a lot more
> but I guess BOOTEFI_HELLO is not normally enabled.
> 
> With addition of efi_bootmgr.c we really want to be able to use
> L"string" to be u16.. and I don't think u-boot has any good reason to
> use 32b wchar.
> 
> But maybe for this code I should use wchar_t instead of u16.
> 
> BR,
> -R

ext4 filenames may contain letters with Unicode values > 2**16,
e.g. using Takri letters: 𑚀𑚁𑚂

So ext4ls probably should be enabled to display these on a Unicode console.

Using -fshort-wchar globally is not necessary. Only UEFI requires 16 bit
wchar_t. We should rather not enforce the UEFI standard on the rest of
the code.

> 
>>> +
>>> + len = strnlen16(s, precision);
>>> +
>>> + if (!(flags & LEFT))
>>> + while (len < field_width--)
>>> + ADDCH(buf, ' ');
>>> + for (i = 0; i < len; ++i)
>>> + ADDCH(buf, *s++);

I would prefer to see a conversion to UTF-8 here.

Conversion from 32bit Unicode (Or the capped 16bit Unicode of EFI) is
quite easy. This is what I used in another project:

uint32_t u = s[i];
char c[5];
if (u < 0x80) {
c[0] = u & 0x7F;
c[1] = 0;
str.append(c);
} else if (u < 0x800) {
c[1] = 0x80 | (u & 0x3F);
u >>= 6;
c[0] = 0xC0 | (u & 0x1F);
c[2] = 0;
str.append(c);
} else if (u < 0x1) {
c[2] = 0x80 | (u & 0x3F);
u >>= 6;
c[1] = 0x80 | (u & 0x3F);
u >>= 6;
c[0] = 0xE0 | (u & 0x0F);
c[3] = 0;
str.append(c);
} else if (u < 0x20) {
c[3] = 0x80 | (u & 0x3F);
u >>= 6;
c[2] = 0x80 | (u & 0x3F);
u >>= 6;
c[1] = 0x80 | (u & 0x3F);
u >>= 6;
c[0] = 0xF0 | (u & 0x07);
c[4] = 0;
str.append(c);
} else {
throw invalid;
}

Best regards

Heinrich

>>> + while (len < field_width--)
>>> + ADDCH(buf, ' ');
>>> + return buf;
>>> +}
>>> +
>>>  #ifdef CONFIG_CMD_NET
>>>  static const char hex_asc[] = "0123456789abcdef";
>>>  #define hex_asc_lo(x)hex_asc[((x) & 0x0f)]
>>> @@ -528,8 +557,14 @@ repeat:
>>>   continue;
>>>
>>>   case 's':
>>> - str = string(str, end, va_arg(args, char *),
>>> -  field_width, precision, flags);
>>> + if (qualifier == 'l') {
>>
>> According to ISO 9899:1999 %ls is used to indicate a wchar_t string,
>> which may be u32 * or u16 * depending on GCC flag -fshort-wchar.
>>
>> Wouldn't it make sense to use some other notation, e.g. %S, to indicate
>> that we explicitly mean u16 *?
>>
>> Please, add a comment into the code indicating why we need u16 * support
>> referring to the UEFI spec.
>>
>> Best regards
>>
>> Heinrich
>>
>>> + str = string16(str, end, va_arg(args, u16 *),
>>> +field_width, precision, flags);
>>> +
>>> + } else {
>>> + str = string(str, end, va_arg(args, char *),
>>> +  field_width, precision, flags);
>>> + }
>>>   continue;
>>>
>>>   case 'p':
>>>
>>
> 

__

[U-Boot] [PATCH] mx6sabreauto: Fix IOMUXC_GPR6 and IOMUXC_GPR7 values

[Breno Lima]

The IPU AXI QoS for the i.MX6QP and i.MX6DP processors have to be set as
commented in the code:
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */

Set IOMUXC_GPR6 and IOMUXC_GPR7 to 0x77177717 instead of 0x007F007F.

Signed-off-by: Breno Lima 
---
 board/freescale/mx6sabreauto/mx6sabreauto.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c 
b/board/freescale/mx6sabreauto/mx6sabreauto.c
index a5703a3..cad6004 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -806,8 +806,8 @@ static void gpr_init(void)
writel(0xF0CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-   writel(0x007F007F, &iomux->gpr[6]);
-   writel(0x007F007F, &iomux->gpr[7]);
+   writel(0x77177717, &iomux->gpr[6]);
+   writel(0x77177717, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/5] board_f: Drop the timer after relocation

[Simon Glass]

Hi Bin,

On 22 July 2017 at 22:36, Bin Meng  wrote:
> Hi Simon,
>
> On Sun, Jul 16, 2017 at 7:41 AM, Simon Glass  wrote:
>> Once U-Boot relocates itself the existing driver-model timer (if any) is
>> no-longer valid until the device is reinitialised. Any use of the device
>> may cause a crash. To handle this, set the timer to NULL after relocation.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  common/board_f.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/common/board_f.c b/common/board_f.c
>> index ffa84e3566..d675dc38ac 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -979,6 +979,7 @@ void board_init_f_r(void)
>>  * UART if available.
>>  */
>> gd->flags &= ~GD_FLG_SERIAL_READY;
>> +   gd->timer = NULL;
>
> This needs to be wrapped with #ifdef CONFIG_TIMER.

Fixed in v2.

>
> But there is already a config option CONFIG_TIMER_EARLY, and gd->timer
> is zeroed in initr_dm(). We should fix problems with existing
> CONFIG_TIMER_EARLY.

Yes I agree, although this patch is needed regardless, I think. We
should not have invalid timers hanging around.

>
>>
>> /*
>>  * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
>> --
>
> Regards,
> Bin

Regards,
Simon
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Re: [U-Boot] [PATCH 2/5] dm: x86: Allow TSC timer to be used before DM is ready

[Simon Glass]

Hi Bin,

On 22 July 2017 at 22:36, Bin Meng  wrote:
> Hi Simon,
>
> On Sun, Jul 16, 2017 at 7:41 AM, Simon Glass  wrote:
>> With bootstage we need access to the timer before driver model is set up.
>> To handle this, put the required state in global_data and provide a new
>> function to set up the device, separate from the driver's probe() method.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/include/asm/global_data.h |  1 +
>>  drivers/timer/tsc_timer.c  | 18 +-
>>  2 files changed, 14 insertions(+), 5 deletions(-)
>>
>
> Please check my comments against [1/5] in this series. We should be
> able to do something with existing CONFIG_TIMER_EARLY. Updating TSC
> timer can only solve this specific timer issue.

Yes I agree. I did wonder about that at the time, but didn't investigate it.

I'll take a look at this next week when I have access to a link.

Regards,
Simon
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[U-Boot] [PATCH v2 1/2] dm: core: Drop use of strlcpy()

[Simon Glass]

We can use printf() to limit the string width. Adjust the code to do this
instead of using strlcpy() which is a bit clumbsy.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Add new patch to drop use of strlcpy()

 drivers/core/dump.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index c3e109e7ed..1bb64098f4 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -14,11 +14,9 @@ static void show_devices(struct udevice *dev, int depth, int 
last_flag)
 {
int i, is_last;
struct udevice *child;
-   char class_name[12];
 
/* print the first 11 characters to not break the tree-format. */
-   strlcpy(class_name, dev->uclass->uc_drv->name, sizeof(class_name));
-   printf(" %-11s [ %c ]", class_name,
+   printf(" %-10.10s [ %c ]", dev->uclass->uc_drv->name,
   dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ');
 
for (i = depth; i >= 0; i--) {
@@ -50,7 +48,7 @@ void dm_dump_all(void)
 
root = dm_root();
if (root) {
-   printf(" Class   Probed   Name\n");
+   printf(" Class  Probed   Name\n");
printf("\n");
show_devices(root, -1, 0);
}
-- 
2.14.0.rc1.383.gd1ce394fe2-goog

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[U-Boot] [PATCH v2 2/2] dm: core: Show driver name with 'dm tree'

[Simon Glass]

It is often useful to see which driver was actually selected for each
device. Add a new 'Driver' column to provide this information. Sample
output:

 Class   Probed   Driver Name

 root[ + ]root_drive root_driver
 keyboard[ + ]i8042_kbd  |-- keyboard
 serial  [ + ]ns16550_se |-- serial
 rtc [   ]rtc_mc1468 |-- rtc
 timer   [ + ]tsc_timer  |-- tsc-timer
 syscon  [ + ]ich6_pinct |-- pch_pinctrl
 pci [ + ]pci_x86|-- pci
 northbridge [ + ]bd82x6x_no |   |-- northbridge@0,0
 video   [ + ]bd82x6x_vi |   |-- gma@2,0
 vidconsole0 [ + ]vidconsole |   |   `-- gma@2,0.vidconsole0
...

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v2:
- Drop one space between 'Probed' and 'Driver'

 drivers/core/dump.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index 1bb64098f4..6c6b944453 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -16,8 +16,8 @@ static void show_devices(struct udevice *dev, int depth, int 
last_flag)
struct udevice *child;
 
/* print the first 11 characters to not break the tree-format. */
-   printf(" %-10.10s [ %c ]", dev->uclass->uc_drv->name,
-  dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ');
+   printf(" %-10.10s [ %c ]   %-10.10s  ", dev->uclass->uc_drv->name,
+  dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
 
for (i = depth; i >= 0; i--) {
is_last = (last_flag >> i) & 1;
@@ -48,7 +48,7 @@ void dm_dump_all(void)
 
root = dm_root();
if (root) {
-   printf(" Class  Probed   Name\n");
+   printf(" Class  Probed  Driver  Name\n");
printf("\n");
show_devices(root, -1, 0);
}
-- 
2.14.0.rc1.383.gd1ce394fe2-goog

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Re: [U-Boot] [PATCH] vsprintf.c: add wide string (%ls) support

[Rob Clark]

On Wed, Aug 2, 2017 at 1:05 PM, Heinrich Schuchardt  wrote:
> On 08/02/2017 11:38 AM, Rob Clark wrote:
>> On Tue, Aug 1, 2017 at 10:22 PM, Heinrich Schuchardt  
>> wrote:
>>> On 07/31/2017 02:42 PM, Rob Clark wrote:
 This is convenient for efi_loader which deals a lot with utf16.

 Signed-off-by: Rob Clark 
 ---
  lib/vsprintf.c | 39 +--
  1 file changed, 37 insertions(+), 2 deletions(-)

 diff --git a/lib/vsprintf.c b/lib/vsprintf.c
 index 874a2951f7..84e157ecb1 100644
 --- a/lib/vsprintf.c
 +++ b/lib/vsprintf.c
 @@ -270,6 +270,35 @@ static char *string(char *buf, char *end, char *s, 
 int field_width,
   return buf;
  }

 +static size_t strnlen16(const u16* s, size_t count)
 +{
 + const u16 *sc;
 +
 + for (sc = s; count-- && *sc; ++sc)
 + /* nothing */;
 + return sc - s;
 +}
 +
 +static char *string16(char *buf, char *end, u16 *s, int field_width,
 + int precision, int flags)
 +{
 + int len, i;
 +
 + if (s == NULL)
 + s = L"";
>>>
>>> The L notation creates a wchar_t string. The width of wchar_t depends on
>>> gcc compiler flag -fshort-wchar.
>>>
>>> vsprintf.c is not compiled with -fshort-wchar. So change this to
>>>
>>> const u16 null[] = { '<', 'N', 'U', 'L', 'L', '>', 0};
>>> s = null;
>>
>> oh, I have another patch that adds -fshort-wchar globally.. which I
>> probably should have split out and sent with this.
>>
>> The problem is we cannot mix objects using short-wchar and ones that
>> don't without a compiler warning.  Travis would complain a lot more
>> but I guess BOOTEFI_HELLO is not normally enabled.
>>
>> With addition of efi_bootmgr.c we really want to be able to use
>> L"string" to be u16.. and I don't think u-boot has any good reason to
>> use 32b wchar.
>>
>> But maybe for this code I should use wchar_t instead of u16.
>>
>> BR,
>> -R
>
> ext4 filenames may contain letters with Unicode values > 2**16,
> e.g. using Takri letters: 𑚀𑚁𑚂
>
> So ext4ls probably should be enabled to display these on a Unicode console.
>
> Using -fshort-wchar globally is not necessary. Only UEFI requires 16 bit
> wchar_t. We should rather not enforce the UEFI standard on the rest of
> the code.

The alternative is disabling a gcc warning about mixing 32b and 16b
wchar.. and really mixing 32b and 16b wchar seems like a bad idea.

We could use -fshort-wchar only if EFI_LOADER is enabled.  Technically
if we are a UEFI implementation, we do not need to have ext2/ext4 (or
really anything other than fat/vfat).

>>
 +
 + len = strnlen16(s, precision);
 +
 + if (!(flags & LEFT))
 + while (len < field_width--)
 + ADDCH(buf, ' ');
 + for (i = 0; i < len; ++i)
 + ADDCH(buf, *s++);
>
> I would prefer to see a conversion to UTF-8 here.
>
> Conversion from 32bit Unicode (Or the capped 16bit Unicode of EFI) is
> quite easy. This is what I used in another project:
>
> uint32_t u = s[i];
> char c[5];
> if (u < 0x80) {
> c[0] = u & 0x7F;
> c[1] = 0;
> str.append(c);
> } else if (u < 0x800) {
> c[1] = 0x80 | (u & 0x3F);
> u >>= 6;
> c[0] = 0xC0 | (u & 0x1F);
> c[2] = 0;
> str.append(c);
> } else if (u < 0x1) {
> c[2] = 0x80 | (u & 0x3F);
> u >>= 6;
> c[1] = 0x80 | (u & 0x3F);
> u >>= 6;
> c[0] = 0xE0 | (u & 0x0F);
> c[3] = 0;
> str.append(c);
> } else if (u < 0x20) {
> c[3] = 0x80 | (u & 0x3F);
> u >>= 6;
> c[2] = 0x80 | (u & 0x3F);
> u >>= 6;
> c[1] = 0x80 | (u & 0x3F);
> u >>= 6;
> c[0] = 0xF0 | (u & 0x07);
> c[4] = 0;
> str.append(c);
> } else {
> throw invalid;
> }

I did add a utf16_to_utf8() (based on code from grub) as part of the
efi-variables patch, since there we are dealing with utf16 coming from
outside of grub.  I guess I could use that.  I think that mostly
matters if we end up printing strings that originate outside of
u-boot, but I guess that will be the case for filenames in a
device-path.

BR,
-R

> Best regards
>
> Heinrich
>
 + while (len < field_width--)
 + ADDCH(buf, ' ');
 + return buf;
 +}
 +
  #ifdef CONFIG_CMD_NET
  static const char hex_asc[] = "0123456789abcdef";
  #define hex_asc_lo(x)hex_asc[((x) & 0x0f)]
 @@ -528,8 +557,14 @@ repeat:
   continue;

   case 's':
 - str = string(str, end, va_arg(args, char *),
 -  field_width, precision, flags);
 + 

Re: [U-Boot] [U-Boot, 5/5] boot: fdt: fixup the memory dt nodes falcon boot

[York Sun]

On 04/18/2017 04:57 AM, B, Ravi wrote:
> In single stage bootmode or falcon boot mode,
> the SPL shall update the memory dt nodes
> spl_fixup_fdt() based on DDR configuration for
> specific platform.
> 
> Signed-off-by: Ravi Babu 
> ---
>   common/spl/spl.c | 40 
>   1 file changed, 40 insertions(+)

Clearly I am late for this thread. I only notice this change when I try 
to merge my FIT improvement for falcon boot.

Why do we need to fixup the device tree for falcon boot at all? The 
device tree is static, saved as argument when exporting it, isn't it? As 
far as the normal boot fixes up the device tree, the exported device 
tree is correct.

York
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Re: [U-Boot] [U-Boot, 5/5] boot: fdt: fixup the memory dt nodes falcon boot

[Tom Rini]

On Wed, Aug 02, 2017 at 07:10:51PM +, York Sun wrote:
> On 04/18/2017 04:57 AM, B, Ravi wrote:
> > In single stage bootmode or falcon boot mode,
> > the SPL shall update the memory dt nodes
> > spl_fixup_fdt() based on DDR configuration for
> > specific platform.
> > 
> > Signed-off-by: Ravi Babu 
> > ---
> >   common/spl/spl.c | 40 
> >   1 file changed, 40 insertions(+)
> 
> Clearly I am late for this thread. I only notice this change when I try 
> to merge my FIT improvement for falcon boot.
> 
> Why do we need to fixup the device tree for falcon boot at all? The 
> device tree is static, saved as argument when exporting it, isn't it? As 
> far as the normal boot fixes up the device tree, the exported device 
> tree is correct.

So, the further argument here is that if you have to edit the dts to
include a valid amount of memory so that the dtb the kernel spits out is
useful in falcon mode, it's not at all useful in development.

-- 
Tom


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[U-Boot] [PATCH v4 03/66] rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64

[Philipp Tomsich]

The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.

To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-rockchip/save_boot_param.S | 37 
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-rockchip/save_boot_param.S 
b/arch/arm/mach-rockchip/save_boot_param.S
index 5e6c8db..945a9dd 100644
--- a/arch/arm/mach-rockchip/save_boot_param.S
+++ b/arch/arm/mach-rockchip/save_boot_param.S
@@ -1,11 +1,47 @@
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include 
 
+#if defined(CONFIG_ARM64)
+.globl SAVE_SP_ADDR
+SAVE_SP_ADDR:
+   .quad 0
+
+ENTRY(save_boot_params)
+   sub sp, sp, #0x100
+   stp x29, x30, [sp, #0x50]
+   stp x27, x28, [sp, #0x40]
+   stp x25, x26, [sp, #0x30]
+   stp x23, x24, [sp, #0x20]
+   stp x21, x22, [sp, #0x10]
+   stp x19, x20, [sp, #0]
+   ldr x8, =SAVE_SP_ADDR
+   mov x9, sp
+   str x9, [x8]
+   b   save_boot_params_ret  /* back to my caller */
+ENDPROC(save_boot_params)
+
+.globl _back_to_bootrom_s
+ENTRY(_back_to_bootrom_s)
+   ldr x0, =SAVE_SP_ADDR
+   ldr x0, [x0]
+   mov sp, x0
+   ldp x29, x30, [sp, #0x50]
+   ldp x27, x28, [sp, #0x40]
+   ldp x25, x26, [sp, #0x30]
+   ldp x23, x24, [sp, #0x20]
+   ldp x21, x22, [sp, #0x10]
+   ldp x19, x20, [sp]
+   add sp, sp, #0x100
+   mov x0, xzr
+   ret
+ENDPROC(_back_to_bootrom_s)
+#else
 .globl SAVE_SP_ADDR
 SAVE_SP_ADDR:
.word 0
@@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s)
mov r0, #0
pop {r1-r12, pc}
 ENDPROC(_back_to_bootrom_s)
+#endif
-- 
2.1.4

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[U-Boot] [PATCH v4 01/66] spl: add a 'return to bootrom' boot method

[Philipp Tomsich]

Some devices (e.g. the RK3368) have only limited SRAM, but provide
support for loading the next boot stage after our SPL performs basic
setup (e.g. DRAM).

For target systems like these, we add a boot device BOOTROM that will
invoke a board-specific hook to return to the bootrom (if supported).

Signed-off-by: Philipp Tomsich 

Reviewed-by: Tom Rini 
Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/spl.h |  1 +
 common/spl/Kconfig | 11 +++
 common/spl/Makefile|  1 +
 common/spl/spl_bootrom.c   | 27 +++
 include/spl.h  | 10 ++
 5 files changed, 50 insertions(+)
 create mode 100644 common/spl/spl_bootrom.c

diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 0e67470..df45511 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -30,6 +30,7 @@ enum {
BOOT_DEVICE_BOARD,
BOOT_DEVICE_DFU,
BOOT_DEVICE_XIP,
+   BOOT_DEVICE_BOOTROM,
BOOT_DEVICE_NONE
 };
 #endif
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 4de8139..ee767b7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -25,6 +25,17 @@ config SPL_BOARD_INIT
  spl_board_init() from board_init_r(). This function should be
  provided by the board.
 
+config SPL_BOOTROM_SUPPORT
+bool "Support returning to the BOOTROM"
+   help
+ Some platforms (e.g. the Rockchip RK3368) provide support in their
+ ROM for loading the next boot-stage after performing basic setup
+ from the SPL stage.
+
+ Enable this option, to return to the BOOTROM through the
+ BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+ boot device list, if not implemented for a given board)
+
 config SPL_RAW_IMAGE_SUPPORT
bool "Support SPL loading and booting of RAW images"
default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 47a64dd..189b272 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,6 +10,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o
 obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
 obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c
new file mode 100644
index 000..6804246
--- /dev/null
+++ b/common/spl/spl_bootrom.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+__weak void board_return_to_bootrom(void)
+{
+}
+
+static int spl_return_to_bootrom(struct spl_image_info *spl_image,
+struct spl_boot_device *bootdev)
+{
+   /*
+* If the board implements a way to return to its ROM (with
+* the expectation that the next stage of will be booted by
+* the ROM), it will implement board_return_to_bootrom() and
+* should not return from it.
+*/
+   board_return_to_bootrom();
+   return false;
+}
+
+SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, 
spl_return_to_bootrom);
diff --git a/include/spl.h b/include/spl.h
index ccb1404..b5c2994 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -278,4 +278,14 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
   struct spl_boot_device *bootdev);
 
 void bl31_entry(void);
+
+/**
+ * board_return_to_bootrom - allow for boards to continue with the boot ROM
+ *
+ * If a board (e.g. the Rockchip RK3368 boards) provide some
+ * supporting functionality for SPL in their boot ROM and the SPL
+ * stage wants to return to the ROM code to continue booting, boards
+ * can implement 'board_return_to_bootrom'.
+ */
+void board_return_to_bootrom(void);
 #endif
-- 
2.1.4

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[U-Boot] [PATCH v4 06/66] spl: use TPL_SYS_MALLOC_F_LEN for TPL

[Philipp Tomsich]

The (upstream) changes to break up SYS_MALLOC_F_LEN for the full
U-Boot and the SPL stage, break TPL (if simple malloc is enabled in
TPL).

This adds support for a TPL-variant of SYS_MALLOC_F_LEN:
- adds TPL_SYS_MALLOC_F_LEN
- rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access
  CONFIG_VAL(SYS_MALLOC_F_LEN)

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

Version-changes: 3
- (new patch) adds changes to SYS_MALLOC_F_LEN for TPL to fix breakage
  from rebasing to u-boot-rockchip/master

Version-changes: 4
- changes (one-line) summary text

---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 Kconfig  | 12 +++-
 common/spl/spl.c |  2 +-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/Kconfig b/Kconfig
index c1451bc..27c64fe 100644
--- a/Kconfig
+++ b/Kconfig
@@ -96,7 +96,17 @@ config SYS_MALLOC_F_LEN
  initial serial device and any others that are needed.
 
 config SPL_SYS_MALLOC_F_LEN
-hex "Size of malloc() pool in spl before relocation"
+hex "Size of malloc() pool in SPL before relocation"
+depends on SYS_MALLOC_F
+default SYS_MALLOC_F_LEN
+help
+  Before relocation, memory is very limited on many platforms. Still,
+  we can provide a small malloc() pool if needed. Driver model in
+  particular needs this to operate, so that it can allocate the
+  initial serial device and any others that are needed.
+
+config TPL_SYS_MALLOC_F_LEN
+hex "Size of malloc() pool in TPL before relocation"
 depends on SYS_MALLOC_F
 default SYS_MALLOC_F_LEN
 help
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b61993f..c84ffd8 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -487,7 +487,7 @@ ulong spl_relocate_stack_gd(void)
gd_t *new_gd;
ulong ptr = CONFIG_SPL_STACK_R_ADDR;
 
-#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_SPL_SYS_MALLOC_F_LEN
+#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
-- 
2.1.4

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[U-Boot] [PATCH v4 02/66] spl: configure 'return to bootrom' separately for SPL and TPL

[Philipp Tomsich]

On the RK3368, we want our TPL to use the 'return to bootrom' boot
method (to have the bootrom load up the SPL stage) and then continue
with different boot methods (MMC, SPI, etc.) from SPL.

This adds the config option needed to control the availabily of the
'return to bootrom' boot-method separately for the TPL stage.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index ee767b7..dd94801 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -698,6 +698,17 @@ config TPL
 
 if TPL
 
+config TPL_BOOTROM_SUPPORT
+bool "Support returning to the BOOTROM (from TPL)"
+   help
+ Some platforms (e.g. the Rockchip RK3368) provide support in their
+ ROM for loading the next boot-stage after performing basic setup
+ from the TPL stage.
+
+ Enable this option, to return to the BOOTROM through the
+ BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+ boot device list, if not implemented for a given board)
+
 config TPL_ENV_SUPPORT
bool "Support an environment"
help
-- 
2.1.4

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[U-Boot] [PATCH v4 05/66] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL

[Philipp Tomsich]

With the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and
SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-rockchip/bootrom.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index 4ca9962..4d38ed6 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -9,8 +9,8 @@
 
 void back_to_bootrom(void)
 {
-#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
-   puts("Returning to boot ROM...");
+#if CONFIG_IS_ENABLED(LIBGENERIC_SUPPORT)
+   printf("Returning to boot ROM...\n");
 #endif
_back_to_bootrom_s();
 }
-- 
2.1.4

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[U-Boot] [PATCH v4 04/66] rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL

[Philipp Tomsich]

The back-to-bootrom option is rather unfortunately named
  CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
  CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM

To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it.  At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.

This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-rockchip/Kconfig| 15 +--
 arch/arm/mach-rockchip/rk3188-board-spl.c |  5 ++---
 arch/arm/mach-rockchip/rk3188-board.c |  2 +-
 arch/arm/mach-rockchip/rk3288-board-spl.c |  4 ++--
 arch/arm/mach-rockchip/rk3288-board.c |  4 ++--
 arch/arm/mach-rockchip/rk3399-board-spl.c |  4 ++--
 configs/evb-rk3288_defconfig  |  2 +-
 configs/fennec-rk3288_defconfig   |  2 +-
 configs/firefly-rk3288_defconfig  |  2 +-
 configs/miqi-rk3288_defconfig |  2 +-
 configs/popmetal-rk3288_defconfig |  2 +-
 configs/rock2_defconfig   |  2 +-
 configs/rock_defconfig|  2 +-
 configs/tinker-rk3288_defconfig   |  2 +-
 doc/README.rockchip   |  2 +-
 include/configs/rk3188_common.h   |  2 +-
 include/configs/rk3288_common.h   |  2 +-
 include/configs/rock.h|  2 +-
 include/configs/rockchip-common.h |  2 +-
 19 files changed, 35 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c924613..37885b8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -101,10 +101,21 @@ config ROCKCHIP_RV1108
  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
  and a DSP.
 
-config ROCKCHIP_SPL_BACK_TO_BROM
+config SPL_ROCKCHIP_BACK_TO_BROM
bool "SPL returns to bootrom"
default y if ROCKCHIP_RK3036
select ROCKCHIP_BROM_HELPER
+   depends on SPL
+   help
+ Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
+  SPL will return to the boot rom, which will then load the U-Boot
+  binary to keep going on.
+
+config TPL_ROCKCHIP_BACK_TO_BROM
+   bool "TPL returns to bootrom"
+   default y if ROCKCHIP_RK3368
+   select ROCKCHIP_BROM_HELPER
+   depends on TPL
help
  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
   SPL will return to the boot rom, which will then load the U-Boot
@@ -122,7 +133,7 @@ config ROCKCHIP_BROM_HELPER
bool
 
 config SPL_MMC_SUPPORT
-   default y if !ROCKCHIP_SPL_BACK_TO_BROM
+   default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c 
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index c3e174d..d3866bf 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -167,8 +167,7 @@ void board_init_f(ulong dummy)
}
 
setup_arm_clock();
-
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && 
!defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
 #endif
 }
@@ -229,7 +228,7 @@ void spl_board_init(void)
}
 
preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom();
 #endif
return;
diff --git a/arch/arm/mach-rockchip/rk3188-board.c 
b/arch/arm/mach-rockchip/rk3188-board.c
index 3e76100..622e046 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -39,7 +39,7 @@ int board_late_init(void)
 
 int board_init(void)
 {
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
struct udevice *pinctrl;
int ret;
 
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 5668fd2..6b7bf85 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -249,7 +249,7 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
return;
}
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && 
!defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
 #endif
 }
@@ -316,7 +316,7 @@ void spl_board_init(void)
}
 
preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom();
 #en

[U-Boot] [PATCH v4 07/66] spl: dm: Kconfig: fix help text for SPL/TPL confusion

[Philipp Tomsich]

TPL_NAND_SUPPORT, TPL_SERIAL_SUPPORT, TPL_SPI_FLASH_SUPPORT and
TPL_SPI_SUPPORT refer to SPL in their help text.  This fixes up
the description to correctly reference TPL.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v4: None
Changes in v3:
- (new patch) added fix-up of SPL/TPL confusion in help text

Changes in v2: None

 common/spl/Kconfig | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index dd94801..8ce9c39 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -717,7 +717,7 @@ config TPL_ENV_SUPPORT
 config TPL_I2C_SUPPORT
bool "Support I2C"
help
- Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for
+ Enable support for the I2C bus in TPL. See SPL_I2C_SUPPORT for
  details.
 
 config TPL_LIBCOMMON_SUPPORT
@@ -747,24 +747,24 @@ config TPL_MMC_SUPPORT
 config TPL_NAND_SUPPORT
bool "Support NAND flash"
help
- Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details.
+ Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.
 
 config TPL_SERIAL_SUPPORT
bool "Support serial"
help
- Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for
+ Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for
  details.
 
 config TPL_SPI_FLASH_SUPPORT
bool "Support SPI flash drivers"
help
- Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT
+ Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT
  for details.
 
 config TPL_SPI_SUPPORT
bool "Support SPI drivers"
help
- Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for
+ Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for
  details.
 
 endif # TPL
-- 
2.1.4

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Re: [U-Boot] [PATCH 2/2] armv8/ls1046a: RGMII PHY requires internal delay on Tx

[York Sun]

On 04/04/2017 04:44 AM, Madalin Bucur wrote:
> Signed-off-by: Madalin Bucur 
> ---
>   drivers/net/fm/ls1046.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
> index bf4..6c91fb9 100644
> --- a/drivers/net/fm/ls1046.c
> +++ b/drivers/net/fm/ls1046.c
> @@ -72,12 +72,12 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
>   if (port == FM1_DTSEC3)
>   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
>   FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
> - return PHY_INTERFACE_MODE_RGMII;
> + return PHY_INTERFACE_MODE_RGMII_TXID;
>   
>   if (port == FM1_DTSEC4)
>   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
>   FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
> - return PHY_INTERFACE_MODE_RGMII;
> + return PHY_INTERFACE_MODE_RGMII_TXID;
>   
>   /* handle SGMII, only MAC 2/5/6/9/10 available */
>   switch (port) {
> 

I don't know what test you have run. This change breaks network on 
LS1043ARDB FM1@DTSEC3.

York
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[U-Boot] U-boot 2017.07 not working on Raspberry Pi

[Paul Barker]

I'm currently testing U-boot 2017.07 on Raspberry Pi, both on a Model
B+ and a Raspberry Pi 3. On both devices I'm seeing two issues with
u-boot:

* U-boot can't boot the Linux kernel, it just hangs at "Starting kernel ...".

* U-boot doesn't recognise any input via a USB keyboard.

These issues were not present in U-boot 2017.05. I see them both when
building U-boot via OpenEmbedded and when building using
arm-linux-gnueabi-gcc on Debian Stretch (GCC 6.3.0).

After bisecting to identify the commits which introduced these issues,
I've found I can get a working U-boot by doing the following:

* Start with U-boot 2017.07

* Revert "dm: arm: rpi: Move to driver model for USB" (25085236)

* Revert "dm: arm: rpi: Use driver model for Ethernet" (d90385be)

* Revert "dm: arm: rpi: Drop CONFIG_OF_EMBED" (25877d4e)

* Drop CONFIG_USB_STORAGE as leaving this enables gives a compile
error when CONFIG_DM_USB is not set.

I've staged these changes here for testing:
https://gitlab.com/toganlabs/u-boot/commits/pbarker/rpi

Reverting these commits is definitely a step backwards though so I'm
hoping for another solution. Has anyone else has seen these issues and
got any ideas? Or has anyone else got U-boot 2017.07 working on the
Raspberry Pi?

Please let me know if you need any more details.

Thanks,

-- 
Paul Barker
Co-Founder & Principal Engineer
Togán Labs Ltd
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[U-Boot] [PATCH v4 09/66] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL

[Philipp Tomsich]

This change introduces TPL variants of the REGMAP and SYSCON config
options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
SPL_SYSCON) in preparation of a finer-grained feature selection for
building feature-rich TPL variants.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/core/Kconfig  | 19 +++
 drivers/core/Makefile |  4 ++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 79a25c6..7afef1f 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -105,6 +105,16 @@ config SPL_REGMAP
  support any bus type (I2C, SPI) but so far this only supports
  direct memory access.
 
+config TPL_REGMAP
+   bool "Support register maps in TPL"
+   depends on TPL_DM
+   help
+ Hardware peripherals tend to have one or more sets of registers
+ which can be accessed to control the hardware. A register map
+ models this with a simple read/write interface. It can in principle
+ support any bus type (I2C, SPI) but so far this only supports
+ direct memory access.
+
 config SYSCON
bool "Support system controllers"
depends on REGMAP
@@ -123,6 +133,15 @@ config SPL_SYSCON
  by this uclass, including accessing registers via regmap and
  assigning a unique number to each.
 
+config TPL_SYSCON
+   bool "Support system controllers in TPL"
+   depends on TPL_REGMAP
+   help
+ Many SoCs have a number of system controllers which are dealt with
+ as a group by a single driver. Some common functionality is provided
+ by this uclass, including accessing registers via regmap and
+ assigning a unique number to each.
+
 config DEVRES
bool "Managed device resources"
depends on DM
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index fd2d4de..3d68c70 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -9,8 +9,8 @@ obj-$(CONFIG_DEVRES) += devres.o
 obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE)  += device-remove.o
 obj-$(CONFIG_$(SPL_)SIMPLE_BUS)+= simple-bus.o
 obj-$(CONFIG_DM)   += dump.o
-obj-$(CONFIG_$(SPL_)REGMAP)+= regmap.o
-obj-$(CONFIG_$(SPL_)SYSCON)+= syscon-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)REGMAP)+= regmap.o
+obj-$(CONFIG_$(SPL_TPL_)SYSCON)+= syscon-uclass.o
 obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
 ifndef CONFIG_DM_DEV_READ_INLINE
 obj-$(CONFIG_OF_CONTROL) += read.o
-- 
2.1.4

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[U-Boot] [PATCH v4 08/66] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON

[Philipp Tomsich]

SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
stricter dependency of SPL_DM was possible.  This commit makes the
prereq more specific.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/core/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index f8b19a4..79a25c6 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -97,7 +97,7 @@ config REGMAP
 
 config SPL_REGMAP
bool "Support register maps in SPL"
-   depends on DM
+   depends on SPL_DM
help
  Hardware peripherals tend to have one or more sets of registers
  which can be accessed to control the hardware. A register map
@@ -116,7 +116,7 @@ config SYSCON
 
 config SPL_SYSCON
bool "Support system controllers in SPL"
-   depends on REGMAP
+   depends on SPL_REGMAP
help
  Many SoCs have a number of system controllers which are dealt with
  as a group by a single driver. Some common functionality is provided
-- 
2.1.4

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Re: [U-Boot] [PATCH v3 2/2] MIPS: Stop building position independent code

[Álvaro Fernández Rojas]

Hi Daniel,

El 31/07/2017 a las 12:52, Daniel Schwierzeck escribió:
> 2017-07-30 18:04 GMT+02:00 Álvaro Fernández Rojas :
>>
>>
>> El 30/07/2017 a las 16:05, Daniel Schwierzeck escribió:
>>>
>>>
>>> Am 30.07.2017 um 14:27 schrieb Álvaro Fernández Rojas:
 I've been a bit busy lately and I couldn't test this until now, but I have 
 to say that this commit breaks u-boot bmips support :(

 BTW, I tried this on several bmips boards (one of them is a Netgear 
 CG3100D, which uses u-boot.bin instead of u-boot.elf)

 Do you have any idea on what could be hapenning?

>>>
>>> maybe you need to specify "--emit-relocs" too when linking u-boot.elf
>>> from u-boot-elf.o. But u-boot-elf.o should already contain the correct
>>> .reloc section with the updated relocation entries so you don't need to
>>> rerun the reloc-tool on u-boot.elf.
>>>
>>
>> I tried that and it doesn't work.
>> However, I've just found out that if I remove the relocs call it boots 
>> again...
>> https://gist.github.com/Noltari/ce3a6a9dda69e74caf7ba33c9c8ade9a
> 
> I wonder how this can work. Even the u-boot.elf now contains
> position-dependent code so that an update of the relocation entries is
> required there too. Without the updated entries, U-Boot can't execute
> after jumping from relocate_code() to board_init_r(). Did you use a
> clean build if U-Boot?
> 
Yeah, I used a clean build of u-boot (upstream with just the patch mentioned 
before):
https://gist.github.com/Noltari/ce3a6a9dda69e74caf7ba33c9c8ade9a#file-u-boot-log

Regards, Álvaro.
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[U-Boot] [PATCH v4 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7

[Philipp Tomsich]

This update has everyone's comments included and even reworks for
Simon's request to retain the _SHIFT macros.  I'll start applying this
together with the DM timer series (to get rid of the hardcoded address
needed for the secure timer init) to the Rockchip tree tomorrow, so it
can be included in this week's pull-request.




Here's the (hopefully final) updated series to enable the RK3368 which
addresses the concerns regarding the prefixing of GRF bit-definitions
with a RK3368-prefix: while I had intended to temporarily pull the
GMAC support to get around the underlying issue, moving the
bit-definitions into the pinctrl-driver's implementation turned out to
rather straightforward (and there's little use in having these
definitions visible outside of the pinctrl driver anyway).

Thanks to everyone, who took the time to comment/discuss the initial
version.

This series (still) has a lot going on, but I didn't want to split it
to allow everyone to understand the motivation between some of the
changes to the SPL/TPL framework.  The short summary of this is
"enablement for DRAM init on the RK3368 with everything else that's
necessary to do it using OF_PLATDATA in TPL".

Enabling the RK3368 created a few more challenges that I'd expected:
 - I needed different stack locations, text addresses and sizes for
   TPL and SPL
 - the TPL stage was to use OF_PLATDATA and SPL was to use full OF_CONTROL
 - with the RK3368 TPL stage, there was a need to extend the back-to-bootrom
   support for Rockchip to AArch64
 - I wanted to start folding some of the Rockchip specific SPL support
   (i.e. back-to-bootrom) back into the general SPL framework to allow
   using it as a general boot method

So I ended up separating quite a bit of features between SPL and TPL
while keeping things transparent to the few other boards using TPL (at
least I hope that things are transparent, as we didn't have any of
those in our lab to test on)...

Tested with: RK3368-uQ7, Debian 9, Linux 4.13-rc1.

Just one final remark: the DMC driver for the RK3368 currently covers
the configuration we use on the RK3368-uQ7 (i.e. 32bit wide, 2 ranks)
and is stress-tested (including 8-way SPEC runs) at all 3 supported
speeds.  I've built a bit of infrastructure (e.g. the way the
memory-schedule is determined) that I hope will be a useful
starting-point in unifying the drivers for the various closely related
DRAM controllers (e.g. for the RK3288) for Rockchip devices in the
future.


Changes in v4:
- removes spurious change to (the armv8) Makefile
- restore the symbolic constant for the shift-values in the IOMUX
  enums
- use symbolic constants for shift amount in IOMUX for SPI pinctrl
- fixes a broken sentence in a comment
- updates pctl and phy reset sequences per feedback from t...@rock-chips.com
- use imply for SPL/TPL preselects where SPL/TPL may not be enabled
  to avoid warning on applying a defconfig (thanks to Andy for reporting)
- (added) sets TPL_LDSCRIPT via Kconfig
- use 'select if' for SPL/TPL presets that need SPL/TPL to avoid errors
  on defconfig, if SPL/TPL is not enabled (thanks to Andy for noticing)
- migrate to Kconfig, so we don't need these in each defconfig

Changes in v3:
- (new patch) added fix-up of SPL/TPL confusion in help text
- change to use function-sections (instead of disabling at the
  Makefile-level for TPL builds) per Tom's suggestion
- commit message now correctly refers to TPL
- adds SGRF syscon support with OF_PLATDATA (to allow access to the
  SGRF address range from TPL)
- correctly states the location of the driver in the commit message
- removes the '#define DEBUG'
- uses the syscon API to access GRF and SGRF to avoid using hard-coded
  addresses
- (after rebase) update defconfig
- (after rebase and defconfig update) lion_rk3368.h: remove
  CONFIG_ENV_IS_NOWHERE
- moves remaining 'u-boot,dm-pre-reloc' to -u-boot.dtsi
- marks sgrf-node as pre-reloc
- defines SPL_LDSCRIPT and TPL_LDSCRIPT via defconfig
- moves SPL_LDSCRIPT and TPL_LDSCRIPT into Kconfig, as requested by
  by Tom; this gets rid of the whitelist-entry for SPL_LDSCRIPT (which
  qualifies as a preexisting condition) and of the newly created one
  for TPL_LDSCRIPT
- moves TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE to Kconfig
- changes the test to CONFIG_TPL_NEEDS_SEPARATE_STACK, as TPL_STACK
  will be a hex-value now (and this always be defined)
- changes Kconfig, so RK3368 will notify the SPL configuration of
  its need to have the TPL text-base, stack-pointer and max-size
  configured
- runs moveconfig.py TPL_STACK TPL_TEXT_BASE TPL_MAX_SIZE

Changes in v2:
- dropped the RK3368_ prefix for the GRF constants
- removed the RK3368-prefix on bit-definitions for GMAC pinctrl
- removed the RK3368 prefix on the SD/MMC pin definitions
- moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX
  definitions) to the rk3368 pinctrl driver implementation
- added SPI clock setup
- moves the bit-definitions (for GRF registers) specific to the GMAC
  into the GM

[U-Boot] [PATCH v2 3/6] rockchip: timer: add device-model timer driver for RK3368 (and similar)

[Philipp Tomsich]

This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.

This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v2:
- remove the DEBUG (missed this initially, as there were no debug()
  calls in the file anyway)
- rework the reload_value code for improved readability
- pull the uc_priv->clock_rate init into the OF_PLATDATA block

 drivers/timer/Kconfig  |   7 +++
 drivers/timer/Makefile |   1 +
 drivers/timer/rockchip_timer.c | 107 +
 3 files changed, 115 insertions(+)
 create mode 100644 drivers/timer/rockchip_timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index fb5af4d..151a699 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -104,4 +104,11 @@ config AE3XX_TIMER
help
  Select this to enable a timer for AE3XX devices.
 
+config ROCKCHIP_TIMER
+bool "Rockchip timer support"
+   depends on TIMER
+   help
+ Select this to enable support for the timer found on
+ Rockchip devices.
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index d16ea53..fa7ce7c 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_STI_TIMER)   += sti-timer.o
 obj-$(CONFIG_ARC_TIMER)+= arc_timer.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
+obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
new file mode 100644
index 000..0848033
--- /dev/null
+++ b/drivers/timer/rockchip_timer.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct rockchip_timer_plat {
+   struct dtd_rockchip_rk3368_timer dtd;
+};
+#endif
+
+/* Driver private data. Contains timer id. Could be either 0 or 1. */
+struct rockchip_timer_priv {
+   struct rk_timer *timer;
+};
+
+static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
+{
+   struct rockchip_timer_priv *priv = dev_get_priv(dev);
+   uint64_t timebase_h, timebase_l;
+   uint64_t cntr;
+
+   timebase_l = readl(&priv->timer->timer_curr_value0);
+   timebase_h = readl(&priv->timer->timer_curr_value1);
+
+   /* timers are down-counting */
+   cntr = timebase_h << 32 | timebase_l;
+   *count = ~0ull - cntr;
+   return 0;
+}
+
+static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct rockchip_timer_priv *priv = dev_get_priv(dev);
+
+   priv->timer = (struct rk_timer *)devfdt_get_addr(dev);
+#endif
+
+   return 0;
+}
+
+static int rockchip_timer_start(struct udevice *dev)
+{
+   struct rockchip_timer_priv *priv = dev_get_priv(dev);
+   const uint64_t reload_val = ~0uLL;
+   const uint32_t reload_val_l = reload_val & 0x;
+   const uint32_t reload_val_h = reload_val >> 32;
+
+   /* disable timer and reset all control */
+   writel(0, &priv->timer->timer_ctrl_reg);
+   /* write reload value */
+   writel(reload_val_l, &priv->timer->timer_load_count0);
+   writel(reload_val_h, &priv->timer->timer_load_count1);
+   /* enable timer */
+   writel(1, &priv->timer->timer_ctrl_reg);
+
+   return 0;
+}
+
+static int rockchip_timer_probe(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct rockchip_timer_priv *priv = dev_get_priv(dev);
+   struct rockchip_timer_plat *plat = dev_get_platdata(dev);
+
+   priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+   uc_priv->clock_rate = plat->dtd.clock_frequency;
+#endif
+
+   return rockchip_timer_start(dev);
+}
+
+static const struct timer_ops rockchip_timer_ops = {
+   .get_count = rockchip_timer_get_count,
+};
+
+static const struct udevice_id rockchip_timer_ids[] = {
+   { .compatible = "rockchip,rk3368-timer" },
+   {}
+};
+
+U_BOOT_DRIVER(arc_timer) = {
+   .name   = "rockchip_rk3368_timer",
+   .id = UCLASS_TIMER,
+   .of_match = rockchip_timer_ids,
+   .probe = rockchip_timer_probe,
+   .ops= &rockchip_timer_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+   .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv),
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   .platdata_auto_alloc_size = sizeof(struct roc

[U-Boot] [PATCH v2 2/6] dm: timer: normalise SPL and TPL support

[Philipp Tomsich]

To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
  decision for each stage and under control of $(SPL_TPL_)TIMER
  instead of having the two-level configuration with TIMER and
  $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
  not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 arch/arm/cpu/armv8/Makefile |  2 ++
 common/spl/Kconfig  |  8 
 configs/chromebook_link64_defconfig |  2 +-
 configs/qemu-x86_64_defconfig   |  2 +-
 drivers/Makefile|  3 +--
 drivers/timer/Kconfig   | 18 ++
 drivers/timer/Makefile  |  2 +-
 7 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index c447085..1249547 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -8,7 +8,9 @@
 extra-y:= start.o
 
 obj-y  += cpu.o
+ifndef CONFIG_$(SPL_TPL_)TIMER
 obj-y  += generic_timer.o
+endif
 obj-y  += cache_v8.o
 obj-y  += exceptions.o
 obj-y  += cache.o
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 08013b7..1386760 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -602,14 +602,6 @@ config SPL_SPI_SUPPORT
  enable SPI drivers that are needed for other purposes also, such
  as a SPI PMIC.
 
-config SPL_TIMER_SUPPORT
-   bool "Support timer drivers"
-   help
- Enable support for timer drivers in SPL. These can be used to get
- a timer value when in SPL, or perhaps for implementing a delay
- function. This enables the drivers in drivers/timer as part of an
- SPL build.
-
 config SPL_USB_HOST_SUPPORT
bool "Support USB host drivers"
help
diff --git a/configs/chromebook_link64_defconfig 
b/configs/chromebook_link64_defconfig
index 11ceb76..5cf409c 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -28,7 +28,7 @@ CONFIG_SPL_NET_SUPPORT=y
 CONFIG_SPL_PCI_SUPPORT=y
 CONFIG_SPL_PCH_SUPPORT=y
 CONFIG_SPL_RTC_SUPPORT=y
-CONFIG_SPL_TIMER_SUPPORT=y
+CONFIG_SPL_TIMER=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index fc1c70d..9517001 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -29,7 +29,7 @@ CONFIG_SPL_NET_SUPPORT=y
 CONFIG_SPL_PCI_SUPPORT=y
 CONFIG_SPL_PCH_SUPPORT=y
 CONFIG_SPL_RTC_SUPPORT=y
-CONFIG_SPL_TIMER_SUPPORT=y
+CONFIG_SPL_TIMER=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
diff --git a/drivers/Makefile b/drivers/Makefile
index b98550e..9d4680a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/
 obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/
 obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/
 obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
+obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
 
 ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
@@ -38,7 +39,6 @@ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
 obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/
 obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/
-obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/
 obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
@@ -82,7 +82,6 @@ obj-y += scsi/
 obj-y += sound/
 obj-y += spmi/
 obj-y += sysreset/
-obj-y += timer/
 obj-y += tpm/
 obj-y += video/
 obj-y += watchdog/
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 17e7dfe..fb5af4d 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -9,6 +9,24 @@ config TIMER
  will be used. The timer is usually a 32 bits free-running up
  counter. There may be no real tick, and no timer interrupt.
 
+config SPL_TIMER
+   bool "Enable driver model for timer drivers in SPL"
+   depends on TIMER && SPL
+   help
+ Enable support for timer drivers in SPL. These can be used to get
+ a timer value when in SPL, or perhaps for implementing a delay
+ function. This enables the drivers in drivers/timer as part of an
+ SPL build.
+
+config TPL_TIMER
+   bool "Enable driver model for timer drivers in TPL"
+   depends on TIMER && TPL
+   help
+ Enable support for timer drivers in TPL. These can be used to get
+ a timer value when in TPL, or perhaps for implementing a delay
+ function. This enables the drivers in drivers/ti

[U-Boot] [PATCH v2 5/6] rockchip: lion-rk3368: defconfig: enable DM timer for all stages

[Philipp Tomsich]

There is no reasonably robust way (this will be needed so early that
diagnostics will be limited) to specify the base-address of the secure
timer through the DTS for TPL and SPL.  In order to allow us a cleaner
way to structure our SPL and TPL stage, we now move to a DM timer
driver.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 configs/lion-rk3368_defconfig | 4 
 1 file changed, 4 insertions(+)

diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 92058b3..f37bac1 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -85,6 +85,10 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_TPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_LZO=y
-- 
2.1.4

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[U-Boot] [PATCH v4 19/66] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL

[Philipp Tomsich]

As include/malloc.h already checks for SYS_MALLOC_SIMPLE using the
CONFIG_IS_ENABLED macro, we need to move to having separate entries
as we switch to fully separate configuration for SPL and TPL.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 8ce9c39..ad7747e 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -62,6 +62,15 @@ config SPL_SYS_MALLOC_SIMPLE
  this will make the SPL binary smaller at the cost of more heap
  usage as the *_simple malloc functions do not re-use free-ed mem.
 
+config TPL_SYS_MALLOC_SIMPLE
+   bool
+   prompt "Only use malloc_simple functions in the TPL"
+   help
+ Say Y here to only use the *_simple malloc functions from
+ malloc_simple.c, rather then using the versions from dlmalloc.c;
+ this will make the TPL binary smaller at the cost of more heap
+ usage as the *_simple malloc functions do not re-use free-ed mem.
+
 config SPL_STACK_R
bool "Enable SDRAM location for SPL stack"
help
-- 
2.1.4

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[U-Boot] [PATCH v4 11/66] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)

[Philipp Tomsich]

To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/ram/Kconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e75c23f..836be25 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -17,6 +17,15 @@ config SPL_RAM
  SPL, enable this option. It might provide a cleaner interface to
  setting up RAM (e.g. SDRAM / DDR) within SPL.
 
+config TPL_RAM
+   bool "Enable RAM support in SPL"
+   depends on RAM && TPL_DM
+   help
+ The RAM subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use RAM drivers in
+ TPL, enable this option. It might provide a cleaner interface to
+ setting up RAM (e.g. SDRAM / DDR) within TPL.
+
 config STM32_SDRAM
bool "Enable STM32 SDRAM support"
depends on RAM
-- 
2.1.4

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[U-Boot] [PATCH v2 6/6] rockchip: rk3368: remove setup of secure timer from TPL/SPL

[Philipp Tomsich]

When using DM timers w/ the timer0 block within the RK3368, we no
longer depend on the ARMv8 generic timer counting.  This allows us to
drop the secure timer initialisation from the TPL and SPL stages.

The secure timer will later be set up by ATF, which starts the ARMv8
generic timer.  Thus, there will be a dependency from Linux to the ATF
through the ARMv8 generic timer... this seems reasonable, as Linux
will require the ATF (and PSCI) to start up the secondary cores anyway
(in other words: we don't add any new dependencies).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v2: None

 arch/arm/mach-rockchip/rk3368-board-spl.c | 20 
 arch/arm/mach-rockchip/rk3368-board-tpl.c | 19 ---
 2 files changed, 39 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c 
b/arch/arm/mach-rockchip/rk3368-board-spl.c
index 691db41..cabf344 100644
--- a/arch/arm/mach-rockchip/rk3368-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
@@ -19,23 +19,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * The ARMv8 generic timer uses the STIMER1 as its clock-source.
- * Set up the STIMER1 to free-running (i.e. auto-reload) to start
- * the generic timer counting (if we don't do this, udelay will not
- * work and block indefinitively).
- */
-static void secure_timer_init(void)
-{
-   struct rk_timer * const stimer1 =
-   (struct rk_timer * const)0xff830020;
-   const u32 TIMER_EN = BIT(0);
-
-   writel(~0u, &stimer1->timer_load_count0);
-   writel(~0u, &stimer1->timer_load_count1);
-   writel(TIMER_EN, &stimer1->timer_ctrl_reg);
-}
-
 void board_debug_uart_init(void)
 {
 }
@@ -52,9 +35,6 @@ void board_init_f(ulong dummy)
hang();
}
 
-   /* Make sure the ARMv8 generic timer counts */
-   secure_timer_init();
-
/* Set up our preloader console */
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c 
b/arch/arm/mach-rockchip/rk3368-board-tpl.c
index 2a91007..c610cfc 100644
--- a/arch/arm/mach-rockchip/rk3368-board-tpl.c
+++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c
@@ -21,23 +21,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * The ARMv8 generic timer uses the STIMER1 as its clock-source.
- * Set up the STIMER1 to free-running (i.e. auto-reload) to start
- * the generic timer counting (if we don't do this, udelay will not
- * work and block indefinitively).
- */
-static void secure_timer_init(void)
-{
-   struct rk_timer * const stimer1 =
-   (struct rk_timer * const)0xff830020;
-   const u32 TIMER_EN = BIT(0);
-
-   writel(~0u, &stimer1->timer_load_count0);
-   writel(~0u, &stimer1->timer_load_count1);
-   writel(TIMER_EN, &stimer1->timer_ctrl_reg);
-}
-
-/*
  * The SPL (and also the full U-Boot stage on the RK3368) will run in
  * secure mode (i.e. EL3) and an ATF will eventually be booted before
  * starting up the operating system... so we can initialize the SGRF
@@ -153,8 +136,6 @@ void board_init_f(ulong dummy)
hang();
}
 
-   /* Make sure the ARMv8 generic timer counts */
-   secure_timer_init();
/* Reset security, so we can use DMA in the MMC drivers */
sgrf_init();
 
-- 
2.1.4

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[U-Boot] [PATCH v4 64/66] moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE

[Philipp Tomsich]

We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into Kconfig.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v4:
- migrate to Kconfig, so we don't need these in each defconfig

Changes in v3:
- runs moveconfig.py TPL_STACK TPL_TEXT_BASE TPL_MAX_SIZE

Changes in v2: None

 arch/arm/mach-rockchip/Kconfig  | 9 +
 include/configs/rk3368_common.h | 4 
 scripts/config_whitelist.txt| 3 ---
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 45029d1..d9b25d5 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -93,6 +93,15 @@ if ROCKCHIP_RK3368
 config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
 
+config TPL_TEXT_BASE
+default 0xff8c1000
+
+config TPL_MAX_SIZE
+default 28672
+
+config TPL_STACK
+default 0xff8c
+
 endif
 
 config ROCKCHIP_RK3399
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 513adab..a89c69a 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -35,10 +35,6 @@
 #define CONFIG_SPL_BSS_START_ADDR   0x40
 #define CONFIG_SPL_BSS_MAX_SIZE 0x2
 
-#define CONFIG_TPL_TEXT_BASE   0xff8c1000
-#define CONFIG_TPL_MAX_SIZE0x7000
-#define CONFIG_TPL_STACK   0xff8c
-
 #define CONFIG_BOUNCE_BUFFER
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 0e09a52..167ea55 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4980,10 +4980,7 @@ CONFIG_TI_KEYSTONE_SERDES
 CONFIG_TI_KSNAV
 CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
-CONFIG_TPL_MAX_SIZE
 CONFIG_TPL_PAD_TO
-CONFIG_TPL_STACK
-CONFIG_TPL_TEXT_BASE
 CONFIG_TPM_TIS_BASE_ADDRESS
 CONFIG_TPS6586X_POWER
 CONFIG_TQM834X
-- 
2.1.4

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[U-Boot] [PATCH v4 15/66] spl: dm: use CONFIG_IS_ENABLED to test for the DM option

[Philipp Tomsich]

Even though there's now a TPL_DM configuration option, the spl logic
still checks for SPL_DM and thus does not pick up the proper config
option.

This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
pick up the desired configuration option instead of having a
hard-coded check for the SPL variant.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 common/spl/spl.c|  5 +++--
 include/linux/kconfig.h | 13 +
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index c84ffd8..4c7dd9e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -6,6 +6,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
+
 #include 
 #include 
 #include 
@@ -243,7 +244,7 @@ static int spl_common_init(bool setup_malloc)
return ret;
}
}
-   if (IS_ENABLED(CONFIG_SPL_DM)) {
+   if (CONFIG_IS_ENABLED(DM)) {
bootstage_start(BOOTSTATE_ID_ACCUM_DM_SPL, "dm_spl");
/* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
@@ -425,7 +426,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
  gd->malloc_ptr / 1024);
 #endif
 
-   if (IS_ENABLED(CONFIG_SPL_ATF_SUPPORT)) {
+   if (CONFIG_IS_ENABLED(ATF_SUPPORT)) {
debug("loaded - jumping to U-Boot via ATF BL31.\n");
bl31_entry();
}
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index 486fb94..fbfc718 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -51,12 +51,25 @@
 #define _IS_SPL 1
 #endif
 
+#ifdef CONFIG_TPL_BUILD
+#define _IS_TPL 1
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define config_val(cfg) _config_val(_IS_TPL, cfg)
+#define _config_val(x, cfg) __config_val(x, cfg)
+#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
+#define ___config_val(arg1_or_junk, cfg)  \
+   config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
+#define config_val(__ignored, val, ...) val
+#else
 #define config_val(cfg) _config_val(_IS_SPL, cfg)
 #define _config_val(x, cfg) __config_val(x, cfg)
 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
 #define ___config_val(arg1_or_junk, cfg)  \
config_val(arg1_or_junk CONFIG_SPL_##cfg, CONFIG_##cfg)
 #define config_val(__ignored, val, ...) val
+#endif
 
 /*
  * CONFIG_VAL(FOO) evaluates to the value of
-- 
2.1.4

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Re: [U-Boot] [PATCH v3 2/2] MIPS: Stop building position independent code

[Álvaro Fernández Rojas]

Hi Paul,

El 31/07/2017 a las 19:13, Paul Burton escribió:
> On Monday, 31 July 2017 03:52:57 PDT Daniel Schwierzeck wrote:
>> 2017-07-30 18:04 GMT+02:00 Álvaro Fernández Rojas :
>>> El 30/07/2017 a las 16:05, Daniel Schwierzeck escribió:
 Am 30.07.2017 um 14:27 schrieb Álvaro Fernández Rojas:
> I've been a bit busy lately and I couldn't test this until now, but I
> have to say that this commit breaks u-boot bmips support :(
>
> BTW, I tried this on several bmips boards (one of them is a Netgear
> CG3100D, which uses u-boot.bin instead of u-boot.elf)
>
> Do you have any idea on what could be hapenning?

 maybe you need to specify "--emit-relocs" too when linking u-boot.elf
 from u-boot-elf.o. But u-boot-elf.o should already contain the correct
 .reloc section with the updated relocation entries so you don't need to
 rerun the reloc-tool on u-boot.elf.
>>>
>>> I tried that and it doesn't work.
>>> However, I've just found out that if I remove the relocs call it boots
>>> again... https://gist.github.com/Noltari/ce3a6a9dda69e74caf7ba33c9c8ade9a
>>
>> I wonder how this can work. Even the u-boot.elf now contains
>> position-dependent code so that an update of the relocation entries is
>> required there too. Without the updated entries, U-Boot can't execute
>> after jumping from relocate_code() to board_init_r(). Did you use a
>> clean build if U-Boot?
> 
> Indeed - without the .rel section being generated by the mips-relocs tool I'd 
> expect relocate_code() to either apply some bogus relocations or none at all 
> (depending what's in the memory starting from __rel_start) and then, if it 
> gets there at all, for the "relocated" U-Boot to fall over pretty quickly.
Is it possible that CFE is taking care of that?
For what I've seen in old versions of CFE, it looks like it does some parsing 
of the .elf files:
https://github.com/Noltari/cfe_bcm63xx/blob/master/cfe/cfe/main/cfe_ldr_elf.c
"This program parses ELF executables and loads them into memory"

> 
> Fernandez - I don't suppose you're aware of an emulated version of any of the 
> supported bmips systems? That would be an easy way for me to take a look. FYI 
> the systems I use most (Boston & Malta) also use u-boot.bin or derivatives 
> thereof & I'm sure the .rel section is copied across to it, so I doubt it has 
> anything to do with binary formats.
Nope, sorry but I've never emulated any bmips hardware...

> 
> Thanks,
> Paul
> 

Regards,
Álvaro.
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[U-Boot] [PATCH v2 1/6] timer: add OF_PLATDATA support for timer-uclass

[Philipp Tomsich]

The timer-uclass depends on full OF_CONTROL through its interrogation
of /chosen and the code to determine the clock-frequency.

For the OF_PLATDATA case, these code-paths are disabled and it becomes
the timer driver's responsibility to correctly set the clock-frequency
in the uclass priv-data.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v2:
- marks blob as maybe_unused (to accomodate the OF_CONTROL case w/o
  warnings)

 drivers/timer/timer-uclass.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index ec10b28..a84755f 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -42,6 +42,7 @@ unsigned long notrace timer_get_rate(struct udevice *dev)
 
 static int timer_pre_probe(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct clk timer_clk;
int err;
@@ -56,6 +57,7 @@ static int timer_pre_probe(struct udevice *dev)
} else
uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
dev_of_offset(dev), "clock-frequency", 0);
+#endif
 
return 0;
 }
@@ -81,16 +83,18 @@ u64 timer_conv_64(u32 count)
 
 int notrace dm_timer_init(void)
 {
-   const void *blob = gd->fdt_blob;
+   __maybe_unused const void *blob = gd->fdt_blob;
struct udevice *dev = NULL;
-   int node;
+   int node = -ENOENT;
int ret;
 
if (gd->timer)
return 0;
 
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
/* Check for a chosen timer to be used for tick */
node = fdtdec_get_chosen_node(blob, "tick-timer");
+#endif
if (node < 0) {
/* No chosen timer, trying first available timer */
ret = uclass_first_device_err(UCLASS_TIMER, &dev);
-- 
2.1.4

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[U-Boot] [PATCH v2 4/6] dts: rk3368: make timer0 accessible for SPL and TPL

[Philipp Tomsich]

To use it with the DM timer driver in SPL and TPL, timer0 needs to be
marked as pre-reloc.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v2:
- add 'clock-frequency' prop to timer in the -u-boot.dtsi

 arch/arm/dts/rk3368-lion-u-boot.dtsi | 5 +
 arch/arm/dts/rk3368.dtsi | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi 
b/arch/arm/dts/rk3368-lion-u-boot.dtsi
index 2053fb1..6052e8a 100644
--- a/arch/arm/dts/rk3368-lion-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
@@ -85,4 +85,9 @@
};
 };
 
+&timer0 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+};
+
 
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 22fb7e7..b4f4f61 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -687,7 +687,7 @@
status = "disabled";
};
 
-   timer@ff81 {
+   timer0: timer@ff81 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff81 0x0 0x20>;
interrupts = ;
-- 
2.1.4

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[U-Boot] [PATCH v4 29/66] rockchip: rk3368: spl: add memory layout for TPL and SPL

[Philipp Tomsich]

For the RK3368, we use a multi-stage boot-process consisting of the
following:
  1.  TPL: initalises DRAM, returns to boot-ROM (which then loads
   the next stage and transfers control to it)
  2.  SPL: a full-features SPL stage including OF_CONTROL and FIT
   image loading, which fetches the ATF, DTB and full U-Boot
   and then transfers control to the ATF (using the BL31
   parameter block to indicate the location of BL33/U-Boot)
  3.  ATF: sets up the secure world and exits to BL33 (i.e. a full
   U-Boot) in the normal world
  4.  full U-Boot

TPL/SPL and the full U-Boot are built from this tree and need to
run from distinct text addresses and with distinct initial stack
pointer addresses.

This commit sets up the configuration to run:
  -  TPL from the SRAM at 0xff8c (note that the first 0x1000
 are reserved for use by the boot-ROM and contain the SP
 when the TPL is entered)
  -  SPL from DRAM at 0x0
  -  U-Boot from DRAM at 0x20

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/rk3368_common.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index ddb7df0..e35f4c0 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -29,6 +29,17 @@
 #define CONFIG_SYS_INIT_SP_ADDR0x0030
 #define CONFIG_SYS_LOAD_ADDR   0x0028
 
+#define CONFIG_SPL_TEXT_BASE0x
+#define CONFIG_SPL_MAX_SIZE 0x4
+#define CONFIG_SPL_BSS_START_ADDR   0x40
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2
+
+#define CONFIG_TPL_LDSCRIPT \
+ "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
+#define CONFIG_TPL_TEXT_BASE   0xff8c1000
+#define CONFIG_TPL_MAX_SIZE0x7000
+#define CONFIG_TPL_STACK   0xff8c
+
 #define CONFIG_BOUNCE_BUFFER
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.1.4

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[U-Boot] [PATCH v4 28/66] rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz

[Philipp Tomsich]

The BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0.
This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.

If the counter-frequency is not correctly set up, the calculation of
delays using the ARMv8 generic timer can not work correctly.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/rk3368_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index b0c858c..ddb7df0 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -21,6 +21,8 @@
 #define CONFIG_SYS_CBSIZE  1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define COUNTER_FREQUENCY   2400
+
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_TEXT_BASE   0x0020
-- 
2.1.4

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[U-Boot] [PATCH v4 49/66] rockchip: Makefile: streamline SPL/TPL configuration

[Philipp Tomsich]

Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths.  This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-rockchip/Makefile | 46 +
 1 file changed, 28 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 8a3cb9f..633c91e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -4,37 +4,47 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+# We don't want the bootrom-helper present in a full U-Boot build, as
+# this may have entered from ATF with the stack-pointer pointing to
+# inaccessible/protected memory (and the bootrom-helper assumes that
+# the stack-pointer is valid before switching to the U-Boot stack).
+obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+
+obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
 
-ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
 endif
+
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+
 ifndef CONFIG_ARM64
 obj-y += rk_timer.o
 endif
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
-
-ifndef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
-endif
 
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
+
+# Clear out SPL objects, in case this is a TPL build
+obj-spl-$(CONFIG_TPL_BUILD) =
+
+# Now add SPL/TPL objects back into the main build
+obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y)
+obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
-- 
2.1.4

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[U-Boot] [PATCH v4 61/66] spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig

[Philipp Tomsich]

Let's clean up behind ourselves and move the (newly defined)
TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig.  Given that
0x0 might be considered to be valid values for TPL_TEXT_BASE and
TPL_STACK, we need to introduce helper config options
("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used
(and not inherited from their SPL variants) for any given
target-platform.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v4: None
Changes in v3:
- moves TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE to Kconfig

Changes in v2: None

 common/spl/Kconfig | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b01d4f1..08013b7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -725,6 +725,45 @@ config TPL_LDSCRIPT
  U-Boot stage.  Set this to the path of the linker-script to
  be used for TPL.
 
+ May be left empty to trigger the Makefile infrastructure to
+ fall back to the linker-script used for the SPL stage.
+
+config TPL_NEEDS_SEPARATE_TEXT_BASE
+bool "TPL needs a separate text-base"
+   default n
+   depends on TPL
+   help
+ Enable, if the TPL stage should not inherit its text-base
+ from the SPL stage.  When enabled, a base address for the
+ .text sections of the TPL stage has to be set below.
+
+config TPL_NEEDS_SEPARATE_STACK
+bool "TPL needs a separate initial stack-pointer"
+   default n
+   depends on TPL
+   help
+ Enable, if the TPL stage should not inherit its initial
+ stack-pointer from the settings for the SPL stage.
+
+config TPL_TEXT_BASE
+hex "Base address for the .text section of the TPL stage"
+   depends on TPL_NEEDS_SEPARATE_TEXT_BASE
+   help
+ The base address for the .text section of the TPL stage.
+
+config TPL_MAX_SIZE
+int "Maximum size (in bytes) for the TPL stage"
+   depends on TPL
+   help
+ The maximum size (in bytes) of the TPL stage.
+
+config TPL_STACK
+hex "Address of the initial stack-pointer for the TPL stage"
+   depends on TPL_NEEDS_SEPARATE_STACK
+   help
+ The address of the initial stack-pointer for the TPL stage.
+ Usually this will be the (aligned) top-of-stack.
+
 config TPL_BOOTROM_SUPPORT
 bool "Support returning to the BOOTROM (from TPL)"
help
-- 
2.1.4

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[U-Boot] [PATCH v4 46/66] rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

[Philipp Tomsich]

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c 
b/drivers/clk/rockchip/clk_rk3368.c
index 2b6c8da..d3f6c29 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -353,7 +353,7 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
 
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
-   struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+   __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
ulong ret = 0;
 
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
-- 
2.1.4

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[U-Boot] [PATCH v4 31/66] rockchip: rk3368: syscon: SGRF support for OF_PLATDATA

[Philipp Tomsich]

In TPL we will need to configure security in the SGRF of the RK3368.
This change adds support for the SGRF as a syscon device, so we can
retrieve its address range through the syscon API in TPL (and can
avoid having to hard-code the address).

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v4: None
Changes in v3:
- adds SGRF syscon support with OF_PLATDATA (to allow access to the
  SGRF address range from TPL)

Changes in v2: None

 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c 
b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 90a993e..99d51f0 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -18,6 +18,8 @@ static const struct udevice_id rk3368_syscon_ids[] = {
  .data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3368-msch",
  .data = ROCKCHIP_SYSCON_MSCH },
+   { .compatible = "rockchip,rk3368-sgrf",
+ .data = ROCKCHIP_SYSCON_SGRF },
{ }
 };
 
@@ -56,4 +58,11 @@ U_BOOT_DRIVER(rockchip_rk3368_msch) = {
.of_match = rk3368_syscon_ids + 2,
.bind = rk3368_syscon_bind_of_platdata,
 };
+
+U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
+   .name = "rockchip_rk3368_sgrf",
+   .id = UCLASS_SYSCON,
+   .of_match = rk3368_syscon_ids + 3,
+   .bind = rk3368_syscon_bind_of_platdata,
+};
 #endif
-- 
2.1.4

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[U-Boot] [PATCH v4 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its

[Philipp Tomsich]

The ITS file generated warnings due to @ designations in the naming
which cause DTC to complain as follows:
  Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no 
reg property
  Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg 
property
  Warning (unit_address_vs_reg): Node /images/pmu@1 has a unit name, but no reg 
property
  Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg 
property
  Warning (unit_address_vs_reg): Node /configurations/conf@1 has a unit name, 
but no reg property

This removes the @ part from the names, as we only have a single
image for each payload aspect (and only a single configuration) anyway.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its 
b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
index f93c251..0519fad 100644
--- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
@@ -13,7 +13,7 @@
#address-cells = <1>;
 
images {
-   uboot@1 {
+   uboot {
description = "U-Boot (64-bit)";
data = /incbin/("../../../u-boot-nodtb.bin");
type = "standalone";
@@ -21,7 +21,7 @@
compression = "none";
load = <0x0020>;
};
-   atf@1 {
+   atf {
description = "ARM Trusted Firmware";
data = /incbin/("../../../bl31.bin");
type = "firmware";
@@ -30,14 +30,14 @@
load = <0x1000>;
entry = <0x1000>;
};
-   pmu@1 {
+   pmu {
description = "Cortex-M0 firmware";
data = /incbin/("../../../rk3399m0.bin");
type = "pmu-firmware";
compression = "none";
load = <0xff8c>;
 };
-   fdt@1 {
+   fdt {
description = "RK3399-Q7 (Puma) flat device-tree";
data = /incbin/("../../../u-boot.dtb");
type = "flat_dt";
@@ -46,12 +46,12 @@
};
 
configurations {
-   default = "conf@1";
-   conf@1 {
+   default = "conf";
+   conf {
description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
-   firmware = "uboot@1";
-   loadables = "atf@1";
-   fdt = "fdt@1";
+   firmware = "uboot";
+   loadables = "atf";
+   fdt = "fdt";
};
};
 };
-- 
2.1.4

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[U-Boot] [PATCH v4 59/66] spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig

[Philipp Tomsich]

Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and
have started to use the TPL-variant for the RK3368, it's time to clean
up behind ourselves: move both variants into Kconfig and remove them
from the whitelist.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v4: None
Changes in v3:
- moves SPL_LDSCRIPT and TPL_LDSCRIPT into Kconfig, as requested by
  by Tom; this gets rid of the whitelist-entry for SPL_LDSCRIPT (which
  qualifies as a preexisting condition) and of the newly created one
  for TPL_LDSCRIPT

Changes in v2: None

 common/spl/Kconfig   | 18 ++
 scripts/Makefile.spl |  9 -
 scripts/config_whitelist.txt |  2 --
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 64f9e1f..b01d4f1 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -18,6 +18,15 @@ config SPL
 
 if SPL
 
+config SPL_LDSCRIPT
+string "Linker script for the SPL stage"
+   depends on SPL
+   help
+ The SPL stage will usually require a different linker-script
+ (as it runs from a different memory region) than the regular
+ U-Boot stage.  Set this to the path of the linker-script to
+ be used for SPL.
+
 config SPL_BOARD_INIT
bool "Call board-specific initialization in SPL"
help
@@ -707,6 +716,15 @@ config TPL
 
 if TPL
 
+config TPL_LDSCRIPT
+string "Linker script for the TPL stage"
+   depends on TPL
+   help
+ The TPL stage will usually require a different linker-script
+ (as it runs from a different memory region) than the regular
+ U-Boot stage.  Set this to the path of the linker-script to
+ be used for TPL.
+
 config TPL_BOOTROM_SUPPORT
 bool "Support returning to the BOOTROM (from TPL)"
help
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 4a9a58f..167b2d9 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -103,9 +103,16 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
 endif
 
 # Linker Script
-ifdef CONFIG_$(SPL_TPL_)LDSCRIPT
+# First test whether there's a linker-script for the specific stage defined...
+ifneq ($(CONFIG_$(SPL_TPL_)LDSCRIPT),)
 # need to strip off double quotes
 LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%))
+else
+# ...then fall back to the generic SPL linker-script
+ifneq ($(CONFIG_SPL_LDSCRIPT),)
+# need to strip off double quotes
+LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
+endif
 endif
 
 ifeq ($(wildcard $(LDSCRIPT)),)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index ee3fcd0..0e09a52 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2252,7 +2252,6 @@ CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 CONFIG_SPL_INIT_MINIMAL
 CONFIG_SPL_JR0_LIODN_NS
 CONFIG_SPL_JR0_LIODN_S
-CONFIG_SPL_LDSCRIPT
 CONFIG_SPL_LOAD_FIT_ADDRESS
 CONFIG_SPL_MAX_FOOTPRINT
 CONFIG_SPL_MAX_PEB_SIZE
@@ -4981,7 +4980,6 @@ CONFIG_TI_KEYSTONE_SERDES
 CONFIG_TI_KSNAV
 CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
-CONFIG_TPL_LDSCRIPT
 CONFIG_TPL_MAX_SIZE
 CONFIG_TPL_PAD_TO
 CONFIG_TPL_STACK
-- 
2.1.4

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[U-Boot] [PATCH v4 14/66] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL

[Philipp Tomsich]

For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL
in SPL: this requires the introduction of a new family of
configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA
from TPL.

Consequently, Makefile.spl needs to be adjusted to test for these
configuration items through the $(SPL_TPL_) macro instead of
hard-coding the SPL variant.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 Makefile |  2 +-
 dts/Kconfig  | 29 +
 scripts/Makefile.spl |  4 ++--
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 3d2b66a..8d19a03 100644
--- a/Makefile
+++ b/Makefile
@@ -1398,7 +1398,7 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 spl/u-boot-spl.bin: spl/u-boot-spl
@:
 spl/u-boot-spl: tools prepare \
-   $(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
+   $(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),dts/dt.dtb)
$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
diff --git a/dts/Kconfig b/dts/Kconfig
index 1bc9656..b4b7ddc 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -32,6 +32,14 @@ config SPL_OF_CONTROL
  which is not enough to support device tree. Enable this option to
  allow such boards to be supported by U-Boot SPL.
 
+config TPL_OF_CONTROL
+   bool "Enable run-time configuration via Device Tree in TPL"
+   depends on TPL && OF_CONTROL
+   help
+ Some boards use device tree in U-Boot but only have 4KB of SRAM
+ which is not enough to support device tree. Enable this option to
+ allow such boards to be supported by U-Boot TPL.
+
 config OF_LIVE
bool "Enable use of a live tree"
depends on OF_CONTROL
@@ -136,4 +144,25 @@ config SPL_OF_PLATDATA
  declarations for each node. See README.platdata for more
  information.
 
+config TPL_OF_PLATDATA
+   bool "Generate platform data for use in TPL"
+   depends on TPL_OF_CONTROL
+   help
+ For very constrained SPL environments the overhead of decoding
+ device tree nodes and converting their contents into platform data
+ is too large. This overhead includes libfdt code as well as the
+ device tree contents itself. The latter is fairly compact, but the
+ former can add 3KB or more to a Thumb 2 Image.
+
+ This option enables generation of platform data from the device
+ tree as C code. This code creates devices using U_BOOT_DEVICE()
+ declarations. The benefit is that it allows driver code to access
+ the platform data directly in C structures, avoidin the libfdt
+ overhead.
+
+ This option works by generating C structure declarations for each
+ compatible string, then adding platform data and U_BOOT_DEVICE
+ declarations for each node. See README.platdata for more
+ information.
+
 endmenu
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ac3c2c7..3e35cd6 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -98,7 +98,7 @@ endif
 
 u-boot-spl-init := $(head-y)
 u-boot-spl-main := $(libs-y)
-ifdef CONFIG_SPL_OF_PLATDATA
+ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA
 u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
 endif
 
@@ -202,7 +202,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 quiet_cmd_copy = COPY$@
   cmd_copy = cp $< $@
 
-ifeq 
($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy)
+ifeq 
($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
 $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
$(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \
$(obj)/$(SPL_BIN).dtb FORCE
-- 
2.1.4

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[U-Boot] [PATCH v4 32/66] rockchip: rk3368: grf: use shifted-constants

[Philipp Tomsich]

The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.

Signed-off-by: Philipp Tomsich 

---

Changes in v4:
- restore the symbolic constant for the shift-values in the IOMUX
  enums

Changes in v3: None
Changes in v2:
- dropped the RK3368_ prefix for the GRF constants

 arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 413 ++--
 drivers/pinctrl/rockchip/pinctrl_rk3368.c   |   9 +-
 2 files changed, 242 insertions(+), 180 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index a438f5d..3b3a3ef 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -1,4 +1,6 @@
-/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -100,315 +102,378 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
 /*GRF_GPIO0C_IOMUX*/
 enum {
-   GPIO0C7_SHIFT   = 14,
-   GPIO0C7_MASK= 3 << GPIO0C7_SHIFT,
-   GPIO0C7_GPIO= 0,
-   GPIO0C7_LCDC_D19,
-   GPIO0C7_TRACE_D9,
-   GPIO0C7_UART1_RTSN,
+   GPIO0C7_SHIFT   = 14,
+   GPIO0C7_MASK= GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
+   GPIO0C7_GPIO= 0,
+   GPIO0C7_LCDC_D19= (1 << GPIO0C7_SHIFT),
+   GPIO0C7_TRACE_D9= (2 << GPIO0C7_SHIFT),
+   GPIO0C7_UART1_RTSN  = (3 << GPIO0C7_SHIFT),
 
GPIO0C6_SHIFT   = 12,
-   GPIO0C6_MASK= 3 << GPIO0C6_SHIFT,
+   GPIO0C6_MASK= GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
GPIO0C6_GPIO= 0,
-   GPIO0C6_LCDC_D18,
-   GPIO0C6_TRACE_D8,
-   GPIO0C6_UART1_CTSN,
+   GPIO0C6_LCDC_D18= (1 << GPIO0C6_SHIFT),
+   GPIO0C6_TRACE_D8= (2 << GPIO0C6_SHIFT),
+   GPIO0C6_UART1_CTSN  = (3 << GPIO0C6_SHIFT),
 
GPIO0C5_SHIFT   = 10,
-   GPIO0C5_MASK= 3 << GPIO0C5_SHIFT,
+   GPIO0C5_MASK= GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
GPIO0C5_GPIO= 0,
-   GPIO0C5_LCDC_D17,
-   GPIO0C5_TRACE_D7,
-   GPIO0C5_UART1_SOUT,
+   GPIO0C5_LCDC_D17= (1 << GPIO0C5_SHIFT),
+   GPIO0C5_TRACE_D7= (2 << GPIO0C5_SHIFT),
+   GPIO0C5_UART1_SOUT  = (3 << GPIO0C5_SHIFT),
 
GPIO0C4_SHIFT   = 8,
-   GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
+   GPIO0C4_MASK= GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
GPIO0C4_GPIO= 0,
-   GPIO0C4_LCDC_D16,
-   GPIO0C4_TRACE_D6,
-   GPIO0C4_UART1_SIN,
+   GPIO0C4_LCDC_D16= (1 << GPIO0C4_SHIFT),
+   GPIO0C4_TRACE_D6= (2 << GPIO0C4_SHIFT),
+   GPIO0C4_UART1_SIN   = (3 << GPIO0C4_SHIFT),
 
GPIO0C3_SHIFT   = 6,
-   GPIO0C3_MASK= 3 << GPIO0C3_SHIFT,
+   GPIO0C3_MASK= GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
GPIO0C3_GPIO= 0,
-   GPIO0C3_LCDC_D15,
-   GPIO0C3_TRACE_D5,
-   GPIO0C3_MCU_JTAG_TDO,
+   GPIO0C3_LCDC_D15= (1 << GPIO0C3_SHIFT),
+   GPIO0C3_TRACE_D5= (2 << GPIO0C3_SHIFT),
+   GPIO0C3_MCU_JTAG_TDO= (3 << GPIO0C3_SHIFT),
 
GPIO0C2_SHIFT   = 4,
-   GPIO0C2_MASK= 3 << GPIO0C2_SHIFT,
+   GPIO0C2_MASK= GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
GPIO0C2_GPIO= 0,
-   GPIO0C2_LCDC_D14,
-   GPIO0C2_TRACE_D4,
-   GPIO0C2_MCU_JTAG_TDI,
+   GPIO0C2_LCDC_D14= (1 << GPIO0C2_SHIFT),
+   GPIO0C2_TRACE_D4= (2 << GPIO0C2_SHIFT),
+   GPIO0C2_MCU_JTAG_TDI= (3 << GPIO0C2_SHIFT),
 
GPIO0C1_SHIFT   = 2,
-   GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
+   GPIO0C1_MASK= GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
GPIO0C1_GPIO= 0,
-   GPIO0C1_LCDC_D13,
-   GPIO0C1_TRACE_D3,
-   GPIO0C1_MCU_JTAG_TRTSN,
+   GPIO0C1_LCDC_D13= (1 << GPIO0C1_SHIFT),
+   GPIO0C1_TRACE_D3= (2 << GPIO0C1_SHIFT),
+   GPIO0C1_MCU_JTAG_TRTSN  = (3 << GPIO0C1_SHIFT),
 
GPIO0C0_SHIFT   = 0,
-   GPIO0C0_MASK= 3 << GPIO0C0_SHIFT,
+   GPIO0C0_MASK= GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
GPIO0C0_GPIO= 0,
-   GPIO0C0_LCDC_D12,
-   GPIO0C0_TRACE_D2,
-   GPIO0C0_MCU_JTAG_TDO,
+   GPIO0C0_LCDC_D12= (1 << GPIO0C0_SHIFT),
+   GPIO0C0_TRACE_D2= (2 << GPIO0C0_SHIFT),
+   GPIO0C0_MCU_JTAG_TDO= (3 << GPIO0C0_SHIFT),
 };
 
 /*GRF_GPIO0D_IOMU

[U-Boot] [PATCH v4 26/66] rockchip: rk3368: mkimage: add support for the RK3368

[Philipp Tomsich]

This commit adds support for RK3368 SoC in mkimage.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 25b0340..04e8272 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -77,6 +77,7 @@ static struct spl_info spl_infos[] = {
{ "rk322x", "RK32", 0x8000 - 0x1000, false, false },
{ "rk3288", "RK32", 0x8000, false, false },
{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
+   { "rk3368", "RK33", 0x8000 - 0x1000, false, true },
{ "rk3399", "RK33", 0x3 - 0x2000, false, true },
{ "rv1108", "RK11", 0x1800, false, false},
 };
-- 
2.1.4

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[U-Boot] [PATCH v4 20/66] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata

[Philipp Tomsich]

This splits the compilation of code modules for TPL and SPL for
OF_CONTROL (and related) features between TPL and SPL.  The typical
use-case of this is a TPL stage that uses OF_PLATDATA at TPL and
provides full OF_CONTROL at SPL (e.g. on the RK3368).

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 lib/Makefile | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/Makefile b/lib/Makefile
index eacc7d6..2eef1eb 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -49,11 +49,11 @@ obj-$(CONFIG_RSA) += rsa/
 obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SHA256) += sha256.o
 
-obj-$(CONFIG_SPL_SAVEENV) += qsort.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
-ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy)
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
+obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
+ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-- 
2.1.4

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[U-Boot] [PATCH v4 63/66] rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL

[Philipp Tomsich]

The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage.  Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 

---

Changes in v4:
- use 'select if' for SPL/TPL presets that need SPL/TPL to avoid errors
  on defconfig, if SPL/TPL is not enabled (thanks to Andy for noticing)

Changes in v3:
- changes Kconfig, so RK3368 will notify the SPL configuration of
  its need to have the TPL text-base, stack-pointer and max-size
  configured

Changes in v2: None

 arch/arm/mach-rockchip/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4a6f629..45029d1 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -69,6 +69,8 @@ config ROCKCHIP_RK3368
select ARM64
select SUPPORT_SPL
select SUPPORT_TPL
+   select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+   select TPL_NEEDS_SEPARATE_STACK if TPL
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
-- 
2.1.4

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[U-Boot] [PATCH v4 41/66] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

[Philipp Tomsich]

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3368.c 
b/drivers/clk/rockchip/clk_rk3368.c
index d05be72..33d2946 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -250,6 +250,37 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
return rate;
 }
 
+static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
+{
+   const struct pll_div *dpll_cfg = NULL;
+   const ulong MHz = 100;
+
+   /* Fout = ((Fin /NR) * NF )/ NO */
+   static const struct pll_div dpll_1200 =
+   PLL_DIVISORS(1200 * MHz, 1, 1);
+   static const struct pll_div dpll_1332 =
+   PLL_DIVISORS(1332 * MHz, 2, 1);
+   static const struct pll_div dpll_1600 =
+   PLL_DIVISORS(1600 * MHz, 3, 2);
+
+   switch (set_rate) {
+   case 1200*MHz:
+   dpll_cfg = &dpll_1200;
+   break;
+   case 1332*MHz:
+   dpll_cfg = &dpll_1332;
+   break;
+   case 1600*MHz:
+   dpll_cfg = &dpll_1600;
+   break;
+   default:
+   error("Unsupported SDRAM frequency!,%ld\n", set_rate);
+   }
+   rkclk_set_pll(cru, DPLL, dpll_cfg);
+
+   return set_rate;
+}
+
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -257,6 +288,10 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong 
rate)
 
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
switch (clk->id) {
+   case CLK_DDR:
+   ret = rk3368_ddr_set_clk(priv->cru, rate);
+   break;
+
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
-- 
2.1.4

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