Hi Anatolji, On 01/08/2017 15:14, Anatolij Gustschin wrote: > For ALT0 function mux mode should be 0, not 16. > > Signed-off-by: Anatolij Gustschin <ag...@denx.de> > --- > arch/arm/include/asm/arch-mx6/mx6q_pins.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h > b/arch/arm/include/asm/arch-mx6/mx6q_pins.h > index a8456a2..3dbdb0c 100644 > --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h > +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h > @@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, > 0x0000, 0, 0) > MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) > MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) > MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) > -MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0) > +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) > MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) > MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) > MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) > @@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, > 0x0878, 1, 0) > MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) > MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) > MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) > -MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0) > +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0, 0) > MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) > MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) > MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) > @@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, > 3, 0x0000, 0, 0) > MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) > MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) > MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) > -MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0) > +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0, 0) > MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) > MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) > MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) > @@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, > 1, 0x0828, 1, 0) > MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) > MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) > MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) > -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0) > +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0, 0) > MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) > MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) > MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) >
The MUX mode is not changed, but 16 means that the SION bit is set. This forces the MUX to ALT0. I have no idea why the SION bit is set for SD, but we have already had some cases with ENET (and GIPOs require to set SION as well). In any case, if SION must be set, it should be not done with the value (16), but with the macro IOMUX_CONFIG_SION. I agree there is no reason why SION must be set. Acked-by : Stefano Babic <sba...@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
