[U-Boot] [PATCH V2 2/6] Tegra: Rework KConfig options to allow 64-bit builds (T210)

2015-07-20 Thread Tom Warren
Moved Tegra config options to mach-tegra/Kconfig so that both
32-bit and 64-bit builds can co-exist for Tegra SoCs.

T210 will be 64-bit only (no SPL) and will requires a 32-bit
AVP/BPMP loader.

Signed-off-by: Tom Warren 
---
 arch/arm/Kconfig| 11 ---
 arch/arm/mach-tegra/Kconfig | 44 
 2 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 506463c..20ab398 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -681,17 +681,6 @@ config TARGET_XILINX_ZYNQMP
 
 config TEGRA
bool "NVIDIA Tegra"
-   select SUPPORT_SPL
-   select SPL
-   select OF_CONTROL
-   select SPL_DISABLE_OF_CONTROL
-   select CPU_V7
-   select DM
-   select DM_SPI_FLASH
-   select DM_SERIAL
-   select DM_I2C
-   select DM_SPI
-   select DM_GPIO
 
 config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 54bd648..7494f8d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -6,15 +6,59 @@ choice
 
 config TEGRA20
bool "Tegra20 family"
+   select SUPPORT_SPL
+   select SPL
+   select OF_CONTROL
+   select SPL_DISABLE_OF_CONTROL
+   select CPU_V7
+   select DM
+   select DM_SPI_FLASH
+   select DM_SERIAL
+   select DM_I2C
+   select DM_SPI
+   select DM_GPIO
 
 config TEGRA30
bool "Tegra30 family"
+   select SUPPORT_SPL
+   select SPL
+   select OF_CONTROL
+   select SPL_DISABLE_OF_CONTROL
+   select CPU_V7
+   select DM
+   select DM_SPI_FLASH
+   select DM_SERIAL
+   select DM_I2C
+   select DM_SPI
+   select DM_GPIO
 
 config TEGRA114
bool "Tegra114 family"
+   select SUPPORT_SPL
+   select SPL
+   select OF_CONTROL
+   select SPL_DISABLE_OF_CONTROL
+   select CPU_V7
+   select DM
+   select DM_SPI_FLASH
+   select DM_SERIAL
+   select DM_I2C
+   select DM_SPI
+   select DM_GPIO
 
 config TEGRA124
bool "Tegra124 family"
+   select SUPPORT_SPL
+   select SPL
+   select OF_CONTROL
+   select SPL_DISABLE_OF_CONTROL
+   select CPU_V7
+   select DM
+   select DM_SPI_FLASH
+   select DM_SERIAL
+   select DM_I2C
+   select DM_SPI
+   select DM_GPIO
 
 endchoice
 
-- 
1.8.2.1.610.g562af5b

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[U-Boot] [PATCH V2 4/6] ARM: Tegra210: Add support to common Tegra source/config files

2015-07-20 Thread Tom Warren
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too.

Signed-off-by: Tom Warren 
---
 arch/arm/include/asm/arch-tegra/ap.h |  6 +--
 arch/arm/include/asm/arch-tegra/clk_rst.h| 28 +++---
 arch/arm/include/asm/arch-tegra/gp_padctrl.h |  3 +-
 arch/arm/include/asm/arch-tegra/pmc.h|  7 ++--
 arch/arm/include/asm/arch-tegra/tegra.h  |  4 +-
 arch/arm/mach-tegra/Kconfig  | 12 ++
 arch/arm/mach-tegra/Makefile |  5 ++-
 arch/arm/mach-tegra/ap.c |  9 -
 arch/arm/mach-tegra/clock.c  |  3 +-
 arch/arm/mach-tegra/cpu.c| 55 
 arch/arm/mach-tegra/cpu.h| 10 +++--
 include/fdtdec.h |  3 ++
 lib/fdtdec.c |  2 +
 13 files changed, 111 insertions(+), 36 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra/ap.h 
b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e..76773b7 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -24,8 +24,6 @@
 #define PG_UP_TAG_0_PID_CPU0x  /* CPU aka "a9" aka "mpcore" */
 #define PG_UP_TAG_00x0
 
-#define CORESIGHT_UNLOCK   0xC5ACCE55;
-
 /* AP base physical address of internal SRAM */
 #define NV_PA_BASE_SRAM0x4000
 
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
 /* Do any chip-specific cache config */
 void config_cache(void);
 
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 /* Do chip-specific vpr config */
 void config_vpr(void);
 #else
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h 
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index de50e08..43efa65 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW   = 2,/* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW= 32,   /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32,   /* Number of ppl clock sources X */
+   TEGRA_CLK_SOURCES_Y = 18,   /* Number of ppl clock sources Y */
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0,0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0,0x294 */
 
-   uint crc_reserved21[23];/* _reserved_21,0x298-2f0 */
+   uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0,0x298 */
+   uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0,0x29c */
+   uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0,0x2a0 */
+
+   uint crc_rst_devices_y; /* _RST_DEVICES_Y_0,0x2a4 */
+   uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0,0x2a8 */
+   uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0,0x2ac */
+
+   uint crc_reserved21[17];/* _reserved_21,0x2b0-2f0 */
 
uint crc_dfll_base; /* _DFLL_BASE_0,0x2f4 */
 
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
-   /* Additional (T114) registers */
+   /* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set;/* _RST_CPUG_CMPLX_SET_0,  0x450 */
uint crc_rst_cpug_cmplx_clr;/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
uint crc_rst_cpulp_cmplx_set;   /* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7];/*  0x574-58c */
struct clk_pll_simple plldp;/* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg;   /* _PLLDP_SS_CFG, 0x598 */
-   u32 _rsrv32_2[25];
-   /* Tegra124 */
-   uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+   /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+   uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
+   uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+   /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+   uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
+   /*
+* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+* two later if PLLA1 is needed, but for now this is cleaner.
+*/
+   uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h

[U-Boot] [PATCH V2 1/6] Tegra210: Fix 64-bit build warning about save_boot_params_ret()

2015-07-20 Thread Tom Warren
Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.

Signed-off-by: Tom Warren 
---
 arch/arm/mach-tegra/board.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f113041..036bf5e 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -18,6 +18,8 @@
 #include 
 #include 
 
+void save_boot_params_ret(void);
+
 DECLARE_GLOBAL_DATA_PTR;
 
 enum {
-- 
1.8.2.1.610.g562af5b

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[U-Boot] [PATCH V2 5/6] P2571: dts: Add DT files for Tegra210/P2571 board

2015-07-20 Thread Tom Warren
Based on T124 Venice2. SDMMC1 is SD-card slot.

Signed-off-by: Tom Warren 
---
 arch/arm/dts/Makefile  |   3 +-
 .../{tegra124-venice2.dts => tegra210-p2571.dts}   |  40 --
 arch/arm/dts/{tegra124.dtsi => tegra210.dtsi}  | 153 -
 3 files changed, 56 insertions(+), 140 deletions(-)
 copy arch/arm/dts/{tegra124-venice2.dts => tegra210-p2571.dts} (65%)
 copy arch/arm/dts/{tegra124.dtsi => tegra210.dtsi} (76%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 19e1de6..9bd7014 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -32,7 +32,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra114-dalmore.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
-   tegra124-venice2.dtb
+   tegra124-venice2.dtb \
+   tegra210-p2571.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra210-p2571.dts
similarity index 65%
copy from arch/arm/dts/tegra124-venice2.dts
copy to arch/arm/dts/tegra210-p2571.dts
index 9e93cf9..ca41390 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra210-p2571.dts
@@ -1,10 +1,10 @@
 /dts-v1/;
 
-#include "tegra124.dtsi"
+#include "tegra210.dtsi"
 
 / {
-   model = "NVIDIA Venice2";
-   compatible = "nvidia,venice2", "nvidia,tegra124";
+   model = "NVIDIA P2571";
+   compatible = "nvidia,p2571", "nvidia,tegra210";
 
chosen {
stdout-path = &uarta;
@@ -18,16 +18,15 @@
i2c4 = "/i2c@7000c700";
i2c5 = "/i2c@7000d100";
sdhci0 = "/sdhci@700b0600";
-   sdhci1 = "/sdhci@700b0400";
+   sdhci1 = "/sdhci@700b";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
+   spi2 = "/spi@7041";
usb0 = "/usb@7d00";
-   usb1 = "/usb@7d008000";
};
 
memory {
-   device_type = "memory";
-   reg = <0x8000 0x8000>;
+   reg = <0x0 0x8000 0x0 0xc000>;
};
 
i2c@7000c000 {
@@ -70,11 +69,15 @@
spi-max-frequency = <2500>;
};
 
-   sdhci@700b0400 {
+   spi@7041 {
status = "okay";
-   cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
-   power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
-   wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+   spi-max-frequency = <2400>;
+   };
+
+   sdhci@700b {
+   status = "okay";
+   cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+   power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
 
@@ -86,11 +89,18 @@
usb@7d00 {
status = "okay";
dr_mode = "otg";
-   nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
 
-   usb@7d008000 {
-   status = "okay";
-   nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+   clocks {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   clk32k_in: clock@0 {
+   compatible = "fixed-clock";
+   reg = <0>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
};
 };
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra210.dtsi
similarity index 76%
copy from arch/arm/dts/tegra124.dtsi
copy to arch/arm/dts/tegra210.dtsi
index 43b7f22..f09a1a7 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra210.dtsi
@@ -1,4 +1,4 @@
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -7,7 +7,7 @@
 #include "skeleton.dtsi"
 
 / {
-   compatible = "nvidia,tegra124";
+   compatible = "nvidia,tegra210";
interrupt-parent = <&gic>;
 
pcie-controller@01003000 {
@@ -35,10 +35,10 @@
  0x8200 0 0x1300 0x1300 0 0x0d00   /* 
non-prefetchable memory (208 MiB) */
  0xc200 0 0x2000 0x2000 0 0x2000>; /* 
prefetchable memory (512 MiB) */
 
-   clocks = <&tegra_car TEGRA124_CLK_PCIE>,
-<&tegra_car TEGRA124_CLK_AFI>,
-<&tegra_car TEGRA124_CLK_PLL_E>,
-<&tegra_car TEGRA124_CLK_CML0>;
+   clocks = <&tegra_car TEGRA210_CLK_PCIE>,
+<&tegra_car TEGRA210_CLK_AFI>,
+<&tegra_car TEGRA210_CLK_PLL_E>,
+<&tegra_car TEGRA210_CLK_CML0>;
clock-names = "pex", "afi", "pll_e", "cml";
resets = <&tegra_car 70>,
 <&teg

[U-Boot] [PATCH V2 6/6] T210: Add support for 64-bit T210-based P2571 board

2015-07-20 Thread Tom Warren
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.

With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).

Signed-off-by: Tom Warren 
---
 arch/arm/mach-tegra/tegra210/Kconfig   |   7 +
 board/nvidia/{beaver => p2571}/Kconfig |   6 +-
 board/nvidia/p2571/MAINTAINERS |   6 +
 .../tegra210 => board/nvidia/p2571}/Makefile   |   6 +-
 board/nvidia/p2571/max77620_init.c |  85 
 board/nvidia/p2571/max77620_init.h |  67 ++
 board/nvidia/p2571/p2571.c |  29 +++
 board/nvidia/p2571/pinmux-config-p2571.h   | 235 +
 configs/{beaver_defconfig => p2571_defconfig}  |   6 +-
 include/configs/{venice2.h => p2571.h} |  42 ++--
 .../{tegra124-common.h => tegra210-common.h}   |  15 +-
 11 files changed, 469 insertions(+), 35 deletions(-)
 copy board/nvidia/{beaver => p2571}/Kconfig (61%)
 create mode 100644 board/nvidia/p2571/MAINTAINERS
 copy {arch/arm/mach-tegra/tegra210 => board/nvidia/p2571}/Makefile (59%)
 create mode 100644 board/nvidia/p2571/max77620_init.c
 create mode 100644 board/nvidia/p2571/max77620_init.h
 create mode 100644 board/nvidia/p2571/p2571.c
 create mode 100644 board/nvidia/p2571/pinmux-config-p2571.h
 copy configs/{beaver_defconfig => p2571_defconfig} (77%)
 copy include/configs/{venice2.h => p2571.h} (62%)
 copy include/configs/{tegra124-common.h => tegra210-common.h} (89%)

diff --git a/arch/arm/mach-tegra/tegra210/Kconfig 
b/arch/arm/mach-tegra/tegra210/Kconfig
index f2a0059..147e6a8 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -3,9 +3,16 @@ if TEGRA210
 choice
prompt "Tegra210 board select"
 
+config TARGET_P2571
+   bool "NVIDIA Tegra210 P2571 base board"
+   help
+ P2571 is a P2530 married to a P1963 I/O board
+
 endchoice
 
 config SYS_SOC
default "tegra210"
 
+source "board/nvidia/p2571/Kconfig"
+
 endif
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/p2571/Kconfig
similarity index 61%
copy from board/nvidia/beaver/Kconfig
copy to board/nvidia/p2571/Kconfig
index 23f7c94..7bc4874 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_BEAVER
+if TARGET_P2571
 
 config SYS_BOARD
-   default "beaver"
+   default "p2571"
 
 config SYS_VENDOR
default "nvidia"
 
 config SYS_CONFIG_NAME
-   default "beaver"
+   default "p2571"
 
 endif
diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS
new file mode 100644
index 000..c165135
--- /dev/null
+++ b/board/nvidia/p2571/MAINTAINERS
@@ -0,0 +1,6 @@
+P2571 BOARD
+M: Tom Warren 
+S: Maintained
+F: board/nvidia/p2571/
+F: include/configs/p2571.h
+F: configs/p2571_defconfig
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/board/nvidia/p2571/Makefile
similarity index 59%
copy from arch/arm/mach-tegra/tegra210/Makefile
copy to board/nvidia/p2571/Makefile
index 1fb8d1a..223062e 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/board/nvidia/p2571/Makefile
@@ -5,7 +5,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += clock.o
-obj-y  += funcmux.o
-obj-y  += pinmux.o
-obj-y  += xusb-padctl.o
+obj-y  += max77620_init.o
+obj-y  += p2571.o
diff --git a/board/nvidia/p2571/max77620_init.c 
b/board/nvidia/p2571/max77620_init.c
new file mode 100644
index 000..ed8d4dc
--- /dev/null
+++ b/board/nvidia/p2571/max77620_init.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include "max77620_init.h"
+
+/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+   struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+   writel(addr, ®->cmd_addr0);
+   writel(config, ®->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+   struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+   writel(data, ®->cmd_data1);
+   writel(config, ®->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+   uint reg;
+   debug("%s entry\n", __func__);
+
+   /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
+   debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__);
+   /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
+   reg = 0x0900 | MAX77620_GPIO5_REG;
+   tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+
+   /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
+   debug("%s: Setting GPIO1 to enable HDMI\n", __func__);
+   reg = 0x0900 | MAX77620_GPIO1_REG;
+   tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(reg, I2C_SEN

Re: [U-Boot] [PATCH 1/8] doc: dfu: tftp: README entry for TFTP extension of DFU

2015-07-20 Thread Tormod Volden
On Mon, Jul 20, 2015 at 9:17 PM, Joe Hershberger wrote:
> On Mon, Jul 20, 2015 at 1:59 PM, Lukasz Majewski wrote:
>>> >> Is thor not faster than DFU?
>>> >
>>> > Yes, it is. However, DFU is standardized (which is despite of its
>>> > low speed its huge advantage) - thor not.
>>> >
>>> >>
>>> >> It seems like DFU should support a bulk endpoint if performance is
>>> >> an issue, right?
>>> >
>>> > Yes, it should, but such modification would be not compliant with
>>> > the standard.
>>>
>>> Who is the standards body? Can they accept suggestions for the next
>>> revision? Is it worth trying to improve the standard?
>>
>> The last revision of DFU standard is from 2006 with Greg KH being a
>> notable USB committee board member :-)
>>
>> I've asked him about the possibility to revise the standard but he
>> replied that chances are small since Linux Foundation is not part
>> of the USB standard committee anymore.
>
> That's a shame. Oh well.

As a dfu-util maintainer I should not encourage breaking the standard
:) but it happened that ST made their own twist to the standard
("DfuSe") for their own purposes. I added support for this to dfu-util
instead of making a new separate tool since much code could be shared,
and I still think that made sense. A good part of dfu-util usage today
is on DfuSe devices, and the added exposure and contributions are
helpful for non-DfuSe devices also. So if not too intrusive changes
are needed and there are people willing to code and test I would be
happy to accept it in dfu-util.

For background, the use of only control endpoints in the DFU standard
was there to keep everything as simple as possible and allow
implementations on the simplest of microcontrollers. Nowadays more
advanced microcontroller devices often use for instance USB mass
storage emulation for firmware updates, wanting to avoid any special
tools or drivers on the host, however this approach also has issues,
especially between various host platforms.

>>> >>That would be more efficient than emulating Ethernet.
>>> >
>>> > To be more precise - I've combined the ability to use Ethernet with
>>> > DFU flashing backend.
>>> >
>>> > In this way boards only equipped with ETH can (re)use DFU code to
>>> > flash data (on MMC, NAND, filesystems, RAM, etc).
>>>
>>> Yes, that's very good. I was simply talking about the "BONUS" where
>>> emulated Ethernet over USB is used. In that case it would be more
>>> efficient to actually have a raw bulk endpoint supported by DFU.
>>
>> Yes, it would. Unfortunately I think that it would be very hard to
>> revise the DFU standard.
>>
>> ETH over USB can be used on devices equipped only with USB (like
>> trats/trats2 devel mobile phones). In that way DFU speed would increase.
>
> Sure. Sounds good.

This is a nice workaround, although I don't know how easy it is to use
for common users, and if it gives much speed penalty compared to raw
bulk endpoints. Whether it makes sense to develop the latter also
depends on how interesting updates over USB (from a host computer)
will be for the uboot userbase or if e.g. pluggable mass storage
devices (and the device as USB host) will be more popular.

Regards,
Tormod
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Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and mx6ul

2015-07-20 Thread Nikolay Dimitrov

Hi Adrian,

On 07/16/2015 01:49 AM, Adrian Alonso wrote:

* The system counter driver for imx7d abd mx6ul, move
   this timer driver to imx-common and rename it as syscounter.c

   For mx6ul and mx7, configurations are used for choose the GPT timer
   or system counter timer (default).

   GPT timer:  CONFIG_GPT_TIMER
   System counter timer:   CONFIG_SYSCOUNTER_TIMER

   For mx6dqp GPT timer is the default setting.

Signed-off-by: Adrian Alonso 
Signed-off-by: Ye.Li 
---
  arch/arm/imx-common/syscounter.c | 126 +++
  arch/arm/include/asm/imx-common/syscounter.h |  29 ++
  include/configs/mx6_common.h |   1 +
  3 files changed, 156 insertions(+)
  create mode 100644 arch/arm/imx-common/syscounter.c
  create mode 100644 arch/arm/include/asm/imx-common/syscounter.h

diff --git a/arch/arm/imx-common/syscounter.c b/arch/arm/imx-common/syscounter.c
new file mode 100644
index 000..f5e5cdc
--- /dev/null
+++ b/arch/arm/imx-common/syscounter.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+   ulong ticks;
+
+   if (usec < 1000)
+   ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+   else
+   ticks = ((usec / 10) * (get_tbclk() / 10));
+
+   return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   tick *= CONFIG_SYS_HZ;
+   do_div(tick, freq);
+
+   return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   usec = usec * freq  + 99;
+   do_div(usec, 100);
+
+   return usec;
+}


Is it possible to use the same naming convention for usec2ticks(),
tick_to_time() and us_to_tick() (e.g. choose either "2" or "_to_")?
Thanks.


+
+int timer_init(void)
+{
+   struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+   unsigned long val, freq;
+
+   freq = CONFIG_SC_TIMER_CLK;
+   asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+   writel(freq, &sctr->cntfid0);
+
+   /* Enable system counter */
+   val = readl(&sctr->cntcr);
+   val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+   val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+   writel(val, &sctr->cntcr);
+
+   gd->arch.tbl = 0;
+   gd->arch.tbu = 0;
+
+   return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+   unsigned long long now;
+
+   asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+   gd->arch.tbl = (unsigned long)(now & 0x);
+   gd->arch.tbu = (unsigned long)(now >> 32);
+
+   return now;
+}
+
+ulong get_timer_masked(void)
+{
+   return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+   return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+   unsigned long long tmp;
+   ulong tmo;
+
+   tmo = us_to_tick(usec);
+   tmp = get_ticks() + tmo;/* get current timestamp */
+
+   while (get_ticks() < tmp)/* loop till event */
+/*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   return freq;
+}
diff --git a/arch/arm/include/asm/imx-common/syscounter.h 
b/arch/arm/include/asm/imx-common/syscounter.h
new file mode 100644
index 000..ddb412e
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/syscounter.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+   u32 cntcr;
+   u32 cntsr;
+   u32 cntcv1;
+   u32 cntcv2;
+   u32 resv1[4];
+   u32 cntfid0;
+   u32 cntfid1;
+   u32 cntfid2;
+   u32 resv2[1001];
+   u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE(1 << 0)
+#define SC_CNTCR_HDBG  (1 << 1)
+#define SC_CNTCR_FREQ0 (1 << 8)
+#define SC_CNTCR_FREQ1 (1 << 9)
+
+#endif
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 86d7b16..690038d 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -

[U-Boot] [PATCH v2 1/6] arm1136: Remove dead code

2015-07-20 Thread Alexander Stein
Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.

Signed-off-by: Alexander Stein 
---
 arch/arm/cpu/arm1136/cpu.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index a7aed4b..5d4b3c2 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -32,16 +32,6 @@ int cleanup_before_linux (void)
 
disable_interrupts ();
 
-#ifdef CONFIG_LCD
-   {
-   extern void lcd_disable(void);
-   extern void lcd_panel_disable(void);
-
-   lcd_disable(); /* proper disable of lcd & panel */
-   lcd_panel_disable();
-   }
-#endif
-
/* turn off I/D-cache */
icache_disable();
dcache_disable();
-- 
2.4.6

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[U-Boot] [PATCH v2 3/6] ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

2015-07-20 Thread Alexander Stein
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.

Signed-off-by: Alexander Stein 
---
 include/configs/rpi-common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 1012cdd..e75fb1e 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -15,6 +15,7 @@
 #define CONFIG_BCM2835
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE  32
 
 #define CONFIG_SYS_TIMER_RATE  100
 #define CONFIG_SYS_TIMER_COUNTER   \
-- 
2.4.6

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[U-Boot] [PATCH v2 2/6] arm1136/arm1176: Merge cache handling code

2015-07-20 Thread Alexander Stein
As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.

Signed-off-by: Alexander Stein 
---
 arch/arm/cpu/arm11/Makefile   |   8 +++
 arch/arm/cpu/arm11/cpu.c  | 150 ++
 arch/arm/cpu/arm1136/Makefile |   1 -
 arch/arm/cpu/arm1136/cpu.c| 150 --
 arch/arm/cpu/arm1176/Makefile |   4 +-
 arch/arm/cpu/arm1176/cpu.c|  51 --
 6 files changed, 161 insertions(+), 203 deletions(-)
 create mode 100644 arch/arm/cpu/arm11/Makefile
 create mode 100644 arch/arm/cpu/arm11/cpu.c
 delete mode 100644 arch/arm/cpu/arm1136/cpu.c
 delete mode 100644 arch/arm/cpu/arm1176/cpu.c

diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile
new file mode 100644
index 000..2379b0f
--- /dev/null
+++ b/arch/arm/cpu/arm11/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  = cpu.o
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
new file mode 100644
index 000..5d4b3c2
--- /dev/null
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH 
+ * Marius Groeger 
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include 
+#include 
+#include 
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+   /*
+* this function is called just before we call linux
+* it prepares the processor for linux
+*
+* we turn off caches etc ...
+*/
+
+   disable_interrupts ();
+
+   /* turn off I/D-cache */
+   icache_disable();
+   dcache_disable();
+   /* flush I/D-cache */
+   cache_flush();
+
+   return 0;
+}
+
+static void cache_flush(void)
+{
+   unsigned long i = 0;
+   /* clean entire data cache */
+   asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+   /* invalidate both caches and flush btb */
+   asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+   /* mem barrier to sync things */
+   asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE  32
+#endif
+
+void invalidate_dcache_all(void)
+{
+   asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+   asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+   asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+   int ok = 1;
+
+   if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+   ok = 0;
+
+   if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+   ok = 0;
+
+   if (!ok)
+   debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+   start, stop);
+
+   return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+   if (!check_cache_range(start, stop))
+   return;
+
+   while (start < stop) {
+   asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+   start += CONFIG_SYS_CACHELINE_SIZE;
+   }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+   if (!check_cache_range(start, stop))
+   return;
+
+   while (start < stop) {
+   asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+   start += CONFIG_SYS_CACHELINE_SIZE;
+   }
+
+   asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+   flush_dcache_range(start, start + size);
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+   icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+   dcache_enable();
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 56a9390..5d6f0aa 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -6,7 +6,6 @@
 #
 
 extra-y= start.o
-obj-y  = cpu.o
 
 obj-$(CONFIG_MX31) += mx31/
 obj-$(CONFIG_MX35) += mx35/
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
deleted file mode 1

[U-Boot] [PATCH v2 5/6] arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox

2015-07-20 Thread Alexander Stein
When using dcache the setup data for the mailbox must be actually written
into memory before calling into firmware. Thus flush and invalidate the
memory.

Signed-off-by: Alexander Stein 
---
Changes in v2:
* Add hint in header about alignment requirements
* Invalidate cache after calling into mailbox
* round size up to next cacheline size

 arch/arm/mach-bcm283x/include/mach/mbox.h | 4 
 arch/arm/mach-bcm283x/mbox.c  | 9 +
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h 
b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 54d369c..ae1b904 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -522,6 +522,10 @@ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
  * a termination value are expected to immediately follow the header in
  * memory, as required by the property protocol.
  *
+ * Each struct bcm2835_mbox_hdr passed must be allocated with
+ * ALLOC_ALIGN_BUFFER(x, y, z, CONFIG_SYS_CACHELINE_SIZE) to ensure proper
+ * cache flush/invalidate.
+ *
  * Returns 0 for success, any other value for error.
  */
 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 1af9be7..740db0c 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -111,9 +111,18 @@ int bcm2835_mbox_call_prop(u32 chan, struct 
bcm2835_mbox_hdr *buffer)
dump_buf(buffer);
 #endif
 
+   flush_dcache_range((unsigned long)buffer,
+  (unsigned long)((void *)buffer +
+  roundup(buffer->buf_size, 32)));
+
ret = bcm2835_mbox_call_raw(chan, phys_to_bus((u32)buffer), &rbuffer);
if (ret)
return ret;
+
+   invalidate_dcache_range((unsigned long)buffer,
+   (unsigned long)((void *)buffer +
+   roundup(buffer->buf_size, 32)));
+
if (rbuffer != phys_to_bus((u32)buffer)) {
printf("mbox: Response buffer mismatch\n");
return -1;
-- 
2.4.6

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[U-Boot] [PATCH v2 4/6] ARM: bcm283x: Allocate all mailbox buffers cacheline aligned

2015-07-20 Thread Alexander Stein
The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use CONFIG_SYS_CACHELINE_SIZE alignment for all mailbox buffer allocations.

Signed-off-by: Alexander Stein 
---
 board/raspberrypi/rpi/rpi.c | 10 +-
 drivers/video/bcm2835.c |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 96fe870..d5d3fec 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -182,7 +182,7 @@ u32 rpi_board_rev = 0;
 
 int dram_init(void)
 {
-   ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
+   ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 
CONFIG_SYS_CACHELINE_SIZE);
int ret;
 
BCM2835_MBOX_INIT_HDR(msg);
@@ -212,7 +212,7 @@ static void set_fdtfile(void)
 
 static void set_usbethaddr(void)
 {
-   ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+   ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 
CONFIG_SYS_CACHELINE_SIZE);
int ret;
 
if (!models[rpi_board_rev].has_onboard_eth)
@@ -245,7 +245,7 @@ int misc_init_r(void)
 
 static int power_on_module(u32 module)
 {
-   ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+   ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 
CONFIG_SYS_CACHELINE_SIZE);
int ret;
 
BCM2835_MBOX_INIT_HDR(msg_pwr);
@@ -269,7 +269,7 @@ static int power_on_module(u32 module)
 
 static void get_board_rev(void)
 {
-   ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+   ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 
CONFIG_SYS_CACHELINE_SIZE);
int ret;
const char *name;
 
@@ -324,7 +324,7 @@ int board_init(void)
 
 int board_mmc_init(bd_t *bis)
 {
-   ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
+   ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 
CONFIG_SYS_CACHELINE_SIZE);
int ret;
 
power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 1f18231..30e22cc 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -38,8 +38,8 @@ struct msg_setup {
 
 void lcd_ctrl_init(void *lcdbase)
 {
-   ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 16);
-   ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 16);
+   ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 
CONFIG_SYS_CACHELINE_SIZE);
+   ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 
CONFIG_SYS_CACHELINE_SIZE);
int ret;
u32 w, h;
 
-- 
2.4.6

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[U-Boot] [PATCH v2 6/6] arm/rpi: Enable dcache

2015-07-20 Thread Alexander Stein
Now that mailbox driver supports cache flush and invalidation, we can
enable dcache.

Signed-off-by: Alexander Stein 
---
Changes in v2:
* Only enable dcache on rpi1, but not on rpi2

 include/configs/rpi-common.h | 1 -
 include/configs/rpi_2.h  | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index e75fb1e..43b460b 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -14,7 +14,6 @@
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_BCM2835
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE  32
 
 #define CONFIG_SYS_TIMER_RATE  100
diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h
index 2e7e74f..0ecd399 100644
--- a/include/configs/rpi_2.h
+++ b/include/configs/rpi_2.h
@@ -9,6 +9,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
+#define CONFIG_SYS_DCACHE_OFF
 
 #include "rpi-common.h"
 
-- 
2.4.6

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[U-Boot] [PATCH v2 0/6] dcache support for Raspberry Pi 1

2015-07-20 Thread Alexander Stein
This patchset enables dcache support for Raspberry Pi 1.
First the cache support code for arm1136 and 1176 was merged.
CONFIG_SYS_CACHELINE_SIZE is defined as 32 bytes which is used as alignment
for mailbox buffer allocations.
Then rpi mailbox code has now dcache flush for writing the mailbox request and
a dcache invalidation for receiving the mailbox answer.
Finally the CONFIG_SYS_DCACHE_OFF switch got removed from rpi1 config. It is
still set for rpi2 config.

dcache supprt increases the MMC read performance on RPI 1 from 5,4 MiB/s to
12.3 MiB/s.

This was tested by the following command:
> fatload mmc 0:1 ${kernel_addr_r} zImage

Changes in v2:
* Merge arm1136/1176 cache code
* Use cacheline size as mailbox buffer alignment
* Flush/invalidate mailbox buffer up to cacheline size

Alexander Stein (6):
  arm1136: Remove dead code
  arm1136/arm1176: Merge cache handling code
  ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
  ARM: bcm283x: Allocate all mailbox buffers cacheline aligned
  arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw
mailbox
  arm/rpi: Enable dcache

 arch/arm/cpu/arm11/Makefile   |   8 ++
 arch/arm/cpu/arm11/cpu.c  | 150 
 arch/arm/cpu/arm1136/Makefile |   1 -
 arch/arm/cpu/arm1136/cpu.c| 160 --
 arch/arm/cpu/arm1176/Makefile |   4 +-
 arch/arm/cpu/arm1176/cpu.c|  51 --
 arch/arm/mach-bcm283x/include/mach/mbox.h |   4 +
 arch/arm/mach-bcm283x/mbox.c  |   9 ++
 board/raspberrypi/rpi/rpi.c   |  10 +-
 drivers/video/bcm2835.c   |   4 +-
 include/configs/rpi-common.h  |   2 +-
 include/configs/rpi_2.h   |   1 +
 12 files changed, 183 insertions(+), 221 deletions(-)
 create mode 100644 arch/arm/cpu/arm11/Makefile
 create mode 100644 arch/arm/cpu/arm11/cpu.c
 delete mode 100644 arch/arm/cpu/arm1136/cpu.c
 delete mode 100644 arch/arm/cpu/arm1176/cpu.c

-- 
2.4.6

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[U-Boot] Please pull u-boot-fsl-qoriq master

2015-07-20 Thread York Sun
Tom,

The following changes since commit 605e15db2b54302364a2528d3c6604fbc57be846:

  Merge git://git.denx.de/u-boot-x86 (2015-07-15 10:41:20 -0400)

are available in the git repository at:


  git://git.denx.de/u-boot-fsl-qoriq.git master

for you to fetch changes up to db14f11dfe348550d8c10c6609277488d9f500d6:

  armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. (2015-07-20 11:44:40 
-0700)


Alison Wang (2):
  arm: ls1021a: Remove the inappropriate use of the function 'sprintf'
  arm/ls102xa: Add little-endian mode support for audio IPs

Bhupesh Sharma (4):
  armv8/ls2085a: Increase the supported kernel size
  armv8/ls2085a: Expose all DDR region(s) to Linux
  driver/fsl_debug_server: Fix the DDR hide logic for LS2085a
  arm/errata: Update required bits for A57 cores erratas

Haikun Wang (7):
  arm/dts/ls2085a: Bring in ls2085a dts files from linux kernel
  arm/dts/ls2085a: Add DSPI dts node
  arm/dts/ls2085a: Add dts files for LS2085AQDS and LS2085ARDB
  armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'
  armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
  armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDS
  armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDB

haikun.w...@freescale.com (2):
  armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD
  armv8/ls2085a/defconfig: Enable FSL_DSPI, OF_CONTROL and DM support

J. German Rivera (2):
  drivers/fsl-mc: Make MC boot error messages more readable
  drivers/fsl-mc: Autoload AOIP image from NOR flash

Jaiprakash Singh (1):
  board/fsl/common: Fix eeprom system version endianness

Prabhakar Kushwaha (21):
  armv8/ls2085ardb: Add eth & phy firmware loading support
  armv8/ls2085aqds: Add support of SerDes protocol 0x49
  armv8/ls2085a: Update LS2085a PCIe compatible
  armv8/ls2085a: call ft_pcie_setup() to change dts status
  armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI
  armv8/ls2085rdb: Update PCA9547PW slave address
  armv8/ls2085RDB: Update board version print logic
  armv8/fsl-ch3: Add support to print SoC personality
  armv8/ls2085a: Avoid hard-coding for board name print
  armv8/ls2085a: Update SoC README for DDR layout
  armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr
  driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_conf
  drivers: fsl-mc: Update flibs to mc-0.6.0.1
  drivers: fsl-mc: Update qbman driver
  drivers: fsl-mc: Return error for major version mismatch
  driver/ldpaa_eth: Retry enqueue if portal was busy
  driver/ldpaa_eth: Add timeout handling DQRR entry read
  driver/ldpaa_eth: Avoid TX conf frames
  driver/ldpaa_eth:Avoid infinite loop in ldpaa_eth_rx
  board/ls2085rdb: Export functions for standalone AQ FW load apps
  board/ls2085a: Increase kernel_size value in env variable

Priyanka Jain (1):
  armv8/ls2085a: Enable "date" command for QDS and RDB

Stuart Yoder (4):
  armv8/ls2085a: enable debug server
  armv8/fsl-lsch3: partition stream IDs
  drivers/fsl-mc: dynamically create ICID pool in DPC
  armv8/fsl-lsch3: device tree fixups for PCI stream IDs

Wang Dongsheng (2):
  ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
  arm/ls102xa: Add PSCI support for ls102xa

Yangbo Lu (1):
  armv8/ls2085ardb: add hwconfig setting for eSDHC

York Sun (3):
  armv8/fsl-lsch3: Fix DDR speed message
  driver/ddr/fsl: Add a hook to update SPD address
  armv8/ls2085ardb: Fix SPD address error on early boards

Zhichun Hua (2):
  armv8: Fix TCR macros for shareability attribute
  armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.

 README |   15 ++
 arch/arm/cpu/armv7/ls102xa/Makefile|4 +
 arch/arm/cpu/armv7/ls102xa/fdt.c   |   21 +--
 arch/arm/cpu/armv7/ls102xa/psci.S  |  126 +++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  |   22 +--
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  |   22 +--
 arch/arm/cpu/armv8/fsl-lsch3/README|   25 +++
 arch/arm/cpu/armv8/fsl-lsch3/cpu.c |   64 ++--
 arch/arm/cpu/armv8/fsl-lsch3/fdt.c |  114 ++
 arch/arm/cpu/armv8/fsl-lsch3/speed.c   |2 +
 arch/arm/cpu/armv8/start.S |8 +-
 arch/arm/dts/Makefile  |2 +
 arch/arm/dts/fsl-ls2085a-qds.dts   |   53 +++
 arch/arm/dts/fsl-ls2085a-rdb.dts   |   35 +
 arch/arm/dts/fsl-ls2085a.dtsi  |  129 
 arch/arm/include/asm/arch-armv7/generictimer.h |   50 ++
 arch/arm/include/asm/arch-fsl-lsch3/clock.h|1 +
 arch/arm/include/asm/arch-fsl-lsch3/config.h   |2 +
 arch/arm/i

Re: [U-Boot] [PATCH 01/13][v4] drivers/fsl-mc: Make MC boot error messages more readable

2015-07-20 Thread York Sun


On 07/01/2015 10:58 PM, Prabhakar Kushwaha wrote:
> From: "J. German Rivera" 
> 
> Make it easier for the user to notice when the MC firmware
> had problems booting.
> 
> Signed-off-by: J. German Rivera 
> Signed-off-by: Prabhakar Kushwaha 
> ---
> Changes for v2: Sending as it is for patchset
> Changes for v3: Sending as it is for patchset
> Changes for v4: Sending as it is for patchset

This set (v4) is applied to u-boot-fsl-qoriq master branch.

York

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Re: [U-Boot] [PATCH] armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.

2015-07-20 Thread York Sun


On 06/29/2015 12:50 AM, Alison Wang wrote:
> From: Zhichun Hua 
> 
> When final MMU table is setup in DDR, TCR attributes must match
> those of the memroy for cacheability and shareability.
> 
> Signed-off-by: Zhichun Hua 
> Signed-off-by: York Sun 

Applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH 1/2] armv8: Fix TCR macros for shareability attribute

2015-07-20 Thread York Sun


On 06/29/2015 12:49 AM, Alison Wang wrote:
> From: Zhichun Hua 
> 
> For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
> position [13:12] of TCR_ELx register.
> 
> Signed-off-by: Zhichun Hua 
> Signed-off-by: York Sun 
> ---

Applied to u-boot-fsl-qoriq master branch.

York

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Re: [U-Boot] [PATCH] arm: ls1021a: Remove the inappropriate use of the function 'sprintf'

2015-07-20 Thread York Sun


On 05/11/2015 12:39 AM, Alison Wang wrote:
> As the function 'sprintf' does not check buffer boundaries but outputs
> to the buffer 'enet' of fixed size (16), this patch removes the function
> 'sprintf', and uses 'strcpy' instead. It will assign the character
> arrays 'enet' and 'phy' the corresponding character strings.
> 
> Signed-off-by: Alison Wang 
> ---

Applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH] board: ks2: README: fix typos

2015-07-20 Thread Tom Rini
On Thu, Jul 16, 2015 at 10:14:49AM -0500, Nishanth Menon wrote:

> Fix up a few typos in documentation.
> 
> Signed-off-by: Nishanth Menon 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa

2015-07-20 Thread York Sun


On 06/03/2015 09:01 PM, Dongsheng Wang wrote:
> From: Wang Dongsheng 
> 
> Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
> 
> Tested on LS1021AQDS, LS1021ATWR.
> Test CPU hotplug times: 60K
> Test kernel boot times: 1.2K
> 
> Signed-off-by: Wang Dongsheng 
> 

Applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S

2015-07-20 Thread York Sun


On 06/03/2015 09:01 PM, Dongsheng Wang wrote:
> From: Wang Dongsheng 
> 
> timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
> completely into a reusable armv7 generic timer. LS1021A will use it
> as well.
> 
> Signed-off-by: Wang Dongsheng 
> 

Applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH] arm: ls102xa: Add little-endian mode support for audio IPs

2015-07-20 Thread York Sun


On 06/09/2015 01:07 AM, Alison Wang wrote:
> As SCFG_ENDIANCR register is added to choose little-endian or big-endian
> for audio IPs on Rev2.0 silion, little-endian mode is selected.
> 
> Signed-off-by: Alison Wang 
> ---

Applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH 1/3] dm: dts: ls2085a: Bring in ls2085a dts files from linux kernel

2015-07-20 Thread York Sun


On 06/26/2015 04:48 AM, Haikun Wang wrote:
> From: Haikun Wang 
> 
> Bring in required device tree files for ls2085a from Linux.
> These are initially unchanged and have a number of pieces not needed by 
> U-Boot.
> 
> Signed-off-by: Haikun Wang 
> ---

This set is applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH] armv8: ls2085a: Enable DSPI get input clk form 'mxc_get_clock'

2015-07-20 Thread York Sun


On 06/26/2015 04:56 AM, Haikun Wang wrote:
> From: Haikun Wang 
> 
> Signed-off-by: Haikun Wang 
> ---

Applied to u-boot-fsl-qoriq master branch.

York
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Re: [U-Boot] [PATCH 1/2] armv8: ls2085aqds: DSPI pin muxing configure through QIXIS

2015-07-20 Thread York Sun


On 06/26/2015 04:58 AM, Haikun Wang wrote:
> From: Haikun Wang 
> 
> DSPI has pin muxing with SDHC and other IPs, this patch check the value of
> RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig"
> configuration, if those pins are configured to DSPI and "hwconfig" enable
> DSPI, set the BRDCFG5 of QIXIS FPGA to configure the SPI routing to on-board
> SPI memory. Otherwise will configure to SDHC.
> Enable DSPI in u-boot "hwconfig" using below command:
> setenv hwconfig "$hwconfig;dspi"
> 
> Signed-off-by: Haikun Wang 
> ---

This set is applied to u-boot-fsl-qoriq master branch with subject fix.

York
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Re: [U-Boot] [PATCH 1/3] configs: ls2085aqds: Enable DSPI flash support for LS2085AQDS

2015-07-20 Thread York Sun


On 07/03/2015 01:51 AM, Haikun Wang wrote:
> From: Haikun Wang 
> 
> Enable DSPI flash related configurations.
> 
> Signed-off-by: Haikun Wang 
> ---

This set is applied to u-boot-fsl-qoriq master branch with subject fix.

York
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Re: [U-Boot] [PATCH] defconfig: ls2085a: Enable FSL_DSPI, OF_CONTROL and DM support

2015-07-20 Thread York Sun


On 07/03/2015 01:51 AM, Haikun Wang wrote:
> Freescale DSPI driver has been converted to Driver Model.
> The new driver is depended on OF_CONTROL, DM, DM_SPI.
> This patch enable FSL_DSPI and its dependence configure options.
> 
> Signed-off-by: Haikun Wang 
> ---

Applied to u-boot-fsl-qoriq master branch with subject fix.

York
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Re: [U-Boot] [PATCH 5/5] arm: mvebu: db-88f6820-gp: Add SDIO/MMC SPL boot support

2015-07-20 Thread Luka Perkov
Hi Stefan,

On Mon, Jul 20, 2015 at 11:20:40AM +0200, Stefan Roese wrote:
> This patch adds the configuration options to boot via SDIO/MMC on the
> Marvell DB-88F6820-GP Armada A38x board. The default boot device
> is still SPI NOR flash.
> 
> To enable MMC booting on this board 2 things need to be changes:
> a) Change kwbimage.cfg
>BOOT_FROM   sdio
> b) In the config header select
>#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
> 
> The generated image needs to be copied to the first bootable MMC
> partition:

Can you please define "bootable" here? Does the partition really need to
have bootable flag configured?

Thanks,
Luka

> dd if=u-boot-spl.kwb of=/dev/sdX1
> 
> Signed-off-by: Stefan Roese 
> Cc: Luka Perkov 
> Cc: Dirk Eibach 
> ---
>  include/configs/db-88f6820-gp.h | 28 
>  1 file changed, 28 insertions(+)
> 
> diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
> index 73b3236..739c2bf 100644
> --- a/include/configs/db-88f6820-gp.h
> +++ b/include/configs/db-88f6820-gp.h
> @@ -110,6 +110,17 @@
>   "initrd_high=0x1000\0"
>  
>  /* SPL */
> +/*
> + * Select the boot device here
> + *
> + * Currently supported are:
> + * SPL_BOOT_SPI_NOR_FLASH- Booting via SPI NOR flash
> + * SPL_BOOT_SDIO_MMC_CARD- Booting via SDIO/MMC card (partition 1)
> + */
> +#define SPL_BOOT_SPI_NOR_FLASH   1
> +#define SPL_BOOT_SDIO_MMC_CARD   2
> +#define CONFIG_SPL_BOOT_DEVICE   SPL_BOOT_SPI_NOR_FLASH
> +
>  /* Defines for SPL */
>  #define CONFIG_SPL_FRAMEWORK
>  #define CONFIG_SPL_SIZE  (140 << 10)
> @@ -131,6 +142,7 @@
>  #define CONFIG_SPL_SERIAL_SUPPORT
>  #define CONFIG_SPL_I2C_SUPPORT
>  
> +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
>  /* SPL related SPI defines */
>  #define CONFIG_SPL_SPI_SUPPORT
>  #define CONFIG_SPL_SPI_FLASH_SUPPORT
> @@ -138,6 +150,22 @@
>  #define CONFIG_SPL_SPI_BUS   0
>  #define CONFIG_SPL_SPI_CS0
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS   0x2
> +#define CONFIG_SYS_U_BOOT_OFFS   CONFIG_SYS_SPI_U_BOOT_OFFS
> +#endif
> +
> +#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
> +/* SPL related MMC defines */
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_LIBDISK_SUPPORT
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
> +#define CONFIG_SYS_MMC_U_BOOT_OFFS   (160 << 10)
> +#define CONFIG_SYS_U_BOOT_OFFS   
> CONFIG_SYS_MMC_U_BOOT_OFFS
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR  (CONFIG_SYS_U_BOOT_OFFS 
> / 512)
> +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS   ((512 << 10) / 512) /* 512KiB */
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER0x0018  /* in SDRAM */
> +#endif
> +#endif
>  
>  /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
>  #define CONFIG_SYS_MVEBU_DDR_A38X
> -- 
> 2.4.6
> 
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Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and mx6ul

2015-07-20 Thread Alonso Adrian
Hi Nikolay,

> -Original Message-
> From: Nikolay Dimitrov [mailto:picmas...@mail.bg]
> Sent: Monday, July 20, 2015 3:43 PM
> To: Alonso Lazcano Adrian-B38018
> Cc: u-boot@lists.denx.de; sba...@denx.de; Estevam Fabio-R49496;
> ota...@ossystems.com.br
> Subject: Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and
> mx6ul
> 
> Hi Adrian,
> 
> On 07/16/2015 01:49 AM, Adrian Alonso wrote:
> > * The system counter driver for imx7d abd mx6ul, move
> >this timer driver to imx-common and rename it as syscounter.c
> >
> >For mx6ul and mx7, configurations are used for choose the GPT timer
> >or system counter timer (default).
> >
> >GPT timer:  CONFIG_GPT_TIMER
> >System counter timer:   CONFIG_SYSCOUNTER_TIMER
> >
> >For mx6dqp GPT timer is the default setting.
> >
> > Signed-off-by: Adrian Alonso 
> > Signed-off-by: Ye.Li 
> > ---
> >   arch/arm/imx-common/syscounter.c | 126
> +++
> >   arch/arm/include/asm/imx-common/syscounter.h |  29 ++
> >   include/configs/mx6_common.h |   1 +
> >   3 files changed, 156 insertions(+)
> >   create mode 100644 arch/arm/imx-common/syscounter.c
> >   create mode 100644 arch/arm/include/asm/imx-common/syscounter.h
> >
> > diff --git a/arch/arm/imx-common/syscounter.c
> > b/arch/arm/imx-common/syscounter.c
> > new file mode 100644
> > index 000..f5e5cdc
> > --- /dev/null
> > +++ b/arch/arm/imx-common/syscounter.c
> > @@ -0,0 +1,126 @@
> > +/*
> > + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + *
> > + * The file use ls102xa/timer.c as a reference.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +/*
> > + * This function is intended for SHORT delays only.
> > + * It will overflow at around 10 seconds @ 400MHz,
> > + * or 20 seconds @ 200MHz.
> > + */
> > +unsigned long usec2ticks(unsigned long usec) {
> > +   ulong ticks;
> > +
> > +   if (usec < 1000)
> > +   ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
> > +   else
> > +   ticks = ((usec / 10) * (get_tbclk() / 10));
> > +
> > +   return ticks;
> > +}
> > +
> > +static inline unsigned long long tick_to_time(unsigned long long
> > +tick) {
> > +   unsigned long freq;
> > +
> > +   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
> > +
> > +   tick *= CONFIG_SYS_HZ;
> > +   do_div(tick, freq);
> > +
> > +   return tick;
> > +}
> > +
> > +static inline unsigned long long us_to_tick(unsigned long long usec)
> > +{
> > +   unsigned long freq;
> > +
> > +   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
> > +
> > +   usec = usec * freq  + 99;
> > +   do_div(usec, 100);
> > +
> > +   return usec;
> > +}
> 
> Is it possible to use the same naming convention for usec2ticks(),
> tick_to_time() and us_to_tick() (e.g. choose either "2" or "_to_")?
> Thanks.

 [Adrian] usec2ticks follows the definition of prototype function in header 
file "include/common.h"
the comment in the header /* arch/$(ARCH)/lib/time.c */ implies that each 
platform should provide
that function; For iMX SoC's case usec2ticks is only used in 
drivers/crypto/fsl/jr.c and drivers/i2c/fsl_i2c.c
IMHO we should keep the same naming convention defined in the 
"include/common.h" file.

> 
> > +
> > +int timer_init(void)
> > +{
> > +   struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
> > +   unsigned long val, freq;
> > +
> > +   freq = CONFIG_SC_TIMER_CLK;
> > +   asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
> > +
> > +   writel(freq, &sctr->cntfid0);
> > +
> > +   /* Enable system counter */
> > +   val = readl(&sctr->cntcr);
> > +   val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
> > +   val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
> > +   writel(val, &sctr->cntcr);
> > +
> > +   gd->arch.tbl = 0;
> > +   gd->arch.tbu = 0;
> > +
> > +   return 0;
> > +}
> > +
> > +unsigned long long get_ticks(void)
> > +{
> > +   unsigned long long now;
> > +
> > +   asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
> > +
> > +   gd->arch.tbl = (unsigned long)(now & 0x);
> > +   gd->arch.tbu = (unsigned long)(now >> 32);
> > +
> > +   return now;
> > +}
> > +
> > +ulong get_timer_masked(void)
> > +{
> > +   return tick_to_time(get_ticks());
> > +}
> > +
> > +ulong get_timer(ulong base)
> > +{
> > +   return get_timer_masked() - base;
> > +}
> > +
> > +void __udelay(unsigned long usec)
> > +{
> > +   unsigned long long tmp;
> > +   ulong tmo;
> > +
> > +   tmo = us_to_tick(usec);
> > +   tmp = get_ticks() + tmo;/* get current timestamp */
> > +
> > +   while (get_ticks() < tmp)   /* loop till event */
> > +/*NOP*/;
> > +}
> > +
> > +/*
> > + * This function is derived from PowerPC code (timebase clock frequency).
> > + * On ARM it returns the number of timer ticks per second.
> > + */
> > +ulong 

Re: [U-Boot] checkarmreloc error for AArch64 (using vexpress_aemv8a_defconfig)

2015-07-20 Thread Chou, David J
Hello Albert,

You are right.  it seems the "file' program in my Ubuntu- 12.04.5 LTS system 
doesn't have the aarch64 database of signatures as you said. But If I moved the 
64 bit u-boot I built in my Ubuntu- 12.04.5 LTS system to an Ubuntu14.04.02 LTS 
system, the "file u-boot" shows " u-boot: ELF 64-bit LSB shared object, ARM 
aarch64, version 1 (SYSV), statically  linked, not stripped".

So, can I conclude the way I build aarch64 u-boot by following is correct?
$ make distclean
$ make vexpress_aemv8a_juno_defconfig ARCH=arm  
CROSS_COMPILE=aarch64-linux-gnu- 
$ make all ARCH=arm CROSS_COMPILE=aarch64-linux-gnu-

Thanks.

Best Regards,
David Chou

-Original Message-
From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net] 
Sent: Monday, July 20, 2015 12:24 PM
To: Chou, David J
Cc: u-boot@lists.denx.de; Sood, Ritu
Subject: Re: [U-Boot] checkarmreloc error for AArch64 (using 
vexpress_aemv8a_defconfig)

Hello David J,

On Mon, 20 Jul 2015 04:15:35 +, Chou, David J  
wrote:
> Hello Albert,
> 
> Thanks for your quick response.  The error message disappeared after I 
> switched to use gcc-linaro-aarch64-linux-gnu-4.8-2014.04_linux tool chain 
> from Linaro in either u-boot-2015.07-rc2 branch or latest u-boot-2015.07 
> branch.  
> 
> I have one question: why the following  build generated a statically linked 
> u-boot  as showed by "$ file u-boot" followed, and also it doesn't show "ARM" 
> after " u-boot: ELF 64-bit LSB shared object," : 
> $ make distclean
> $ make vexpress_aemv8a_juno_defconfig ARCH=arm 
> CROSS_COMPILE=aarch64-linux-gnu- $ make all ARCH=arm 
> CROSS_COMPILE=aarch64-linux-gnu- $ file u-boot
> u-boot: ELF 64-bit LSB shared object, version 1 (SYSV), statically 
> linked, not stripped
> 
> But when I built a 32-bit arm u-boot using following command, it generated a  
> dynamically linked u-boot, and  "file  u-boot" shows "ARM" after " u-boot: 
> ELF 32-bit LSB shared object,":
> $ make distclean
> $ make vexpress_ca15_tc2_defconfig ARCH=arm CROSS_COMPILE=arm-eabi- $ 
> make all ARCH=arm CROSS_COMPILE=arm-eabi- $ file u-boot
> u-boot: ELF 32-bit LSB shared object, ARM, version 1 (SYSV), 
> dynamically linked (uses shared libs), not stripped


> Is there anything wrong in my  commands (shown in following" again  to make a 
> 64 bit aarch64 u-boot, what commands you use to generated 64 bits u-boot ?
> $ make distclean
> $ make vexpress_aemv8a_juno_defconfig ARCH=arm 
> CROSS_COMPILE=aarch64-linux-gnu- $ make all ARCH=arm 
> CROSS_COMPILE=aarch64-linux-gnu-
> 
> Is the 64bits u-boot you generated statically linked or dynamically linked 
> when you use "file u-boot" to check it? Does "file u-boot" show "ARM" after " 
> u-boot: ELF 64-bit LSB shared object,"?  Can you show the "file u-boot" 
> result for your 64 bit u-boot?  

Actually, 'file' is simpy wrong.

U-boot is statically linked. U-Boot could not be dynamically linked, since 
U-Boot does not run above an OS that could provide dynamic libraries. After 
all, it is U-Boot's role to get such an OS to boot.

Also, while your 'file' cannot recognize the AARCH64 file, mine can:

u-boot: ELF 64-bit LSB executable, ARM aarch64, version 1 (SYSV), statically 
linked, not stripped

See? "ARM aarch64".

So how come yours does not?

It's all about the database of signatures that the 'file' command uses.
mine has the signature for "ARM aarch64", yours does not.

And both yours and mine wrongly find a "dynamically linked" signature in 32-bit 
ARM u-boot.

If you want to check this, copy the 32-bit u-boot ELF file over to an ARM 
32-bit target running Linux, an do an 'ldd u-boot'. This should show you the 
libraries if u-boot was really dynamic. But it won't (on my OpenRD-Client it 
fails with "unknown exit code" 139). Compare this with, say, 'ldd /bin/bash', 
which lists the five libraries bash needs.

So the thing is, you're trusting 'file', and you should not. :)

> Thanks.

No problem.

> Best Regards,
> David Chou

Amicalement,
--
Albert.
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[U-Boot] [PATCH v2 01/16] ARM: tegra: allow custom usb manufacturer/product/vendor ids/strings

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Allow for optional custom USB gadget manufacturer/product/vendor
IDs/strings to be specified.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
 include/configs/tegra-common-usb-gadget.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/tegra-common-usb-gadget.h 
b/include/configs/tegra-common-usb-gadget.h
index 287460c..645d965 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -15,9 +15,15 @@
 #define CONFIG_CI_UDC
 #define CONFIG_CI_UDC_HAS_HOSTPC
 #define CONFIG_USB_GADGET_DUALSPEED
+#ifndef CONFIG_G_DNL_VENDOR_NUM
 #define CONFIG_G_DNL_VENDOR_NUM 0x0955
+#endif
+#ifndef CONFIG_G_DNL_PRODUCT_NUM
 #define CONFIG_G_DNL_PRODUCT_NUM 0x701A
+#endif
+#ifndef CONFIG_G_DNL_MANUFACTURER
 #define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
+#endif
 #define CONFIG_USBDOWNLOAD_GADGET
 /* USB mass storage protocol */
 #define CONFIG_USB_GADGET_MASS_STORAGE
-- 
2.4.3

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[U-Boot] [PATCH v2 00/16] assortment of tegra fixes/enhancements

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

This patch set is an assortment of tegra fixes/enhancements distilled
straight from our downstream integration work.

Changes in v2:
- dropped Colibri T20 specific ONFI detection enablement patch (formerly
  9) as I noticed this already being done globally as part of
  tegra20-common.h
- enable UBI/UBIFS support (11)
- limit TFTP block size (13) on Colibri T20 to 1536 due to issues
  observed otherwise
- drop unrelated clean-up in (3) to be done as part of a separate
  patch (14)
- new patch (15) fixing nRESET_OUT
- new patch (16) fixing USB DM regression on Apalis/Colibri T30

Marcel Ziswiler (15):
  ARM: tegra: allow custom usb manufacturer/product/vendor ids/strings
  ARM: tegra: allow reading recovery mode boot type
  apalis/colibri_t20/t30: integrate recovery mode detection
  colibri_t20: fix device-tree compatible node
  colibri_t20: add lcd display support
  colibri_t20: add i2c support
  colibri_t20: disable PMIC sleep mode on low supply voltage
  tegra: nand: fix read_byte required for proper onfi detection
  mtd/nand/tegra: alignment workaround
  colibri_t20: enable mtdparts support
  colibri_t20: enable ubi/ubifs support
  apalis/colibri_t20/t30: enable raw initrd support
  apalis/colibri_t20/30: clean-up
  colibri_t20: fix reset out pin
  apalis/colibri_t30: fix usb dm regression

Max Krummenacher (1):
  apalis/colibri_t20/t30: increase tftp blocksize

 arch/arm/dts/tegra20-colibri.dts  |  63 ++-
 arch/arm/dts/tegra30-apalis.dts   |   2 +-
 arch/arm/dts/tegra30-colibri.dts  |   4 +-
 arch/arm/include/asm/arch-tegra/tegra.h   |   2 +
 board/toradex/apalis_t30/apalis_t30.c |  15 +++-
 board/toradex/colibri_t20/colibri_t20.c   |  68 +
 board/toradex/colibri_t30/colibri_t30.c   |  18 -
 drivers/mtd/nand/tegra_nand.c | 122 ++
 include/configs/apalis_t30.h  |  16 +++-
 include/configs/colibri_t20.h |  56 --
 include/configs/colibri_t30.h |  16 +++-
 include/configs/tegra-common-usb-gadget.h |   6 ++
 12 files changed, 287 insertions(+), 101 deletions(-)

-- 
2.4.3

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[U-Boot] [PATCH v2 05/16] colibri_t20: add lcd display support

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Add LCD display support defaulting to VESA VGA resolution. Different
resolutions configurable via device tree.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
Changes in v2: fixed PWM instance

 arch/arm/dts/tegra20-colibri.dts| 29 +
 board/toradex/colibri_t20/colibri_t20.c | 18 ++
 include/configs/colibri_t20.h   | 10 ++
 3 files changed, 57 insertions(+)

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index 257ca27..bf14c6b 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -17,6 +17,17 @@
sdhci0 = "/sdhci@c8000600";
};
 
+   host1x {
+   status = "okay";
+   dc@5420 {
+   status = "okay";
+   rgb {
+   status = "okay";
+   nvidia,panel = <&lcd_panel>;
+   };
+   };
+   };
+
usb@c500 {
dr_mode = "otg";
};
@@ -46,4 +57,22 @@
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
+
+   lcd_panel: panel {
+   clock = <25175000>;
+   xres = <640>;
+   yres = <480>;
+   left-margin = <48>; /* horizontal back porch */
+   right-margin = <16>;/* horizontal front porch */
+   hsync-len = <96>;
+   lower-margin = <11>;/* vertical front porch */
+   upper-margin = <31>;/* vertical back porch */
+   vsync-len = <2>;
+   hsync-active-high;
+   vsync-active-high;
+   nvidia,bits-per-pixel = <16>;
+   nvidia,pwm = <&pwm 0 0>;
+   nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) 
GPIO_ACTIVE_HIGH>;
+   nvidia,panel-timings = <0 0 0 0>;
+   };
 };
diff --git a/board/toradex/colibri_t20/colibri_t20.c 
b/board/toradex/colibri_t20/colibri_t20.c
index 7210a8a..81d344c 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -75,3 +75,21 @@ void pin_mux_usb(void)
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
 }
 #endif
+
+#ifdef CONFIG_VIDEO_TEGRA
+/*
+ * Routine: pin_mux_display
+ * Description: setup the pin muxes/tristate values for the LCD interface)
+ */
+void pin_mux_display(void)
+{
+   /*
+* Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
+* device-tree
+*/
+   pinmux_tristate_disable(PMUX_PINGRP_DTA);
+
+   pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+   pinmux_tristate_disable(PMUX_PINGRP_SDC);
+}
+#endif
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index d80d352..82a887b 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -45,6 +45,16 @@
 /* General networking support */
 #define CONFIG_CMD_DHCP
 
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPPLCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES10
+#define CONFIG_CMD_BMP
+#define CONFIG_LCD_LOGO
+
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
-- 
2.4.3

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[U-Boot] [PATCH v2 08/16] tegra: nand: fix read_byte required for proper onfi detection

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command now required for proper ONFI detection.

This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late.

While at it also disable subpage writes.

Signed-off-by: Marcel Ziswiler 
---
 drivers/mtd/nand/tegra_nand.c | 39 +--
 1 file changed, 9 insertions(+), 30 deletions(-)

diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index b660f3b..9c90634 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -86,16 +86,6 @@ struct fdt_nand {
 
 struct nand_drv {
struct nand_ctlr *reg;
-
-   /*
-   * When running in PIO mode to get READ ID bytes from register
-   * RESP_0, we need this variable as an index to know which byte in
-   * register RESP_0 should be read.
-   * Because common code in nand_base.c invokes read_byte function two
-   * times for NAND_CMD_READID.
-   * And our controller returns 4 bytes at once in register RESP_0.
-   */
-   int pio_byte_index;
struct fdt_nand config;
 };
 
@@ -181,25 +171,16 @@ static int nand_waitfor_cmd_completion(struct nand_ctlr 
*reg)
 static uint8_t read_byte(struct mtd_info *mtd)
 {
struct nand_chip *chip = mtd->priv;
-   u32 dword_read;
struct nand_drv *info;
 
info = (struct nand_drv *)chip->priv;
 
-   /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
-   if (info->pio_byte_index > 3) {
-   info->pio_byte_index = 0;
-   writel(CMD_GO | CMD_PIO
-   | CMD_RX | CMD_CE0,
-   &info->reg->command);
-   if (!nand_waitfor_cmd_completion(info->reg))
-   printf("Command timeout\n");
-   }
+   writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
+  &info->reg->command);
+   if (!nand_waitfor_cmd_completion(info->reg))
+   printf("Command timeout\n");
 
-   dword_read = readl(&info->reg->resp);
-   dword_read = dword_read >> (8 * info->pio_byte_index);
-   info->pio_byte_index++;
-   return (uint8_t)dword_read;
+   return (uint8_t)readl(&info->reg->resp);
 }
 
 /**
@@ -314,6 +295,9 @@ static void nand_command(struct mtd_info *mtd, unsigned int 
command,
if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
column >>= 1;
 
+   /* Disable subpage writes as we do not provide ecc->hwctl */
+   chip->options |= NAND_NO_SUBPAGE_WRITE;
+
nand_clear_interrupt_status(info->reg);
 
/* Stop DMA engine, clear DMA completion status */
@@ -330,12 +314,8 @@ static void nand_command(struct mtd_info *mtd, unsigned 
int command,
case NAND_CMD_READID:
writel(NAND_CMD_READID, &info->reg->cmd_reg1);
writel(column & 0xFF, &info->reg->addr_reg1);
-   writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
-   | CMD_RX |
-   ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
-   | CMD_CE0,
-   &info->reg->command);
+   writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
+  &info->reg->command);
-   info->pio_byte_index = 0;
break;
case NAND_CMD_PARAM:
writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
@@ -376,7 +356,6 @@ static void nand_command(struct mtd_info *mtd, unsigned int 
command,
| ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
| CMD_CE0,
&info->reg->command);
-   info->pio_byte_index = 0;
break;
case NAND_CMD_RESET:
writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
-- 
2.4.3

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[U-Boot] [PATCH v2 09/16] mtd/nand/tegra: alignment workaround

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Integrate cache alignment bounce buffer to workaround issues as follows:

Loading file '/boot/zImage' to addr 0x0100 with size 4499152 (0x0044a6d0)...
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Done
Kernel image @ 0x100 [ 0x00 - 0x44a6d0 ]

Starting kernel ...

undefined instruction
pc : [<005ff03c>]  lr : [<800c>]
sp : 0144b6e8  ip : 01000188 fp : 0144a6c8
r10:   r9 : 411fc090 r8 : 0100
r7 : 0cfb  r6 : 0144a6d0 r5 :   r4 : 8000
r3 : 000c  r2 : 0100 r1 : 0cfb  r0 : 
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

Signed-off-by: Marcel Ziswiler 
---
Changes in v2:
Migrated to using generic bounce buffer implementation as suggested by Simon.

 drivers/mtd/nand/tegra_nand.c | 83 +--
 1 file changed, 32 insertions(+), 51 deletions(-)

diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 9f90683..02d8aed 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "tegra_nand.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -93,35 +94,6 @@ static struct nand_drv nand_ctrl;
 static struct mtd_info *our_mtd;
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
-#ifdef CONFIG_SYS_DCACHE_OFF
-static inline void dma_prepare(void *start, unsigned long length,
-  int is_writing)
-{
-}
-#else
-/**
- * Prepare for a DMA transaction
- *
- * For a write we flush out our data. For a read we invalidate, since we
- * need to do this before we read from the buffer after the DMA has
- * completed, so may as well do it now.
- *
- * @param startStart address for DMA buffer (should be 
cache-aligned)
- * @param length   Length of DMA buffer in bytes
- * @param is_writing   0 if reading, non-zero if writing
- */
-static void dma_prepare(void *start, unsigned long length, int is_writing)
-{
-   unsigned long addr = (unsigned long)start;
-
-   length = ALIGN(length, ARCH_DMA_MINALIGN);
-   if (is_writing)
-   flush_dcache_range(addr, addr + length);
-   else
-   invalidate_dcache_range(addr, addr + length);
-}
-#endif
-
 /**
  * Wait for command completion
  *
@@ -534,6 +506,8 @@ static int nand_rw_page(struct mtd_info *mtd, struct 
nand_chip *chip,
char *tag_ptr;
struct nand_drv *info;
struct fdt_nand *config;
+   unsigned int bbflags;
+   struct bounce_buffer bbstate, bbstate_oob;
 
if ((uintptr_t)buf & 0x03) {
printf("buf %p has to be 4-byte aligned\n", buf);
@@ -550,21 +524,21 @@ static int nand_rw_page(struct mtd_info *mtd, struct 
nand_chip *chip,
 
stop_command(info->reg);
 
+   if (is_writing)
+   bbflags = GEN_BB_READ;
+   else
+   bbflags = GEN_BB_WRITE;
+
+   bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
+   bbflags);
writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
-   writel(virt_to_phys(buf), &info->reg->data_block_ptr);
+   writel((u32)bbstate.bounce_buffer, &info->reg->data_block_ptr);
 
+   /* Set ECC selection, configure ECC settings */
if (with_ecc) {
-   writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
if (is_writing)
memcpy(tag_ptr, chip->oob_poi + free->offset,
-   chip->ecc.layout->oobavail +
-   TAG_ECC_BYTES);
-   } else {
-   writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
-   }
-
-   /* Set ECC selection, configure ECC settings */
-   if (with_ecc) {
+  chip->ecc.layout->oobavail + TAG_ECC_BYTES);
tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
reg_val |= (CFG_SKIP_SPARE_SEL_4
| CFG_SKIP_SPARE_ENABLE
@@ -577,7 +551,8 @@ static int nand_rw_page(struct mtd_info *mtd, struct 
nand_chip *chip,
 
if (!is_writing)
tag_size += SKIPPED_SPARE_BYTES;
-   dma_prepare(tag_ptr, tag_size, is_writing);
+   bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
+   bbflags);
} else {
tag_size = mtd->oobsize;
reg_val |= (CFG_SKIP_SPARE_DISABLE
@@ -585,14 +560,12 @@ static int nand_rw_page(struct mtd_info *mtd, struct 
nand_chip *chip,
| CFG_ECC_EN_TAG_DISABLE
| CFG_HW_ECC_DISABLE
| (tag_size - 1));
-   dma_prepare(chip->oob_poi, tag_size, is_writing);
+   bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi

[U-Boot] [PATCH v2 07/16] colibri_t20: disable PMIC sleep mode on low supply voltage

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

The Colibri T20's PMIC enters a sleep mode on low supply voltage < 3.0V
±2.5% (2.92...3.08V). Rising the main supply voltage again does not
bring it back to regular operation. Not even a full reset does bring
the module back. A full power cycle was required to reboot the system.
A long positive pulse on the PMICs resume pin also reboots the system
but this pin is only accessible as a test point on the module.

This patch configures the PMIC through I2C to not enter this sleep mode
plus force it to normal state upon sleep request exit should this ever
happen.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
 board/toradex/colibri_t20/colibri_t20.c | 35 +
 1 file changed, 35 insertions(+)

diff --git a/board/toradex/colibri_t20/colibri_t20.c 
b/board/toradex/colibri_t20/colibri_t20.c
index 81d344c..42b293d 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -13,9 +13,44 @@
 #include 
 #include 
 #include 
+#include 
+
+#define PMU_I2C_ADDRESS0x34
+#define MAX_I2C_RETRY  3
+#define PMU_SUPPLYENE  0x14
+#define PMU_SUPPLYENE_SYSINEN  (1<<5)
+#define PMU_SUPPLYENE_EXITSLREQ(1<<1)
 
 int arch_misc_init(void)
 {
+   /* Disable PMIC sleep mode on low supply voltage */
+   struct udevice *dev;
+   u8 addr, data[1];
+   int err;
+
+   err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
+   if (err) {
+   debug("%s: Cannot find PMIC I2C chip\n", __func__);
+   return err;
+   }
+
+   addr = PMU_SUPPLYENE;
+
+   err = dm_i2c_read(dev, addr, data, 1);
+   if (err) {
+   debug("failed to get PMU_SUPPLYENE\n");
+   return err;
+   }
+
+   data[0] &= ~PMU_SUPPLYENE_SYSINEN;
+   data[0] |= PMU_SUPPLYENE_EXITSLREQ;
+
+   err = dm_i2c_write(dev, addr, data, 1);
+   if (err) {
+   debug("failed to set PMU_SUPPLYENE\n");
+   return err;
+   }
+
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
NVBOOTTYPE_RECOVERY)
printf("USB recovery mode\n");
-- 
2.4.3

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[U-Boot] [PATCH v2 11/16] colibri_t20: enable ubi/ubifs support

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Now as all is in place actually enable UBI/UBIFS support to be able to
boot the Linux kernel and root file system from NAND.

Signed-off-by: Marcel Ziswiler 
---
 include/configs/colibri_t20.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index a5f0a35..72a328f 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -81,6 +81,14 @@
 #undef  CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
 #define CONFIG_ENV_SIZE(SZ_64K)
 
+/* UBI */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS   /* increases size by almost 60 KB */
+#define CONFIG_LZO
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_RBTREE
+
 /* Debug commands */
 #define CONFIG_CMD_CACHE
 
-- 
2.4.3

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[U-Boot] [PATCH v2 03/16] apalis/colibri_t20/t30: integrate recovery mode detection

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Allow detecting whether or not U-Boot was launched through the
recovery mode of the resp. NVIDIA SoC.

Make use of a board specific arch_misc_init() and enable the same via
CONFIG_ARCH_MISC_INIT configuration option.

Signed-off-by: Marcel Ziswiler 
---
Changes in v2:
Drop unrelated clean-up to be done as part of a separate patch.

 board/toradex/apalis_t30/apalis_t30.c   | 12 
 board/toradex/colibri_t20/colibri_t20.c | 12 
 board/toradex/colibri_t30/colibri_t30.c | 12 
 include/configs/apalis_t30.h|  2 ++
 include/configs/colibri_t20.h   |  2 ++
 include/configs/colibri_t30.h   |  2 ++
 6 files changed, 42 insertions(+)

diff --git a/board/toradex/apalis_t30/apalis_t30.c 
b/board/toradex/apalis_t30/apalis_t30.c
index 6244214..b7a2219 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -9,7 +9,10 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
+#include 
 #include 
 #include 
 
@@ -18,6 +21,15 @@
 #define PMU_I2C_ADDRESS0x2D
 #define MAX_I2C_RETRY  3
 
+int arch_misc_init(void)
+{
+   if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+   NVBOOTTYPE_RECOVERY)
+   printf("USB recovery mode\n");
+
+   return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_t20/colibri_t20.c 
b/board/toradex/colibri_t20/colibri_t20.c
index 8ae9ccf..7210a8a 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -8,8 +8,20 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
+#include 
+
+int arch_misc_init(void)
+{
+   if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+   NVBOOTTYPE_RECOVERY)
+   printf("USB recovery mode\n");
+
+   return 0;
+}
 
 #ifdef CONFIG_TEGRA_MMC
 /*
diff --git a/board/toradex/colibri_t30/colibri_t30.c 
b/board/toradex/colibri_t30/colibri_t30.c
index f4bc7d8..7ca79eb 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -8,10 +8,22 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include "pinmux-config-colibri_t30.h"
 #include 
 #include 
 
+int arch_misc_init(void)
+{
+   if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+   NVBOOTTYPE_RECOVERY)
+   printf("USB recovery mode\n");
+
+   return 0;
+}
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index aba9ba6..283b002 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -11,6 +11,8 @@
 
 #include "tegra30-common.h"
 
+#define CONFIG_ARCH_MISC_INIT
+
 /* High-level configuration options */
 #define V_PROMPT   "Apalis T30 # "
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Apalis T30"
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 8228e42..d80d352 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -9,6 +9,8 @@
 
 #include "tegra20-common.h"
 
+#define CONFIG_ARCH_MISC_INIT
+
 /* High-level configuration options */
 #define V_PROMPT   "Colibri T20 # "
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T20"
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 4655668..249b5c0 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -11,6 +11,8 @@
 
 #include "tegra30-common.h"
 
+#define CONFIG_ARCH_MISC_INIT
+
 /* High-level configuration options */
 #define V_PROMPT   "Colibri T30 # "
 #define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T30"
-- 
2.4.3

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[U-Boot] [PATCH v2 06/16] colibri_t20: add i2c support

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Add I2C support in order to subsequently allow disabling the PMIC sleep
mode on low supply voltage.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/tegra20-colibri.dts | 28 
 include/configs/colibri_t20.h|  4 
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index bf14c6b..8eaac4f 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -11,6 +11,9 @@
};
 
aliases {
+   i2c0 = "/i2c@7000d000";
+   i2c1 = "/i2c@7000c000";
+   i2c2 = "/i2c@7000c400";
usb0 = "/usb@c5008000";
usb1 = "/usb@c500";
usb2 = "/usb@c5004000";
@@ -52,6 +55,31 @@
};
};
 
+   /*
+* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+* board)
+*/
+   i2c@7000c000 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
+   /* GEN2_I2C: unused */
+
+   /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
+   i2c@7000c400 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
+   /*
+* PWR_I2C: power I2C to PMIC and temperature sensor
+*/
+   i2c@7000d000 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 82a887b..24880c3 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -23,6 +23,10 @@
 
 #define CONFIG_MACH_TYPE   MACH_TYPE_COLIBRI_T20
 
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_CMD_I2C
+
 /* SD/MMC support */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
-- 
2.4.3

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[U-Boot] [PATCH v2 14/16] apalis/colibri_t20/30: clean-up

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Various clean-ups either in comments, order or spacing without any
functional impact:
- Add some comments in the device trees resp. reorder some parameters
  for consistency across all our modules.
- Sort some include files alphabetically (while leaving common.h on
  top of course).
- Streamline some comments in the configuration files and fix the
  spacing from using spaces to tabs.

Signed-off-by: Marcel Ziswiler 
---
 arch/arm/dts/tegra20-colibri.dts|  4 +++-
 arch/arm/dts/tegra30-colibri.dts|  2 +-
 board/toradex/apalis_t30/apalis_t30.c   |  3 ++-
 board/toradex/colibri_t30/colibri_t30.c |  6 +++---
 include/configs/apalis_t30.h|  8 +---
 include/configs/colibri_t20.h   | 12 +++-
 include/configs/colibri_t30.h   |  8 +---
 7 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index 8eaac4f..f058d45 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -36,11 +36,13 @@
};
 
usb@c5004000 {
+   /* VBUS_LAN */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 
GPIO_ACTIVE_HIGH>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
 
usb@c5008000 {
+   /* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
 
@@ -82,8 +84,8 @@
 
sdhci@c8000600 {
status = "okay";
-   cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
bus-width = <4>;
+   cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
 
lcd_panel: panel {
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 36533dc..1da7260 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -82,9 +82,9 @@
/* EHCI instance 1: USB2_DP/N -> AX88772B */
usb@7d004000 {
status = "okay";
-   phy_type = "utmi";
/* VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
+   phy_type = "utmi";
};
 
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
diff --git a/board/toradex/apalis_t30/apalis_t30.c 
b/board/toradex/apalis_t30/apalis_t30.c
index b7a2219..879006f 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -6,13 +6,13 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -59,6 +59,7 @@ int tegra_pcie_board_init(void)
debug("%s: Cannot find PMIC I2C chip\n", __func__);
return err;
}
+
/* TPS659110: VDD2_OP_REG = 1.05V */
data[0] = 0x27;
addr = 0x25;
diff --git a/board/toradex/colibri_t30/colibri_t30.c 
b/board/toradex/colibri_t30/colibri_t30.c
index 7ca79eb..44b5beb 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -6,14 +6,14 @@
  */
 
 #include 
-#include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
-#include "pinmux-config-colibri_t30.h"
 #include 
-#include 
+#include "pinmux-config-colibri_t30.h"
 
 int arch_misc_init(void)
 {
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 8f7f833..7fc4bd9 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2014-2015 Marcel Ziswiler
  *
+ * Configuration settings for the Toradex Apalis T30 modules.
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -28,7 +30,7 @@
 #define CONFIG_SYS_I2C_TEGRA
 #define CONFIG_CMD_I2C
 
-/* SD/MMC */
+/* SD/MMC support */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_TEGRA_MMC
@@ -40,10 +42,10 @@
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_SYS_MMC_ENV_PART2
 
-/* USB Host support */
+/* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT3
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 65c4bee..f068cfa 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -1,6 +1,8 @@
 /*
  * Copyright (C) 2012 Lucas Stach
  *
+ * Configuration settings for the Toradex Colibri T20 modules.
+ *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
@@ -38,7 +40,7 @@
 #define CONFIG_USB_EHCI_TEGRA
 #define CONFIG_USB_ULPI
 #define CONFIG_USB_ULPI_VIEWPORT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT3
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 
@@ -65,7 +67,7 @@
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
-#defin

[U-Boot] [PATCH v2 16/16] apalis/colibri_t30: fix usb dm regression

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Unfortunately currently both Apalis T30 as well as Colibri T30 crash
upon starting USB host support. This is due to the following patch not
having taken into account that our T30 device trees were defaulting to
peripheral only mode instead of otg:

commit ddb9a502d18008e845d5a8fa03ec48630fa77fb7
dm: usb: tegra: Move most of init/uninit into a function

This patch fixes this by defaulting to otg now.

Signed-off-by: Marcel Ziswiler 
---
 arch/arm/dts/tegra30-apalis.dts  | 2 +-
 arch/arm/dts/tegra30-colibri.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 13ab42b..3e0545c 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -267,7 +267,7 @@
/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
usb@7d00 {
status = "okay";
-   dr_mode = "peripheral";
+   dr_mode = "otg";
/* USBO1_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 1da7260..487e1f6 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -76,7 +76,7 @@
/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
usb@7d00 {
status = "okay";
-   dr_mode = "peripheral";
+   dr_mode = "otg";
};
 
/* EHCI instance 1: USB2_DP/N -> AX88772B */
-- 
2.4.3

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[U-Boot] [PATCH v2 04/16] colibri_t20: fix device-tree compatible node

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Use toradex,colibri_t20 as the device-tree compatible node value rather
than toradex,t20 in accordance to our Apalis/Colibri T30 products.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/tegra20-colibri.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index 3131b92..257ca27 100644
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -4,7 +4,7 @@
 
 / {
model = "Toradex Colibri T20";
-   compatible = "toradex,t20", "nvidia,tegra20";
+   compatible = "toradex,colibri_t20", "nvidia,tegra20";
 
chosen {
stdout-path = &uarta;
-- 
2.4.3

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[U-Boot] [PATCH v2 12/16] apalis/colibri_t20/t30: enable raw initrd support

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Enable optional raw initrd support to allow boot using an initrd.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
 include/configs/apalis_t30.h  | 3 +++
 include/configs/colibri_t20.h | 3 +++
 include/configs/colibri_t30.h | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 283b002..898ccdf 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -79,6 +79,9 @@
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS 32
 
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 72a328f..4c45ef8 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -113,6 +113,9 @@
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS 32
 
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 249b5c0..3ef4778 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -72,6 +72,9 @@
 #undef CONFIG_SYS_MAXARGS
 #define CONFIG_SYS_MAXARGS 32
 
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
-- 
2.4.3

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[U-Boot] [PATCH v2 13/16] apalis/colibri_t20/t30: increase tftp blocksize

2015-07-20 Thread Marcel Ziswiler
From: Max Krummenacher 

Enable CONFIG_IP_DEFRAG and set CONFIG_TFTP_BLOCKSIZE to 16384.
This increases the tftp download speed considerably.

While at it enable CONFIG_TFTP_TSIZE which limits the progress bar to
fifty '#' independent of the downloaded file size.

Signed-off-by: Max Krummenacher 
Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
Changes in v2:
Only limit it to 1536 bytes on Colibri T20 to avoid issues observed
otherwise.

 include/configs/apalis_t30.h  | 3 +++
 include/configs/colibri_t20.h | 3 +++
 include/configs/colibri_t30.h | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index 898ccdf..8f7f833 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -60,6 +60,9 @@
 
 /* General networking support */
 #define CONFIG_CMD_DHCP
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE  16384
+#define CONFIG_TFTP_TSIZE
 
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 4c45ef8..65c4bee 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -48,6 +48,9 @@
 
 /* General networking support */
 #define CONFIG_CMD_DHCP
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE  1536
+#define CONFIG_TFTP_TSIZE
 
 /* LCD support */
 #define CONFIG_LCD
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 3ef4778..f91c2e2 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -53,6 +53,9 @@
 
 /* General networking support */
 #define CONFIG_CMD_DHCP
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE  16384
+#define CONFIG_TFTP_TSIZE
 
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE
-- 
2.4.3

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[U-Boot] [PATCH v2 10/16] colibri_t20: enable mtdparts support

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Enable mtdparts aka dynamic MTD partition support.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
Changes in v2:
Actually set mtdparts environment variable as part of the board extra ones.

 include/configs/colibri_t20.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 24880c3..a5f0a35 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -64,6 +64,17 @@
 #define CONFIG_TEGRA_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE 1
 
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS/* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE  /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=tegra_nand"
+#define MTDPARTS_DEFAULT   "mtdparts=tegra_nand:"  \
+   "2m(u-boot)ro," \
+   "1m(u-boot-env),"   \
+   "1m(cfgblock)ro,"   \
+   "-(ubi)"
+
 /* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway 
*/
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET  (SZ_2M)
@@ -76,6 +87,9 @@
 /* Miscellaneous commands */
 #define CONFIG_FAT_WRITE
 
+#define BOARD_EXTRA_ENV_SETTINGS \
+   "mtdparts=" MTDPARTS_DEFAULT "\0"
+
 /* Increase console I/O buffer size */
 #undef CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_CBSIZE  1024
-- 
2.4.3

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[U-Boot] [PATCH v2 02/16] ARM: tegra: allow reading recovery mode boot type

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Add defines to allow reading recovery mode (RCM) boot type from the boot
information table (BIT) written by the boot ROM (BR) to the IRAM.

Signed-off-by: Marcel Ziswiler 
Reviewed-by: Simon Glass 
---
Changes in v2: Reword commit mesage as per Simon's suggestion.

 arch/arm/include/asm/arch-tegra/tegra.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-tegra/tegra.h 
b/arch/arm/include/asm/arch-tegra/tegra.h
index d63af0e..9ff0831 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -56,6 +56,8 @@ struct timerus {
 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
 #define NV_WB_RUN_ADDRESS  0x4002
 
+#define NVBOOTTYPE_RECOVERY2   /* BR entered RCM */
+#define NVBOOTINFOTABLE_BOOTTYPE 0xC   /* Boot type in BIT in IRAM */
 #define NVBOOTINFOTABLE_BCTSIZE0x38/* BCT size in BIT in IRAM */
 #define NVBOOTINFOTABLE_BCTPTR 0x3C/* BCT pointer in BIT in IRAM */
 
-- 
2.4.3

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[U-Boot] [PATCH v2 15/16] colibri_t20: fix reset out pin

2015-07-20 Thread Marcel Ziswiler
From: Marcel Ziswiler 

Make sure SODIMM pin 87 nRESET_OUT is released properly by explicitly
setting its pin mux function to GMI. This solves some issues with e.g.
USB not being fully operational on carrier boards with USB hubs
connected to reset if U-Boot got loaded via recovery mode aka rcm.

Signed-off-by: Marcel Ziswiler 
---
 board/toradex/colibri_t20/colibri_t20.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/toradex/colibri_t20/colibri_t20.c 
b/board/toradex/colibri_t20/colibri_t20.c
index 42b293d..83e1ddc 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -51,6 +51,9 @@ int arch_misc_init(void)
return err;
}
 
+   /* make sure SODIMM pin 87 nRESET_OUT is released properly */
+   pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
+
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
NVBOOTTYPE_RECOVERY)
printf("USB recovery mode\n");
-- 
2.4.3

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Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and mx6ul

2015-07-20 Thread Nikolay Dimitrov

Hi Adrian,

On 07/21/2015 01:11 AM, Alonso Adrian wrote:

Hi Nikolay,


-Original Message-
From: Nikolay Dimitrov [mailto:picmas...@mail.bg]
Sent: Monday, July 20, 2015 3:43 PM
To: Alonso Lazcano Adrian-B38018
Cc: u-boot@lists.denx.de; sba...@denx.de; Estevam Fabio-R49496;
ota...@ossystems.com.br
Subject: Re: [U-Boot] [PATCH 09/11] imx: system counter driver for imx7d and
mx6ul

Hi Adrian,

On 07/16/2015 01:49 AM, Adrian Alonso wrote:

* The system counter driver for imx7d abd mx6ul, move
this timer driver to imx-common and rename it as syscounter.c

For mx6ul and mx7, configurations are used for choose the GPT timer
or system counter timer (default).

GPT timer:  CONFIG_GPT_TIMER
System counter timer:   CONFIG_SYSCOUNTER_TIMER

For mx6dqp GPT timer is the default setting.

Signed-off-by: Adrian Alonso 
Signed-off-by: Ye.Li 
---
   arch/arm/imx-common/syscounter.c | 126

+++

   arch/arm/include/asm/imx-common/syscounter.h |  29 ++
   include/configs/mx6_common.h |   1 +
   3 files changed, 156 insertions(+)
   create mode 100644 arch/arm/imx-common/syscounter.c
   create mode 100644 arch/arm/include/asm/imx-common/syscounter.h

diff --git a/arch/arm/imx-common/syscounter.c
b/arch/arm/imx-common/syscounter.c
new file mode 100644
index 000..f5e5cdc
--- /dev/null
+++ b/arch/arm/imx-common/syscounter.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec) {
+   ulong ticks;
+
+   if (usec < 1000)
+   ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+   else
+   ticks = ((usec / 10) * (get_tbclk() / 10));
+
+   return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long
+tick) {
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   tick *= CONFIG_SYS_HZ;
+   do_div(tick, freq);
+
+   return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   usec = usec * freq  + 99;
+   do_div(usec, 100);
+
+   return usec;
+}


Is it possible to use the same naming convention for usec2ticks(),
tick_to_time() and us_to_tick() (e.g. choose either "2" or "_to_")?
Thanks.


  [Adrian] usec2ticks follows the definition of prototype function in header file 
"include/common.h"
the comment in the header /* arch/$(ARCH)/lib/time.c */ implies that each 
platform should provide
that function; For iMX SoC's case usec2ticks is only used in 
drivers/crypto/fsl/jr.c and drivers/i2c/fsl_i2c.c
IMHO we should keep the same naming convention defined in the 
"include/common.h" file.


I see. Thanks for explaining!






+
+int timer_init(void)
+{
+   struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+   unsigned long val, freq;
+
+   freq = CONFIG_SC_TIMER_CLK;
+   asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+   writel(freq, &sctr->cntfid0);
+
+   /* Enable system counter */
+   val = readl(&sctr->cntcr);
+   val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+   val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+   writel(val, &sctr->cntcr);
+
+   gd->arch.tbl = 0;
+   gd->arch.tbu = 0;
+
+   return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+   unsigned long long now;
+
+   asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+   gd->arch.tbl = (unsigned long)(now & 0x);
+   gd->arch.tbu = (unsigned long)(now >> 32);
+
+   return now;
+}
+
+ulong get_timer_masked(void)
+{
+   return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+   return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+   unsigned long long tmp;
+   ulong tmo;
+
+   tmo = us_to_tick(usec);
+   tmp = get_ticks() + tmo;/* get current timestamp */
+
+   while (get_ticks() < tmp)/* loop till event */
+/*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   return freq;
+}
diff --git a/arch/arm/include/asm/imx-common/syscounter.h
b/arch/arm/include/asm/imx-common/syscounter.h
new file mode 100644
index 000..ddb412e
--- /dev/null
+++ b/arch/arm/include/asm/imx-commo

[U-Boot] [PATCH][v3] imx: imximage: add new CHECK/CLR BIT command

2015-07-20 Thread Adrian Alonso
* Extend imximage DCD version 2 to support DCD commands
  CMD_WRITE_CLR_BIT 4 [address] [mask bit] means:
while ((*address & ~mask) != 0);
  CMD_CHECK_BITS_SET 4 [address] [mask bit] means:
while ((*address & mask) != mask);
  CMD_CHECK_BITS_CLR 4 [address] [mask bit] means:
*address = *address & ~mask;
* Add set_dcd_param_v2 helper function to set DCD
  command parameters

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan 
---
Changes for V2
- Add set_dcd_param_v2 helper function to set DCD command tag
  and parameters
Changes for V3
- Remove void set_dcd_param_v1, set_dcd_param to NULL for IMXIMAGE_V1
- Fix comments related to Check data command length

 tools/imximage.c | 95 
 tools/imximage.h | 25 ++-
 2 files changed, 93 insertions(+), 27 deletions(-)

diff --git a/tools/imximage.c b/tools/imximage.c
index 6f469ae..909efab 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -21,7 +21,10 @@
 static table_entry_t imximage_cmds[] = {
{CMD_BOOT_FROM, "BOOT_FROM","boot command",   },
{CMD_BOOT_OFFSET,   "BOOT_OFFSET",  "Boot offset",},
-   {CMD_DATA,  "DATA", "Reg Write Data", },
+   {CMD_WRITE_DATA,"DATA", "Reg Write Data", },
+   {CMD_WRITE_CLR_BIT, "CLR_BIT",  "Reg clear bit",  },
+   {CMD_CHECK_BITS_SET,"CHECK_BITS_SET",   "Reg Check bits set", },
+   {CMD_CHECK_BITS_CLR,"CHECK_BITS_CLR",   "Reg Check bits clr", },
{CMD_CSF,   "CSF",   "Command Sequence File", },
{CMD_IMAGE_VERSION, "IMAGE_VERSION","image version",  },
{-1,"", "",   },
@@ -62,7 +65,7 @@ static table_entry_t imximage_boot_loadsize[] = {
  */
 static table_entry_t imximage_versions[] = {
{IMXIMAGE_V1,   "", " (i.MX25/35/51 compatible)", },
-   {IMXIMAGE_V2,   "", " (i.MX53/6 compatible)", },
+   {IMXIMAGE_V2,   "", " (i.MX53/6/7 compatible)",   },
{-1,"", " (Invalid)", },
 };
 
@@ -79,6 +82,7 @@ static uint32_t imximage_csf_size = UNDEFINED;
 static uint32_t imximage_init_loadsize;
 
 static set_dcd_val_t set_dcd_val;
+static set_dcd_param_t set_dcd_param;
 static set_dcd_rst_t set_dcd_rst;
 static set_imx_hdr_t set_imx_hdr;
 static uint32_t max_dcd_entries;
@@ -156,6 +160,43 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, char 
*name, int lineno,
}
 }
 
+static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
+   int32_t cmd)
+{
+   dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+
+   switch (cmd) {
+   case CMD_WRITE_DATA:
+   dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+   dcd_v2->write_dcd_command.length = cpu_to_be16(
+   dcd_len * sizeof(dcd_addr_data_t) + 4);
+   dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
+   break;
+   case CMD_WRITE_CLR_BIT:
+   dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+   dcd_v2->write_dcd_command.length = cpu_to_be16(
+   dcd_len * sizeof(dcd_addr_data_t) + 4);
+   dcd_v2->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
+   break;
+   /*
+* Check data command only supports one entry,
+* so use 0xC = size(address + value + command).
+*/
+   case CMD_CHECK_BITS_SET:
+   dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+   dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
+   dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+   break;
+   case CMD_CHECK_BITS_CLR:
+   dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+   dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
+   dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+   break;
+   default:
+   break;
+   }
+}
+
 static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
int fld, uint32_t value, uint32_t off)
 {
@@ -200,10 +241,7 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, 
uint32_t dcd_len,
dcd_v2->header.length = cpu_to_be16(
dcd_len * sizeof(dcd_addr_data_t) + 8);
dcd_v2->header.version = DCD_VERSION;
-   dcd_v2->write_dcd_command.tag = DCD_COMMAND_TAG;
-   dcd_v2->write_dcd_command.length = cpu_to_be16(
-   dcd_len * sizeof(dcd_addr_data_t) + 4);
-   dcd_v2->write_dcd_command.param = DCD_COMMAND_PARAM;
+   set_dcd_param_v2(imxhdr, dcd_len, CMD_WRITE_DATA);
 }
 
 static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
@@ -2

[U-Boot] [PATCH 01/15][v2] power: pmic: add pfuze3000 support

2015-07-20 Thread Adrian Alonso
* Add pmic pfuze3000 support, implement power_pfuze3000_init to be
  used in power_init_board callback function.

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan 
---
Changes for V2:
- Correct pfuze device name to pfuze3000; Freescale documentation uses
  Pfuze 3000 as product name for the pmic, align driver name with the
  actual product name.

 drivers/power/pmic/Makefile |  1 +
 drivers/power/pmic/pmic_pfuze3000.c | 32 +++
 include/power/pfuze3000_pmic.h  | 78 +
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/power/pmic/pmic_pfuze3000.c
 create mode 100644 include/power/pfuze3000_pmic.h

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index ae86f04..b271acb 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
+obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
 obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
 obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
diff --git a/drivers/power/pmic/pmic_pfuze3000.c 
b/drivers/power/pmic/pmic_pfuze3000.c
new file mode 100644
index 000..ac807a8
--- /dev/null
+++ b/drivers/power/pmic/pmic_pfuze3000.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Peng Fan 
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int power_pfuze3000_init(unsigned char bus)
+{
+   static const char name[] = "PFUZE3000";
+   struct pmic *p = pmic_alloc();
+
+   if (!p) {
+   printf("%s: POWER allocation error!\n", __func__);
+   return -ENOMEM;
+   }
+
+   p->name = name;
+   p->interface = PMIC_I2C;
+   p->number_of_regs = PMIC_NUM_OF_REGS;
+   p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR;
+   p->hw.i2c.tx_num = 1;
+   p->bus = bus;
+
+   return 0;
+}
diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h
new file mode 100644
index 000..e8b892b
--- /dev/null
+++ b/include/power/pfuze3000_pmic.h
@@ -0,0 +1,78 @@
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc
+ *  Peng Fan 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __PFUZE3000_PMIC_H_
+#define __PFUZE3000_PMIC_H_
+
+/* PFUZE3000 registers */
+enum {
+   PFUZE3000_DEVICEID  = 0x00,
+
+   PFUZE3000_REVID = 0x03,
+   PFUZE3000_FABID = 0x04,
+   PFUZE3000_INTSTAT0  = 0x05,
+   PFUZE3000_INTMASK0  = 0x06,
+   PFUZE3000_INTSENSE0 = 0x07,
+   PFUZE3000_INTSTAT1  = 0x08,
+   PFUZE3000_INTMASK1  = 0x09,
+   PFUZE3000_INTSENSE1 = 0x0A,
+
+   PFUZE3000_INTSTAT3  = 0x0E,
+   PFUZE3000_INTMASK3  = 0x0F,
+   PFUZE3000_INTSENSE3 = 0x10,
+   PFUZE3000_INTSTAT4  = 0x11,
+   PFUZE3000_INTMASK4  = 0x12,
+   PFUZE3000_INTSENSE4 = 0x13,
+
+   PFUZE3000_COINCTL   = 0x1A,
+   PFUZE3000_PWRCTL= 0x1B,
+   PFUZE3000_MEMA  = 0x1C,
+   PFUZE3000_MEMB  = 0x1D,
+   PFUZE3000_MEMC  = 0x1E,
+   PFUZE3000_MEMD  = 0x1F,
+
+   PFUZE3000_SW1AVOLT  = 0x20,
+   PFUZE3000_SW1ASTBY  = 0x21,
+   PFUZE3000_SW1AOFF   = 0x22,
+   PFUZE3000_SW1AMODE  = 0x23,
+   PFUZE3000_SW1ACONF  = 0x24,
+
+   PFUZE3000_SW1BVOLT  = 0x2E,
+   PFUZE3000_SW1BSTBY  = 0x2F,
+   PFUZE3000_SW1BOFF   = 0x30,
+   PFUZE3000_SW1BMODE  = 0x31,
+   PFUZE3000_SW1BCONF  = 0x32,
+
+   PFUZE3000_SW2VOLT   = 0x35,
+   PFUZE3000_SW2STBY   = 0x36,
+   PFUZE3000_SW2OFF= 0x37,
+   PFUZE3000_SW2MODE   = 0x38,
+   PFUZE3000_SW2CONF   = 0x39,
+
+   PFUZE3000_SW3VOLT   = 0x3C,
+   PFUZE3000_SW3STBY   = 0x3D,
+   PFUZE3000_SW3OFF= 0x3E,
+   PFUZE3000_SW3MODE   = 0x3F,
+   PFUZE3000_SW3CONF   = 0x40,
+
+   PFUZE3000_SWBSTCTL  = 0x66,
+
+   PFUZE3000_LDOGCTL   = 0x69,
+   PFUZE3000_VREFDDRCTL= 0x6A,
+   PFUZE3000_VSNVSCTL  = 0x6B,
+   PFUZE3000_VLDO1CTL  = 0x6C,
+   PFUZE3000_VLDO2CTL  = 0x6D,
+   PFUZE3000_VCC_SDCTL = 0x6E,
+   PFUZE3000_V33CTL= 0x6F,
+   PFUZE3000_VLDO3CTL  = 0x70,
+   PFUZE3000_VLD4CTL   = 0x71,
+
+   PMIC_NUM_OF_REGS= 0x7F,
+};
+
+int power_pfuze3000_init(unsigned char bus);
+
+#endif
-- 
2.1.4

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[U-Boot] [PATCH 02/15][v2] imx: usb: ehci-mx7 add usb driver for i.MX7D

2015-07-20 Thread Adrian Alonso
* Add support for usb driver for i.MX7D SoC

Signed-off-by: Adrian Alonso 
Signed-off-by: Ye.Li 
Signed-off-by: Peng Fan 
---
Changes for V2: Resend

 drivers/usb/host/Makefile   |   1 +
 drivers/usb/host/ehci-mx7.c | 103 
 2 files changed, 104 insertions(+)
 create mode 100644 drivers/usb/host/ehci-mx7.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 4d35d3e..7267160 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
 obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
 obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
+obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx7.o
 obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
 obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
diff --git a/drivers/usb/host/ehci-mx7.c b/drivers/usb/host/ehci-mx7.c
new file mode 100644
index 000..7429d62
--- /dev/null
+++ b/drivers/usb/host/ehci-mx7.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2009 Daniel Mack 
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ehci.h"
+
+#define USB_NC_OFFSET  0x200
+
+#define UCTRL_PM   (1 << 9)/* OTG Power Mask */
+#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
+
+/* USBCMD */
+#define UCMD_RUN_STOP   (1 << 0) /* controller run/stop */
+#define UCMD_RESET (1 << 1) /* controller reset */
+
+/* Base address for this IP block is 0x02184800 */
+struct usbnc_regs {
+   u32 ctrl1;
+   u32 ctrl2;
+   u32 reserve1[11];
+   u32 phy_ctrl2;
+   u32 reserve2[6];
+   u32 adp_cfg1;
+   u32 reserve3;
+   u32 adp_status;
+};
+
+static void usb_oc_config(int index)
+{
+   struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+   (0x1 * index) + USB_NC_OFFSET);
+   void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
+   u32 val;
+
+   val = __raw_readl(ctrl);
+   val |= UCTRL_OVER_CUR_POL;
+   __raw_writel(val, ctrl);
+
+   val = __raw_readl(ctrl);
+   val |= (UCTRL_OVER_CUR_DIS | UCTRL_PM);
+   __raw_writel(val, ctrl);
+}
+
+int __weak board_ehci_hcd_init(int port)
+{
+   return 0;
+}
+
+int __weak board_ehci_power(int port, int on)
+{
+   return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+   struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+   struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
+   (0x1 * index));
+
+   if (index > 3)
+   return -EINVAL;
+   enable_usboh3_clk(1);
+   mdelay(1);
+
+   /* Do board specific initialization */
+   board_ehci_hcd_init(index);
+
+   usb_oc_config(index);
+
+   *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+   *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+   HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+   board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1);
+   if (init == USB_INIT_DEVICE)
+   return 0;
+   setbits_le32(&ehci->usbmode, CM_HOST);
+   __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+   setbits_le32(&ehci->portsc, USB_EN);
+
+   mdelay(10);
+
+   return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+   return 0;
+}
-- 
2.1.4

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[U-Boot] [PATCH 03/15][v2] imx: mmc: fsl_esdhc fix dcache issue

2015-07-20 Thread Adrian Alonso
DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.

We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.

With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.

Signed-off-by: Peng Fan 
Signed-off-by: Ye.Li 
Signed-off-by: Nitin Garg 
Signed-off-by: Jason Liu 
Signed-off-by: Adrian Alonso 
---
Changes for V2: Resend

 drivers/mmc/fsl_esdhc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c4719e6..0510bf0 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
err = esdhc_setup_data(mmc, data);
if(err)
return err;
+
+   if (data->flags & MMC_DATA_READ)
+   check_and_invalidate_dcache_range(cmd, data);
}
 
/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
struct mmc_data *data)
}
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+   /*
+* Need invalidate the dcache here again to avoid any
+* cache-fill during the DMA operations such as the
+* speculative pre-fetching etc.
+*/
if (data->flags & MMC_DATA_READ)
check_and_invalidate_dcache_range(cmd, data);
 #endif
-- 
2.1.4

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[U-Boot] [PATCH 06/15][v2] imx: ocotp: mxc add i.MX7D support

2015-07-20 Thread Adrian Alonso
* Ocotp of i.MX7D has different operation rule.
  This patch is to add support for i.MX7D ocotp.

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan 
Signed-off-by: Ye.Li 
---
Changes for V2: Resend

 drivers/misc/mxc_ocotp.c | 74 +++-
 1 file changed, 73 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index d92044e..7f0e9e4 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -25,8 +25,21 @@
 #define BM_CTRL_ERROR  0x0200
 #define BM_CTRL_BUSY   0x0100
 #define BO_CTRL_ADDR   0
+#ifdef CONFIG_MX7
+#define BM_CTRL_ADDR0x000f
+#define BM_CTRL_RELOAD  0x0400
+#else
 #define BM_CTRL_ADDR   0x007f
-
+#endif
+
+#ifdef CONFIG_MX7
+#define BO_TIMING_FSOURCE   12
+#define BM_TIMING_FSOURCE   0x0007f000
+#define BV_TIMING_FSOURCE_NS1001
+#define BO_TIMING_PROG  0
+#define BM_TIMING_PROG  0x0fff
+#define BV_TIMING_PROG_US   10
+#else
 #define BO_TIMING_STROBE_READ  16
 #define BM_TIMING_STROBE_READ  0x003f
 #define BV_TIMING_STROBE_READ_NS   37
@@ -36,6 +49,7 @@
 #define BO_TIMING_STROBE_PROG  0
 #define BM_TIMING_STROBE_PROG  0x0fff
 #define BV_TIMING_STROBE_PROG_US   10
+#endif
 
 #define BM_READ_CTRL_READ_FUSE 0x0001
 
@@ -109,6 +123,25 @@ int fuse_read(u32 bank, u32 word, u32 *val)
return finish_access(regs, __func__);
 }
 
+#ifdef CONFIG_MX7
+static void set_timing(struct ocotp_regs *regs)
+{
+   u32 ipg_clk;
+   u32 fsource, prog;
+   u32 timing;
+
+   ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+   fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
+   +   100) + 1;
+   prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 100) + 1;
+
+   timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
+
+   clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
+   timing);
+}
+#else
 static void set_timing(struct ocotp_regs *regs)
 {
u32 ipg_clk;
@@ -130,12 +163,17 @@ static void set_timing(struct ocotp_regs *regs)
clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
BM_TIMING_STROBE_PROG, timing);
 }
+#endif
 
 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
int write)
 {
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+#ifdef CONFIG_MX7
+   u32 addr = bank;
+#else
u32 addr = bank << 3 | word;
+#endif
 
set_timing(regs);
clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
@@ -155,7 +193,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
setup_direct_access(regs, bank, word, false);
writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
wait_busy(regs, 1);
+#ifdef CONFIG_MX7
+   *val = readl((®s->read_fuse_data0) + (word << 2));
+#else
*val = readl(®s->read_fuse_data);
+#endif
 
return finish_access(regs, __func__);
 }
@@ -176,8 +218,38 @@ int fuse_prog(u32 bank, u32 word, u32 val)
return ret;
 
setup_direct_access(regs, bank, word, true);
+#ifdef CONFIG_MX7
+   switch (word) {
+   case 0:
+   writel(0, ®s->data1);
+   writel(0, ®s->data2);
+   writel(0, ®s->data3);
+   writel(val, ®s->data0);
+   break;
+   case 1:
+   writel(val, ®s->data1);
+   writel(0, ®s->data2);
+   writel(0, ®s->data3);
+   writel(0, ®s->data0);
+   break;
+   case 2:
+   writel(0, ®s->data1);
+   writel(val, ®s->data2);
+   writel(0, ®s->data3);
+   writel(0, ®s->data0);
+   break;
+   case 3:
+   writel(0, ®s->data1);
+   writel(0, ®s->data2);
+   writel(val, ®s->data3);
+   writel(0, ®s->data0);
+   break;
+   }
+   wait_busy(regs, BV_TIMING_PROG_US);
+#else
writel(val, ®s->data);
wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+#endif
udelay(WRITE_POSTAMBLE_US);
 
return finish_access(regs, __func__);
-- 
2.1.4

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[U-Boot] [PATCH 05/15][v2] imx: mxc_gpio: add support for imx7d SoC

2015-07-20 Thread Adrian Alonso
* Add mxc_gpio support for imx7d SoC
* Use CONFIG_MX7 to extend mxc gpio driver support for imx7d

Signed-off-by: Peng Fan 
Signed-off-by: Adrian Alonso 
---
Changes for V2: Resend

 arch/arm/include/asm/arch-mx7/gpio.h | 12 
 drivers/gpio/mxc_gpio.c  |  8 +---
 2 files changed, 17 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx7/gpio.h

diff --git a/arch/arm/include/asm/arch-mx7/gpio.h 
b/arch/arm/include/asm/arch-mx7/gpio.h
new file mode 100644
index 000..b7890c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/gpio.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX7_GPIO_H
+#define __ASM_ARCH_MX7_GPIO_H
+
+#include 
+
+#endif /* __ASM_ARCH_MX7_GPIO_H */
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 2012f99..332ed40 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -40,14 +40,16 @@ static unsigned long gpio_ports[] = {
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX7)
[3] = GPIO4_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX7)
[4] = GPIO5_BASE_ADDR,
[5] = GPIO6_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
[6] = GPIO7_BASE_ADDR,
 #endif
 };
-- 
2.1.4

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[U-Boot] [PATCH 07/15][v2] imx: mx7 dm thermal driver support

2015-07-20 Thread Adrian Alonso
* Add thermal driver support for imx7 SoC
  read_cpu_temperature is SoC dependent
* Redefine config macro to support imx7 and imx6 SoC

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan 
---
Changes for V2:
- Rework patch so it can be applyed on top of patch
  imx6: standardise OCOTP and fuse config to mx6_common

 arch/arm/imx-common/cpu.c |  10 ++--
 drivers/thermal/Makefile  |   2 +-
 drivers/thermal/imx_thermal.c | 100 +++---
 include/configs/embestmx6boards.h |   2 +-
 include/configs/gw_ventana.h  |   2 +-
 include/configs/mx6cuboxi.h   |   2 +-
 include/configs/mx6sabre_common.h |   2 +-
 include/configs/mx6slevk.h|   2 +-
 include/configs/mx6sxsabresd.h|   2 +-
 include/configs/tbs2910.h |   2 +-
 10 files changed, 108 insertions(+), 18 deletions(-)

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 5e56cfe..2e803f3 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -148,14 +148,16 @@ int print_cpuinfo(void)
u32 cpurev;
__maybe_unused u32 max_freq;
 
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
struct udevice *thermal_dev;
-   int cpu_tmp, minc, maxc, ret;
+   int cpu_tmp, ret;
 #endif
 
cpurev = get_cpu_rev();
 
 #if defined(CONFIG_MX6)
+   int minc, maxc;
+
printf("CPU:   Freescale i.MX%s rev%d.%d",
   get_imx_type((cpurev & 0xFF000) >> 12),
   (cpurev & 0x000F0) >> 4,
@@ -175,7 +177,7 @@ int print_cpuinfo(void)
mxc_get_clock(MXC_ARM_CLK) / 100);
 #endif
 
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_MX6) && defined(CONFIG_IMX_THERMAL)
puts("CPU:   ");
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
@@ -192,6 +194,8 @@ int print_cpuinfo(void)
break;
}
printf("(%dC to %dC)", minc, maxc);
+#endif
+#if defined(CONFIG_IMX_THERMAL)
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 6d4cacd..d768f5e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -6,4 +6,4 @@
 #
 
 obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
-obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o
+obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 0d893c9..046c094 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -19,6 +19,14 @@
 #include 
 #include 
 
+struct thermal_data {
+   unsigned int fuse;
+   int critical;
+   int minc;
+   int maxc;
+};
+
+#if defined(CONFIG_MX6)
 /* board will busyloop until this many degrees C below CPU max temperature */
 #define TEMPERATURE_HOT_DELTA   5 /* CPU maxT - 5C */
 #define FACTOR01000
@@ -34,13 +42,6 @@
 #define MISC0_REFTOP_SELBIASOFF(1 << 3)
 #define TEMPSENSE1_MEASURE_FREQ0x
 
-struct thermal_data {
-   unsigned int fuse;
-   int critical;
-   int minc;
-   int maxc;
-};
-
 static int read_cpu_temperature(struct udevice *dev)
 {
int temperature;
@@ -124,6 +125,79 @@ static int read_cpu_temperature(struct udevice *dev)
return temperature;
 }
 
+#elif defined(CONFIG_MX7)
+#define TEMPERATURE_MIN-40
+#define TEMPERATURE_HOT85
+#define TEMPERATURE_MAX125
+#define MEASURE_FREQ   327
+
+static int read_cpu_temperature(struct udevice *dev)
+{
+   unsigned int reg, tmp, start;
+   unsigned int raw_25c, te1;
+   int temperature;
+   unsigned int *priv = dev_get_priv(dev);
+   u32 fuse = *priv;
+   struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ANATOP_BASE_ADDR;
+   /*
+* fuse data layout:
+* [31:21] sensor value @ 25C
+* [20:18] hot temperature value
+* [17:9] sensor value of room
+* [8:0] sensor value of hot
+*/
+
+   raw_25c = fuse >> 21;
+   if (raw_25c == 0)
+   raw_25c = 25;
+
+   te1 = (fuse >> 9) & 0x1ff;
+
+   /*
+* now we only use single measure, every time we read
+* the temperature, we will power on/down anadig thermal
+* module
+*/
+   writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, 
&ccm_anatop->tempsense1_clr);
+   writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set);
+
+   /* write measure freq */
+   reg = readl(&ccm_anatop->tempsense1);
+   reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK;
+   reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ);
+   writel(reg, &ccm_anatop->tempsense1);
+
+   writel(TE

[U-Boot] [PATCH 08/15][v2] imx: system counter driver for imx7d and mx6ul

2015-07-20 Thread Adrian Alonso
* The system counter driver for imx7d abd mx6ul, move
  this timer driver to imx-common and rename it as syscounter.c

  For mx6ul and mx7, configurations are used for choose the GPT timer
  or system counter timer (default).

  GPT timer:  CONFIG_GPT_TIMER
  System counter timer:   CONFIG_SYSCOUNTER_TIMER

  For mx6dqp GPT timer is the default setting.

Signed-off-by: Adrian Alonso 
Signed-off-by: Ye.Li 
---
Changes for V2: Resend

 arch/arm/imx-common/syscounter.c | 126 +++
 arch/arm/include/asm/imx-common/syscounter.h |  29 ++
 include/configs/mx6_common.h |   1 +
 3 files changed, 156 insertions(+)
 create mode 100644 arch/arm/imx-common/syscounter.c
 create mode 100644 arch/arm/include/asm/imx-common/syscounter.h

diff --git a/arch/arm/imx-common/syscounter.c b/arch/arm/imx-common/syscounter.c
new file mode 100644
index 000..f5e5cdc
--- /dev/null
+++ b/arch/arm/imx-common/syscounter.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+   ulong ticks;
+
+   if (usec < 1000)
+   ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+   else
+   ticks = ((usec / 10) * (get_tbclk() / 10));
+
+   return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   tick *= CONFIG_SYS_HZ;
+   do_div(tick, freq);
+
+   return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   usec = usec * freq  + 99;
+   do_div(usec, 100);
+
+   return usec;
+}
+
+int timer_init(void)
+{
+   struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+   unsigned long val, freq;
+
+   freq = CONFIG_SC_TIMER_CLK;
+   asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+   writel(freq, &sctr->cntfid0);
+
+   /* Enable system counter */
+   val = readl(&sctr->cntcr);
+   val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+   val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+   writel(val, &sctr->cntcr);
+
+   gd->arch.tbl = 0;
+   gd->arch.tbu = 0;
+
+   return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+   unsigned long long now;
+
+   asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+   gd->arch.tbl = (unsigned long)(now & 0x);
+   gd->arch.tbu = (unsigned long)(now >> 32);
+
+   return now;
+}
+
+ulong get_timer_masked(void)
+{
+   return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+   return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+   unsigned long long tmp;
+   ulong tmo;
+
+   tmo = us_to_tick(usec);
+   tmp = get_ticks() + tmo;/* get current timestamp */
+
+   while (get_ticks() < tmp)   /* loop till event */
+/*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   unsigned long freq;
+
+   asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+   return freq;
+}
diff --git a/arch/arm/include/asm/imx-common/syscounter.h 
b/arch/arm/include/asm/imx-common/syscounter.h
new file mode 100644
index 000..ddb412e
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/syscounter.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+   u32 cntcr;
+   u32 cntsr;
+   u32 cntcv1;
+   u32 cntcv2;
+   u32 resv1[4];
+   u32 cntfid0;
+   u32 cntfid1;
+   u32 cntfid2;
+   u32 resv2[1001];
+   u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE(1 << 0)
+#define SC_CNTCR_HDBG  (1 << 1)
+#define SC_CNTCR_FREQ0 (1 << 8)
+#define SC_CNTCR_FREQ1 (1 << 9)
+
+#endif
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 54ab890..ed9f8fe 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -30,6 +30,7 @@
 
 #define CONFIG_MP
 #define CONFIG_MXC_GPT_HCLK
+#define CONFIG_GPT_TIMER
 
 #define CONFIG_SYS_NO_FLASH
 
-- 
2.1.4

___
U-Boot ma

[U-Boot] [PATCH 10/15][v2] imx: imx7d: clock control module support

2015-07-20 Thread Adrian Alonso
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
  root frequency generation denominated clock slices.
  Core clock slice: hihg speed clock for ARM core
  Bus clock slice: for bus clocks
  IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  In u-boot, we have to:
  - Configure PFD3- PFD7 for freq we needed in u-boot
  - Set clock root for peripherals (ip channel)

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan 
Signed-off-by: Ye.Li 
---
Changes for V2: Split from patch imx: imx7d: initial arch level support

 arch/arm/cpu/armv7/mx7/clock.c  | 1130 +++
 arch/arm/cpu/armv7/mx7/clock_slice.c|  757 ++
 arch/arm/include/asm/arch-mx7/clock.h   |  348 +
 arch/arm/include/asm/arch-mx7/clock_slice.h |  116 +++
 4 files changed, 2351 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/mx7/clock.c
 create mode 100644 arch/arm/cpu/armv7/mx7/clock_slice.c
 create mode 100644 arch/arm/include/asm/arch-mx7/clock.h
 create mode 100644 arch/arm/include/asm/arch-mx7/clock_slice.h

diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c
new file mode 100644
index 000..fe92de9
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/clock.c
@@ -0,0 +1,1130 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ANATOP_BASE_ADDR;
+struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+   gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+   gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+   gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+   return 0;
+}
+
+u32 get_ahb_clk(void)
+{
+   return get_root_clk(AHB_CLK_ROOT);
+}
+
+static u32 get_ipg_clk(void)
+{
+   /*
+* The AHB and IPG are fixed at 2:1 ratio, and synchronized to
+* each other.
+*/
+   return get_ahb_clk() / 2;
+}
+
+u32 imx_get_uartclk(void)
+{
+   return get_root_clk(UART1_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+   return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+   clock_enable(CCGR_OCOTP, enable);
+}
+
+void enable_thermal_clk(void)
+{
+   enable_ocotp_clk(1);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+   u32 target;
+
+   if (enable) {
+   /* disable the clock gate first */
+   clock_enable(CCGR_USB_HSIC, 0);
+
+   /* 120Mhz */
+   target = CLK_ROOT_ON | 
USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+   clock_set_target_val(USB_HSIC_CLK_ROOT, target);
+
+   /* enable the clock gate */
+   clock_enable(CCGR_USB_CTRL, 1);
+   clock_enable(CCGR_USB_HSIC, 1);
+   clock_enable(CCGR_USB_PHY1, 1);
+   clock_enable(CCGR_USB_PHY2, 1);
+   } else {
+   clock_enable(CCGR_USB_CTRL, 0);
+   clock_enable(CCGR_USB_HSIC, 0);
+   clock_enable(CCGR_USB_PHY1, 0);
+   clock_enable(CCGR_USB_PHY2, 0);
+   }
+
+}
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+   u32 reg, div_sel;
+   u32 num, denom;
+
+   /*
+* Alought there are four choices for the bypass src,
+* we choose OSC_24M which is the default set in ROM.
+*/
+   switch (pll) {
+   case PLL_CORE:
+   reg = readl(&ccm_anatop->pll_arm);
+
+   if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
+   return 0;
+
+   if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+   return MXC_HCLK;
+
+   div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+  CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
+
+   return (infreq * div_sel) / 2;
+
+   case PLL_SYS:
+   reg = readl(&ccm_anatop->pll_480);
+
+   if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
+   return 0;
+
+   if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
+   return MXC_HCLK;
+
+   if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
+   CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
+   return 48

[U-Boot] [PATCH 13/15][v2] imx: imx7d: add timer support for imx7d

2015-07-20 Thread Adrian Alonso
* Add timer support for imx7d SoC

Signed-off-by: Adrian Alonso 
---
Changes for V2: Split from patch imx: imx7d: initial arch level support

 arch/arm/imx-common/timer.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index c12556a..bc4a673 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -49,6 +49,8 @@ static inline int gpt_has_clk_source_osc(void)
return 1;
 
return 0;
+#elif defined(CONFIG_MX7)
+   return 1;
 #else
return 0;
 #endif
@@ -56,6 +58,9 @@ static inline int gpt_has_clk_source_osc(void)
 
 static inline ulong gpt_get_clk(void)
 {
+#if defined(CONFIG_MX7)
+   return MXC_HCLK >> 3;
+#else
 #ifdef CONFIG_MXC_GPT_HCLK
if (gpt_has_clk_source_osc())
return MXC_HCLK >> 3;
@@ -64,6 +69,7 @@ static inline ulong gpt_get_clk(void)
 #else
return MXC_CLK32;
 #endif
+#endif
 }
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -106,7 +112,8 @@ int timer_init(void)
/* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) ||
-   is_cpu_type(MXC_CPU_MX6SX)) {
+   is_cpu_type(MXC_CPU_MX6SX) ||
+   is_cpu_type(MXC_CPU_MX7D)) {
i |= GPTCR_24MEN;
 
/* Produce 3Mhz clock */
-- 
2.1.4

___
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[U-Boot] [PATCH 12/15][v2] imx: imx7d: add hab secure boot support

2015-07-20 Thread Adrian Alonso
* HAB secure boot support
  - get_hab_status: checks if secure boot is enabled or not
  - authenticate_image: verifies image properly signed based
on CSF entry
* Uboot command for hab authenticate
  - hab_auth_img: authenticate image via HAB
  - hab_status: display HAB status

Signed-off-by: Adrian Alonso 
---
Changes for V2: Split from patch imx: imx7d: initial arch level support

 arch/arm/cpu/armv7/mx7/Makefile |   9 ++
 arch/arm/cpu/armv7/mx7/hab.c| 277 
 arch/arm/include/asm/arch-mx7/hab.h |  69 +
 3 files changed, 355 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/mx7/Makefile
 create mode 100644 arch/arm/cpu/armv7/mx7/hab.c
 create mode 100644 arch/arm/include/asm/arch-mx7/hab.h

diff --git a/arch/arm/cpu/armv7/mx7/Makefile b/arch/arm/cpu/armv7/mx7/Makefile
new file mode 100644
index 000..d36501d
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y  := soc.o clock.o clock_slice.o
+obj-$(CONFIG_SECURE_BOOT)+= hab.o
diff --git a/arch/arm/cpu/armv7/mx7/hab.c b/arch/arm/cpu/armv7/mx7/hab.c
new file mode 100644
index 000..43b06bd
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/hab.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*  start of HAB API updates */
+#define hab_rvt_report_event_p \
+(  \
+   ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)\
+)
+
+#define hab_rvt_report_status_p
\
+(  \
+   ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)  \
+)
+
+#define hab_rvt_authenticate_image_p   \
+(  \
+   ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)\
+)
+
+#define hab_rvt_entry_p
\
+(  \
+   ((hab_rvt_entry_t *)HAB_RVT_ENTRY)  \
+)
+
+#define hab_rvt_exit_p \
+(  \
+   ((hab_rvt_exit_t *)HAB_RVT_EXIT)\
+)
+
+#define IVT_SIZE   0x20
+#define ALIGN_SIZE 0x1000
+#define CSF_PAD_SIZE   0x2000
+
+/*
+ * ++  0x0 (DDR_UIMAGE_START) -
+ * |   Header   |  |
+ * ++  0x40|
+ * ||  |
+ * ||  |
+ * ||  |
+ * ||  |
+ * | Image Data |  |
+ * .|  |
+ * .|   > Stuff to be authenticated +
+ * .|  ||
+ * ||  ||
+ * ||  ||
+ * ++  ||
+ * ||  ||
+ * | Fill Data  |  ||
+ * ||  ||
+ * ++ Align to ALIGN_SIZE  ||
+ * |IVT |  ||
+ * ++ + IVT_SIZE  - |
+ * ||   |
+ * |  CSF DATA  | <-+
+ * ||
+ * ++
+ * ||
+ * | Fill Data  |
+ * ||
+ * ++ + CSF_PAD_SIZE
+ */
+
+bool is_hab_enabled(void)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = &ocotp->bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   uint32_t reg = readl(&fuse->cfg0);
+
+   return (reg & 0x200) == 0x200;
+}
+
+void display_event(uint8_t *event_data, size_t bytes)
+{
+   uint32_t i;
+
+   if (!(event_data && bytes > 0))
+   return;
+
+   for (i = 0; i < bytes; i++) {
+   if (i == 0)
+   printf("\t0x%02x", event

[U-Boot] [PATCH 15/15][v2] imx: mx7dsabresd: Add support for MX7D SABRESD board

2015-07-20 Thread Adrian Alonso
* Add i.MX7D SABRESD target board support with enabled modules:
  UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.

  Build target: mx7dsabresd_config

Signed-off-by: Peng Fan 
Signed-off-by: Fugang Duan 
Signed-off-by: Ye.Li 
Signed-off-by: Adrian Alonso 
---
Changes for V2:
- Include arch/arm/Kconfig target config option

 arch/arm/Kconfig  |   7 +
 board/freescale/mx7dsabresd/Kconfig   |  15 +
 board/freescale/mx7dsabresd/MAINTAINERS   |   6 +
 board/freescale/mx7dsabresd/Makefile  |   6 +
 board/freescale/mx7dsabresd/imximage.cfg  | 103 +
 board/freescale/mx7dsabresd/mx7dsabresd.c | 642 ++
 configs/mx7dsabresd_defconfig |  10 +
 include/configs/mx7_common.h  |  22 +
 include/configs/mx7dsabresd.h | 355 +
 9 files changed, 1166 insertions(+)
 create mode 100644 board/freescale/mx7dsabresd/Kconfig
 create mode 100644 board/freescale/mx7dsabresd/MAINTAINERS
 create mode 100644 board/freescale/mx7dsabresd/Makefile
 create mode 100644 board/freescale/mx7dsabresd/imximage.cfg
 create mode 100644 board/freescale/mx7dsabresd/mx7dsabresd.c
 create mode 100644 configs/mx7dsabresd_defconfig
 create mode 100644 include/configs/mx7_common.h
 create mode 100644 include/configs/mx7dsabresd.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 506463c..40aabb6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -578,6 +578,12 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
 
+config TARGET_MX7DSABRESD
+   bool "Support mx7dsabresd"
+   select CPU_V7
+   select DM
+   select DM_THERMAL
+
 config TARGET_GW_VENTANA
bool "Support gw_ventana"
select CPU_V7
@@ -923,6 +929,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx7dsabresd/Kconfig"
 source "board/freescale/vf610twr/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/genesi/mx51_efikamx/Kconfig"
diff --git a/board/freescale/mx7dsabresd/Kconfig 
b/board/freescale/mx7dsabresd/Kconfig
new file mode 100644
index 000..d7c6ae4
--- /dev/null
+++ b/board/freescale/mx7dsabresd/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX7DSABRESD
+
+config SYS_BOARD
+   default "mx7dsabresd"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_SOC
+   default "mx7"
+
+config SYS_CONFIG_NAME
+   default "mx7dsabresd"
+
+endif
diff --git a/board/freescale/mx7dsabresd/MAINTAINERS 
b/board/freescale/mx7dsabresd/MAINTAINERS
new file mode 100644
index 000..6b01c35
--- /dev/null
+++ b/board/freescale/mx7dsabresd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX7DSABRESD BOARD
+M: Fabio Estevam 
+S: Maintained
+F: board/freescale/mx7dsabresd
+F: include/configs/mx7dsabresd.h
+F: configs/mx7dsabresd_defconfig
diff --git a/board/freescale/mx7dsabresd/Makefile 
b/board/freescale/mx7dsabresd/Makefile
new file mode 100644
index 000..14336ab
--- /dev/null
+++ b/board/freescale/mx7dsabresd/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := mx7dsabresd.o
diff --git a/board/freescale/mx7dsabresd/imximage.cfg 
b/board/freescale/mx7dsabresd/imximage.cfg
new file mode 100644
index 000..5088d0e
--- /dev/null
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include 
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM  qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM  nor
+#else
+BOOT_FROM  sd
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type   AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F45
+
+DATA 4 0x30391000 0x0002
+DATA 4 0x307a 0x03040001
+DATA 4 0x307a01a0 0x8043
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x8014
+DATA 4 0x307a0064 0x0040005e
+DATA 4 0x307a0490 0x0001
+DATA 4 0x307a00d0 0x00020001
+DATA 4 0x307a00d4 0x0001
+DATA 4 0x307a00dc 0x0934
+DATA 4 0x307a00e0 0x0408
+DATA 4 0x307a00e4 0x00090004
+DATA 4 0x307a00f4 0x033f
+DATA 4 0x307a0100 0x0908120a
+DATA 4 0x307a0104 0x0002020e
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x2006
+DATA 4 0x307

[U-Boot] [PATCH 11/15][v2] imx: imx7d: Add SoC system support

2015-07-20 Thread Adrian Alonso
* Add SoC system support, Misc arch dependent functions for
  system bring up:
  s_init: system init enable clock base settings
  enable_caches: configures Cortex-A7 L2 caches
  get_boot_device: identifies boot device

Signed-off-by: Adrian Alonso 
Signed-off-by: Peng Fan 
Signed-off-by: Ye.Li 
---
Changes for V2: Split from patch imx: imx7d: initial arch level support

 arch/arm/cpu/armv7/mx7/soc.c| 360 
 arch/arm/include/asm/arch-imx/cpu.h |   1 +
 arch/arm/include/asm/imx-common/boot_mode.h |  21 ++
 3 files changed, 382 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/mx7/soc.c

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
new file mode 100644
index 000..4213dad
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -0,0 +1,360 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef CONFIG_VIDEO_MXS
+#include 
+#endif
+
+struct src *src_reg = (struct src *)SRC_BASE_ADDR;
+
+#if defined(CONFIG_IMX_THERMAL)
+static const struct imx_thermal_plat imx7_thermal_plat = {
+   .regs = (void *)ANATOP_BASE_ADDR,
+   .fuse_bank = 3,
+   .fuse_word = 3,
+};
+
+U_BOOT_DEVICE(imx7_thermal) = {
+   .name = "imx_thermal",
+   .platdata = &imx7_thermal_plat,
+};
+#endif
+
+u32 get_cpu_rev(void)
+{
+   struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ANATOP_BASE_ADDR;
+   u32 reg = readl(&ccm_anatop->digprog);
+   u32 type = (reg >> 16) & 0xff;
+
+   reg &= 0xff;
+   return (type << 12) | reg;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+   u32 cpurev = get_cpu_rev();
+   u32 type = ((cpurev >> 12) & 0xff);
+
+   if (type == MXC_CPU_MX7D)
+   cpurev = (MXC_CPU_MX7D) << 12 | (cpurev & 0xFFF);
+
+   return cpurev;
+}
+#endif
+
+static void init_aips(void)
+{
+   struct aipstz_regs *aips1, *aips2, *aips3;
+
+   aips1 = (struct aipstz_regs *)AIPS1_ON_BASE_ADDR;
+   aips2 = (struct aipstz_regs *)AIPS2_ON_BASE_ADDR;
+   aips3 = (struct aipstz_regs *)AIPS3_ON_BASE_ADDR;
+
+   /*
+* Set all MPROTx to be non-bufferable, trusted for R/W,
+* not forced to user-mode.
+*/
+   writel(0x, &aips1->mprot0);
+   writel(0x, &aips1->mprot1);
+   writel(0x, &aips2->mprot0);
+   writel(0x, &aips2->mprot1);
+   writel(0x, &aips3->mprot0);
+   writel(0x, &aips3->mprot1);
+
+   /*
+* Set all OPACRx to be non-bufferable, not require
+* supervisor privilege level for access,allow for
+* write access and untrusted master access.
+*/
+   writel(0x, &aips1->opacr0);
+   writel(0x, &aips1->opacr1);
+   writel(0x, &aips1->opacr2);
+   writel(0x, &aips1->opacr3);
+   writel(0x, &aips1->opacr4);
+   writel(0x, &aips2->opacr0);
+   writel(0x, &aips2->opacr1);
+   writel(0x, &aips2->opacr2);
+   writel(0x, &aips2->opacr3);
+   writel(0x, &aips2->opacr4);
+   writel(0x, &aips3->opacr0);
+   writel(0x, &aips3->opacr1);
+   writel(0x, &aips3->opacr2);
+   writel(0x, &aips3->opacr3);
+   writel(0x, &aips3->opacr4);
+}
+
+static void imx_set_pcie_phy_power_down(void)
+{
+   /* TODO */
+}
+
+static void imx_set_wdog_powerdown(bool enable)
+{
+   struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+   struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+   struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+   struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+
+   writew(enable, &wdog1->wmcr);
+   writew(enable, &wdog2->wmcr);
+   writew(enable, &wdog3->wmcr);
+   writew(enable, &wdog4->wmcr);
+}
+
+static void set_epdc_qos(void)
+{
+#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
+#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400)
+#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00)
+#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00)
+
+   writel(0, REGS_QOS_BASE);  /*  Disable clkgate & soft_reset */
+   writel(0, REGS_QOS_BASE + 0x60);  /*  Enable all masters */
+   writel(0, REGS_QOS_EPDC);   /*  Disable clkgate & soft_reset */
+   writel(0, REGS_QOS_PXP0);   /*  Disable clkgate & soft_reset */
+   writel(0, REGS_QOS_PXP1);   /*  Disable clkgate & soft_reset */
+
+   writel(0x0f020722, REGS_QOS_EPDC + 0xd0);   /*  WR, init = 7 with red 
flag */
+   writel(0x0f020722, REGS_QOS_EPDC + 0xe0);   /*  RD,  init = 7 with red 
flag */
+
+   writel(1, REGS_QOS_PXP0);   /* 

[U-Boot] [PATCH 14/15][v2] imx: imx7d: add imx-common cpu support for imx7d

2015-07-20 Thread Adrian Alonso
* Add imx-common cpu support for imx7d SoC
* Update reset_cause for imx7d
* Enable watchdog driver built for imx7d

Signed-off-by: Adrian Alonso 
---
Changes for V2: Split from patch imx: imx7d: initial arch level support

 arch/arm/Makefile|  4 ++--
 arch/arm/cpu/armv7/Makefile  |  3 ++-
 arch/arm/imx-common/Makefile | 17 ++---
 arch/arm/imx-common/cpu.c| 17 +
 drivers/watchdog/Makefile|  2 +-
 5 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f30098..6708140 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -78,11 +78,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 
mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 
mx31 mx35))
 libs-y += arch/arm/imx-common/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
 libs-y += arch/arm/imx-common/
 endif
 endif
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 5a76100..8defb1b 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y += cache_v7.o
 obj-y  += cpu.o cp15.o
 obj-y  += syslib.o
 
-ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif
@@ -45,6 +45,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos/
 obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
 obj-$(if $(filter mx5,$(SOC)),y) += mx5/
 obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_OMAP34XX) += omap3/
 obj-$(CONFIG_OMAP44XX) += omap4/
 obj-$(CONFIG_OMAP54XX) += omap5/
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b9f1ca4..99bec53 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -7,20 +7,31 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
 obj-y  = iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-obj-y  += timer.o cpu.o speed.o
+obj-y  += cpu.o speed.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+ifeq ($(SOC),$(filter $(SOC),mx5))
+obj-y  += timer.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx7))
+obj-y  += cpu.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_GPT_TIMER) += timer.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
 obj-y  += misc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_GPT_TIMER) += timer.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 2e803f3..3cd30e7 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -46,13 +46,26 @@ static char *get_reset_cause(void)
case 0x8:
return "IPP USER";
case 0x00010:
+#ifdef CONFIG_MX7
+   return "WDOG1";
+#else
return "WDOG";
+#endif
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
+#ifdef CONFIG_MX7
+   case 0x00080:
+   return "WDOG3";
+   case 0x00100:
+   return "WDOG4";
+   case 0x00200:
+   return "TEMPSENSE";
+#else
case 0x1:
return "WARM BOOT";
+#endif
default:
return "unknown reset";
}
@@ -122,6 +135,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
switch (imxtype) {
+   case MXC_CPU_MX7D:
+   return "7D";/* Dual-core version of the mx7 */
case MXC_CPU_MX6Q:
return "6Q";/* Quad-core version of the mx6 */
case MXC_CPU_MX6D:
@@ -236,6 +251,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifndef CONFIG_MX7
 u32 get_ahb_clk(void)
 {
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -247,6 +263,7 @@ u32 get_ahb_clk(void)
 
return get_periph_clk() / (ahb_podf + 1);
 }
+#endif
 
 void arch_preboot_os(void)
 {
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 482a4bd..9e9cb55 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -7,7 +7,7 @@
 
 obj-$(CONFIG

Re: [U-Boot] [PATCH 15/15][v2] imx: mx7dsabresd: Add support for MX7D SABRESD board

2015-07-20 Thread Fabio Estevam
Hi Adrian,

On Mon, Jul 20, 2015 at 9:17 PM, Adrian Alonso  wrote:

> --- /dev/null
> +++ b/board/freescale/mx7dsabresd/MAINTAINERS
> @@ -0,0 +1,6 @@
> +MX7DSABRESD BOARD
> +M: Fabio Estevam 

I think it makes more sense to put your name here :-)
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Re: [U-Boot] [PATCH 3/3] mtd: nand: mxs invalidate dcache before DMA read

2015-07-20 Thread Peng Fan
Hi Marek,
On Mon, Jul 20, 2015 at 09:27:35PM +0200, Marek Vasut wrote:
>On Monday, July 20, 2015 at 11:40:22 AM, Peng Fan wrote:
>> Follow linux dma follow:
>
>Nit: "flow" at the end, not "follow" ;-)
Thanks.
Do you have a chance to review this patch,
https://patchwork.ozlabs.org/patch/497619/ ?

>
>> Before DMA read, be sure to invalidate the cache over the address
>> range of DMA buffer to prevent cache coherency problems.
>> After DMA read, invalidate dcache again.
>> 
>> Signed-off-by: Peng Fan 
>
>Acked-by: Marek Vasut 
>
>Best regards,
>Marek Vasut

Thanks,
Peng
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Re: [U-Boot] [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S

2015-07-20 Thread Wang Dongsheng
Thanks. :)

Regards,
-Dongsheng

> -Original Message-
> From: Sun York-R58495
> Sent: Tuesday, July 21, 2015 5:14 AM
> To: Wang Dongsheng-B40534
> Cc: i...@hellion.org.uk; hdego...@redhat.com; albert.u.b...@aribaud.net;
> jan.kis...@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-
> B35336; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from
> sunxi/psci_sun7i.S
> 
> 
> 
> On 06/03/2015 09:01 PM, Dongsheng Wang wrote:
> > From: Wang Dongsheng 
> >
> > timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
> > completely into a reusable armv7 generic timer. LS1021A will use it as
> > well.
> >
> > Signed-off-by: Wang Dongsheng 
> >
> 
> Applied to u-boot-fsl-qoriq master branch.
> 
> York
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[U-Boot] [PATCH] layerscape: sata: Add layerscape sata support

2015-07-20 Thread Yuantian.Tang
From: Tang Yuantian 

Freescale ARM-based Layerscape SoCs contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds some basic SATA APIs which would be called by
specific board.

Signed-off-by: Tang Yuantian 
---
 board/freescale/common/Makefile  |  6 +
 board/freescale/common/ls_sata.c | 52 
 board/freescale/common/ls_sata.h | 39 ++
 3 files changed, 97 insertions(+)
 create mode 100644 board/freescale/common/ls_sata.c
 create mode 100644 board/freescale/common/ls_sata.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 87d0578..8508005 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -43,6 +43,12 @@ else
 obj-$(CONFIG_DEEP_SLEEP)   += mpc85xx_sleep.o
 endif
 
+ifdef CONFIG_ARM
+ifdef CONFIG_SATA1
+obj-y += ls_sata.o
+endif
+endif
+
 obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
 
 obj-$(CONFIG_MPC8541CDS)   += cds_pci_ft.o
diff --git a/board/freescale/common/ls_sata.c b/board/freescale/common/ls_sata.c
new file mode 100644
index 000..2aab939
--- /dev/null
+++ b/board/freescale/common/ls_sata.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "ls_sata.h"
+
+void ls_sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+   unsigned int __iomem *dcfg_ecc = (void *)0x20220520;
+   out_le32(dcfg_ecc, 0x0002);
+#endif
+
+#ifdef CONFIG_SATA2
+   ccsr_ahci = (void __iomem *)CONFIG_SYS_SATA2;
+   out_le32(&ccsr_ahci->ppcfg, 0xa003fffe);
+#endif
+
+#ifdef CONFIG_SATA1
+   ccsr_ahci = (void __iomem *)CONFIG_SYS_SATA1;
+   out_le32(&ccsr_ahci->ppcfg, 0xa003fffe);
+#ifdef CONFIG_LS102XA
+   out_le32(&ccsr_ahci->pp2c, 0x28183411);
+   out_le32(&ccsr_ahci->pp3c, 0x0e081004);
+   out_le32(&ccsr_ahci->pp4c, 0x00480811);
+   out_le32(&ccsr_ahci->pp5c, 0x192c96a4);
+   out_le32(&ccsr_ahci->ptc, 0x0825);
+#endif
+#endif
+}
+
+int ls_sata_start(void)
+{
+   int rc;
+
+   rc = ahci_init((void *)CONFIG_SYS_SATA1);
+   if (rc)
+   return rc;
+
+   scsi_scan(0);
+
+   return 0;
+}
diff --git a/board/freescale/common/ls_sata.h b/board/freescale/common/ls_sata.h
new file mode 100644
index 000..a69854c
--- /dev/null
+++ b/board/freescale/common/ls_sata.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS_SATA_H
+#define __LS_SATA_H
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 paxic;  /* port AXI config */
+   u32 axicc;  /* AXI cache control */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/* port link config */
+   u32 plc1;   /* port link config1 */
+   u32 plc2;   /* port link config2 */
+   u32 pls;/* port link status */
+   u32 pls1;   /* port link status1 */
+   u32 pcmdc;  /* port CMD config */
+   u32 ppcs;   /* port phy control status */
+   u32 pberr;  /* port 0/1 BIST error */
+   u32 cmds;   /* port 0/1 CMD status error */
+};
+
+void ls_sata_init(void);
+
+int ls_sata_start(void);
+
+#endif
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 5/5] arm: mvebu: db-88f6820-gp: Add SDIO/MMC SPL boot support

2015-07-20 Thread Stefan Roese

Hi Luka,

On 20.07.2015 23:34, Luka Perkov wrote:

On Mon, Jul 20, 2015 at 11:20:40AM +0200, Stefan Roese wrote:

This patch adds the configuration options to boot via SDIO/MMC on the
Marvell DB-88F6820-GP Armada A38x board. The default boot device
is still SPI NOR flash.

To enable MMC booting on this board 2 things need to be changes:
a) Change kwbimage.cfg
BOOT_FROM   sdio
b) In the config header select
#define CONFIG_SPL_BOOT_DEVICE  SPL_BOOT_SDIO_MMC_CARD

The generated image needs to be copied to the first bootable MMC
partition:


Can you please define "bootable" here? Does the partition really need to
have bootable flag configured?


Correct. Thats how I understand it from the documentation. Trying to 
boot from a partition that did not have this "bootable" flag set did not 
work IIRC.


Thanks,
Stefan
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[U-Boot] [PATCH 0/7] UniPhier SoC changes for v2015.10-rc1

2015-07-20 Thread Masahiro Yamada

Masahiro Yamada (7):
  ARM: UniPhier: add environment sets for non-FIT Linux boot
  ARM: UniPhier: add environment variable for TFTP boot
  ARM: UniPhier: disable CONFIG_FIT
  ARM: UniPhier: update CONFIG_BOOTARGS
  ARM: UniPhier: add PH1-sLD3 SoC support
  ARM: dts: UniPhier: add I2C ch4 device node for PH1-sLD3
  ARM: UniPhier: document reference support card

 arch/arm/dts/uniphier-ph1-sld3.dtsi|   9 ++
 arch/arm/mach-uniphier/Kconfig |  12 ++-
 arch/arm/mach-uniphier/Makefile|   7 +-
 arch/arm/mach-uniphier/include/mach/sc-regs.h  |   6 +-
 arch/arm/mach-uniphier/include/mach/sg-regs.h  |   5 +-
 arch/arm/mach-uniphier/ph1-sld3/Makefile   |  16 
 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c |  36 +++
 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c|  97 +++
 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c  |   1 +
 .../arm/mach-uniphier/ph1-sld3/early_clkrst_init.c |   1 +
 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c|  23 +
 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S   |  31 +++
 arch/arm/mach-uniphier/ph1-sld3/memconf.c  |  52 +++
 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c  |  24 +
 arch/arm/mach-uniphier/ph1-sld3/platdevice.c   |   1 +
 arch/arm/mach-uniphier/ph1-sld3/pll_init.c |  10 ++
 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c |  18 
 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c |  45 +
 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c |  37 
 arch/arm/mach-uniphier/ph1-sld3/sg_init.c  |   9 ++
 arch/arm/mach-uniphier/ph1-sld3/umc_init.c |  15 +++
 configs/ph1_ld4_defconfig  |   2 -
 configs/ph1_pro4_defconfig |   2 -
 configs/ph1_sld3_defconfig |  28 ++
 configs/ph1_sld8_defconfig |   2 -
 doc/README.uniphier|  54 ++-
 include/configs/uniphier.h | 103 -
 27 files changed, 602 insertions(+), 44 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/Makefile
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/memconf.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/platdevice.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sg_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/umc_init.c
 create mode 100644 configs/ph1_sld3_defconfig

-- 
1.9.1

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[U-Boot] [PATCH 4/7] ARM: UniPhier: update CONFIG_BOOTARGS

2015-07-20 Thread Masahiro Yamada
Both "earlyprintk" and "loglevel=8" should be useful for the
development.

Signed-off-by: Masahiro Yamada 
---

 include/configs/uniphier.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 0a86c8d..5ec60d6 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -221,7 +221,7 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
"tftpboot; bootm;"
 
-#define CONFIG_BOOTARGS" user_debug=0x1f init=/sbin/init"
+#define CONFIG_BOOTARGS" earlyprintk loglevel=8"
 
 #ifdef CONFIG_FIT
 #define CONFIG_BOOTFILE"fitImage"
-- 
1.9.1

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[U-Boot] [PATCH 7/7] ARM: UniPhier: document reference support card

2015-07-20 Thread Masahiro Yamada
Signed-off-by: Masahiro Yamada 
---

 doc/README.uniphier | 46 --
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/doc/README.uniphier b/doc/README.uniphier
index 4dacc9c..52d681b 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -85,6 +85,48 @@ Supported devices
  - Support card (SRAM, NOR flash, some peripherals)
 
 
+Micro Support Card
+--
+
+The recommended bit switch settings are as follows:
+
+ SW2OFF(1)/ON(0)   Description
+ --
+ bit 1   < BKSZ[0]
+ bit 2   > BKSZ[1]
+ bit 3   < SoC Bus Width 16/32
+ bit 4   < SERIAL_SEL[0]
+ bit 5   > SERIAL_SEL[1]
+ bit 6   > BOOTSWAP_EN
+ bit 7   < CS1/CS5
+ bit 8   < SOC_SERIAL_DISABLE
+
+ SW8OFF(1)/ON(0)   Description
+ --
+ bit 1>CS1_SPLIT
+ bit 2BURST_EN
+ bit 8>FLASHBUS32_16
+
+The BKSZ[1:0] specifies the address range of memory slot and peripherals
+as follows:
+
+ BKSZDescription  RAM slotPeripherals
+ 
+ 0b00   15MB RAM / 1MB Peri-0eff0f00-0fff
+ 0b01   31MB RAM / 1MB Peri-1eff1f00-1fff
+ 0b10   64MB RAM / 1MB Peri-3eff3f00-3fff
+ 0b11  127MB RAM / 1MB Peri-7eff7f00-7fff
+
+Set BSKZ[1:0] to 0b01 for U-Boot.
+This mode is the most handy because EA[24] is always supported by the save pin
+mode of the system bus.  On the other hand, EA[25] is not supported for some
+newer SoCs.  Even if it is, EA[25] is not connected on most of the boards.
+
 --
-Masahiro Yamada 
-Feb. 2015
+Masahiro Yamada 
+Jul. 2015
-- 
1.9.1

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[U-Boot] [PATCH 3/7] ARM: UniPhier: disable CONFIG_FIT

2015-07-20 Thread Masahiro Yamada
To use FIT boot, we have to describe Image Tree Source in addition.
So, it is not intended for beginners.  Disable it by default.

Signed-off-by: Masahiro Yamada 
---

 configs/ph1_ld4_defconfig  | 2 --
 configs/ph1_pro4_defconfig | 2 --
 configs/ph1_sld8_defconfig | 2 --
 3 files changed, 6 deletions(-)

diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index a71511c..f84dcdf 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -4,8 +4,6 @@ CONFIG_MACH_PH1_LD4=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index d02712e..2fc844d 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -3,8 +3,6 @@ CONFIG_ARCH_UNIPHIER=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index ee4cebc..2af45d2 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -4,8 +4,6 @@ CONFIG_MACH_PH1_SLD8=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
-- 
1.9.1

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[U-Boot] [PATCH 1/7] ARM: UniPhier: add environment sets for non-FIT Linux boot

2015-07-20 Thread Masahiro Yamada
Currently, the environment variables "norboot" and "nandboot" only
work with CONFIG_FIT, but we do not want to depend on CONFIG_FIT to
boot the kernel.

This commit adds environments useful for booting Linux with separate
uImage + ramdisk + DTB.

Signed-off-by: Masahiro Yamada 
---

 include/configs/uniphier.h | 61 --
 1 file changed, 43 insertions(+), 18 deletions(-)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 5c7a342..a909621 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -209,7 +209,6 @@
 
 #define CONFIG_LOADADDR0x8400
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
-#define CONFIG_BOOTFILE"fit.itb"
 
 #define CONFIG_CMDLINE_EDITING /* add command line history */
 
@@ -224,23 +223,49 @@
 
 #define CONFIG_BOOTARGS" user_debug=0x1f init=/sbin/init"
 
-#defineCONFIG_EXTRA_ENV_SETTINGS   \
-   "netdev=eth0\0" \
-   "image_offset=0x0008\0" \
-   "image_size=0x00f0\0"   \
-   "verify=n\0"\
-   "nandupdate=nand erase 0 0x10 &&"   \
-  "tftpboot u-boot-spl.bin &&" \
-  "nand write $loadaddr 0 0x1 &&"  \
-  "tftpboot u-boot-dtb.img &&" \
-  "nand write $loadaddr 0x1 0xf\0" \
-   "norboot=run add_default_bootargs &&"   \
-   "bootm $image_offset\0" \
-   "nandboot=run add_default_bootargs &&"  \
-"nand read $loadaddr $image_offset $image_size &&" \
-"bootm\0"  \
-   "add_default_bootargs=setenv bootargs $bootargs"\
-   " console=ttyS0,$baudrate\0"\
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE"fitImage"
+#define LINUXBOOT_ENV_SETTINGS \
+   "fit_addr=0x0010\0" \
+   "fit_addr_r=0x8410\0" \
+   "fit_size=0x00f0\0" \
+   "norboot=run add_default_bootargs &&" \
+   "bootm $fit_addr\0" \
+   "nandboot=run add_default_bootargs &&" \
+   "nand read $fit_addr_r $fit_addr $fit_size &&" \
+   "bootm $fit_addr_r\0"
+#else
+#define CONFIG_BOOTFILE"uImage"
+#define LINUXBOOT_ENV_SETTINGS \
+   "fdt_addr=0x0010\0" \
+   "fdt_addr_r=0x8410\0" \
+   "fdt_size=0x8000\0" \
+   "kernel_addr=0x0020\0" \
+   "kernel_addr_r=0x8420\0" \
+   "kernel_size=0x0080\0" \
+   "ramdisk_addr=0x00a0\0" \
+   "ramdisk_addr_r=0x84a0\0" \
+   "ramdisk_size=0x0060\0" \
+   "norboot=run add_default_bootargs &&" \
+   "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
+   "nandboot=run add_default_bootargs &&" \
+   "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
+   "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
+   "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
+   "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
+#endif
+
+#defineCONFIG_EXTRA_ENV_SETTINGS   \
+   "netdev=eth0\0" \
+   "verify=n\0"\
+   "nandupdate=nand erase 0 0x0010 &&" \
+   "tftpboot u-boot-spl.bin &&"\
+   "nand write $loadaddr 0 0x0001 &&"  \
+   "tftpboot u-boot-dtb.img &&"\
+   "nand write $loadaddr 0x0001 0x000f\0"  \
+   "add_default_bootargs=setenv bootargs $bootargs"\
+   " console=ttyS0,$baudrate\0"\
+   LINUXBOOT_ENV_SETTINGS
 
 /* Open Firmware flat tree */
 #define CONFIG_OF_LIBFDT
-- 
1.9.1

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[U-Boot] [PATCH 6/7] ARM: dts: UniPhier: add I2C ch4 device node for PH1-sLD3

2015-07-20 Thread Masahiro Yamada
This I2C device is used SoC-internally for controlling the DMD core.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ph1-sld3.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi 
b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 2fa42a6..5e29436 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -129,6 +129,15 @@
status = "disabled";
};
 
+   i2c4: i2c@5860 {
+   compatible = "panasonic,uniphier-i2c";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x5860 0x40>;
+   clock-frequency = <40>;
+   status = "okay";
+   };
+
system-bus-controller-misc@5980 {
compatible = 
"socionext,uniphier-system-bus-controller-misc",
 "syscon";
-- 
1.9.1

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[U-Boot] [PATCH 5/7] ARM: UniPhier: add PH1-sLD3 SoC support

2015-07-20 Thread Masahiro Yamada
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Kconfig | 12 ++-
 arch/arm/mach-uniphier/Makefile|  7 +-
 arch/arm/mach-uniphier/include/mach/sc-regs.h  |  6 +-
 arch/arm/mach-uniphier/include/mach/sg-regs.h  |  5 +-
 arch/arm/mach-uniphier/ph1-sld3/Makefile   | 16 
 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c | 36 
 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c| 97 ++
 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c  |  1 +
 .../arm/mach-uniphier/ph1-sld3/early_clkrst_init.c |  1 +
 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c| 23 +
 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S   | 31 +++
 arch/arm/mach-uniphier/ph1-sld3/memconf.c  | 52 
 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c  | 24 ++
 arch/arm/mach-uniphier/ph1-sld3/platdevice.c   |  1 +
 arch/arm/mach-uniphier/ph1-sld3/pll_init.c | 10 +++
 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c | 18 
 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 45 ++
 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c | 37 +
 arch/arm/mach-uniphier/ph1-sld3/sg_init.c  |  9 ++
 arch/arm/mach-uniphier/ph1-sld3/umc_init.c | 15 
 configs/ph1_sld3_defconfig | 28 +++
 doc/README.uniphier|  8 +-
 include/configs/uniphier.h | 28 ++-
 23 files changed, 494 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/Makefile
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/memconf.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/platdevice.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/sg_init.c
 create mode 100644 arch/arm/mach-uniphier/ph1-sld3/umc_init.c
 create mode 100644 configs/ph1_sld3_defconfig

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index feda49e..7b49ad3 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -10,13 +10,17 @@ choice
prompt "UniPhier SoC select"
default MACH_PH1_PRO4
 
-config MACH_PH1_PRO4
-   bool "PH1-Pro4"
+config MACH_PH1_SLD3
+   bool "PH1-sLD3"
select UNIPHIER_SMP
 
 config MACH_PH1_LD4
bool "PH1-LD4"
 
+config MACH_PH1_PRO4
+   bool "PH1-Pro4"
+   select UNIPHIER_SMP
+
 config MACH_PH1_SLD8
bool "PH1-sLD8"
 
@@ -64,11 +68,11 @@ choice
 
 config DDR_FREQ_1600
bool "DDR3 1600"
-   depends on MACH_PH1_PRO4 || MACH_PH1_LD4
+   depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
 
 config DDR_FREQ_1333
bool "DDR3 1333"
-   depends on MACH_PH1_LD4 || MACH_PH1_SLD8
+   depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
 
 endchoice
 
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 24591d6..103db6d 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -32,6 +32,7 @@ obj-y += timer.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
 
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
+obj-$(CONFIG_MACH_PH1_SLD3)+= ph1-sld3/
+obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
+obj-$(CONFIG_MACH_PH1_PRO4)+= ph1-pro4/
+obj-$(CONFIG_MACH_PH1_SLD8)+= ph1-sld8/
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h 
b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index 20878e2..df50294 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -1,7 +1,7 @@
 /*
  * UniPhier SC (System Control) block registers
  *
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2015 Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -9,7 +9,11 @@
 #ifndef ARCH_SC_REGS_H
 #define ARCH_SC_REGS_H
 
+#if defined(CONFIG_MACH_PH1_SLD3)
+#define SC_BASE_ADDR   0xf184
+#else
 #define SC_BASE_ADDR   0x6184

[U-Boot] [PATCH 2/7] ARM: UniPhier: add environment variable for TFTP boot

2015-07-20 Thread Masahiro Yamada
The command "run tftpboot" downloads some files onto the RAM
via TFTP and boots the kernel.

Signed-off-by: Masahiro Yamada 
---

 include/configs/uniphier.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index a909621..0a86c8d 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -233,6 +233,9 @@
"bootm $fit_addr\0" \
"nandboot=run add_default_bootargs &&" \
"nand read $fit_addr_r $fit_addr $fit_size &&" \
+   "bootm $fit_addr_r\0" \
+   "tftpboot=run add_default_bootargs &&" \
+   "tftpboot $fit_addr_r $bootfile &&" \
"bootm $fit_addr_r\0"
 #else
 #define CONFIG_BOOTFILE"uImage"
@@ -240,18 +243,25 @@
"fdt_addr=0x0010\0" \
"fdt_addr_r=0x8410\0" \
"fdt_size=0x8000\0" \
+   "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr=0x0020\0" \
"kernel_addr_r=0x8420\0" \
"kernel_size=0x0080\0" \
"ramdisk_addr=0x00a0\0" \
"ramdisk_addr_r=0x84a0\0" \
"ramdisk_size=0x0060\0" \
+   "ramdisk_file=rootfs.cpio.uboot\0" \
"norboot=run add_default_bootargs &&" \
"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
"nandboot=run add_default_bootargs &&" \
"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
+   "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+   "tftpboot=run add_default_bootargs &&" \
+   "tftpboot $kernel_addr_r $bootfile &&" \
+   "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
+   "tftpboot $fdt_addr_r $fdt_file &&" \
"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
 #endif
 
-- 
1.9.1

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Re: [U-Boot] [PATCH 0/3] add dfu support for at91 sam9260 based boards

2015-07-20 Thread Lukasz Majewski
Hi Heiko,

> Hello Lukasz,
> 
> Am 20.07.2015 um 16:03 schrieb Lukasz Majewski:
> > Hi Marek,
> >
> >> add dfu supprt for at91 sam9260 based boards. The USB
> >> gadget driver is ported from linux:
> >>
> >> b2ba27a5c56ff: usb: gadget: at91_udc: move prepare clk into process
> >> context
> >>
> >> it drops a lot of checkpatch warnings/errors:
> >>
> >> checkpatch.pl found 12 error(s), 31 warning(s), 43 checks(s)
> >>
> >> but for further updates I did not fix them.
> >> The errors are all from this sort:
> >>
> >> error: drivers/usb/gadget/at91_udc.c,87: space prohibited before
> >> open square bracket '['
> >>
> >> a lot of "line over 80 characters" warnings ...
> >>
> >>
> >> Heiko Schocher (3):
> >>ARM: at91: add cpu.h
> >>usb: gadget: at91_udc: add support for at91_udc
> >>at91, taurus, smartweb: add dfu support
> >
> > Marek, do you plan to review this patch series?
> >
> > (I would need at least one review before I pull the code).
> 
> Maybe a Reviewed-by or Acked-by from you (and Marek) is enough,
> as it is maybe pickedup by Andreas Biessmann (at91 maintainer)
> 

No problem. I will review the code.

> Thanks!
> 
> bye,
> Heiko
> >
> >>
> >>   arch/arm/mach-at91/include/mach/cpu.h |  149 +++
> >>   board/siemens/smartweb/smartweb.c |   29 +
> >>   board/siemens/taurus/taurus.c |   27 +
> >>   drivers/usb/gadget/Makefile   |1 +
> >>   drivers/usb/gadget/at91_udc.c | 2203
> >> +
> >> drivers/usb/gadget/at91_udc.h |  171 +++
> >> include/configs/smartweb.h|   34 +-
> >> include/configs/taurus.h  |   28 +-
> >> include/linux/usb/at91_udc.h  |   20 + 9 files changed,
> >> 2657 insertions(+), 5 deletions(-) create mode 100644
> >> arch/arm/mach-at91/include/mach/cpu.h create mode 100644
> >> drivers/usb/gadget/at91_udc.c create mode 100644
> >> drivers/usb/gadget/at91_udc.h create mode 100644
> >> include/linux/usb/at91_udc.h
> >>
> >
> >
> >
> 



-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 0/3] add dfu support for at91 sam9260 based boards

2015-07-20 Thread Marek Vasut
On Monday, July 20, 2015 at 04:03:08 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
> > add dfu supprt for at91 sam9260 based boards. The USB
> > gadget driver is ported from linux:
> > 
> > b2ba27a5c56ff: usb: gadget: at91_udc: move prepare clk into process
> > context
> > 
> > it drops a lot of checkpatch warnings/errors:
> > 
> > checkpatch.pl found 12 error(s), 31 warning(s), 43 checks(s)
> > 
> > but for further updates I did not fix them.
> > The errors are all from this sort:
> > 
> > error: drivers/usb/gadget/at91_udc.c,87: space prohibited before open
> > square bracket '['
> > 
> > a lot of "line over 80 characters" warnings ...
> > 
> > Heiko Schocher (3):
> >   ARM: at91: add cpu.h
> >   usb: gadget: at91_udc: add support for at91_udc
> >   at91, taurus, smartweb: add dfu support
> 
> Marek, do you plan to review this patch series?
> 
> (I would need at least one review before I pull the code).

I took a brief look. One thing I don't quite like is the omnipresent #ifdef 
__UBOOT__ stuff. I'd much rather love to see some kind of a porting layer
so the driver can just be picked from linux as-is, but that might be too much
hassle.

Otherwise, I'm fine with it, though I nitpicked a bit.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] at91, taurus, smartweb: add dfu support

2015-07-20 Thread Marek Vasut
On Monday, June 15, 2015 at 02:43:01 PM, Heiko Schocher wrote:
> [root@pollux dfu-util]# ./src/dfu-util -l
> dfu-util 0.8
> 
> Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
> Copyright 2010-2014 Tormod Volden and Stefan Schmidt
> This program is Free Software and has ABSOLUTELY NO WARRANTY
> Please report bugs to dfu-u...@lists.gnumonks.org
> 
> Found DFU: [0908:02d2] ver=0212, devnum=119, cfg=1, intf=0, alt=0,
> name="Linux", serial="UNKNOWN" [root@pollux dfu-util]#
> 
> Signed-off-by: Heiko Schocher 
> ---
> 
>  board/siemens/smartweb/smartweb.c | 29 +
>  board/siemens/taurus/taurus.c | 27 +++
>  include/configs/smartweb.h| 34 ++
>  include/configs/taurus.h  | 28 +++-
>  4 files changed, 113 insertions(+), 5 deletions(-)
> 
> diff --git a/board/siemens/smartweb/smartweb.c
> b/board/siemens/smartweb/smartweb.c index cf8a7f5..2d42488 100644
> --- a/board/siemens/smartweb/smartweb.c
> +++ b/board/siemens/smartweb/smartweb.c
> @@ -25,6 +25,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #ifdef CONFIG_MACB
> @@ -108,6 +109,29 @@ static void smartweb_macb_hw_init(void)
>  }
>  #endif /* CONFIG_MACB */
> 
> +#ifdef CONFIG_USB_GADGET_AT91
> +#include 
> +
> +void at91_udp_hw_init(void)
> +{
> + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> +
> + /* Enable PLLB */
> + writel(get_pllb_init(), &pmc->pllbr);
> + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> + ;

Unbounded loops are no good :-)

> + /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
> + at91_periph_clk_enable(ATMEL_ID_UDP);
> +
> + writel(AT91SAM926x_PMC_UDP, &pmc->scer);
> +}

[...]
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Re: [U-Boot] [PATCH 2/3] mtd: nand: mxs check maximum ecc that platfrom supports

2015-07-20 Thread Marek Vasut
On Monday, July 20, 2015 at 11:40:21 AM, Peng Fan wrote:
> Check maximum ecc strength for each platfrom to avoid the calculated ecc
> exceed the limitation.
> 
> Signed-off-by: Peng Fan 
> Signed-off-by: Han Xu 

Reviewed-by: Marek Vasut 

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] mtd: nand: mxs invalidate dcache before DMA read

2015-07-20 Thread Marek Vasut
On Tuesday, July 21, 2015 at 02:27:43 AM, Peng Fan wrote:
> Hi Marek,
> 
> On Mon, Jul 20, 2015 at 09:27:35PM +0200, Marek Vasut wrote:
> >On Monday, July 20, 2015 at 11:40:22 AM, Peng Fan wrote:
> >> Follow linux dma follow:
> >Nit: "flow" at the end, not "follow" ;-)
> 
> Thanks.
> Do you have a chance to review this patch,
> https://patchwork.ozlabs.org/patch/497619/ ?

I checked them both, I had no comments for the other.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/15][v2] imx: usb: ehci-mx7 add usb driver for i.MX7D

2015-07-20 Thread Marek Vasut
On Tuesday, July 21, 2015 at 02:17:06 AM, Adrian Alonso wrote:
> * Add support for usb driver for i.MX7D SoC
> 
> Signed-off-by: Adrian Alonso 
> Signed-off-by: Ye.Li 
> Signed-off-by: Peng Fan 

Hi!

Do we really need yet-another-driver for i.MX ?

> ---
> Changes for V2: Resend
> 
>  drivers/usb/host/Makefile   |   1 +
>  drivers/usb/host/ehci-mx7.c | 103
>  2 files changed, 104
> insertions(+)
>  create mode 100644 drivers/usb/host/ehci-mx7.c
> 
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 4d35d3e..7267160 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
>  obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
>  obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
>  obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
> +obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx7.o
>  obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
>  obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
>  obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
> diff --git a/drivers/usb/host/ehci-mx7.c b/drivers/usb/host/ehci-mx7.c
> new file mode 100644
> index 000..7429d62
> --- /dev/null
> +++ b/drivers/usb/host/ehci-mx7.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (c) 2009 Daniel Mack 
> + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "ehci.h"
> +
> +#define USB_NC_OFFSET0x200
> +
> +#define UCTRL_PM (1 << 9)/* OTG Power Mask */
> +#define UCTRL_OVER_CUR_POL   (1 << 8) /* OTG Polarity of Overcurrent */
> +#define UCTRL_OVER_CUR_DIS   (1 << 7) /* Disable OTG Overcurrent Detection
> */ +

Are these bits EHCI spiecific or MX7 Chipidea controller specific ?

> +/* USBCMD */
> +#define UCMD_RUN_STOP   (1 << 0) /* controller run/stop */
> +#define UCMD_RESET   (1 << 1) /* controller reset */
> +
> +/* Base address for this IP block is 0x02184800 */
> +struct usbnc_regs {
> + u32 ctrl1;
> + u32 ctrl2;

Please stop mixing tab and space, use tab :)

> + u32 reserve1[11];
> + u32 phy_ctrl2;
> + u32 reserve2[6];
> + u32 adp_cfg1;
> + u32 reserve3;
> + u32 adp_status;
> +};
> +
> +static void usb_oc_config(int index)
> +{
> + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
> + (0x1 * index) + USB_NC_OFFSET);
> + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
> + u32 val;
> +
> + val = __raw_readl(ctrl);
> + val |= UCTRL_OVER_CUR_POL;
> + __raw_writel(val, ctrl);

setbits_le32() here.

> + val = __raw_readl(ctrl);
> + val |= (UCTRL_OVER_CUR_DIS | UCTRL_PM);
> + __raw_writel(val, ctrl);

Here as well.

> +}
> +
> +int __weak board_ehci_hcd_init(int port)
> +{
> + return 0;
> +}
> +
> +int __weak board_ehci_power(int port, int on)
> +{
> + return 0;
> +}

Can you add kerneldoc style comments to the functions please ?

> +int ehci_hcd_init(int index, enum usb_init_type init,
> + struct ehci_hccr **hccr, struct ehci_hcor **hcor)
> +{
> + struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
> + (0x1 * index));
> +
> + if (index > 3)
> + return -EINVAL;
> + enable_usboh3_clk(1);
> + mdelay(1);
> +
> + /* Do board specific initialization */
> + board_ehci_hcd_init(index);
> +
> + usb_oc_config(index);
> +
> + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> + *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
> + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
> +
> + board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1);
> + if (init == USB_INIT_DEVICE)
> + return 0;
> + setbits_le32(&ehci->usbmode, CM_HOST);
> + __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);

Just use writel().

> + setbits_le32(&ehci->portsc, USB_EN);
> +
> + mdelay(10);
> +
> + return 0;
> +}
> +
> +int ehci_hcd_stop(int index)
> +{

You cannot stop the controller at all once you start it ? That looks
like yet another hardware flub :-(

> + return 0;
> +}

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/3] ARM: at91: add cpu.h

2015-07-20 Thread Marek Vasut
On Monday, June 15, 2015 at 02:42:59 PM, Heiko Schocher wrote:
> add cpu.h from linux:
> 
> 7538ec7d1e5: ARM: at91: remove no-MMU at91x40 support
> 
> so it is easier to port linux code, which is based on it.
> 
> Signed-off-by: Heiko Schocher 
> ---
> 
>  arch/arm/mach-at91/include/mach/cpu.h | 149
> ++ 1 file changed, 149 insertions(+)
>  create mode 100644 arch/arm/mach-at91/include/mach/cpu.h
> 
> diff --git a/arch/arm/mach-at91/include/mach/cpu.h
> b/arch/arm/mach-at91/include/mach/cpu.h new file mode 100644
> index 000..a5e698d
> --- /dev/null
> +++ b/arch/arm/mach-at91/include/mach/cpu.h
> @@ -0,0 +1,149 @@
> +/*
> + * from linux:
> + * 7538ec7d1e5: ARM: at91: remove no-MMU at91x40 support
> + *
> + * arch/arm/mach-at91/include/mach/cpu.h
> + *
> + * Copyright (C) 2006 SAN People
> + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD
>  + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + *
> + */
> +
> +#ifndef __AT91_MACH_CPU_H__
> +#define __AT91_MACH_CPU_H__
> +
> +#ifdef CONFIG_AT91RM9200
> +#define cpu_is_at91rm9200()  (1)
> +#else
> +#define cpu_is_at91rm9200()  (0)
> +#endif

The () are not needed .

Best regards,
Marek Vasut
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[U-Boot] [PATCH 04/15][v2] imx: iomux-v3: add imx7d support for iomuxc

2015-07-20 Thread Adrian Alonso
* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr
  (0x302C) each conroller provides control and mux mode pad
  registers but shares iomuxc input select register with iomuxc-lpsr
  IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings
  for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3
  driver for these LPSR pins.

Signed-off-by: Adrian Alonso 
Signed-off-by: Fugang Duan 
Signed-off-by: Ye.Li 
---
Changes for V2:
- Update commit log information

 arch/arm/imx-common/iomux-v3.c |   20 +-
 arch/arm/include/asm/arch-mx7/mx7-pins.h   |   19 +
 arch/arm/include/asm/arch-mx7/mx7d_pins.h  | 1308 
 arch/arm/include/asm/imx-common/iomux-v3.h |   32 +
 4 files changed, 1378 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-mx7/mx7-pins.h
 create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_pins.h

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 7fb23dd..07e75a6 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
  *   
  *
- * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -41,6 +41,18 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
}
 #endif
 
+#ifdef CONFIG_IOMUX_LPSR
+   u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
+
+   if (lpsr == IOMUX_CONFIG_LPSR) {
+   base = (void *)IOMUXC_LPSR_BASE_ADDR;
+   mux_mode &= ~IOMUX_CONFIG_LPSR;
+   /* set daisy chain sel_input */
+   if (sel_input_ofs)
+   sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
+   }
+#endif
+
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
 
@@ -55,6 +67,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
 #endif
+
+#ifdef CONFIG_IOMUX_LPSR
+   if (lpsr == IOMUX_CONFIG_LPSR)
+   base = (void *)IOMUXC_BASE_ADDR;
+#endif
+
 }
 
 /* configures a list of pads within declared with IOMUX_PADS macro */
diff --git a/arch/arm/include/asm/arch-mx7/mx7-pins.h 
b/arch/arm/include/asm/arch-mx7/mx7-pins.h
new file mode 100644
index 000..164c2be
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7-pins.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MX7_PINS_H__
+#define __ASM_ARCH_MX7_PINS_H__
+
+#include 
+
+#if defined(CONFIG_MX7D)
+#include "mx7d_pins.h"
+#elif defined(CONFIG_MX7S)
+#include "mx7s_pins.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX7D */
+
+#endif /*__ASM_ARCH_MX7_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h 
b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
new file mode 100644
index 000..d8b4097
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
@@ -0,0 +1,1308 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX7D_PINS_H__
+#define __ASM_ARCH_IMX7D_PINS_H__
+
+#include 
+
+enum {
+   MX7D_PAD_GPIO1_IO00__GPIO1_IO0   = 
IOMUX_PAD(0x0030, 0x, IOMUX_CONFIG_LPSR | 0, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO00__PWM4_OUT= 
IOMUX_PAD(0x0030, 0x, IOMUX_CONFIG_LPSR | 1, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B= 
IOMUX_PAD(0x0030, 0x, IOMUX_CONFIG_LPSR | 3, 0x, 0, 0),
+
+   MX7D_PAD_GPIO1_IO01__GPIO1_IO1   = 
IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO01__PWM1_OUT= 
IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3   = 
IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO01__SAI1_MCLK   = 
IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x, 0, 0),
+
+   MX7D_PAD_GPIO1_IO02__GPIO1_IO2   = 
IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO02__PWM2_OUT= 
IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1   = 
IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0),
+   MX7D_PAD_GPIO1_IO02__SAI2_MCLK   = 
IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x, 0, 0),
+   MX7D_PAD_GPIO1_IO02__CCM_CLKO1   = 
IOMUX_PAD(0x0038, 0x0008, I

Re: [U-Boot] [PATCH 01/11][v2] imx: imximage: add new CHECK/CLR BIT command

2015-07-20 Thread Stefano Babic
Hi Adrian, hi Peng,

On 16/07/2015 00:49, Adrian Alonso wrote:
> * Extend imximage DCD version 2 to support DCD commands
>   CMD_WRITE_CLR_BIT 4 [address] [mask bit] means:
> while ((*address & ~mask) != 0);
>   CMD_CHECK_BITS_SET 4 [address] [mask bit] means:
> while ((*address & mask) != mask);
>   CMD_CHECK_BITS_CLR 4 [address] [mask bit] means:
> *address = *address & ~mask;
> * Add set_dcd_param_v2 helper function to set DCD
>   command parameters
> 
> Signed-off-by: Adrian Alonso 
> Signed-off-by: Peng Fan 
> ---
> Changes for V2
> - Add set_dcd_param_v2 helper function to set DCD command tag
>   and parameters
> 
>  tools/imximage.c | 99 
> 
>  tools/imximage.h | 25 ++
>  2 files changed, 97 insertions(+), 27 deletions(-)
> 
> diff --git a/tools/imximage.c b/tools/imximage.c
> index 6f469ae..cc0392f 100644
> --- a/tools/imximage.c
> +++ b/tools/imximage.c
> @@ -21,7 +21,10 @@
>  static table_entry_t imximage_cmds[] = {
>   {CMD_BOOT_FROM, "BOOT_FROM","boot command",   },
>   {CMD_BOOT_OFFSET,   "BOOT_OFFSET",  "Boot offset",},
> - {CMD_DATA,  "DATA", "Reg Write Data", },
> + {CMD_WRITE_DATA,"DATA", "Reg Write Data", },
> + {CMD_WRITE_CLR_BIT, "CLR_BIT",  "Reg clear bit",  },
> + {CMD_CHECK_BITS_SET,"CHECK_BITS_SET",   "Reg Check bits set", },
> + {CMD_CHECK_BITS_CLR,"CHECK_BITS_CLR",   "Reg Check bits clr", },
>   {CMD_CSF,   "CSF",   "Command Sequence File", },
>   {CMD_IMAGE_VERSION, "IMAGE_VERSION","image version",  },
>   {-1,"", "",   },
> @@ -62,7 +65,7 @@ static table_entry_t imximage_boot_loadsize[] = {
>   */
>  static table_entry_t imximage_versions[] = {
>   {IMXIMAGE_V1,   "", " (i.MX25/35/51 compatible)", },
> - {IMXIMAGE_V2,   "", " (i.MX53/6 compatible)", },
> + {IMXIMAGE_V2,   "", " (i.MX53/6/7 compatible)",   },
>   {-1,"", " (Invalid)", },
>  };
>  
> @@ -79,6 +82,7 @@ static uint32_t imximage_csf_size = UNDEFINED;
>  static uint32_t imximage_init_loadsize;
>  
>  static set_dcd_val_t set_dcd_val;
> +static set_dcd_param_t set_dcd_param;
>  static set_dcd_rst_t set_dcd_rst;
>  static set_imx_hdr_t set_imx_hdr;
>  static uint32_t max_dcd_entries;
> @@ -128,6 +132,12 @@ static void err_imximage_version(int version)
>   exit(EXIT_FAILURE);
>  }
>  
> +static void set_dcd_param_v1(struct imx_header *imxhdr, uint32_t dcd_len,
> + int32_t cmd)
> +{
> + /* DCD V1 no parameter settings */
> +}

It is better you check if you drop this and you check if the pointer is
set to NULL before calling.

> +
>  static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int lineno,
>   int fld, uint32_t value, uint32_t off)
>  {
> @@ -156,6 +166,43 @@ static void set_dcd_val_v1(struct imx_header *imxhdr, 
> char *name, int lineno,
>   }
>  }
>  
> +static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
> + int32_t cmd)
> +{
> + dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
> +
> + switch (cmd) {
> + case CMD_WRITE_DATA:
> + dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
> + dcd_v2->write_dcd_command.length = cpu_to_be16(
> + dcd_len * sizeof(dcd_addr_data_t) + 4);
> + dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
> + break;
> + case CMD_WRITE_CLR_BIT:
> + dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
> + dcd_v2->write_dcd_command.length = cpu_to_be16(
> + dcd_len * sizeof(dcd_addr_data_t) + 4);
> + dcd_v2->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
> + break;
> + case CMD_CHECK_BITS_SET:
> + dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
> + /*
> +  * Check data command only supports one entry,
> +  * so use 0xC = size(address + value + command).
> +  */

Comment applied to both CHECK_BITS, you could move it before (or put it
also in CMD_CHECK_BITS_CLR case).

> + dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
> + dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
> + break;
> + case CMD_CHECK_BITS_CLR:
> + dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
> + dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
> + dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
> + break;
> + default:
> + break;
> + }
> +}
> +
>  static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
>  

[U-Boot] [PATCH] Reproducible U-Boot build support, using SOURCE_DATE_EPOCH

2015-07-20 Thread Paul Kocialkowski
In order to achieve reproducible builds in U-Boot, timestamps that are defined
at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH environment
variable allows setting a fixed value for those timestamps.

Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can be
built reproducibly. This is the case for e.g. sunxi devices.

However, some other devices might need some more tweaks, especially regarding
the image generation tools.

Signed-off-by: Paul Kocialkowski 
---
 Makefile  |  7 ---
 tools/default_image.c | 21 -
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 37cc4c3..71aeac7 100644
--- a/Makefile
+++ b/Makefile
@@ -1231,9 +1231,10 @@ define filechk_version.h
 endef
 
 define filechk_timestamp.h
-   (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
-   LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
-   LC_ALL=C date +'#define U_BOOT_TZ "%z"')
+   (SOURCE_DATE="$${SOURCE_DATE_EPOCH:+@$$SOURCE_DATE_EPOCH}"; \
+   LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_DATE "%b %d 
%C%y"'; \
+   LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_TIME "%T"'; 
\
+   LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_TZ "%z"' )
 endef
 
 $(version_h): include/config/uboot.release FORCE
diff --git a/tools/default_image.c b/tools/default_image.c
index cf5c0d4..18940af 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -88,6 +88,9 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
int ifd,
struct image_tool_params *params)
 {
uint32_t checksum;
+   char *source_date_epoch;
+   struct tm *time_universal;
+   time_t time;
 
image_header_t * hdr = (image_header_t *)ptr;
 
@@ -96,9 +99,25 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
int ifd,
sizeof(image_header_t)),
sbuf->st_size - sizeof(image_header_t));
 
+   source_date_epoch = getenv("SOURCE_DATE_EPOCH");
+   if (source_date_epoch != NULL) {
+   time = (time_t) strtol(source_date_epoch, NULL, 10);
+
+   time_universal = gmtime(&time);
+   if (time_universal == NULL) {
+   fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
+   __func__);
+   time = 0;
+   } else {
+   time = mktime(time_universal);
+   }
+   } else {
+   time = sbuf->st_mtime;
+   }
+
/* Build new header */
image_set_magic(hdr, IH_MAGIC);
-   image_set_time(hdr, sbuf->st_mtime);
+   image_set_time(hdr, time);
image_set_size(hdr, sbuf->st_size - sizeof(image_header_t));
image_set_load(hdr, params->addr);
image_set_ep(hdr, params->ep);
-- 
1.9.1

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Re: [U-Boot] [Reproducible-builds] [PATCH] build: create time and date independent binary

2015-07-20 Thread Paul Kocialkowski
> Did you see my v2 patch [1] for u-boot?
> 
> It also builds now u-boot images created with mkimage reproducible ...
> 
> If I interpret your patch from above correct, you add with
> SOURCE_DATE_EPOCH a specific fix timestamp?
> 
> I think, this could be included to my approach too ...
> 
> If SOURCE_DATE_EPOCH is defined, use it, fi not defined
> define U_BOOT_DATE, U_BOOT_TIME and U_BOOT_TZ
> with my default settings from [1] ...
> 
> All only if CONFIG_SYS_EXACT_BINARY is set in the u-boot
> config of course ...
> 
> What do you think?

I think adding a config option adds all sorts of unnecessary
complications. SOURCE_DATE_EPOCH is sufficient for what we want.

Thanks a lot for your work, it has been a great base for the patch I
just sent: http://patchwork.ozlabs.org/patch/497577/

Feel free to add your signed-off-by line since it's inspired by your
patch.

-- 
Paul Kocialkowski, Replicant developer

Replicant is a fully free Android distribution running on several
devices, a free software mobile operating system putting the emphasis on
freedom and privacy/security.

Website: http://www.replicant.us/
Blog: http://blog.replicant.us/
Wiki/tracker/forums: http://redmine.replicant.us/


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Re: [U-Boot] [PATCH] Reproducible U-Boot build support, using SOURCE_DATE_EPOCH

2015-07-20 Thread Paul Kocialkowski
Le lundi 20 juillet 2015 à 10:01 +0200, Paul Kocialkowski a écrit :
> In order to achieve reproducible builds in U-Boot, timestamps that are defined
> at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH 
> environment
> variable allows setting a fixed value for those timestamps.
> 
> Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can 
> be
> built reproducibly. This is the case for e.g. sunxi devices.
> 
> However, some other devices might need some more tweaks, especially regarding
> the image generation tools.

Lunar, since you have contributed to this patch, feel free to add your
Signed-Off-By line here before it's merged!

Heiko, since this is based on your original patch, feel free to do the
same!

It would be nice to have this tested on as many boards as possible to
spot other areas that make the binaries not reproducible. However, I
doubt this patch will evolve much and other fixes should be sent in
subsequent patches.

> Signed-off-by: Paul Kocialkowski 
> ---
>  Makefile  |  7 ---
>  tools/default_image.c | 21 -
>  2 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 37cc4c3..71aeac7 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1231,9 +1231,10 @@ define filechk_version.h
>  endef
>  
>  define filechk_timestamp.h
> - (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
> - LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
> - LC_ALL=C date +'#define U_BOOT_TZ "%z"')
> + (SOURCE_DATE="$${SOURCE_DATE_EPOCH:+@$$SOURCE_DATE_EPOCH}"; \
> + LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_DATE "%b %d 
> %C%y"'; \
> + LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_TIME "%T"'; 
> \
> + LC_ALL=C date -u -d "$${SOURCE_DATE:-now}" +'#define U_BOOT_TZ "%z"' )
>  endef
>  
>  $(version_h): include/config/uboot.release FORCE
> diff --git a/tools/default_image.c b/tools/default_image.c
> index cf5c0d4..18940af 100644
> --- a/tools/default_image.c
> +++ b/tools/default_image.c
> @@ -88,6 +88,9 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
> int ifd,
>   struct image_tool_params *params)
>  {
>   uint32_t checksum;
> + char *source_date_epoch;
> + struct tm *time_universal;
> + time_t time;
>  
>   image_header_t * hdr = (image_header_t *)ptr;
>  
> @@ -96,9 +99,25 @@ static void image_set_header(void *ptr, struct stat *sbuf, 
> int ifd,
>   sizeof(image_header_t)),
>   sbuf->st_size - sizeof(image_header_t));
>  
> + source_date_epoch = getenv("SOURCE_DATE_EPOCH");
> + if (source_date_epoch != NULL) {
> + time = (time_t) strtol(source_date_epoch, NULL, 10);
> +
> + time_universal = gmtime(&time);
> + if (time_universal == NULL) {
> + fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
> + __func__);
> + time = 0;
> + } else {
> + time = mktime(time_universal);
> + }
> + } else {
> + time = sbuf->st_mtime;
> + }
> +
>   /* Build new header */
>   image_set_magic(hdr, IH_MAGIC);
> - image_set_time(hdr, sbuf->st_mtime);
> + image_set_time(hdr, time);
>   image_set_size(hdr, sbuf->st_size - sizeof(image_header_t));
>   image_set_load(hdr, params->addr);
>   image_set_ep(hdr, params->ep);



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[U-Boot] [PATCH v2 07/11] arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory

2015-07-20 Thread Stefan Roese
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.

This will be the new structure:

 drivers/ddr/marvell/axp
 Supporting Armada XP (AXP) devices (and perhaps Armada 370)

 drivers/ddr/marvell/a38x
 Supporting Armada 38x devices (and perhaps Armada 39x)

Signed-off-by: Stefan Roese 
---

Changes in v2: None

 arch/arm/mach-mvebu/include/mach/cpu.h| 2 +-
 arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h  | 2 +-
 drivers/ddr/{mvebu => marvell/axp}/Makefile   | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_axp.h | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_config.h  | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_mc_static.h   | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_training_static.h | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_vars.h| 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_dfs.c | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_dqs.c | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.c | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.h | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_init.c| 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_init.h| 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_patterns_64bit.h  | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_pbs.c | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_read_leveling.c   | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_sdram.c   | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_spd.c | 0
 drivers/ddr/{mvebu => marvell/axp}/ddr3_write_leveling.c  | 0
 drivers/ddr/{mvebu => marvell/axp}/xor.c  | 0
 drivers/ddr/{mvebu => marvell/axp}/xor.h  | 0
 drivers/ddr/{mvebu => marvell/axp}/xor_regs.h | 0
 include/configs/db-mv784mp-gp.h   | 2 +-
 include/configs/maxbcm.h  | 2 +-
 scripts/Makefile.spl  | 2 +-
 26 files changed, 5 insertions(+), 5 deletions(-)
 rename drivers/ddr/{mvebu => marvell/axp}/Makefile (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_config.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_mc_static.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_training_static.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_axp_vars.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_dfs.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_dqs.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_hw_training.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_init.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_init.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_patterns_64bit.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_pbs.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_read_leveling.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_sdram.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_spd.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/ddr3_write_leveling.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/xor.c (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/xor.h (100%)
 rename drivers/ddr/{mvebu => marvell/axp}/xor_regs.h (100%)

diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h 
b/arch/arm/mach-mvebu/include/mach/cpu.h
index 4bdb633..8bcdef6 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -125,7 +125,7 @@ int serdes_phy_config(void);
 /*
  * DDR3 init / training code ported from Marvell bin_hdr. Now
  * available in mainline U-Boot in:
- * drivers/ddr/mvebu/
+ * drivers/ddr/marvell
  */
 int ddr3_init(void);
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h 
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
index e5aa1b0..e10574e 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
@@ -7,7 +7,7 @@
 #ifndef __HIGHSPEED_ENV_SPEC_H
 #define __HIGHSPEED_ENV_SPEC_H
 
-#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+#include "../../../drivers/ddr/marvell/axp/ddr3_hw_training.h"
 
 typedef enum {
SERDES_UNIT_UNCONNECTED = 0x0,
diff --git a/drivers/ddr/mvebu/Makefile b/drivers/ddr/marvell/axp/Makefile
similarity index 100%
rename from drivers/ddr/mvebu/Makefile
rename to drivers/ddr/marvell/axp/Makefile
diff --git a/drivers/ddr/mvebu/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
similarity index 100%
rename from drivers/ddr/mvebu/ddr3_axp.h
rename to drivers/ddr/mar

[U-Boot] [PATCH v2 04/11] Makefile: Fix mvebu build target to use SPL load and exe-address

2015-07-20 Thread Stefan Roese
The u-boot-spl.kwb build target needs the SPL text-base
(CONFIG_SPL_TEXT_BASE) as load and execution address.

Signed-off-by: Stefan Roese 
---

Changes in v2: None

 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index a7dce06..744ae80 100644
--- a/Makefile
+++ b/Makefile
@@ -887,7 +887,7 @@ MKIMAGEFLAGS_u-boot.kwb = -n 
$(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
 
 MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-   -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
+   -T kwbimage -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
 
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
-- 
2.4.6

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[U-Boot] [PATCH v2 02/11] arm: mvebu: spl.c: Add call to board_early_init_f()

2015-07-20 Thread Stefan Roese
Pin muxing needs to be done before UART output, since on A38x the UART
pins need some re-muxing for output to work.

Signed-off-by: Stefan Roese 
---

Changes in v2: None

 arch/arm/mach-mvebu/spl.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 402e520..2df25aa 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -26,6 +26,13 @@ void board_init_f(ulong dummy)
/* Linux expects the internal registers to be at 0xf100 */
arch_cpu_init();
 
+   /*
+* Pin muxing needs to be done before UART output, since
+* on A38x the UART pins need some re-muxing for output
+* to work.
+*/
+   board_early_init_f();
+
preloader_console_init();
 
/* First init the serdes PHY's */
-- 
2.4.6

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[U-Boot] [PATCH v2 01/11] arm: mvebu: Use default reg base address for SPL on A38x

2015-07-20 Thread Stefan Roese
On A38x switching the regs base address without running from
SDRAM doesn't seem to work. So let the SPL still use the
default base address and switch to the new address in the
mail u-boot later.

Signed-off-by: Stefan Roese 
---

Changes in v2: None

 arch/arm/mach-mvebu/include/mach/soc.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h 
b/arch/arm/mach-mvebu/include/mach/soc.h
index 1aaea67..c295255 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -28,7 +28,17 @@
 /* SOC specific definations */
 #define INTREG_BASE0xd000
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
+/*
+ * On A38x switching the regs base address without running from
+ * SDRAM doesn't seem to work. So let the SPL still use the
+ * default base address and switch to the new address in the
+ * main u-boot later.
+ */
+#define SOC_REGS_PHY_BASE  0xd000
+#else
 #define SOC_REGS_PHY_BASE  0xf100
+#endif
 #define MVEBU_REGISTER(x)  (SOC_REGS_PHY_BASE + x)
 
 #define MVEBU_SDRAM_SCRATCH(MVEBU_REGISTER(0x01504))
-- 
2.4.6

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[U-Boot] [PATCH v2 11/11] arm: mvebu: db-88f6820: Add SPL support with DDR init code

2015-07-20 Thread Stefan Roese
This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board.

Signed-off-by: Stefan Roese 

---

Changes in v2:
- Rebased on top of current version (v2015.07)

 board/Marvell/db-88f6820-gp/README  | 18 +++
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 31 +
 board/Marvell/db-88f6820-gp/kwbimage.cfg|  2 +-
 configs/db-88f6820-gp_defconfig |  1 +
 include/configs/db-88f6820-gp.h | 35 +
 5 files changed, 86 insertions(+), 1 deletion(-)
 create mode 100644 board/Marvell/db-88f6820-gp/README

diff --git a/board/Marvell/db-88f6820-gp/README 
b/board/Marvell/db-88f6820-gp/README
new file mode 100644
index 000..9bea5b3
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/README
@@ -0,0 +1,18 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+---
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+To update the SPI NOR flash, please use the following
+command:
+
+=> sf probe;tftpboot 200 db-88f6820-gp/u-boot-spl.kwb;\
+sf update 200 0 6
+
+Note that the original Marvell U-Boot seems to have
+problems with the "sf update" command. This does not
+work reliable. So here this command should be used:
+
+=> sf probe;tftpboot 200 db-88f6820-gp/u-boot-spl.kwb;\
+sf erase 0 6;sf write 200 0 6
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c 
b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 51ac495..e661fa1 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BIT(nr)(1UL << (nr))
@@ -54,6 +56,35 @@ static struct marvell_io_exp io_exp[] = {
{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
 };
 
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+   0x1, /* active interfaces */
+   /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+   { { { {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0},
+ {0x1, 0, 0, 0} },
+   SPEED_BIN_DDR_1866L,/* speed_bin */
+   BUS_WIDTH_8,/* memory_width */
+   MEM_4G, /* mem_size */
+   DDR_FREQ_800,   /* frequency */
+   0, 0,   /* cas_l cas_wl */
+   HWS_TEMP_LOW} },/* temperature */
+   5,  /* Num Of Bus Per Interface*/
+   BUS_MASK_32BIT  /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+   /* Return the board topology as defined in the board code */
+   return &board_topology_map;
+}
+
 int board_early_init_f(void)
 {
/* Configure MPP */
diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg 
b/board/Marvell/db-88f6820-gp/kwbimage.cfg
index e812454..cc05792 100644
--- a/board/Marvell/db-88f6820-gp/kwbimage.cfg
+++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg
@@ -9,4 +9,4 @@ VERSION 1
 BOOT_FROM  spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY board/Marvell/db-88f6820-gp/binary.0 005b 0068
+BINARY spl/u-boot-spl.bin 005b 0068
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 569ddfd..0ff6706 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_ARM=y
 CONFIG_TARGET_DB_88F6820_GP=y
 # CONFIG_CMD_IMLS is not set
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index a429107..73b3236 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -11,6 +11,7 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_ARMADA_XP   /* SOC Family Name */
+#define CONFIG_ARMADA_38X
 #define CONFIG_DB_88F6820_GP   /* Board target name for DDR training */
 
 #define CONFIG_SYS_L2_PL310
@@ -108,6 +109,40 @@
"fdt_high=0x1000\0" \
"initrd_high=0x1000\0"
 
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE(140 << 10)
+#define CONFIG_SPL_TEXT_BASE   0x4030
+#define CONFIG_SPL_MAX_SIZE(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR  (0x4000 + CONFIG_

[U-Boot] [PATCH v2 10/11] arm: mvebu: a38x: Use correct PEX register access macros

2015-07-20 Thread Stefan Roese
Remove the incorrect PEX macros from the DDR header. And insert the
correct ones in ctrl_pex.h instead.

Signed-off-by: Stefan Roese 

---

Changes in v2:
- New patch "arm: mvebu: a38x: Use correct PEX register access macros"

 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h  | 4 
 drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h | 5 -
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h 
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 5032759..df395bf 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -19,6 +19,10 @@
 #define MV_MISC_REGS_BASE  MISC_REGS_OFFSET
 #define SOC_CTRL_REG   (MV_MISC_REGS_BASE + 0x4)
 
+#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
+(0x4 + ((if) - 1) * 0x4000) : \
+0x8)
+#define PEX_IF_REGS_BASE(if)   (PEX_IF_REGS_OFFSET(if))
 #define PEX_CAPABILITIES_REG(if)   ((PEX_IF_REGS_BASE(if)) + 0x60)
 #define PEX_LINK_CTRL_STATUS2_REG(if)  ((PEX_IF_REGS_BASE(if)) + 0x90)
 #define PEX_CTRL_REG(if)   ((PEX_IF_REGS_BASE(if)) + 0x1a00)
diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h 
b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
index 02d8c61..7500a72 100644
--- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
@@ -421,11 +421,6 @@
 #define PCCRIR_REVID_MASK  (0xff << PCCRIR_REVID_OFFS)
 
 /* Power Management Clock Gating Control Register */
-#define MV_PEX_IF_REGS_OFFSET(pex_if)  \
-   (pex_if < 8 ? (0x4 + ((pex_if) / 4) * 0x4 + \
-  ((pex_if) % 4) * 0x4000) :   \
-(0x42000 + ((pex_if) % 8) * 0x4))
-#define PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit))
 #define POWER_MNG_CTRL_REG 0x18220
 #define PEX_DEVICE_AND_VENDOR_ID   0x000
 #define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
-- 
2.4.6

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[U-Boot] [PATCH v2 05/11] arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory

2015-07-20 Thread Stefan Roese
With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.

Signed-off-by: Stefan Roese 
---

Changes in v2: None

 arch/arm/mach-mvebu/Makefile   | 3 ++-
 arch/arm/mach-mvebu/serdes/{ => axp}/Makefile  | 0
 arch/arm/mach-mvebu/serdes/{ => axp}/board_env_spec.h  | 0
 arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_lib.c  | 0
 arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.c | 0
 arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.h | 0
 board/maxbcm/maxbcm.c  | 4 ++--
 7 files changed, 4 insertions(+), 3 deletions(-)
 rename arch/arm/mach-mvebu/serdes/{ => axp}/Makefile (100%)
 rename arch/arm/mach-mvebu/serdes/{ => axp}/board_env_spec.h (100%)
 rename arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_lib.c (100%)
 rename arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.c (100%)
 rename arch/arm/mach-mvebu/serdes/{ => axp}/high_speed_env_spec.h (100%)

diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 4f477cd..9cdbefd 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -20,5 +20,6 @@ obj-y += timer.o
 obj-$(CONFIG_SPL_BUILD) += spl.o
 obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
 
-obj-y  += serdes/
+obj-$(CONFIG_SYS_MVEBU_DDR_AXP)+= serdes/axp/
+
 endif
diff --git a/arch/arm/mach-mvebu/serdes/Makefile 
b/arch/arm/mach-mvebu/serdes/axp/Makefile
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/Makefile
rename to arch/arm/mach-mvebu/serdes/axp/Makefile
diff --git a/arch/arm/mach-mvebu/serdes/board_env_spec.h 
b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/board_env_spec.h
rename to arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_lib.c 
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/high_speed_env_lib.c
rename to arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_spec.c 
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/high_speed_env_spec.c
rename to arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c
diff --git a/arch/arm/mach-mvebu/serdes/high_speed_env_spec.h 
b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
similarity index 100%
rename from arch/arm/mach-mvebu/serdes/high_speed_env_spec.h
rename to arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
index 2fbb90c..119ba4c 100644
--- a/board/maxbcm/maxbcm.c
+++ b/board/maxbcm/maxbcm.c
@@ -11,8 +11,8 @@
 #include 
 #include 
 
-#include "../drivers/ddr/mvebu/ddr3_hw_training.h"
-#include "../arch/arm/mach-mvebu/serdes/high_speed_env_spec.h"
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-- 
2.4.6

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[U-Boot] [PATCH v2 00/11] Add SPL support including DDR init for Marvell Armada 38x

2015-07-20 Thread Stefan Roese

This patch-set adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr) into
the A38x boot image. Not linked with the main U-Boot. With this code
addition and the also included SERDES / PHY setup code, the Armada 38x
support in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.

Tested on Marvell Armada 38x DB-88F6820-GP using onboard soldered SDRAM.

Thanks,
Stefan

Changes in v2:
- New patch "arm: mvebu: Call timer_init early before PHY and DDR init"
- New patch "arm: mvebu: a38x: Use correct PEX register access macros"
- Rebased on top of current version (v2015.07)

Stefan Roese (11):
  arm: mvebu: Use default reg base address for SPL on A38x
  arm: mvebu: spl.c: Add call to board_early_init_f()
  arm: mvebu: Disable MMU before changing register base address
  Makefile: Fix mvebu build target to use SPL load and exe-address
  arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new
directory
  arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr
  arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new
directory
  arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr
  arm: mvebu: Call timer_init early before PHY and DDR init
  arm: mvebu: a38x: Use correct PEX register access macros
  arm: mvebu: db-88f6820: Add SPL support with DDR init code

 Makefile   |2 +-
 arch/arm/mach-mvebu/Makefile   |4 +-
 arch/arm/mach-mvebu/cpu.c  |   18 +
 arch/arm/mach-mvebu/include/mach/cpu.h |2 +-
 arch/arm/mach-mvebu/include/mach/soc.h |   10 +
 arch/arm/mach-mvebu/serdes/a38x/Makefile   |   10 +
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c |  347 +++
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h |   86 +
 .../serdes/a38x/high_speed_env_spec-38x.c  |  158 ++
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.c   | 2228 +
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.h   |  251 ++
 .../serdes/a38x/high_speed_topology_spec-38x.c | 1009 
 .../serdes/a38x/high_speed_topology_spec.h |  124 +
 arch/arm/mach-mvebu/serdes/a38x/seq_exec.c |  170 ++
 arch/arm/mach-mvebu/serdes/a38x/seq_exec.h |   65 +
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c  |  388 +++
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h  |  372 +++
 arch/arm/mach-mvebu/serdes/{ => axp}/Makefile  |0
 .../mach-mvebu/serdes/{ => axp}/board_env_spec.h   |0
 .../serdes/{ => axp}/high_speed_env_lib.c  |0
 .../serdes/{ => axp}/high_speed_env_spec.c |0
 .../serdes/{ => axp}/high_speed_env_spec.h |2 +-
 arch/arm/mach-mvebu/spl.c  |9 +
 arch/arm/mach-mvebu/timer.c|7 +
 board/Marvell/db-88f6820-gp/README |   18 +
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c|   31 +
 board/Marvell/db-88f6820-gp/kwbimage.cfg   |2 +-
 board/maxbcm/maxbcm.c  |4 +-
 configs/db-88f6820-gp_defconfig|1 +
 drivers/ddr/marvell/a38x/Makefile  |   19 +
 drivers/ddr/marvell/a38x/ddr3_a38x.c   |  741 ++
 drivers/ddr/marvell/a38x/ddr3_a38x.h   |   98 +
 drivers/ddr/marvell/a38x/ddr3_a38x_mc_static.h |  226 ++
 drivers/ddr/marvell/a38x/ddr3_a38x_topology.h  |   22 +
 drivers/ddr/marvell/a38x/ddr3_a38x_training.c  |   40 +
 drivers/ddr/marvell/a38x/ddr3_debug.c  | 1551 
 drivers/ddr/marvell/a38x/ddr3_hws_hw_training.c|  148 ++
 drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h|   49 +
 .../ddr/marvell/a38x/ddr3_hws_hw_training_def.h|  467 
 drivers/ddr/marvell/a38x/ddr3_hws_sil_training.h   |   17 +
 drivers/ddr/marvell/a38x/ddr3_init.c   |  852 +++
 drivers/ddr/marvell/a38x/ddr3_init.h   |  395 +++
 drivers/ddr/marvell/a38x/ddr3_logging_def.h|  101 +
 drivers/ddr/marvell/a38x/ddr3_patterns_64bit.h |  924 +++
 drivers/ddr/marvell/a38x/ddr3_topology_def.h   |   76 +
 drivers/ddr/marvell/a38x/ddr3_training.c   | 2644 
 drivers/ddr/marvell/a38x/ddr3_training_bist.c  |  289 +++
 .../marvell/a38x/ddr3_training_centralization.c|  714 ++
 drivers/ddr/marvell/a38x/ddr3_training_db.c|  652 +
 drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c   |  686 +
 drivers/ddr/marvell/a38x/ddr3_training_hw_algo.h   |   14 +
 drivers/ddr/marvell/a38x/ddr3_training_ip.h|  180 ++
 drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h   |   54 +
 .../marvell/a38x/ddr3_training_ip_centralization.h |   15 +
 drivers/ddr/marvell/a38x/ddr3_training_ip_db.h |   34 +
 drivers/ddr/marvell/a38x/ddr3_training_

[U-Boot] [PATCH v2 03/11] arm: mvebu: Disable MMU before changing register base address

2015-07-20 Thread Stefan Roese
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000. is also not
accessible, as its still locked to cache.

Signed-off-by: Stefan Roese 
---

Changes in v2: None

 arch/arm/mach-mvebu/cpu.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 9bc9f00..9496d5f 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -163,6 +163,14 @@ static void update_sdram_window_sizes(void)
}
 }
 
+void mmu_disable(void)
+{
+   asm volatile(
+   "mrc p15, 0, r0, c1, c0, 0\n"
+   "bic r0, #1\n"
+   "mcr p15, 0, r0, c1, c0, 0\n");
+}
+
 #ifdef CONFIG_ARCH_CPU_INIT
 static void set_cbar(u32 addr)
 {
@@ -172,6 +180,16 @@ static void set_cbar(u32 addr)
 
 int arch_cpu_init(void)
 {
+#ifndef CONFIG_SPL_BUILD
+   /*
+* Only with disabled MMU its possible to switch the base
+* register address on Armada 38x. Without this the SDRAM
+* located at >= 0x4000. is also not accessible, as its
+* still locked to cache.
+*/
+   mmu_disable();
+#endif
+
/* Linux expects the internal registers to be at 0xf100 */
writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-- 
2.4.6

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[U-Boot] [PATCH v2 09/11] arm: mvebu: Call timer_init early before PHY and DDR init

2015-07-20 Thread Stefan Roese
Without calling timer_init(), the xdelay() functions return immediately.
We need to call timer_init() early, so that these functions work and
the PHY and DDR init code works correctly.

Signed-off-by: Stefan Roese 

---

Changes in v2:
- New patch "arm: mvebu: Call timer_init early before PHY and DDR init"

 arch/arm/mach-mvebu/spl.c   | 2 ++
 arch/arm/mach-mvebu/timer.c | 7 +++
 2 files changed, 9 insertions(+)

diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 2df25aa..e65f6ca 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -35,6 +35,8 @@ void board_init_f(ulong dummy)
 
preloader_console_init();
 
+   timer_init();
+
/* First init the serdes PHY's */
serdes_phy_config();
 
diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c
index 40c4bc2..c516c41 100644
--- a/arch/arm/mach-mvebu/timer.c
+++ b/arch/arm/mach-mvebu/timer.c
@@ -41,6 +41,8 @@
 #define timestamp  gd->arch.tbl
 #define lastdecgd->arch.lastinc
 
+static int init_done;
+
 /* Timer reload and current value registers */
 struct kwtmr_val {
u32 reload; /* Timer reload reg */
@@ -112,6 +114,11 @@ void __udelay(unsigned long usec)
  */
 int timer_init(void)
 {
+   /* Only init the timer once */
+   if (init_done)
+   return 0;
+   init_done = 1;
+
/* load value into timer */
writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-- 
2.4.6

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[U-Boot] [PATCH 5/5] arm: mvebu: db-88f6820-gp: Add SDIO/MMC SPL boot support

2015-07-20 Thread Stefan Roese
This patch adds the configuration options to boot via SDIO/MMC on the
Marvell DB-88F6820-GP Armada A38x board. The default boot device
is still SPI NOR flash.

To enable MMC booting on this board 2 things need to be changes:
a) Change kwbimage.cfg
   BOOT_FROM   sdio
b) In the config header select
   #define CONFIG_SPL_BOOT_DEVICE   SPL_BOOT_SDIO_MMC_CARD

The generated image needs to be copied to the first bootable MMC
partition:

dd if=u-boot-spl.kwb of=/dev/sdX1

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
Cc: Dirk Eibach 
---
 include/configs/db-88f6820-gp.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 73b3236..739c2bf 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -110,6 +110,17 @@
"initrd_high=0x1000\0"
 
 /* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH  - Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD  - Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH 1
+#define SPL_BOOT_SDIO_MMC_CARD 2
+#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
+
 /* Defines for SPL */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_SIZE(140 << 10)
@@ -131,6 +142,7 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
 
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
 /* SPL related SPI defines */
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
@@ -138,6 +150,22 @@
 #define CONFIG_SPL_SPI_BUS 0
 #define CONFIG_SPL_SPI_CS  0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR(CONFIG_SYS_U_BOOT_OFFS 
/ 512)
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER  0x0018  /* in SDRAM */
+#endif
+#endif
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SYS_MVEBU_DDR_A38X
-- 
2.4.6

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[U-Boot] [PATCH 1/5] arm: mvebu: Add SPL SDIO/MMC boot support

2015-07-20 Thread Stefan Roese
This patch adds basic SDIO/MMC booting support to MVEBU SoC's. Since
I don't know of a way to test the boot-device upon runtime, this patch
hardcodes the spl_boot_device instead.

Tested on Marvell DB-88F6820-GP board.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
Cc: Dirk Eibach 
---
 arch/arm/mach-mvebu/spl.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index e65f6ca..af61ded 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -14,10 +14,21 @@ DECLARE_GLOBAL_DATA_PTR;
 
 u32 spl_boot_device(void)
 {
-   /* Right now only booting via SPI NOR flash is supported */
+#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
return BOOT_DEVICE_SPI;
+#endif
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+   return BOOT_DEVICE_MMC1;
+#endif
 }
 
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+   return MMCSD_MODE_RAW;
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
/* Set global data pointer */
-- 
2.4.6

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