On 06/29/2015 12:50 AM, Alison Wang wrote: > From: Zhichun Hua <zhichun....@freescale.com> > > When final MMU table is setup in DDR, TCR attributes must match > those of the memroy for cacheability and shareability. > > Signed-off-by: Zhichun Hua <zhichun....@freescale.com> > Signed-off-by: York Sun <york...@freescale.com>
Applied to u-boot-fsl-qoriq master branch. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
