Re: [U-Boot] Special memory test Question

2008-10-09 Thread Wolfgang Denk
Dear "Martin Jarman",

In message <[EMAIL PROTECTED]> you wrote:
> I have an Atmel atngw100 development board and a standalone application that 
> crashes within 10 to 30 seconds of starting.  I have just discovered that 

Are other applications (including U-Boot itself and maybe Linux)
running fine?

> the special memory test described in 5.9.2.10 of DULG also crashes the board 
> after a similar amount of time.
> 
> With a fresh copy of the Atmel's release of the U-boot binary installed 
> (version 1.1.3-00248-gae9bc0c),
> I press SPACE to abort autoboot, and then type:
> 
> loop .b 1040
> 
> (1040 is an address in SDRAM)
> Nothing happens for about 20 Seconds, then there is an 'Unhandled exception' 
> and the processor reboots.

Is there by chance any watchdog on your system that mith have such a
timeout / reset period?

Best regards,

Wolfgang Denk

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[U-Boot] ARM/Versatile - bootup

2008-10-09 Thread Roman Mashak
Hello

Studying the ARM/Versatile port of U-Boot in order to understand
booting and initialization nuances.

As per documentation from http://infocenter.arm.com/  SDRAM on this
platform is selected by CS#0 and gets mapped in 0x_ -
0x0800_. Versatile configuration defines TEXT_BASE=0x0100_, so
it is 16Mb away from 0x0; Linux port of Versatile defines loading
address of the kernel as 0x_8000, resulting in 32kB gap form the
beginning of RAM.

I understand that 16Mb gap is to let kernel image to fit in RAM, but
isn't it too large, seems a waste of space to me? Then why do we need
to keep 32KB space, what's the point?

As U-Boot image usually occupies ~200KB, wouldn't it be easier to
allocate ~8Mb room, which would be quite enough for the U-Boot, its
environment, malloc area, stack etc., Linux kKernel then starts and
reclaims the memory of U-Boot.

Would appreciate if someone explains me this nuance. Thanks in advance!

-- 
Roman Mashak
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[U-Boot] RV: Problem with flash on a MPC5200B board

2008-10-09 Thread txema lopez
Hy Sylvain,

I have a custom Lite5200B based board with two S29GL128 expansion flash
in two banks (CS0/CSBOOT, CS1) in 8 bit mode.
This is my flash configuration in my config/ file. AFAIK the
U-Boot CFI driver detects the flash chip mode, so the configuration is
quite simple.

#define CFG_MAX_FLASH_SECT  512 /* max num of sects on one chip
*/

#define CFG_FLASH_ERASE_TOUT24  /* Flash Erase Timeout (in ms)
*/
#define CFG_FLASH_WRITE_TOUT500 /* Flash Write Timeout (in ms)
*/


#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_USE_BUFFER_WRITE

The chip select configuration register of both banks could be important.

#define CFG_BOOTCS_CFG  0x00021800
#define CFG_CS1_CFG 0x00021800

Best regards,
Txema
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Re: [U-Boot] Run hello world with Uboot !

2008-10-09 Thread thaoth

Hi Nobuhiro,
I have tested your patch and it works well.

Thank you for great work.
-- 
View this message in context: 
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Sent from the Uboot - Users mailing list archive at Nabble.com.

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Re: [U-Boot] [patch 0/2] Some more USB-OHCI bugfixes

2008-10-09 Thread Stelian Pop
Le mercredi 08 octobre 2008 à 10:54 +0200, Remy Bohmer a écrit :

> I made it 2 seperate patches. The 1st of this series is fully tested and 
> correct
> on at least the AT91SAM9261 cores. I hope it fixes the known problems on
> AT91SAM9263 (and other) cores also, maybe Stelian can verify this.
> If it does not help on sam9263, it should not make it worse either...

It still doesn't help (on AT91SAM9263):

usb start
(Re)start USB...
USB:   scanning bus for devices... New Device 0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x40
set address 1
usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x12
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x9
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x19
get_conf_no 0 Result 25, wLength 25
if 0, ep 0
##EP epmaxpacketin[1] = 2
set configuration 1
usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0
new device strings: Mfr=0, Product=1, SerialNumber=0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 
0xFF
USB device number 1 default language ID 0x409
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 
length 0xFF
Manufacturer 
Product  OHCI Root Hub
SerialNumber 
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 
0x4
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 
0x9
usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x2 length 0x0
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 0x4
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 0x4
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x2 length 
0x0
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x2 length 0x0
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 0x4
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x2 length 
0x0
New Device 1
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x40
ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or 
did
not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or 
did
not provide a handshake (OUT) (5)
usb_new_device: usb_get_descriptor() failed
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x1 index 0x2 length 0x0
2 USB Device(s) found
   scanning bus for storage devices... 0 Storage Device(s) found
U-Boot> 

-- 
Stelian Pop <[EMAIL PROTECTED]>

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Re: [U-Boot] [PATCH] mpc83xx: fix PCI scan hang on the standaloneMPC837xE-MDS boards

2008-10-09 Thread Anton Vorontsov
Hi,

On Thu, Oct 09, 2008 at 01:01:04PM +0800, Liu Dave-R63238 wrote:
> Hello Anton,
> 
> 1)
> I strongly suggest you use the hardware reset configuration word from
> flash,
> not from FPGA.

Well, then we always have to re-flash the u-boot for every change
of the SGMII/RGMII setup... not very convenient. :-/

Other option is to use I2C EEPROM as a HRCW source, and change
SGMII/RGMII setup there. But this feels quite hackish... Never tried
this approach though.

> You can set the PCI host and internal arbiter enabled in the HRCW in
> flash
> to avoid these issue.

Luckily there is easy workaround for this problem.

> 2)
> Also, I strongly suggest you use the production 837xEMDS pilot rev2.05
> board.
> Because the early 837xEMDS board is missing PCI bus pull up resistors.

Much thanks for the information.

-- 
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Jean-Christophe PLAGNIOL-VILLARD
On 10:54 Wed 08 Oct , Remy Bohmer wrote:
> The max packet size is encoded as 0,1,2,3 for 8,16,32,64 bytes.
> At some places directly 8,16,32,64 was used instead of the encoded
> value. Made a enum for the options to make this more clear and to help
> preventing similar errors in the future.
> 
> After fixing this bug it became clear that another bug existed where
> the 'pipe' is and-ed with PIPE_* flags, where it should have been
> 'usb_pipetype(pipe)', or even better usb_pipeint(pipe).
> 
> Also removed the triple 'get_device_descriptor' sequence, it has no use,
> and Windows nor Linux behaves that way.
> There is also a poll going on with a timeout when usb_control_msg() fails.
> However, the poll is useless, because the flag will never be set on a error,
> because there is no code that runs in a parallel that can set this flag.
> Changed this to something more logical.
> 
> Tested on AT91SAM9261ek and compared the flow on the USB bus to what
> Linux is doing. There is no difference anymore in the early initialisation
> sequence.
> 
> Signed-off-by: Remy Bohmer <[EMAIL PROTECTED]>
> ---
>  common/usb.c   |   50 
> +++--
>  drivers/usb/usb_ohci.c |   14 +
>  include/usb.h  |   16 ---
>  3 files changed, 43 insertions(+), 37 deletions(-)
> 
> Index: u-boot-git-22092008/common/usb.c
> ===
> --- u-boot-git-22092008.orig/common/usb.c 2008-10-08 10:51:49.0 
> +0200
> +++ u-boot-git-22092008/common/usb.c  2008-10-08 10:51:50.0 +0200
> @@ -196,15 +196,14 @@ int usb_control_msg(struct usb_device *d
>   if (timeout == 0)
>   return (int)size;
>  
> - while (timeout--) {
> - if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC))
> - break;
> - wait_ms(1);
> - }
>   if (dev->status == 0)
>   return dev->act_len;
please add {} to if too or remove the else
> - else
> + else {
> + /* Let's wait a while for the timeout to elaps.
> +  * it has no real use, but it keeps the interface happy. */
> + wait_ms(timeout);
>   return -1;
> + }
>  }
>  
>  /*---
> @@ -442,14 +441,14 @@ int usb_get_configuration_no(struct usb_
>  
>  
>   config = (struct usb_config_descriptor *)&buffer[0];
> - result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 8);
>   struct usb_device *parent = dev->parent;
> @@ -809,20 +805,22 @@ int usb_new_device(struct usb_device *de
>  
>   desc = (struct usb_device_descriptor *)tmpbuf;
>   dev->descriptor.bMaxPacketSize0 = 64;   /* Start off at 64 bytes  */
> - dev->maxpacketsize = 64;/* Default to 64 byte max packet size */
> + /* Default to 64 byte max packet size */
> + dev->maxpacketsize = PACKET_SIZE_64;
>   dev->epmaxpacketin [0] = 64;
>   dev->epmaxpacketout[0] = 64;
> - for (j = 0; j < 3; ++j) {
> - err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
> - if (err < 0) {
> - USB_PRINTF("usb_new_device: 64 byte descr\n");
> - break;
> - }
> +
> + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
> + if (err < 0) {
> + USB_PRINTF("usb_new_device: usb_get_descriptor() failed\n");
> + return 1;
>   }
> +
> Index: u-boot-git-22092008/include/usb.h
> ===
> --- u-boot-git-22092008.orig/include/usb.h2008-10-08 10:51:45.0 
> +0200
> +++ u-boot-git-22092008/include/usb.h 2008-10-08 10:51:50.0 +0200
> @@ -129,6 +129,13 @@ struct usb_config_descriptor {
>   struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
>  } __attribute__ ((packed));
>  
> +enum {
> + /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
> + PACKET_SIZE_8   = 0,
> + PACKET_SIZE_16  = 1,
> + PACKET_SIZE_32  = 2,
> + PACKET_SIZE_64  = 3,
why not diectly the value?
> +};
>  
>  struct usb_device {
>   int devnum; /* Device number on USB bus */
> @@ -137,9 +144,12 @@ struct usb_device {
>   char prod[32];  /* product */
>   char serial[32];/* serial number */
>  
> - int maxpacketsize;  /* Maximum packet size; encoded as 
> 0,1,2,3 = 8,16,32,64 */

Best Regards,
J.
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[U-Boot] [PATCH] Fix USB init sequence for the lwmon5 board.

2008-10-09 Thread sascha.laue
From: Sascha Laue <[EMAIL PROTECTED]>

Signed-off-by: Sascha Laue <[EMAIL PROTECTED]>
---
 board/lwmon5/lwmon5.c |   44 +++-
 1 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 8975bfd..5e310f4 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -145,7 +145,7 @@ int misc_init_r(void)
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
-   unsigned long sdr0_pfc1;
+   unsigned long sdr0_pfc1, sdr0_srst;
 
/*
 * FLASH stuff...
@@ -207,6 +207,15 @@ int misc_init_r(void)
/*
 * USB suff...
 */
+
+   /* Reset USB peripherie */
+   mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D );
+mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI \
+   | SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 \
+   | SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40 );
+
+   udelay(100);
+
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
@@ -234,13 +243,38 @@ int misc_init_r(void)
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
-   /*
-* Clear resets
-*/
+   /* the 440EPx controllers need this sequence to initiate the EHCI */
+   
+   /* deassert reset to USBPHY */
+   mfsdr(SDR0_SRST1, sdr0_srst);
+   sdr0_srst &= ~SDR0_SRST1_USB20PHY;
+   mtsdr(SDR0_SRST1, sdr0_srst);
+
udelay (1000);
-   mtsdr(SDR0_SRST1, 0x);
+
+   /* deassert reset to HOST*/
+   mfsdr(SDR0_SRST1, sdr0_srst);
+   sdr0_srst &= ~( SDR0_SRST0_USB2H );
+   mtsdr(SDR0_SRST1, sdr0_srst);
+
+   udelay(4000);
+
+   /* deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1, OPB2PLB40 cores */
+   mfsdr(SDR0_SRST1, sdr0_srst);
+   sdr0_srst &= ~( SDR0_SRST1_OPBA1| \ 
+   SDR0_SRST1_P4OPB0   | \
+   SDR0_SRST1_OPBA2| \
+   SDR0_SRST1_PLB42OPB1| \
+   SDR0_SRST1_OPB2PLB40);
+   mtsdr(SDR0_SRST1, sdr0_srst);
+
udelay (1000);
+   
+   /* deassert all other resets */
mtsdr(SDR0_SRST0, 0x);
+   mtsdr(SDR0_SRST1, 0x);
+
+   udelay(1000);
 
printf("USB:   Host(int phy) Device(ext phy)\n");
 
-- 
1.5.2.4

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Re: [U-Boot] [PATCH] Fix USB init sequence for the lwmon5 board.

2008-10-09 Thread Wolfgang Denk
Dear [EMAIL PROTECTED],

In message <[EMAIL PROTECTED]> you wrote:
> From: Sascha Laue <[EMAIL PROTECTED]>

Please remove this from the message body.

> @@ -207,6 +207,15 @@ int misc_init_r(void)
>   /*
>* USB suff...
>*/
> +
> + /* Reset USB peripherie */
> + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D );
> +mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI \

Indentation by TAB, please.


Viele Grüße,

Wolfgang Denk

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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Wolfgang Denk
Dear Jean-Christophe PLAGNIOL-VILLARD,

In message <[EMAIL PROTECTED]> you wrote:
>
> > if (dev->status == 0)
> > return dev->act_len;
> please add {} to if too or remove the else
> > -   else
> > +   else {
> > +   /* Let's wait a while for the timeout to elaps.
> > +* it has no real use, but it keeps the interface happy. */
> > +   wait_ms(timeout);
> > return -1;
> > +   }

Good catch.

Actually the "else" should be removed.

Best regards,

Wolfgang Denk

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[U-Boot] Linux does not boot from flash, but will from RAM

2008-10-09 Thread Curran, Tom
I am using u-boot on the Avnet V5FX30T (Xilinx FPGA, PPC440) eval board
to boot a Linux 2.6.27-rc4 kernel.  I can use u-boot to tftp the kernel,
ramdisk, and device tree blob to RAM and boot from there OK.  I copied
the kernel, ramdisk and blob to flash and verified those elements were
programmed in flash correctly with 'iminfo', but when I try to boot from
flash the boot process hangs at "Loading Ramdisk to 03d59000, end
03ec8f20 ... OK".  At this point u-boot will restart (after a
WDT-induced reset?) after a few minutes.  Interestingly enough, I can
boot from flash IF the ramdisk is already in RAM with a "bootm
$(kernel_flash_addr) $(ramdisk_ram_addr) $(blob_flash_addr)".  This
leads me to believe something is going wrong in the copying of the
ramdisk from flash to RAM.  Perhaps I am doing something wrong or missed
a step somewhere?  I have read the FAQ, but have not found anything
relevant.  Perhaps someone here has had this problem too and can offer a
solution?  Any help is appreciated.  Many thanks in advance!

--Tom
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Re: [U-Boot] [PATCH] Fix USB init sequence for the lwmon5 board.

2008-10-09 Thread Matthias Fuchs
On Thursday 09 October 2008 13:25, [EMAIL PROTECTED] wrote:
> From: Sascha Laue <[EMAIL PROTECTED]>
> 
> Signed-off-by: Sascha Laue <[EMAIL PROTECTED]>
> ---
>  board/lwmon5/lwmon5.c |   44 +++-
>  1 files changed, 39 insertions(+), 5 deletions(-)
> 
> diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
> index 8975bfd..5e310f4 100644
> --- a/board/lwmon5/lwmon5.c
> +++ b/board/lwmon5/lwmon5.c
> @@ -145,7 +145,7 @@ int misc_init_r(void)
>   u32 reg;
>   unsigned long usb2d0cr = 0;
>   unsigned long usb2phy0cr, usb2h0cr = 0;
> - unsigned long sdr0_pfc1;
> + unsigned long sdr0_pfc1, sdr0_srst;
>  
>   /*
>* FLASH stuff...
> @@ -207,6 +207,15 @@ int misc_init_r(void)
>   /*
>* USB suff...
>*/
> +
> + /* Reset USB peripherie */
> + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D );
> +mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI \
> + | SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 \
> + | SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40 );
> +
I think these mtsdrs are not needed. These bits are all set after CPU reset.
So setting them again makes no sense.

But this reset sequence is full of magic at all. So I could imagine that it's 
needed :-)

Matthias

> + udelay(100);
> +
>   /* SDR Setting */
>   mfsdr(SDR0_PFC1, sdr0_pfc1);
>   mfsdr(SDR0_USB0, usb2d0cr);
> @@ -234,13 +243,38 @@ int misc_init_r(void)
>   mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
>   mtsdr(SDR0_USB2H0CR, usb2h0cr);
>  
> - /*
> -  * Clear resets
> -  */
> + /* the 440EPx controllers need this sequence to initiate the EHCI */
> + 
> + /* deassert reset to USBPHY */
> + mfsdr(SDR0_SRST1, sdr0_srst);
> + sdr0_srst &= ~SDR0_SRST1_USB20PHY;
> + mtsdr(SDR0_SRST1, sdr0_srst);
> +
>   udelay (1000);
> - mtsdr(SDR0_SRST1, 0x);
> +
> + /* deassert reset to HOST*/
> + mfsdr(SDR0_SRST1, sdr0_srst);
> + sdr0_srst &= ~( SDR0_SRST0_USB2H );
> + mtsdr(SDR0_SRST1, sdr0_srst);
> +
> + udelay(4000);
> +
> + /* deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1, OPB2PLB40 cores */
> + mfsdr(SDR0_SRST1, sdr0_srst);
> + sdr0_srst &= ~( SDR0_SRST1_OPBA1| \ 
> + SDR0_SRST1_P4OPB0   | \
> + SDR0_SRST1_OPBA2| \
> + SDR0_SRST1_PLB42OPB1| \
> + SDR0_SRST1_OPB2PLB40);
> + mtsdr(SDR0_SRST1, sdr0_srst);
> +
>   udelay (1000);
> + 
> + /* deassert all other resets */
>   mtsdr(SDR0_SRST0, 0x);
> + mtsdr(SDR0_SRST1, 0x);
> +
> + udelay(1000);
>  
>   printf("USB:   Host(int phy) Device(ext phy)\n");
>  

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[U-Boot] [OFF TOPIC] Linux Physmap drivers

2008-10-09 Thread Alemao
Hi all,

Im trying to use a physmap driver for NOR and NAND flash devices.

With NOR, everything ok. It uses CFI driver.

The problem is with NAND, cause it is connected at Freescale
LocalBus UPM, and at a first look, the UPM driver is loading after the
physmap (lines 14-15 in kernel output)

Here some outputs from the board:

Bootloader (U-Boot 1.2.0):

CPU:   e300c1, MPC8360E, Rev: 21 at 499.999 MHz, CSB:  333 MHz
Board: MPC8360KTX
I2C:   ready
DDR RAM: 128 MB
FLASH: 16 MB
NAND:  64 MiB
In:serial
Out:   serial
Err:   serial


Kernel (linux-2.6.17):

1   physmap nor flash device: 100 at ff00
2   NOR flash: Found 1 x16 devices at 0x0 in 16-bit bank
3Amd/Fujitsu Extended Query Table at 0x0040
4number of CFI chips: 1
5   Using physmap partition definition
6   Creating 6 MTD partitions on "NOR flash":
7   0x-0x0004 : "u-boot"
8   0x0004-0x0006 : "env."
9   0x0006-0x0008 : "sys"
10  0x0008-0x000c : "logs"
11  0x000c-0x0086 : "admin"
12  0x0086-0x0100 : "users"
13
14  physmap nand flash device: 400 at 6000
15  UPM: User-Programmable Machine NAND driver


Device Tree Source:

[EMAIL PROTECTED] {
compatible = "fsl,board-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = ;// BRx, ORx, etc

ranges = <0 0 ff00 100 // nor flash,  16 MB
  1 0 6000 400>;   // nand flash, 64 MB

[EMAIL PROTECTED],0 {
compatible = "atmel,29LV256", "cfi-flash";
reg = <0 0 100>;
bank-width = <2>;
device-width = <1>;
};

[EMAIL PROTECTED],0 {
compatible = "stmicro,NAND512W3A", "fsl,upm-nand";
reg = <1 0 400>;   //reg = <1 0 1>;
width = <1>;
upm = "A";
upm-addr-offset = <16>;
upm-cmd-offset = <8>;
gpios = <4 18>;
gpio-parent = <&qe_pio>;
wait-pattern;
wait-write;
};
};

The CFI driver is at linux/drivers/mtd/chips
The UPM driver is at linux/drivers/mtd/nand

So, how can I load the UPM driver before physmap?

Thanks in advance,

--
Alemao
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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Markus Klotzbücher
On Thu, Oct 09, 2008 at 03:19:22PM +0200, Wolfgang Denk wrote:
> Dear Jean-Christophe PLAGNIOL-VILLARD,
> 
> In message <[EMAIL PROTECTED]> you wrote:
> >
> > >   if (dev->status == 0)
> > >   return dev->act_len;
> > please add {} to if too or remove the else
> > > - else
> > > + else {
> > > + /* Let's wait a while for the timeout to elaps.
> > > +  * it has no real use, but it keeps the interface happy. */
> > > + wait_ms(timeout);
> > >   return -1;
> > > + }
> 
> Good catch.

Quite honest, I think this is *way* to pedantic. I'd really prefer to
let people who are contributing significantly do their work instead of
bugging them with such rare coding style violations.

> Actually the "else" should be removed.

How so?

Best regards
Markus

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Re: [U-Boot] [PATCH v2 4/6] Restore alphabetic ordering in common/Makefile

2008-10-09 Thread Bartlomiej Sieka
Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 14:58 Wed 08 Oct , Bartlomiej Sieka wrote:
>> [dropped [EMAIL PROTECTED] and [EMAIL PROTECTED] from CC]
>>
>> Hi Jean-Christophe,
>>
>> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 15:26 Wed 01 Oct , Bartlomiej Sieka wrote:
 Signed-off-by: Bartlomiej Sieka <[EMAIL PROTECTED]>
 ---
  common/Makefile |2 +-
  1 files changed, 1 insertions(+), 1 deletions(-)

 diff --git a/common/Makefile b/common/Makefile
 index 8bddf8e..bb6655d 100644
>>> Please base your patch on u-boot-arm/next
>> Sorry, I'm not sure here -- the patch makes a simple change to
>> common/Makefile, so why would re-basing to arm/next be necessary?
>>  
>>> and I've plane to split it in a subsection to not have it in the middle of 
>>> the
>>> command
>> Is this comment related to the patch? Could you please elaborate?
> I've split the Makefile in 4 subgroup
> # core
> # core command
> # environment
> # command
> 
> It will be good to regroup non command file to
> # others
> or something like this

Yes, this makes sense in general. So let's skip this patch (4/6) for now
and have the auto-update feature merged first. Makefile clean-ups and
rearrangements can be done later on.

Regards,
Bartlomiej Sieka
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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Stefan Roese
On Thursday 09 October 2008, Markus Klotzbücher wrote:
> On Thu, Oct 09, 2008 at 03:19:22PM +0200, Wolfgang Denk wrote:
> > Dear Jean-Christophe PLAGNIOL-VILLARD,
> >
> > In message <[EMAIL PROTECTED]> you wrote:
> > > > if (dev->status == 0)
> > > > return dev->act_len;
> > >
> > > please add {} to if too or remove the else
> > >
> > > > -   else
> > > > +   else {
> > > > +   /* Let's wait a while for the timeout to elaps.
> > > > +* it has no real use, but it keeps the interface 
> > > > happy. */
> > > > +   wait_ms(timeout);
> > > > return -1;
> > > > +   }
> >
> > Good catch.
>
> Quite honest, I think this is *way* to pedantic. I'd really prefer to
> let people who are contributing significantly do their work instead of
> bugging them with such rare coding style violations.

ACK from me here. "Minor" coding style violations like these braces issue or 
too long lines should not delay patches.

> > Actually the "else" should be removed.
>
> How so?

Because of the "return dev->act_len;" above. :)

Best regards,
Stefan

=
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Re: [U-Boot] [patch 0/2] Some more USB-OHCI bugfixes

2008-10-09 Thread Stelian Pop
Le jeudi 09 octobre 2008 à 11:51 +0200, Remy Bohmer a écrit :

> Looking at the logging, it seems that communication to the root hub
> itself is working properly, but everything to the bus fails.
> Are you sure that _all_ peripheral clocks are running? Are you sure
> that the 48MHz clock is running (derived from PLLB), and configured
> properly?
> This clock is required, but is usually _not_ configured by U-boot (for
> the AT91SAM series) but by the bootstrap code. You could check if the
> current settings for PLLB matches the settings done by Linux.

Bingo ! The bootstrap code does appear to setup some wrong values for
the PLLB multiplier/divisor. Once I set up the PLLB to use the same
values as Linux, USB starts to work ! Yay !

Still, only one of my three USB sticks works, the other two exhibit some
error, so maybe there is something additional to be done:

The working USB stick says:

usb start
(Re)start USB...
USB:   scanning bus for devices... New Device 0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x40
set address 1
usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x12
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x9
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x19
get_conf_no 0 Result 25, wLength 25
if 0, ep 0
##EP epmaxpacketin[1] = 2
set configuration 1
usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0
new device strings: Mfr=0, Product=1, SerialNumber=0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 
0xFF
USB device number 1 default language ID 0x409
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 
length 0xFF
Manufacturer 
Product  OHCI Root Hub
SerialNumber 
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 
0x4
usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 
0x9
usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x2 length 0x0
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x1 length 
0x0
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 
0x0
New Device 1
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x40
usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4
usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 
0x0
set address 2
usb_control_msg: request: 0x5, requesttype: 0x0, value 0x2 index 0x0 length 0x0
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 
0x12
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x9
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 
0x27
get_conf_no 0 Result 39, wLength 39
if 0, ep 0
if 0, ep 1
if 0, ep 2
##EP epmaxpacketout[1] = 64
##EP epmaxpacketin[2] = 64
##EP epmaxpacketin[3] = 64
set configuration 1
usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0
new device strings: Mfr=1, Product=2, SerialNumber=3
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 
0xFF
USB device number 2 default language ID 0x409
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 
length 0xFF
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x409 
length 0xFF
usb_control_msg: request: 0x6, requesttype: 0x80, value 0x303 index 0x409 
length 0xFF
Manufacturer P Technology
Product  USB Mass Storage Device
SerialNumber 00058D
usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 0x4
2 USB Device(s) found
   scanning bus for storage devices... usb_control_msg: request: 0xFF, 
requesttype: 0x21, value 0x0 index 0x0 length 0x0
usb_control_msg: request: 0x1, requesttype: 0x2, value 0x0 index 0x82 length 0x0
usb_control_msg: request: 0x1, requesttype: 0x2, value 0x0 index 0x1 length 0x0
1 Storage Device(s) found
U-Boot> usb storage
  Device 0: Vendor: UT163Rev: 0.00 Prod: USB Flash Disk  
Type: Removable Hard Disk
Capacity: 963.9 MB = 0.9 GB (1974271 x 512)
U-Boot> 

And the failing one says:

usb start
(Re)start USB...
USB:   scanning bus for devices... New Device 0
usb_c

Re: [U-Boot] [patch 0/2] Some more USB-OHCI bugfixes

2008-10-09 Thread Remy Bohmer
Hello Stelian,

> It still doesn't help (on AT91SAM9263):

grmbl...
I believe this has to be debugged on this specific controller, since I
do not have one here I cannot debug it myself... :-(
At least we made a large step forward on many other cores, but
apparently we are not there yet for all cores...

Looking at the logging, it seems that communication to the root hub
itself is working properly, but everything to the bus fails.
Are you sure that _all_ peripheral clocks are running? Are you sure
that the 48MHz clock is running (derived from PLLB), and configured
properly?
This clock is required, but is usually _not_ configured by U-boot (for
the AT91SAM series) but by the bootstrap code. You could check if the
current settings for PLLB matches the settings done by Linux.

Good luck... (I hope to hear from you if you get it working, or if I
can do anything to assist you on this)


Kind Regards,

Remy


>
> usb start
> (Re)start USB...
> USB:   scanning bus for devices... New Device 0
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 
> length 0x40
> set address 1
> usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 
> 0x0
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 
> length 0x12
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 
> length 0x9
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 
> length 0x19
> get_conf_no 0 Result 25, wLength 25
> if 0, ep 0
> ##EP epmaxpacketin[1] = 2
> set configuration 1
> usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 
> 0x0
> new device strings: Mfr=0, Product=1, SerialNumber=0
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 
> length 0xFF
> USB device number 1 default language ID 0x409
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 
> length 0xFF
> Manufacturer
> Product  OHCI Root Hub
> SerialNumber
> usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 
> length 0x4
> usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 
> length 0x9
> usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 
> 0x4
> usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 
> 0x0
> usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x2 length 
> 0x0
> usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 
> 0x4
> usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 
> 0x4
> usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 
> 0x4
> usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x2 length 
> 0x0
> usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x2 length 
> 0x0
> usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 
> 0x4
> usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x2 length 
> 0x0
> New Device 1
> usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 
> length 0x40
> ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) 
> or did
> not provide a handshake (OUT) (5)
> ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) 
> or did
> not provide a handshake (OUT) (5)
> usb_new_device: usb_get_descriptor() failed
> usb_control_msg: request: 0x1, requesttype: 0x23, value 0x1 index 0x2 length 
> 0x0
> 2 USB Device(s) found
>   scanning bus for storage devices... 0 Storage Device(s) found
> U-Boot>
>
> --
> Stelian Pop <[EMAIL PROTECTED]>
>
>
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[U-Boot] [PATCH] Introduce CONFIG_4xx_HAS_OPB

2008-10-09 Thread Josh Boyer
The lib_ppc/board.c file will fill in the bi_opbfreq variable
in the bd_t structure for PowerPC 4xx platforms.  However, it
currently seems to be coupled together with the bi_pci_busfreq
variable under a series of ifdefs for particular CPU types.
As a result, it is rather easy to miss getting bi_opbfreq
populated on boards when doing a board port.  This is the
case for CONFIG_405EZ for example.

This patch introduces a CONFIG_4xx_HAS_OPB option that is
set to indicate that the platform uses that variable in the
bd_t structure.  It decouples this from the PCI bus setting
and sets is properly for CPUs that have this defined.

Signed-off-by: Josh Boyer <[EMAIL PROTECTED]>

diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 54ac01d..6673cd4 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -112,12 +112,14 @@ typedef struct bd_info {
unsigned char   bi_enet3addr[6];
 #endif
 
+#if defined(CONFIG_4xx_HAS_OPB)
+   unsigned intbi_opbfreq; /* OPB clock in Hz */
+#endif
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
 defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 defined(CONFIG_460EX) || defined(CONFIG_460GT)
-   unsigned intbi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
 #endif
 #if defined(CONFIG_NX823)
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index e216663..be6696d 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -46,6 +46,15 @@
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 #endif
 
+/* Configure the OPB variable */
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
+defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_4xx_HAS_OPB
+#endif
+
 /* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
 #if defined(CONFIG_405EX) || \
 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index c02ac62..977fc19 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -611,10 +611,12 @@ void board_init_f (ulong bootflag)
 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
bd->bi_pci_busfreq = get_PCI_freq ();
-   bd->bi_opbfreq = get_OPB_freq ();
 #elif defined(CONFIG_XILINX_405)
bd->bi_pci_busfreq = get_PCI_freq ();
 #endif
+#if defined(CONFIG_4xx_HAS_OPB)
+   bd->bi_opbfreq = get_OPB_freq ();
+#endif
 #endif
 
debug ("New Stack Pointer is: %08lx\n", addr_sp);
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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Markus Klotzbücher
On Thu, Oct 09, 2008 at 04:59:54PM +0200, Stefan Roese wrote:
> On Thursday 09 October 2008, Markus Klotzbücher wrote:
> > On Thu, Oct 09, 2008 at 03:19:22PM +0200, Wolfgang Denk wrote:
> > > Dear Jean-Christophe PLAGNIOL-VILLARD,
> > >
> > > In message <[EMAIL PROTECTED]> you wrote:
> > > > >   if (dev->status == 0)
> > > > >   return dev->act_len;
> > > >
> > > > please add {} to if too or remove the else
> > > >
> > > > > - else
> > > > > + else {
> > > > > + /* Let's wait a while for the timeout to elaps.
> > > > > +  * it has no real use, but it keeps the interface 
> > > > > happy. */
> > > > > + wait_ms(timeout);
> > > > >   return -1;
> > > > > + }
> > >
> > > Good catch.
> >
> > Quite honest, I think this is *way* to pedantic. I'd really prefer to
> > let people who are contributing significantly do their work instead of
> > bugging them with such rare coding style violations.
> 
> ACK from me here. "Minor" coding style violations like these braces issue or 
> too long lines should not delay patches.
> 
> > > Actually the "else" should be removed.
> >
> > How so?
> 
> Because of the "return dev->act_len;" above. :)

Ahh, I see!
:-)

Best regards
Markus

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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Jerry Van Baren
Stefan Roese wrote:
> On Thursday 09 October 2008, Markus Klotzbücher wrote:
>> On Thu, Oct 09, 2008 at 03:19:22PM +0200, Wolfgang Denk wrote:
>>> Dear Jean-Christophe PLAGNIOL-VILLARD,
>>>
>>> In message <[EMAIL PROTECTED]> you wrote:
>   if (dev->status == 0)
>   return dev->act_len;
 please add {} to if too or remove the else

> - else
> + else {
> + /* Let's wait a while for the timeout to elaps.
> +  * it has no real use, but it keeps the interface happy. */
> + wait_ms(timeout);
>   return -1;
> + }
>>> Good catch.
>> Quite honest, I think this is *way* to pedantic. I'd really prefer to
>> let people who are contributing significantly do their work instead of
>> bugging them with such rare coding style violations.
> 
> ACK from me here. "Minor" coding style violations like these braces issue or 
> too long lines should not delay patches.
> 
>>> Actually the "else" should be removed.
>> How so?
> 
> Because of the "return dev->act_len;" above. :)
> 
> Best regards,
> Stefan

Also agreed.

While we are painting the bike shed, I would suggest a better structure 
would be to flip the conditional so that the normal flow goes out the 
end of the module and the abnormal flow returns early.  (The comment is 
also a coding standards violation for multiline comments and has two 
typos in it.)

if (dev->status != 0) {
/*
 * Let's wait a while for the timeout to elapse.
 * It has no real use, but it keeps the interface happy.
 */
wait_ms(timeout);
return -1;
}

return dev->act_len;
}

Hmmm, looking at the original changeset, my above point has some 
validity.  While we (gcc) can do a flow analysis and recognize that 
something will be returned in all cases due to the if/else, it doesn't 
jump out at a casual observation of the code.  On the surface, the code 
looks like it can fall off the end of the function (e.g. return "void"), 
which would be very wrong.  Making it obvious that the Right Thing[tm] 
is returned: priceless.

> --- u-boot-git-22092008.orig/common/usb.c 2008-10-08 10:51:49.0 
> +0200
> +++ u-boot-git-22092008/common/usb.c  2008-10-08 10:51:50.0 +0200
> @@ -196,15 +196,14 @@ int usb_control_msg(struct usb_device *d
>   if (timeout == 0)
>   return (int)size;
> 
> - while (timeout--) {
> - if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC))
> - break;
> - wait_ms(1);
> - }
>   if (dev->status == 0)
>   return dev->act_len;
> - else
> + else {
> + /* Let's wait a while for the timeout to elaps.
> +  * it has no real use, but it keeps the interface happy. */
> + wait_ms(timeout);
>   return -1;
> + }
>  }

I like green paint,
gvb
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[U-Boot] [PATCH 00/13 v3] ARM: OMAP3: Add support for some of TIs ARM-Cortex A8 OMAP3 boards

2008-10-09 Thread dirk . behme
Subject: [PATCH 00/13 v3] ARM: OMAP3: Add support for some of TIs ARM-Cortex A8 
OMAP3 boards

This patch series adds U-Boot v1 support for some of TI's ARM-Cortex A8 based 
OMAP3 boards. These are BeagleBoard [1][2], EVM [3] and Overo [4].

The patch series is based on U-Boot tar ball [5] for BeagleBoard and EVM done 
by several TI employees.

To be able to easily add new boards, most of the code is common for all boards. 
After the header files (patches 1-3) and the common code for ARM Cortex A8 
(patch 4) and OMAP3 SoC (patches 5-7), support and drivers for NAND, MMC and 
I2C is added (patches 8-10). Patches 11-13 then introduce the individual board 
support for Beagle, EVM and Overo. 

As discussed earlier on this list, we compile for armv5 to be compatible with 
existing toolchains.

This patch adds ~300k of new code.

Thanks to

Steve Sakoman <[EMAIL PROTECTED]>
Pillai, Manikandan <[EMAIL PROTECTED]>
Syed Mohammed, Khasim <[EMAIL PROTECTED]>

and all others who helped with this.

Dirk

Changes in version v3:

- Replace space by tabs in headers as proposed by Jean-Christophe 
PLAGNIOL-VILLARD
- Fix/update NAND driver and seperate it into an own patch as proposed by Scott 
Wood
- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move MMC driver to drivers/mmc/ as suggested by Haavard Skinnemoen.
- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific 
common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.
- Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman.
- Remove SMC911X network init as proposed by Ben Warren.
- Rebase against u-boot-arm.git next, commit 
4995fed33099bb9813504869056bab72446fe8f9, "add tool to check patch and filr for 
CFG_ present" (CFG vs. CONFIG changes)

This v3 patch series makes all previous (v1, v2) OMAP3 patches obsolete.

[1] http://beagleboard.org/

[2] http://elinux.org/BeagleBoard

[3] http://focus.ti.com/docs/toolsw/folders/print/tmdxevm3503.html

[4] http://www.gumstix.net/Overo/

[5] http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
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[U-Boot] [PATCH 01/13 v3] ARM: OMAP3: Add pin mux, clock and cpu headers

2008-10-09 Thread dirk . behme
Subject: [PATCH 01/13 v3] ARM: OMAP3: Add pin mux, clock and cpu headers

From: Dirk Behme <[EMAIL PROTECTED]>

Add pin mux, clock and cpu header files for OMAP3.

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:

- Replace space by tabs in headers as proposed by Jean-Christophe 
PLAGNIOL-VILLARD

 include/asm-arm/arch-omap3/bits.h |   48 +++
 include/asm-arm/arch-omap3/clocks.h   |   62 
 include/asm-arm/arch-omap3/clocks_omap3.h |  101 +++
 include/asm-arm/arch-omap3/cpu.h  |  249 ++
 include/asm-arm/arch-omap3/mux.h  |  407 ++
 5 files changed, 867 insertions(+)

Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, 
+ * Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ */
+
+#define IEN(1 << 8)
+
+#define IDIS   (0 << 8)
+#define PTU(1 << 4)
+#define PTD(0 << 4)
+#define EN (1 << 3)
+#define DIS(0 << 3)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
+/*
+ * To get the actual address the offset has to added
+ * with OMAP34XX_CTRL_BASE to get the actual address
+ */
+
+/*SDRC*/
+#define CONTROL_PADCONF_SDRC_D00x0030
+#define CONTROL_PADCONF_SDRC_D10x0032
+#define CONTROL_PADCONF_SDRC_D20x0034
+#define CONTROL_PADCONF_SDRC_D30x0036
+#define CONTROL_PADCONF_SDRC_D40x0038
+#define CONTROL_PADCONF_SDRC_D50x003A
+#define CONTROL_PADCONF_SDRC_D60x003C
+#define CONTROL_PADCONF_SDRC_D70x003E
+#define CONTROL_PADCONF_SDRC_D80x0040
+#define CONTROL_PADCONF_SDRC_D90x0042
+#define CONTROL_PADCONF_SDRC_D10   0x0044
+#define CONTROL_PADCONF_SDRC_D11   0x0046
+#define CONTROL_PADCONF_SDRC_D12   0x0048
+#define CONTROL_PADCONF_SDRC_D13   0x004A
+#define CONTROL_PADCONF_SDRC_D14   0x004C
+#define CONTROL_PADCONF_SDRC_D15   0x004E
+#define CONTROL_PADCONF_SDRC_D16   0x0050
+#define CONTROL_PADCONF_SDRC_D17   0x0052
+#define CONTROL_PADCONF_SDRC_D18   0x0054
+#define CONTROL_PADCONF_SDRC_D19   0x0056
+#define CONTROL_PADCONF_SDRC_D20   0x0058
+#define CONTROL_PADCONF_SDRC_D21   0x005A
+#define CONTROL_PADCONF_SDRC_D22   0x005C
+#define CONTROL_PADCONF_SDRC_D23   0x005E
+#define CONTROL_PADCONF_SDRC_D24   0x0060
+#define CONTROL_PADCONF_SDRC_D25   0x0062
+#define CONTROL_PADCONF_SDRC_D26   0x0064
+#define CONTROL_PADCONF_SDRC_D27   0x0066
+#define CONTROL_PADCONF_SDRC_D28   0x0068
+#define CONTROL_PADCONF_SDRC_D29   0x006A
+#define CONTROL_PADCONF_SDRC_D30   0x006C
+#define CONTROL_PADCONF_SDRC_D31   0x006E
+#define CONTROL_PADCONF_SDRC_CLK   0x0070
+#define CONTROL_PADCONF_SDRC_DQS0  0x0072
+#define CONTROL_PADCONF_SDRC_DQS1  0x0074
+#define CONTROL_PADCONF_SDRC_DQS2  0x0076
+#define CONTROL_PADCONF_SDRC_DQS3  0x0078
+/*GPMC*/
+#define CONTROL_PADCONF_GPMC_A10x007A
+#define CONTROL_PADCONF_GPMC_A20x007C
+#define CONTROL_PADCONF_GPMC_A30x007E
+#define CONTROL_PADCONF_GPMC_A40x0080
+#define CONTROL_PADCONF_GPMC_A50x0082
+#define CONTROL_PADCONF_GPMC_A60x0084
+#define CONTROL_PADCONF_GPMC_A70x0086
+#define CONTROL_PADCONF_GPMC_A80x0088
+#define CONTROL_PADCONF_GPMC_A90x008A
+#define CONTROL_PADCONF_GPMC_A10   0x008C
+#define CONTROL_PADCONF_GPMC_D00x008E
+#define CONTROL_PADCONF_GPMC_D10x0090
+#define CONTROL_PADCONF_GPMC_D20x0092
+#define CONTROL_PADCONF_GPMC_D30x0094
+#define CONTRO

[U-Boot] [PATCH 02/13 v3] ARM: OMAP3: Add i2c, memory and additional pin mux headers

2008-10-09 Thread dirk . behme
Subject: [PATCH 02/13 v3] ARM: OMAP3: Add i2c, memory and additional pin mux 
headers

From: Dirk Behme <[EMAIL PROTECTED]>

Add OMAP3 I2C, memory and additional pin mux headers

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:

- Replace space by tabs in headers as proposed by Jean-Christophe 
PLAGNIOL-VILLARD

 include/asm-arm/arch-omap3/i2c.h |  128 ++
 include/asm-arm/arch-omap3/mem.h |  221 
 include/asm-arm/arch-omap3/mux.h |  347 +++
 3 files changed, 696 insertions(+)

Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===
--- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -404,4 +404,351 @@
 #define CONTROL_PADCONF_sdrc_cke0  0x0262
 #define CONTROL_PADCONF_sdrc_cke1  0x0264
 
+#define MUX_VAL(OFFSET,VALUE)\
+   writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#defineCP(x)   (CONTROL_PADCONF_##x)
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT_ES2() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0),  (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),  (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),  (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),  (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),  (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),  (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),  (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),  (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),  (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),  (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1),  (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),  (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),  (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),  (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),  (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),  (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),  (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),  (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),  (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),  (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),  (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),  (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),  (IEN  | PTD 

[U-Boot] [PATCH 03/13 v3] ARM: OMAP3: Add overo pin mux, omap3 and prototype headers

2008-10-09 Thread dirk . behme
Subject: [PATCH 03/13 v3] ARM: OMAP3: Add overo pin mux, omap3 and prototype 
headers

From: Dirk Behme <[EMAIL PROTECTED]>

Add overo pin mux, omap3 and prototype headers

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:

- Replace space by tabs in headers as proposed by Jean-Christophe 
PLAGNIOL-VILLARD

Changes in version v2:

- Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman.

 include/asm-arm/arch-omap3/mux.h   |  332 +
 include/asm-arm/arch-omap3/omap3.h |  135 +
 include/asm-arm/arch-omap3/sys_proto.h |   72 +++
 3 files changed, 539 insertions(+)

Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h
===
--- u-boot-arm.orig/include/asm-arm/arch-omap3/mux.h
+++ u-boot-arm/include/asm-arm/arch-omap3/mux.h
@@ -751,4 +751,336 @@
  MUX_VAL(CP(sdrc_cke0),(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
  MUX_VAL(CP(sdrc_cke1),(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
 
+#define MUX_DEFAULT_OVERO() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0),  (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),  (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),  (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),  (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),  (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),  (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),  (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),  (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),  (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),  (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1),  (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),  (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),  (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),  (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),  (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),  (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),  (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),  (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),  (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),  (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),  (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),  (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),  (IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4),  (IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5),  (IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6),  (IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7),  (I

[U-Boot] [PATCH 04/13 v3] ARM: OMAP3: Add ARM Cortex A8 common directory

2008-10-09 Thread dirk . behme
From: Dirk Behme <[EMAIL PROTECTED]>

Add ARM Cortex A8 common directory

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---
 cpu/arm_cortexa8/Makefile  |   43 +++
 cpu/arm_cortexa8/config.mk |   36 +++
 cpu/arm_cortexa8/cpu.c |  221 +++
 cpu/arm_cortexa8/start.S   |  522 +
 4 files changed, 822 insertions(+)

Index: u-boot-arm/cpu/arm_cortexa8/cpu.c
===
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/cpu.c
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH 
+ * Marius Groeger <[EMAIL PROTECTED]>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#ifndef CONFIG_L2_OFF
+void l2cache_disable(void);
+#endif
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1(void)
+{
+   unsigned long value;
+
+   __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
+@ read control reg\n":"=r"(value)
+::"memory");
+   return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1(unsigned long value)
+{
+   __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
+@ write it back\n"::"r"(value)
+: "memory");
+
+   read_p15_c1();
+}
+
+static void cp_delay(void)
+{
+   volatile int i;
+
+   /* Many OMAP regs need at least 2 nops  */
+   for (i = 0; i < 100; i++) ;
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU (1<<0)  /* mmu off/on */
+#define C1_ALIGN   (1<<1)  /* alignment faults off/on */
+#define C1_DC  (1<<2)  /* dcache off/on */
+#define C1_WB  (1<<3)  /* merging write buffer on/off */
+#define C1_BIG_ENDIAN  (1<<7)  /* big endian off/on */
+#define C1_SYS_PROT(1<<8)  /* system protection */
+#define C1_ROM_PROT(1<<9)  /* ROM protection */
+#define C1_IC  (1<<12) /* icache off/on */
+#define C1_HIGH_VECTORS(1<<13) /* location of vectors: low/high 
addresses */
+#define RESERVED_1 (0xf << 3)  /* must be 111b for R/W */
+
+int cpu_init(void)
+{
+   /*
+* setup up stacks if necessary
+*/
+#ifdef CONFIG_USE_IRQ
+   IRQ_STACK_START =
+   _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 
4;
+   FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+   return 0;
+}
+
+int cleanup_before_linux(void)
+{
+   unsigned int i;
+
+   /*
+* this function is called just before we call linux
+* it prepares the processor for linux
+*
+* we turn off caches etc ...
+*/
+   disable_interrupts();
+
+   /* turn off I/D-cache */
+   asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
+   i &= ~(C1_DC | C1_IC);
+   asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i));
+
+   /* invalidate I-cache */
+   arm_cache_flush();
+#ifndef CONFIG_L2_OFF
+   /* turn off L2 cache */
+   l2cache_disable();
+   /* invalidate L2 cache also */
+   v7_flush_dcache_all(get_device_type());
+#endif
+   i = 0;
+   /* mem barrier to sync up things */
+   asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+
+#ifndef CONFIG_L2_OFF
+   l2cache_enable();
+#endif
+
+   return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+   disable_interrupts();
+   reset_cpu(0);
+
+   /* NOTREACHED */
+   return 0;
+}
+
+void icache_enable(void)
+{
+   ulong reg;
+
+   reg = read_p15_c1();/* get control reg. */
+   cp_delay();
+   write_p15_c1(reg | C1_IC);
+}
+
+void icache_disable(void)
+{
+   ulong reg;
+
+   reg = read_p15_c1();
+   cp_delay();
+   write_p15_c1(reg & ~C1_IC);
+}
+
+void l2cache_enable()
+{
+   unsigned long i;
+   volatile unsigned int j;
+
+   /* ES2 onwards we can disab

[U-Boot] [PATCH 05/13 v3] ARM: OMAP3: Add lowlevel init and sys_info common files

2008-10-09 Thread dirk . behme
Subject: [PATCH 05/13 v3] ARM: OMAP3: Add lowlevel init and sys_info common 
files

From: Dirk Behme <[EMAIL PROTECTED]>

Add assembly lowlevel init and sys_info common files

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:
- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific 
common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.

 cpu/arm_cortexa8/omap3/Makefile|   43 +++
 cpu/arm_cortexa8/omap3/config.mk   |   36 +++
 cpu/arm_cortexa8/omap3/lowlevel_init.S |  360 +
 cpu/arm_cortexa8/omap3/sys_info.c  |  333 ++
 4 files changed, 772 insertions(+)

Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
===
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= lib$(SOC).a
+
+SOBJS  := lowlevel_init.o
+OBJS   := sys_info.o
+
+all:   .depend $(LIB)
+
+$(LIB):$(OBJS) $(SOBJS)
+   $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#
+
+.depend:   Makefile $(OBJS:.o=.c) $(SOBJS:.o=.S)
+   $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@
+
+sinclude .depend
+
+#
Index: u-boot-arm/cpu/arm_cortexa8/omap3/config.mk
===
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <[EMAIL PROTECTED]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
+-msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =
+#
+# Supply options according to compiler version
+#
+# =
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+   $(call cc-option,-malignment-traps,))
Index: u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
===
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
@@ -0,0 +1,360 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, 
+ *
+ * Initial Code by:
+ * Richard Woodruff <[EMAIL PROTECTED]>
+ * Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY o

[U-Boot] [PATCH 06/13 v3] ARM: OMAP3: Add board, clock and interrupts common files

2008-10-09 Thread dirk . behme
Subject: [PATCH 06/13 v3] ARM: OMAP3: Add board, clock and interrupts common 
files

From: Dirk Behme <[EMAIL PROTECTED]>

Add board, clock, cpu and interrupts common files

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:

- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific 
common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.

 cpu/arm_cortexa8/omap3/Makefile |2 
 cpu/arm_cortexa8/omap3/board.c  |  326 
 cpu/arm_cortexa8/omap3/clock.c  |  305 +
 cpu/arm_cortexa8/omap3/interrupts.c |  304 +
 4 files changed, 936 insertions(+), 1 deletion(-)

Index: u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
===
--- u-boot-arm.orig/cpu/arm_cortexa8/omap3/Makefile
+++ u-boot-arm/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB= lib$(SOC).a
 
 SOBJS  := lowlevel_init.o
-OBJS   := sys_info.o
+OBJS   := sys_info.o board.o clock.o interrupts.o
 
 all:   .depend $(LIB)
 
Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c
===
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c
@@ -0,0 +1,326 @@
+/*
+ *
+ * Common board functions for OMAP3 based boards.
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, 
+ *
+ * Author :
+ *  Sunil Kumar <[EMAIL PROTECTED]>
+ *  Shashi Ranjan <[EMAIL PROTECTED]>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *  Richard Woodruff <[EMAIL PROTECTED]>
+ *  Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NOT_EARLY 0
+
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1 0x
+#define UNLOCK_2 0x
+#define UNLOCK_3 0x
+
+/**
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ */
+static inline void delay(unsigned long loops)
+{
+   __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/**
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ *  (GP Device only)
+ */
+void secure_unlock_mem(void)
+{
+   /* Protection Module Register Target APE (PM_RT) */
+   writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+   writel(UNLOCK_1, RT_READ_PERMISSION_0);
+   writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+   writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+   writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+   writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+   writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+   writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+   writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+   writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+   writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+   /* IVA Changes */
+   writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+   writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+   writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+   writel(UNLOCK_1, SMS_RG_ATT0);  /* SDRC region 0 public */
+}
+
+/**
+ * Routine: secureworld_exit()
+ * Description: If chip is EMU and boot type is external
+ * configure secure registers and exit secure world
+ *  general use.
+ */
+void secureworld_exit()
+{
+   unsigned long i;
+
+   /* configrue non-secure access control register */
+   __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
+   /* enabling co-processor C

[U-Boot] [PATCH 07/13 v3] ARM: OMAP3: Add memory and syslib common files

2008-10-09 Thread dirk . behme
Subject: [PATCH 07/13 v3] ARM: OMAP3: Add memory and syslib common files

From: Dirk Behme <[EMAIL PROTECTED]>

Add memory and syslib common files.

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:

- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific 
common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.

 cpu/arm_cortexa8/omap3/Makefile |2 
 cpu/arm_cortexa8/omap3/mem.c|  298 
 cpu/arm_cortexa8/omap3/syslib.c |   72 +
 examples/Makefile   |6 
 4 files changed, 375 insertions(+), 3 deletions(-)

Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c
===
--- /dev/null
+++ u-boot-arm/cpu/arm_cortexa8/omap3/mem.c
@@ -0,0 +1,298 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, 
+ *
+ * Author :
+ * Manikandan Pillai <[EMAIL PROTECTED]>
+ *
+ * Initial Code from:
+ * Richard Woodruff <[EMAIL PROTECTED]>
+ * Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Only One NAND allowed on board at a time.
+ * The GPMC CS Base for the same
+ */
+unsigned int boot_flash_base;
+unsigned int boot_flash_off;
+unsigned int boot_flash_sec;
+unsigned int boot_flash_type;
+volatile unsigned int boot_flash_env_addr;
+
+/* help common/env_flash.c */
+#ifdef ENV_IS_VARIABLE
+
+uchar(*boot_env_get_char_spec) (int index);
+int (*boot_env_init) (void);
+int (*boot_saveenv) (void);
+void (*boot_env_relocate_spec) (void);
+
+/* 16 bit NAND */
+uchar env_get_char_spec(int index);
+int env_init(void);
+int saveenv(void);
+void env_relocate_spec(void);
+extern char *env_name_spec;
+
+#if defined(CONFIG_CMD_NAND)
+u8 is_nand;
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+u8 is_onenand;
+#endif
+
+#endif /* ENV_IS_VARIABLE */
+
+#if defined(CONFIG_CMD_NAND)
+static u32 gpmc_m_nand[GPMC_MAX_REG] = {
+   M_NAND_GPMC_CONFIG1,
+   M_NAND_GPMC_CONFIG2,
+   M_NAND_GPMC_CONFIG3,
+   M_NAND_GPMC_CONFIG4,
+   M_NAND_GPMC_CONFIG5,
+   M_NAND_GPMC_CONFIG6, 0
+};
+unsigned int nand_cs_base;
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+static u32 gpmc_onenand[GPMC_MAX_REG] = {
+   ONENAND_GPMC_CONFIG1,
+   ONENAND_GPMC_CONFIG2,
+   ONENAND_GPMC_CONFIG3,
+   ONENAND_GPMC_CONFIG4,
+   ONENAND_GPMC_CONFIG5,
+   ONENAND_GPMC_CONFIG6, 0
+};
+unsigned int onenand_cs_base;
+
+#endif
+
+/**
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontinuous support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **/
+void make_cs1_contiguous(void)
+{
+   u32 size, a_add_low, a_add_high;
+
+   size = get_sdr_cs_size(SDRC_CS0_OSET);
+   size /= SZ_32M; /* find size to offset CS1 */
+   a_add_high = (size & 3) << 8;   /* set up low field */
+   a_add_low = (size & 0x3C) >> 2; /* set up high field */
+   writel((a_add_high | a_add_low), SDRC_CS_CFG);
+
+}
+
+/
+ *  mem_ok() - test used to see if timings are correct
+ * for a part. Helps in guessing which part
+ * we are currently using.
+ ***/
+u32 mem_ok(u32 cs)
+{
+   u32 val1, val2, addr;
+   u32 pattern = 0x12345678;
+
+   addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
+
+   writel(0x0, addr + 0x400);  /* clear pos A */
+   writel(pattern, addr);/* pattern to pos B */
+   writel(0x0, addr + 4);/* remove pattern off the bus */
+   val1 = readl(addr + 0x400); /* get pos A value */
+   val2 = readl(addr);   /* get val2 */
+
+   if ((val1 != 0) || (val2 != pattern))  /* see if pos A value changed */
+   return 0;
+   else
+   return 1;
+}
+
+/

[U-Boot] [PATCH 09/13 v3] ARM: OMAP3: Add MMC support

2008-10-09 Thread dirk . behme
Subject: [PATCH 09/13 v3] ARM: OMAP3: Add MMC support

From: Dirk Behme <[EMAIL PROTECTED]>

Add MMC support

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in v2:

 - Move MMC driver to drivers/mmc/ as suggested by Haavard Skinnemoen. Thanks!

---
 drivers/mmc/Makefile  |3 
 drivers/mmc/omap3_mmc.c   |  557 ++
 include/asm-arm/arch-omap3/mmc.h  |  235 
 include/asm-arm/arch-omap3/mmc_host_def.h |  166 
 4 files changed, 961 insertions(+)

Index: u-boot-arm/include/asm-arm/arch-omap3/mmc.h
===
--- /dev/null
+++ u-boot-arm/include/asm-arm/arch-omap3/mmc.h
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, 
+ * Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "mmc_host_def.h"
+
+/* Responses */
+#define RSP_TYPE_NONE(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R1  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R2  (RSP_TYPE_LGHT136 | CCCE_CHECK   | CICE_NOCHECK)
+#define RSP_TYPE_R3  (RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R4  (RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
+#define RSP_TYPE_R5  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R6  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+#define RSP_TYPE_R7  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
+
+/* All supported commands */
+#define MMC_CMD0  (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD1  (INDEX(1)  | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD2  (INDEX(2)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD3  (INDEX(3)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_SDCMD3(INDEX(3)  | RSP_TYPE_R6   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD4  (INDEX(4)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD6  (INDEX(6)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD7_SELECT   (INDEX(7)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD7_DESELECT (INDEX(7)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD8  (INDEX(8)  | RSP_TYPE_R1   | DP_DATA| DDIR_READ)
+#define MMC_SDCMD8(INDEX(8)  | RSP_TYPE_R7   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD9  (INDEX(9)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1   | DP_DATA| DDIR_READ)
+#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1   | DP_DATA| DDIR_WRITE)
+#define MMC_ACMD6 (INDEX(6)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_ACMD41(INDEX(41) | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
+#define MMC_ACMD51(INDEX(51) | RSP_TYPE_R1   | DP_DATA| DDIR_READ)
+#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
+
+#define MMC_AC_CMD_RCA_MASK (unsigned int)(0x << 16)
+#define MMC_BC_CMD_DSR_MASK (unsigned int)(0x << 16)
+#define MMC_DSR_DEFAULT (0x0404)
+#define SD_CMD8_CHECK_PATTERN  (0xAA)
+#define SD_CMD8_2_7_3_6_V_RANGE(0x01 << 8)
+
+/* Clock Configurations and Macros */
+
+#define MMC_CLOCK_REFERENCE(96)
+#define MMC_RELATIVE_CARD_ADDRESS  (0x1234)
+#define MMC_INIT_SEQ_CLK   (MMC_CLOCK_REFERENCE * 1000 / 80)
+#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
+#define CLKDR(r, f, u) r)*100) / ((f)*(u))) + 1)
+#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
+
+#define MMC_OCR_REG_ACCESS_MODE_MASK   (0x3 << 29)
+#define MMC_OCR_REG_ACCESS_MODE_BYTE   (0x0 <

[U-Boot] [PATCH 10/13 v3] ARM: OMAP3: Add I2C support

2008-10-09 Thread dirk . behme
Subject: [PATCH 10/13 v3] ARM: OMAP3: Add I2C support

From: Dirk Behme <[EMAIL PROTECTED]>

Add I2C support

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---
Changes in version v2:

- Remove SMC911X network init as proposed by Ben Warren. Thanks!

 drivers/i2c/Makefile   |1 
 drivers/i2c/omap24xx_i2c.c |  132 ++---
 drivers/net/Makefile   |1 
 3 files changed, 80 insertions(+), 54 deletions(-)

Index: u-boot-arm/drivers/i2c/Makefile
===
--- u-boot-arm.orig/drivers/i2c/Makefile
+++ u-boot-arm/drivers/i2c/Makefile
@@ -29,6 +29,7 @@ COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
 COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
+COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
 COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 
Index: u-boot-arm/drivers/i2c/omap24xx_i2c.c
===
--- u-boot-arm.orig/drivers/i2c/omap24xx_i2c.c
+++ u-boot-arm/drivers/i2c/omap24xx_i2c.c
@@ -25,8 +25,10 @@
 #include 
 #include 
 
+#define inb(a) __raw_readb(a)
+#define outb(a, v) __raw_writeb(a, v)
 #define inw(a) __raw_readw(a)
-#define outw(a,v) __raw_writew(a,v)
+#define outw(a, v) __raw_writew(a, v)
 
 static void wait_for_bb (void);
 static u16 wait_for_pin (void);
@@ -40,28 +42,28 @@ void i2c_init (int speed, int slaveadd)
udelay(1000);
outw(0x0, I2C_SYSC); /* will probably self clear but */
 
-   if (inw (I2C_CON) & I2C_CON_EN) {
-   outw (0, I2C_CON);
+   if (inw(I2C_CON) & I2C_CON_EN) {
+   outw(0, I2C_CON);
udelay (5);
}
 
/* 12Mhz I2C module clock */
-   outw (0, I2C_PSC);
+   outw(0, I2C_PSC);
speed = speed/1000; /* 100 or 400 */
scl = ((12000/(speed*2)) - 7);  /* use 7 when PSC = 0 */
-   outw (scl, I2C_SCLL);
-   outw (scl, I2C_SCLH);
+   outw(scl, I2C_SCLL);
+   outw(scl, I2C_SCLH);
/* own address */
-   outw (slaveadd, I2C_OA);
-   outw (I2C_CON_EN, I2C_CON);
+   outw(slaveadd, I2C_OA);
+   outw(I2C_CON_EN, I2C_CON);
 
/* have to enable intrrupts or OMAP i2c module doesn't work */
-   outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
- I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
+   outw(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
+I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
udelay (1000);
flush_fifo();
-   outw (0x, I2C_STAT);
-   outw (0, I2C_CNT);
+   outw(0x, I2C_STAT);
+   outw(0, I2C_CNT);
 }
 
 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
@@ -73,11 +75,11 @@ static int i2c_read_byte (u8 devaddr, u8
wait_for_bb ();
 
/* one byte only */
-   outw (1, I2C_CNT);
+   outw(1, I2C_CNT);
/* set slave address */
-   outw (devaddr, I2C_SA);
+   outw(devaddr, I2C_SA);
/* no stop bit needed here */
-   outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
+   outw(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
 
status = wait_for_pin ();
 
@@ -85,7 +87,7 @@ static int i2c_read_byte (u8 devaddr, u8
/* Important: have to use byte access */
*(volatile u8 *) (I2C_DATA) = regoffset;
udelay (2);
-   if (inw (I2C_STAT) & I2C_STAT_NACK) {
+   if (inw(I2C_STAT) & I2C_STAT_NACK) {
i2c_error = 1;
}
} else {
@@ -94,42 +96,46 @@ static int i2c_read_byte (u8 devaddr, u8
 
if (!i2c_error) {
/* free bus, otherwise we can't use a combined transction */
-   outw (0, I2C_CON);
-   while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
+   outw(0, I2C_CON);
+   while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) {
udelay (1);
/* Have to clear pending interrupt to clear I2C_STAT */
-   outw (0x, I2C_STAT);
+   outw(0x, I2C_STAT);
}
 
wait_for_bb ();
/* set slave address */
-   outw (devaddr, I2C_SA);
+   outw(devaddr, I2C_SA);
/* read one byte from slave */
-   outw (1, I2C_CNT);
+   outw(1, I2C_CNT);
/* need stop bit here */
-   outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- I2C_CON);
+   outw(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
+I2C_CON);
 
status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
-   *value =

[U-Boot] [PATCH 11/13 v3] ARM: OMAP3: Add BeagleBoard

2008-10-09 Thread dirk . behme
Subject: [PATCH 11/13 v3] ARM: OMAP3: Add BeagleBoard

From: Dirk Behme <[EMAIL PROTECTED]>

Add BeagleBoard

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---
Changes in version v2:

- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)

 Makefile   |7 
 board/omap3/beagle/Makefile|   46 ++
 board/omap3/beagle/beagle.c|  113 +++
 board/omap3/beagle/config.mk   |   17 ++
 board/omap3/beagle/u-boot.lds  |   63 
 include/configs/omap3_beagle.h |  292 +
 6 files changed, 538 insertions(+)

Index: u-boot-arm/board/omap3/beagle/Makefile
===
--- /dev/null
+++ u-boot-arm/board/omap3/beagle/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= lib$(BOARD).a
+
+OBJS   := beagle.o
+
+$(LIB):$(OBJS)
+   $(AR) crv $@ $^
+
+clean:
+   rm -f $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak .depend
+
+#
+
+.depend:   Makefile $(OBJS:.o=.c)
+   $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#
Index: u-boot-arm/board/omap3/beagle/beagle.c
===
--- /dev/null
+++ u-boot-arm/board/omap3/beagle/beagle.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, 
+ *
+ * Author :
+ *  Sunil Kumar <[EMAIL PROTECTED]>
+ *  Shashi Ranjan <[EMAIL PROTECTED]>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *  Richard Woodruff <[EMAIL PROTECTED]>
+ *  Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+const omap3_sysinfo sysinfo = {
+   SDP_3430_V1,
+   SDP_3430_V2,
+   "3530",
+   "OMAP3 Beagle board",
+};
+
+/**
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+   DECLARE_GLOBAL_DATA_PTR;
+
+   gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+   /* board id for Linux */
+   gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
+   /* boot param addr */
+   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+   return 0;
+}
+
+/**
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+   unsigned char byte;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+   i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+   /* set vaux3 to 2.8V */
+   byte = 0x20;
+   i2c_write(0x4B, 0x7A, 1, &byte, 1);
+   byte = 0x03;
+   i2c_write(0x4B, 0x7D, 1, &byte, 1);
+
+   /* set vpll2 to 1.8V */
+   byte = 0xE0;
+   i2c_write(0x4B, 0x8E, 1, &byte, 1);
+   byte = 0x05;
+   i2c_write(0x4B, 0x91, 1, &byte, 1);
+
+   /* set VDAC t

[U-Boot] [PATCH 12/13 v3] ARM: OMAP3: Add EVM board

2008-10-09 Thread dirk . behme
Subject: [PATCH 12/13 v3] ARM: OMAP3: Add EVM board

From: Dirk Behme <[EMAIL PROTECTED]>

Add EVM board

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---
Changes in version v2:

- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)

 Makefile|3 
 board/omap3/evm/Makefile|   46 ++
 board/omap3/evm/config.mk   |   17 ++
 board/omap3/evm/evm.c   |  199 ++
 board/omap3/evm/u-boot.lds  |   63 
 include/configs/omap3_evm.h |  327 
 6 files changed, 655 insertions(+)

Index: u-boot-arm/board/omap3/evm/Makefile
===
--- /dev/null
+++ u-boot-arm/board/omap3/evm/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= lib$(BOARD).a
+
+OBJS   := evm.o
+
+$(LIB):$(OBJS)
+   $(AR) crv $@ $^
+
+clean:
+   rm -f $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak .depend
+
+#
+
+.depend:   Makefile $(OBJS:.o=.c)
+   $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#
Index: u-boot-arm/board/omap3/evm/config.mk
===
--- /dev/null
+++ u-boot-arm/board/omap3/evm/config.mk
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, 
+#
+# Begale Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Physical Address:
+# 8000' (bank0)
+# A000/ (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e8
+
+
Index: u-boot-arm/board/omap3/evm/evm.c
===
--- /dev/null
+++ u-boot-arm/board/omap3/evm/evm.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, 
+ *
+ * Author :
+ *  Manikandan Pillai <[EMAIL PROTECTED]>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *  Richard Woodruff <[EMAIL PROTECTED]>
+ *  Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+const omap3_sysinfo sysinfo = {
+   OMAP3EVM_V1,
+   OMAP3EVM_V2,
+   "35X-Family",
+   "OMAP3 EVM board",
+};
+
+static int setup_net_chip(void);
+
+/**
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+   DECLARE_GLOBAL_DATA_PTR;
+
+   gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+   /* board id for Linux */
+   gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
+   /* boot param addr */
+   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+   return 0;
+}
+
+/**
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ 

[U-Boot] [PATCH 13/13 v3] ARM: OMAP3: Add Overo board

2008-10-09 Thread dirk . behme
Subject: [PATCH 13/13 v3] ARM: OMAP3: Add Overo board

From: Dirk Behme <[EMAIL PROTECTED]>

Add Overo board

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---
Changes in version v2:

- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)

 Makefile  |3 
 board/omap3/overo/Makefile|   46 ++
 board/omap3/overo/config.mk   |   12 +
 board/omap3/overo/overo.c |  119 +
 board/omap3/overo/u-boot.lds  |   63 +
 include/configs/omap3_overo.h |  283 ++
 6 files changed, 526 insertions(+)

Index: u-boot-arm/board/omap3/overo/Makefile
===
--- /dev/null
+++ u-boot-arm/board/omap3/overo/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= lib$(BOARD).a
+
+OBJS   := overo.o
+
+$(LIB):$(OBJS)
+   $(AR) crv $@ $^
+
+clean:
+   rm -f $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak .depend
+
+#
+
+.depend:   Makefile $(OBJS:.o=.c)
+   $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#
Index: u-boot-arm/board/omap3/overo/config.mk
===
--- /dev/null
+++ u-boot-arm/board/omap3/overo/config.mk
@@ -0,0 +1,12 @@
+# Overo uses OMAP3 (ARM-CortexA8) cpu
+#
+# Physical Address:
+# 8000' (bank0)
+# A000/ (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e8
+
+
Index: u-boot-arm/board/omap3/overo/overo.c
===
--- /dev/null
+++ u-boot-arm/board/omap3/overo/overo.c
@@ -0,0 +1,119 @@
+/*
+ * Maintainer : Steve Sakoman <[EMAIL PROTECTED]>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ *  Richard Woodruff <[EMAIL PROTECTED]>
+ *  Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ *  Sunil Kumar <[EMAIL PROTECTED]>
+ *  Shashi Ranjan <[EMAIL PROTECTED]>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+const omap3_sysinfo sysinfo = {
+   SDP_3430_V1,
+   SDP_3430_V2,
+   "3503",
+   "Gumstix Overo board",
+};
+
+/**
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+   DECLARE_GLOBAL_DATA_PTR;
+
+   gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+   /* board id for Linux */
+   gd->bd->bi_arch_number = MACH_TYPE_OVERO;
+   /* boot param addr */
+   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+   return 0;
+}
+
+/**
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+

[U-Boot] [PATCH 08/13 v3] ARM: OMAP3: Add NAND support

2008-10-09 Thread dirk . behme
Subject: [PATCH 08/13 v3] ARM: OMAP3: Add NAND support

From: Dirk Behme <[EMAIL PROTECTED]>

Add NAND support

Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>

---

Changes in version v3:

- Fix/update NAND driver and seperate it into an own patch as proposed by Scott 
Wood

 drivers/mtd/nand/Makefile |1 
 drivers/mtd/nand/omap3.c  |  380 ++
 2 files changed, 381 insertions(+)

Index: u-boot-arm/drivers/mtd/nand/Makefile
===
--- u-boot-arm.orig/drivers/mtd/nand/Makefile
+++ u-boot-arm/drivers/mtd/nand/Makefile
@@ -38,6 +38,7 @@ endif
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
+COBJS-$(CONFIG_NAND_OMAP3) += omap3.o
 endif
 
 COBJS  := $(COBJS-y)
Index: u-boot-arm/drivers/mtd/nand/omap3.c
===
--- /dev/null
+++ u-boot-arm/drivers/mtd/nand/omap3.c
@@ -0,0 +1,380 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, 
+ * Rohit Choraria <[EMAIL PROTECTED]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+unsigned char cs;
+volatile unsigned long gpmc_cs_base_add;
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+/*
+ * omap_nand_hwcontrol - Set the address pointers corretly for the
+ * following address/data/command operation
+ */
+static void omap_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+   unsigned int ctrl)
+{
+   register struct nand_chip *this = mtd->priv;
+
+   /* Point the IO_ADDR to DATA and ADDRESS registers instead
+  of chip address */
+   switch (ctrl) {
+   case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
+   this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
+   this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+   break;
+   case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
+   this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR;
+   this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+   break;
+   case NAND_CTRL_CHANGE | NAND_NCE:
+   this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+   this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+   break;
+   }
+
+   if (cmd != NAND_CMD_NONE)
+   writeb(cmd, this->IO_ADDR_W);
+}
+
+/*
+ * omap_nand_wait - called primarily after a program/erase operation
+ * so that we access NAND again only after the device
+ * is ready again.
+ * @mtd:MTD device structure
+ * @chip:  nand_chip structure
+ */
+static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+   register struct nand_chip *this = mtd->priv;
+   int status = 0;
+
+   this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
+   this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+   /* Send the status command and loop until the device is free */
+   while (!(status & 0x40)) {
+   writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
+   status = readb(this->IO_ADDR_R);
+   }
+   return status;
+}
+
+/*
+ * omap_nand_write_buf16 - [DEFAULT] write buffer to chip
+ * @mtd:   MTD device structure
+ * @buf:   data buffer
+ * @len:   number of bytes to write
+ *
+ * Default write function for 16bit buswith
+ */
+static void omap_nand_write_buf16(struct mtd_info *mtd, const u_char *buf,
+   int len)
+{
+   int i;
+   struct nand_chip *this = mtd->priv;
+   u16 *p = (u16 *) buf;
+   len >>= 1;
+
+   for (i = 0; i < len; i++) {
+   writew(p[i], this->IO_ADDR_W);
+   while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL));
+   }
+}
+
+/*
+ * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
+ *   GPMC controller
+ * @mtd:MTD device structure
+ *
+ */
+static void omap_hwecc_init(struct nand_chip *chip)
+{
+   uns

[U-Boot] Please pull u-boot-mpc85xx.git

2008-10-09 Thread Andy Fleming
are available in the git repository at:

  git://www.denx.de/git/u-boot-mpc85xx.git master

This supercedes the previous pull request.  This includes Wolfgang's and Kumar's
patches.

Haiying Wang (3):
  Minor fixes for I2C address on MPC8572DS
  Add ID EEPROM support for MPC8572DS
  Remove redundant #define for MPC8536DS

Jason Jin (1):
  Fix the incorrect DDR clk freq reporting on 8536DS

Kumar Gala (2):
  85xx: Remove setting of *cache-line-size in device trees
  MPC8572DS: Fix compile warnings

Rafal Czubak (1):
  FSL: Fix get_cpu_board_revision() return value.

Wolfgang Grandegger (1):
  85xx: Using proper I2C source clock divider for MPC8544

 board/freescale/common/sys_eeprom.c |2 +-
 cpu/mpc85xx/cpu.c   |3 ++-
 cpu/mpc85xx/fdt.c   |3 ---
 cpu/mpc85xx/speed.c |7 ---
 include/asm-ppc/immap_85xx.h|7 +++
 include/configs/MPC8536DS.h |3 +--
 include/configs/MPC8572DS.h |   19 +--
 7 files changed, 32 insertions(+), 12 deletions(-)
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Re: [U-Boot] [OFF TOPIC] Linux Physmap drivers

2008-10-09 Thread Wolfgang Denk
Dear Alemao,

In message <[EMAIL PROTECTED]> you wrote:
> 
> Im trying to use a physmap driver for NOR and NAND flash devices.

As you even committed yourself, this is off tiopic here. Please  post
such requests to the appropriate mailing lists, not here.

Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Wolfgang Denk
Dear Markus =?iso-8859-1?Q?Klotzb=FCcher?=,

In message <[EMAIL PROTECTED]> you wrote:
>
> > > > if (dev->status == 0)
> > > > return dev->act_len;
> > > please add {} to if too or remove the else
> > > > -   else
> > > > +   else {
> > > > +   /* Let's wait a while for the timeout to elaps.
> > > > +* it has no real use, but it keeps the interface 
> > > > happy. */
> > > > +   wait_ms(timeout);
> > > > return -1;
> > > > +   }
...
> > Actually the "else" should be removed.
> 
> How so?

Like that:

if (dev->status == 0)
return dev->act_len;

/*
 * Let's wait a while for the timeout to elaps.
 * it has no real use, but it keeps the interface happy.
 */
wait_ms(timeout); 
return -1;

What exactly was your problem?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
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Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Wolfgang Denk
Dear Stefan Roese,

In message <[EMAIL PROTECTED]> you wrote:
>
> > > >
> > > > > - else
> > > > > + else {
> > > > > + /* Let's wait a while for the timeout to elaps.
> > > > > +  * it has no real use, but it keeps the interface 
> > > > > happy. */
> > > > > + wait_ms(timeout);
> > > > >   return -1;
> > > > > + }
> > >
> > > Good catch.
> >
> > Quite honest, I think this is *way* to pedantic. I'd really prefer to
> > let people who are contributing significantly do their work instead of
> > bugging them with such rare coding style violations.
> 
> ACK from me here. "Minor" coding style violations like these braces issue or 
> too long lines should not delay patches.

NAK, and NAK again from me. Note that it's not only a single small
violation, there is a whole list of it evenin this short code snippet:
- incorrect brace style
- unnecessary indentation
- incorrect multi-line comment style

It is much easier to fix such code when it's being added, than to fix
it later (which may or may not happen). See all the examples that got
commited that way - and that haven't been fixed since.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED]
Experience is what causes a person to make new  mistakes  instead  of
old ones.
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Re: [U-Boot] [PATCH 08/13 v3] ARM: OMAP3: Add NAND support

2008-10-09 Thread Scott Wood
[EMAIL PROTECTED] wrote:
> +unsigned char cs;
> +volatile unsigned long gpmc_cs_base_add;

Make these static.  gpmc_cs_base_add should be a pointer, not "unsigned 
long".  Volatile isn't needed since you use I/O accessors, and 
definitely isn't needed on the address itself.

> +/*
> + * omap_nand_hwcontrol - Set the address pointers corretly for the
> + *   following address/data/command operation
> + */
> +static void omap_nand_hwcontrol(struct mtd_info *mtd, int cmd,
> + unsigned int ctrl)
> +{
> + register struct nand_chip *this = mtd->priv;
> +
> + /* Point the IO_ADDR to DATA and ADDRESS registers instead
> +of chip address */
> + switch (ctrl) {
> + case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
> + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
> + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
> + break;
> + case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
> + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR;
> + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
> + break;
> + case NAND_CTRL_CHANGE | NAND_NCE:
> + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
> + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
> + break;
> + }

IO_ADDR_R never seems to change; you can leave it out of here and 
omap_nand_wait.

> +/*
> + * omap_nand_wait - called primarily after a program/erase operation
> + *   so that we access NAND again only after the device
> + *   is ready again.
> + * @mtd:MTD device structure
> + * @chip:nand_chip structure
> + */
> +static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
> +{
> + register struct nand_chip *this = mtd->priv;
> + int status = 0;
> +
> + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
> + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
> + /* Send the status command and loop until the device is free */
> + while (!(status & 0x40)) {
> + writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
> + status = readb(this->IO_ADDR_R);
> + }

Maybe should just do this, to avoid changing client-visible state:
writeb(NAND_CMD_STATUS, &gpmc_cs_base_add[GPMC_NAND_CMD]);

No need for the "& 0xFF".

> + /* Init ECC Control Register */
> + /* Clear all ECC  | Enable Reg1 */
> + val = ((0x0001 << 8) | 0x0001);
> + writel(val, GPMC_BASE + GPMC_ECC_CONTROL);
> + writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG);

Symbolic constants for the bit values would be nice.

> +/*
> + *  omap_calculate_ecc - Generate non-inverted ECC bytes.
> + *
> + *  Using noninverted ECC can be considered ugly since writing a blank
> + *  page ie. padding will clear the ECC bytes. This is no problem as
> + *  long nobody is trying to write data on the seemingly unused page.
> + *  Reading an erased page will produce an ECC mismatch between
> + *  generated and read ECC bytes that has to be dealt with separately.

Where is it dealt with separately?

> + unsigned long val = 0x0;

Unnecessary initialization.

> + unsigned long reg;
> +
> + /* Start Reading from HW ECC1_Result = 0x200 */
> + reg = (unsigned long) (GPMC_BASE + GPMC_ECC1_RESULT);
> + val = readl(reg);

readl() takes a pointer.  ARM gets away without a warning here because 
it uses macros rather than inline functions, but it's bad practice.

> + /* Stop reading anymore ECC vals and clear old results
> +  * enable will be called if more reads are required */
> + reg = (unsigned long) (GPMC_BASE + GPMC_ECC_CONFIG);
> + writel(0x000, reg);

Likewise.

> +void omap_nand_switch_ecc(int hardware)
> +{
> + struct nand_chip *nand;
> +
> + if (nand_curr_device < 0 ||
> + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
> + !nand_info[nand_curr_device].name) {
> + printf("Error: Can't switch ecc, no devices available\n");
> + return;
> + }
> +
> + nand = (&nand_info[nand_curr_device])->priv;
> +
> + if (!hardware) {
> + nand->ecc.mode = NAND_ECC_SOFT;
> + nand->ecc.layout = &sw_nand_oob_64;
> + nand->ecc.size = 256;   /* set default eccsize */
> + nand->ecc.bytes = 3;
> + nand->ecc.steps = 8;
> + nand->ecc.hwctl = 0;
> + nand->ecc.calculate = nand_calculate_ecc;
> + nand->ecc.correct = nand_correct_data;
> + } else {
> + nand->ecc.mode = NAND_ECC_HW;
> + nand->ecc.layout = &hw_nand_oob_64;
> + nand->ecc.size = 512;
> + nand->ecc.bytes = 3;
> + nand->ecc.steps = 4;
> + nand->ecc.hwctl = omap_enable_hwecc;
> + nand->ecc.correct = omap_correct_data;
> + nand->ecc

Re: [U-Boot] [patch 1/2] fix USB initialisation procedure

2008-10-09 Thread Markus Klotzbücher
On Thu, Oct 09, 2008 at 08:45:21PM +0200, Wolfgang Denk wrote:
> In message <[EMAIL PROTECTED]> you wrote:
> >
> > > > >
> > > > > > -   else
> > > > > > +   else {
> > > > > > +   /* Let's wait a while for the timeout to elaps.
> > > > > > +* it has no real use, but it keeps the interface 
> > > > > > happy. */
> > > > > > +   wait_ms(timeout);
> > > > > > return -1;
> > > > > > +   }
> > > >
> > > > Good catch.
> > >
> > > Quite honest, I think this is *way* to pedantic. I'd really prefer to
> > > let people who are contributing significantly do their work instead of
> > > bugging them with such rare coding style violations.
> > 
> > ACK from me here. "Minor" coding style violations like these braces issue 
> > or 
> > too long lines should not delay patches.
> 
> NAK, and NAK again from me. Note that it's not only a single small
> violation, there is a whole list of it evenin this short code snippet:
> - incorrect brace style
> - unnecessary indentation
> - incorrect multi-line comment style
> 
> It is much easier to fix such code when it's being added, than to fix
> it later (which may or may not happen). See all the examples that got
> commited that way - and that haven't been fixed since.

True, you're technically right, of course, and I don't question
enforcing coding style in general. I just think that being too
critical has the potential of putting people off, and IMHO this list
can be very critical. Sometimes it's better to get a patch with a
couple of coding style violations than keeping the bug it would have
fixed.

Best regards
Markus

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] Problem with flash on a MPC5200B board

2008-10-09 Thread Sylvain Lamontagne
Hi again everyone

I tried a lot of stuff today but was still unable get it to work.
Here is my Flash configuration:

/*
 * Flash configuration
*/
#define CFG_FLASH_BASE   0xFF00
#define CFG_FLASH_SIZE   0x100
//#define CFG_ENV_ADDR  0xFFFE
#define CFG_ENV_OFFSET0x00FE
//#define CFG_FLASH_MAX_SIZE   0x00ff
#define CFG_ENV_ADDR(CFG_FLASH_BASE + CFG_ENV_OFFSET)
#define CFG_MAX_FLASH_BANKS 1   /* max num of memory banks  */
#define CFG_MAX_FLASH_SECT  128 /* max num of sectors on one chip */
#define CFG_FLASH_SECT_SIZE 0x2
#define CFG_FLASH_ERASE_TOUT24  /* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT500 /* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
//#define CONFIG_FLASH_16BIT
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_BANKS_LIST{CFG_FLASH_BASE}


I think the problem may come from the Manufacturer ID and Device ID, from
the datasheet it's supposed to be:
Manufacturer ID   xx01h/1h
Device ID, Word 1227Eh/7Eh

The CFI detection seems to report them as
manufacturer id is 0x5
device id is 0x56

How can I force it ?
Or maybe I'm totally searching in the wrong direction...

Sylvain

2008/10/8 Sylvain Lamontagne <[EMAIL PROTECTED]>

> Humm ... Nobody can help me ?
> If you need more informations I can get them, I would really like to
> understand the debug output I'm seeing.
>
> Thank you
>
> Sylvain
>
> 2008/10/7 Sylvain Lamontagne <[EMAIL PROTECTED]>
>
> Hi Everyone
>>
>> I'm pretty new to U-Boot and Embedded system globally, but in the last few
>> weeks I have learn a lot and I'm now trying to port correctly U-Boot v 1.3.4
>> to a custom board based on a Icecube. I'm able to boot a linux kernel with
>> it when I use the RAM with the bootm command.
>>
>> Unfortunately, I must make it work with the FLASH. The chip used for the
>> flash is a S29GL128 or a S29GL256 from Spansion, they are 16bits chips but
>> the bus is only 8bits. By reading the datasheet, these chips are supposed to
>> support the Common Flash Interface so I'm trying to make then work with the
>> CFI driver of U-Boot.
>>
>> Here is what I get when booting with DEBUG activated:
>>
>> U-Boot 1.3.4 (Oct  7 2008 - 16:39:49)
>>>
>>> CPU:   MPC5200B v2.2, Core v1.4 at 378 MHz
>>>   Bus 84 MHz, IPB 84 MHz, PCI 21 MHz
>>> Board: Icecube Based Board
>>> I2C:   93 kHz, ready
>>> DRAM:  64 MB
>>> Top of RAM usable for U-Boot at: 0400
>>> Reserving 551k for U-Boot at: 03f76000
>>> Reserving 130k for malloc() at: 03f55800
>>> Reserving 68 Bytes for Board Info at: 03f557bc
>>> Reserving 60 Bytes for Global Data at: 03f55780
>>> Stack Pointer at: 03f55768
>>> New Stack Pointer is: 03f55768
>>> Now running in RAM - U-Boot at: 03f76000
>>> FLASH: flash detect cfi
>>> fwc addr ff00 cmd f0 f0 8bit x 8 bit
>>> fwc addr ff00 cmd f0 f0 8bit x 8 bit
>>> fwc addr ff55 cmd 98 98 8bit x 8 bit
>>> is= cmd 51(Q) addr ff10 is= 0 51
>>> fwc addr ff000555 cmd 98 98 8bit x 8 bit
>>> is= cmd 51(Q) addr ff10 is= 0 51
>>> fwc addr ff00 cmd f0 f0f0 16bit x 8 bit
>>> fwc addr ff00 cmd f0 f0f0 16bit x 8 bit
>>> fwc addr ffaa cmd 98 9898 16bit x 8 bit
>>> is= cmd 51(Q) addr ff20 is= 5151 5151
>>> is= cmd 52(R) addr ff22 is= 5252 5252
>>> is= cmd 59(Y) addr ff24 is= 5959 5959
>>> device interface is 2
>>> found port 2 chip 1 port 16 bits chip 8 bits
>>> 00 : 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 06  [EMAIL PROTECTED]'6...
>>> 10 : 06 09 13 03 05 03 02 19 02 00 06 00 01 ff 00 00  
>>> 20 : 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20  ...
>>> fwc addr ff00 cmd f0 f0f0 16bit x 8 bit
>>> fwc addr ff001554 cmd aa  16bit x 8 bit
>>> fwc addr ff000aaa cmd 55  16bit x 8 bit
>>> fwc addr ff001554 cmd 90 9090 16bit x 8 bit
>>> fwc addr ff00 cmd f0 f0f0 16bit x 8 bit
>>> fwc addr ffaa cmd 98 9898 16bit x 8 bit
>>> manufacturer is 2
>>> manufacturer id is 0x5
>>> device id is 0x56
>>> device id2 is 0x0
>>> cfi version is 0x3133
>>> size_ratio 1 port 16 bits chip 8 bits
>>> found 1 erase regions
>>> erase region 0: 0x02ff
>>> erase_region_count = 256 erase_region_size = 131072
>>> ERROR: too many flash sectors
>>> fwc addr ff00 cmd f0 f0 8bit x 8 bit
>>> flash_protect ON: from 0xFFF0 to 0xFFF43FFF
>>> flash_protect ON: from 0xFFFE to 0x
>>> 32 MB
>>> basetask = 0, tasks = 2
>>> task_org = 0x03fb4c00
>>> TDT start = 0x0040, end = 0x01b8
>>> PCI:   Bus Dev VenId DevId Class Int
>>> PCI Scan: Found Bus 0, Device 24, Function 0
>>>00  18  168c  001b  0200  00
>>> PCI Scan: Found Bus 0, Device 26, Function 0
>>>00  1a  1057  5809  0680  00
>>> In:serial
>>> Out:   serial
>>> Err:   serial
>>> U-Boot relocated to 03f76000
>>> Net:   mpc5xxx_fec_init_phy... Begin
>>> mpc5xxx_fec_init_phy... Don

[U-Boot] U-Boot Relocation (all sections, not just .text)

2008-10-09 Thread Graeme Russ
Hi All,

I am trying to fully relocate U-Boot out of the Boot Flash into RAM
on my i386 (AMD sc520) board in order to allow the Boot Flash to be
flashed from within U-Boot itself (upgrade in place)

I have added code to patch the command table so all the code can
be relocated. Further investigation revealed that the code has
absolute references into the Boot Flash - printf() format strings
are a prime example, but I'm sure there are others

After a bit of searching around the 'net I discovered gcc's -fpie and
ld's -pie flags which generation a Position Independent Executable.

This looks like it will do the trick - .text is (practically)
identical for varying values of TEXT_BASE and ld produces a .got
section as expected. However, ld creates a lot more sections than
just .got

Before I go down the path of dissecting all this new and wonderful
information, I thought I would quickly ask:

 - Am I looking at the problem the wrong way?
 - Has anyone here looked into making U-Boot 100% relocatable before?
 - Is U-Boot already 100% relocatable (not just code) for any other
   platforms?
 - Has anyone here used pie before and had to write code to adjust
   the offset tables?
 - Does anyone know of a good reference for pie / .got / elf (I have
   found bits and pieces here and there, but no definitive reference)

And lastly - Is it worth the effort, or I should I just set TEXT_BASE
to a known memory location and not bother with the relocation at all?


tia

Graeme
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Re: [U-Boot] Problem with flash on a MPC5200B board

2008-10-09 Thread Jerry Van Baren
Sylvain Lamontagne wrote:
> Hi again everyone
> 
> I tried a lot of stuff today but was still unable get it to work.
> Here is my Flash configuration:
> 
> /*
>  * Flash configuration
> */
> #define CFG_FLASH_BASE   0xFF00
> #define CFG_FLASH_SIZE   0x100
> //#define CFG_ENV_ADDR  0xFFFE
> #define CFG_ENV_OFFSET0x00FE
> //#define CFG_FLASH_MAX_SIZE   0x00ff
> #define CFG_ENV_ADDR(CFG_FLASH_BASE + CFG_ENV_OFFSET)
> #define CFG_MAX_FLASH_BANKS 1   /* max num of memory banks  */
> #define CFG_MAX_FLASH_SECT  128 /* max num of sectors on one chip */
> #define CFG_FLASH_SECT_SIZE 0x2
> #define CFG_FLASH_ERASE_TOUT24  /* Flash Erase Timeout (in ms)  */
> #define CFG_FLASH_WRITE_TOUT500 /* Flash Write Timeout (in ms)  */
> 
> #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
> //#define CONFIG_FLASH_16BIT
> #define CFG_FLASH_CFI_DRIVER
> #define CFG_FLASH_CFI
> #define CFG_FLASH_USE_BUFFER_WRITE
> #define CFG_FLASH_BANKS_LIST{CFG_FLASH_BASE}
> 
> 
> I think the problem may come from the Manufacturer ID and Device ID, from
> the datasheet it's supposed to be:
> Manufacturer ID   xx01h/1h
> Device ID, Word 1227Eh/7Eh
> 
> The CFI detection seems to report them as
> manufacturer id is 0x5
> device id is 0x56
> 
> How can I force it ?
> Or maybe I'm totally searching in the wrong direction...

There is no force.  No Jedi Knights.  Sorry.

You need to figure out your hardware and why the CFI detection isn't 
working or why it *is* working but the flash you have isn't what you 
expected.

My advice is to *manually* do the CFI command sequences to read the QRY 
response and the manufacturer's ID info using "mw" (memory write) commands.

Ahh, here are some good instructions:
   

Things I've found by manually probing: byte lanes swapped (gotta love 
those hardware folks helping me...), bits swapped end-for-end (not 
really - I haven't had this for flash but I have for other h/w g), 
chip width and data lane width, misunderstanding of how the data should 
look when the chip is in command/status mode, etc.

> Sylvain
> 
> 2008/10/8 Sylvain Lamontagne <[EMAIL PROTECTED]>
> 
>> Humm ... Nobody can help me ?
>> If you need more informations I can get them, I would really like to
>> understand the debug output I'm seeing.
>>
>> Thank you
>>
>> Sylvain
>>
>> 2008/10/7 Sylvain Lamontagne <[EMAIL PROTECTED]>
>>
>> Hi Everyone
>>> I'm pretty new to U-Boot and Embedded system globally, but in the last few
>>> weeks I have learn a lot and I'm now trying to port correctly U-Boot v 1.3.4
>>> to a custom board based on a Icecube. I'm able to boot a linux kernel with
>>> it when I use the RAM with the bootm command.
>>>
>>> Unfortunately, I must make it work with the FLASH. The chip used for the
>>> flash is a S29GL128 or a S29GL256 from Spansion, they are 16bits chips but

Which specific one are you using on your board, 128 or 256?  Are they 
really Spansion parts or are the "just like Spansion" parts?  How many 
are soldered down on the board?

>>> the bus is only 8bits. By reading the datasheet, these chips are supposed to
>>> support the Common Flash Interface so I'm trying to make then work with the
>>> CFI driver of U-Boot.

Your results (below) are indicating that they are CFI.

>>> Here is what I get when booting with DEBUG activated:
>>>
>>> U-Boot 1.3.4 (Oct  7 2008 - 16:39:49)
 CPU:   MPC5200B v2.2, Core v1.4 at 378 MHz
   Bus 84 MHz, IPB 84 MHz, PCI 21 MHz
 Board: Icecube Based Board
 I2C:   93 kHz, ready
 DRAM:  64 MB
 Top of RAM usable for U-Boot at: 0400
 Reserving 551k for U-Boot at: 03f76000
 Reserving 130k for malloc() at: 03f55800
 Reserving 68 Bytes for Board Info at: 03f557bc
 Reserving 60 Bytes for Global Data at: 03f55780
 Stack Pointer at: 03f55768
 New Stack Pointer is: 03f55768
 Now running in RAM - U-Boot at: 03f76000
 FLASH: flash detect cfi
 fwc addr ff00 cmd f0 f0 8bit x 8 bit
 fwc addr ff00 cmd f0 f0 8bit x 8 bit
 fwc addr ff55 cmd 98 98 8bit x 8 bit
 is= cmd 51(Q) addr ff10 is= 0 51
 fwc addr ff000555 cmd 98 98 8bit x 8 bit
 is= cmd 51(Q) addr ff10 is= 0 51
 fwc addr ff00 cmd f0 f0f0 16bit x 8 bit
 fwc addr ff00 cmd f0 f0f0 16bit x 8 bit
 fwc addr ffaa cmd 98 9898 16bit x 8 bit
 is= cmd 51(Q) addr ff20 is= 5151 5151
 is= cmd 52(R) addr ff22 is= 5252 5252
 is= cmd 59(Y) addr ff24 is= 5959 5959

Sorry, I am not sure how to interpret this.  Do it by hand and see what 
the results are.  The address offsets seem to say 2 chips x8, but the 
data seems to be saying 4 chips x8.

Get the raw data by hand and dissect it.

 device interface is 2
 found port 2 chip 1 port 16 bits chip 8 bits
 00 : 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 06  [EMAIL 
 PROTECTED]'6...
 10 : 06 09 13 03 05 03 02 19 02

Re: [U-Boot] Linux does not boot from flash, but will from RAM

2008-10-09 Thread Jerry Van Baren
Curran, Tom wrote:
> I am using u-boot on the Avnet V5FX30T (Xilinx FPGA, PPC440) eval board
> to boot a Linux 2.6.27-rc4 kernel.  I can use u-boot to tftp the kernel,
> ramdisk, and device tree blob to RAM and boot from there OK.  I copied
> the kernel, ramdisk and blob to flash and verified those elements were
> programmed in flash correctly with 'iminfo', but when I try to boot from
> flash the boot process hangs at "Loading Ramdisk to 03d59000, end
> 03ec8f20 ... OK".  At this point u-boot will restart (after a
> WDT-induced reset?) after a few minutes.  Interestingly enough, I can
> boot from flash IF the ramdisk is already in RAM with a "bootm
> $(kernel_flash_addr) $(ramdisk_ram_addr) $(blob_flash_addr)".  This
> leads me to believe something is going wrong in the copying of the
> ramdisk from flash to RAM.  Perhaps I am doing something wrong or missed
> a step somewhere?  I have read the FAQ, but have not found anything
> relevant.  Perhaps someone here has had this problem too and can offer a
> solution?  Any help is appreciated.  Many thanks in advance!
> 
> --Tom

Hi Tom,

Do you have *no* console output from linux with the ramdisk-in-flash 
version?  I assume you have normal console diarrhea when the ramdisk is 
in ram.  Is linux booting at all?  If your console output isn't 
outputting, it is hard to tell the difference between crashing before 
linux even starts or something much less fatal like the ramdisk not 
mounting properly (rebooting in 180 seconds...).

Can you look in the linux debug output buffer in memory in the failed 
boot?  Find the symbol log_buf in the map file System.map. This will be 
a virtual address, e.g. c013c494 b log_buf . Drop the first nibble to 
get the physical address, e.g. 0x0013c494. Dump this area of memory to 
find what was sent to the system log before the crash.

What happens if you load your ramdisk into ram at 03d59000 (like your 
failed boot) rather than whatever $(ramdisk_ram_addr) is?

Best regards,
gvb

P.S. You should use curly braces ${variable} rather than $(variable).
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Re: [U-Boot] [PATCH] 85xx: Using proper I2C source clock divider for MPC8544

2008-10-09 Thread Kumar Gala

On Sep 30, 2008, at 3:55 AM, Wolfgang Grandegger wrote:

> Measurements with our MPC8544 board showed that the I2C bus frequency
> is wrong by a factor of 1.5. Obviously, the interpretation of the
> MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
> correct. There seems to be an error in the 8544 RM.
>
> Signed-off-by: Wolfgang Grandegger <[EMAIL PROTECTED]>
> ---
> cpu/mpc85xx/speed.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)

can you do me a favor and dump the value of MPC85xx_PORDEVSR2.  Also  
can you tell me what rev 8544 you have.

- k
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[U-Boot] [PATCH 1/4] Make pixis_set_sgmii more general to support MPC85xx boards.

2008-10-09 Thread Jason Jin
From: Liu Yu <[EMAIL PROTECTED]>

The pixis sgmii command depend on the FPGA support on the board, some 85xx
boards support SGMII riser card but did not support this command, define
CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.

Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
PIXIS_VCFGEN1_MASK in header file for both boards.

Signed-off-by: Liu Yu <[EMAIL PROTECTED]>
---
 board/freescale/common/pixis.c |   22 +++---
 include/configs/MPC8544DS.h|3 +++
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index b5a0e84..978a255 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -283,7 +283,7 @@ U_BOOT_CMD(
   "diswd   - Disable watchdog timer \n",
   NULL);
 
-#ifdef CONFIG_FSL_SGMII_RISER
+#ifdef CONFIG_PIXIS_SGMII_CMD
 int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
int which_tsec = -1;
@@ -295,17 +295,33 @@ int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, 
char *argv[])
which_tsec = simple_strtoul(argv[1], NULL, 0);
 
switch (which_tsec) {
+#ifdef CONFIG_TSEC1
case 1:
mask = PIXIS_VSPEED2_TSEC1SER;
switch_mask = PIXIS_VCFGEN1_TSEC1SER;
break;
+#endif
+#ifdef CONFIG_TSEC2
+   case 2:
+   mask = PIXIS_VSPEED2_TSEC2SER;
+   switch_mask = PIXIS_VCFGEN1_TSEC2SER;
+   break;
+#endif
+#ifdef CONFIG_TSEC3
case 3:
mask = PIXIS_VSPEED2_TSEC3SER;
switch_mask = PIXIS_VCFGEN1_TSEC3SER;
break;
+#endif
+#ifdef CONFIG_TSEC4
+   case 4:
+   mask = PIXIS_VSPEED2_TSEC4SER;
+   switch_mask = PIXIS_VCFGEN1_TSEC4SER;
+   break;
+#endif
default:
-   mask = PIXIS_VSPEED2_TSEC1SER | PIXIS_VSPEED2_TSEC3SER;
-   switch_mask = PIXIS_VCFGEN1_TSEC1SER | PIXIS_VCFGEN1_TSEC3SER;
+   mask = PIXIS_VSPEED2_MASK;
+   switch_mask = PIXIS_VCFGEN1_MASK;
break;
}
 
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b650874..76e5fb4 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -202,6 +202,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED2_TSEC3SER 0x1
 #define PIXIS_VCFGEN1_TSEC1SER 0x20
 #define PIXIS_VCFGEN1_TSEC3SER 0x40
+#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
+#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 
 
 /* define to use L1 as initial stack */
@@ -374,6 +376,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_TSEC3   1
 #define CONFIG_TSEC3_NAME  "eTSEC3"
 
+#define CONFIG_PIXIS_SGMII_CMD
 #define CONFIG_FSL_SGMII_RISER 1
 #define SGMII_RISER_PHY_OFFSET 0x1c
 
-- 
1.5.4

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[U-Boot] [PATCH 2/4] Enabled the Freescale SGMII riser card on 8572DS

2008-10-09 Thread Jason Jin
From: Liu Yu <[EMAIL PROTECTED]>

This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.

Signed-off-by: Liu Yu <[EMAIL PROTECTED]>
---
 board/freescale/mpc8572ds/mpc8572ds.c |   48 +
 include/configs/MPC8572DS.h   |   24 
 2 files changed, 72 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8572ds/mpc8572ds.c 
b/board/freescale/mpc8572ds/mpc8572ds.c
index 70b548b..0520137 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -32,8 +32,10 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -521,6 +523,52 @@ unsigned long get_board_ddr_clk(ulong dummy)
 }
 #endif
 
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+   struct tsec_info_struct tsec_info[4];
+   volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+   int num = 0;
+
+#ifdef CONFIG_TSEC1
+   SET_STD_TSEC_INFO(tsec_info[num], 1);
+   if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+   tsec_info[num].flags |= TSEC_SGMII;
+   num++;
+#endif
+#ifdef CONFIG_TSEC2
+   SET_STD_TSEC_INFO(tsec_info[num], 2);
+   if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+   tsec_info[num].flags |= TSEC_SGMII;
+   num++;
+#endif
+#ifdef CONFIG_TSEC3
+   SET_STD_TSEC_INFO(tsec_info[num], 3);
+   if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+   tsec_info[num].flags |= TSEC_SGMII;
+   num++;
+#endif
+#ifdef CONFIG_TSEC4
+   SET_STD_TSEC_INFO(tsec_info[num], 4);
+   if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+   tsec_info[num].flags |= TSEC_SGMII;
+   num++;
+#endif
+
+   if (!num) {
+   printf("No TSECs initialized\n");
+
+   return 0;
+   }
+
+   fsl_sgmii_riser_init(tsec_info, num);
+
+   tsec_eth_init(bis, tsec_info, num);
+
+   return 0;
+}
+#endif
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index d7e3a88..febc755 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -238,6 +238,22 @@ extern unsigned long get_board_ddr_clk(unsigned long 
dummy);
 #define PIXIS_VCLKH0x19/* VELA VCLKH register */
 #define PIXIS_VCLKL0x1A/* VELA VCLKL register */
 #define CFG_PIXIS_VBOOT_MASK   0xc0
+#define PIXIS_VSPEED2_TSEC1SER 0x8
+#define PIXIS_VSPEED2_TSEC2SER 0x4
+#define PIXIS_VSPEED2_TSEC3SER 0x2
+#define PIXIS_VSPEED2_TSEC4SER 0x1
+#define PIXIS_VCFGEN1_TSEC1SER 0x20
+#define PIXIS_VCFGEN1_TSEC2SER 0x20
+#define PIXIS_VCFGEN1_TSEC3SER 0x20
+#define PIXIS_VCFGEN1_TSEC4SER 0x20
+#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
+   | PIXIS_VSPEED2_TSEC2SER \
+   | PIXIS_VSPEED2_TSEC3SER \
+   | PIXIS_VSPEED2_TSEC4SER)
+#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
+   | PIXIS_VCFGEN1_TSEC2SER \
+   | PIXIS_VCFGEN1_TSEC3SER \
+   | PIXIS_VCFGEN1_TSEC4SER)
 
 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
@@ -403,6 +419,14 @@ extern unsigned long get_board_ddr_clk(unsigned long 
dummy);
 #define CONFIG_TSEC4   1
 #define CONFIG_TSEC4_NAME  "eTSEC4"
 
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER 1
+#define SGMII_RISER_PHY_OFFSET 0x1c
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CFG_TBIPA_VALUE0x10 /* avoid conflict with eTSEC4 
paddr */
+#endif
+
 #define TSEC1_PHY_ADDR 0
 #define TSEC2_PHY_ADDR 1
 #define TSEC3_PHY_ADDR 2
-- 
1.5.4

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[U-Boot] [PATCH 3/4] Enabled the Freescale SGMII riser card on 8536DS

2008-10-09 Thread Jason Jin
Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
---
 board/freescale/mpc8536ds/mpc8536ds.c |   43 +
 include/configs/MPC8536DS.h   |3 ++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c 
b/board/freescale/mpc8536ds/mpc8536ds.c
index 8216c70..3401133 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -34,8 +34,11 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -608,6 +611,46 @@ get_board_ddr_clk(ulong dummy)
 }
 #endif
 
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+   struct tsec_info_struct tsec_info[2];
+   volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+   int num = 0;
+   uint devdisr = gur->devdisr;
+   uint sdrs2_io_sel =
+   (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+
+#ifdef CONFIG_TSEC1
+   SET_STD_TSEC_INFO(tsec_info[num], 1);
+   if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
+   tsec_info[num].phyaddr = 0;
+   tsec_info[num].flags |= TSEC_SGMII;
+   }
+   num++;
+#endif
+#ifdef CONFIG_TSEC3
+   SET_STD_TSEC_INFO(tsec_info[num], 3);
+   if (sdrs2_io_sel == 4) {
+   tsec_info[num].phyaddr = 1;
+   tsec_info[num].flags |= TSEC_SGMII;
+   }
+   num++;
+#endif
+
+   if (!num) {
+   printf("No TSECs initialized\n");
+   return 0;
+   }
+
+   if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
+   fsl_sgmii_riser_init(tsec_info, num);
+
+   tsec_eth_init(bis, tsec_info, num);
+#endif
+   return pci_eth_init(bis);
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 2578bef..365818c 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -428,6 +428,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_TSEC3   1
 #define CONFIG_TSEC3_NAME  "eTSEC3"
 
+#define CONFIG_FSL_SGMII_RISER 1
+#define SGMII_RISER_PHY_OFFSET 0x1c
+
 #define TSEC1_PHY_ADDR 1   /* TSEC1 -> PHY1 */
 #define TSEC3_PHY_ADDR 0   /* TSEC3 -> PHY0 */
 
-- 
1.5.4

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[U-Boot] [PATCH 4/4] Do not init SATA when disabled on 8536DS.

2008-10-09 Thread Jason Jin
SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the
driver still try to access the SATA registers, the cpu will hangup.
This patch try to fix this by reading the serdes status before the SATA
initialize.

Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
---
 board/freescale/mpc8536ds/mpc8536ds.c |   12 
 lib_ppc/board.c   |   16 ++--
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c 
b/board/freescale/mpc8536ds/mpc8536ds.c
index 3401133..37d4b61 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -651,6 +651,18 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
 }
 
+int is_sata_supported()
+{
+   volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+   uint devdisr = gur->devdisr;
+   uint sdrs2_io_sel =
+   (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+   if (sdrs2_io_sel & 0x04)
+   return 0;
+
+   return 1;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index c02ac62..564faf2 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -635,6 +635,16 @@ void board_init_f (ulong bootflag)
/* NOTREACHED - relocate_code() does not return */
 }
 
+int __is_sata_supported()
+{
+   /* For some boards, when sata disabled by the switch, and the
+* driver still access the sata registers, the cpu will hangup.
+* please define platform specific is_sata_supported() if your
+* board have such issue.*/
+   return 1;
+}
+int is_sata_supported() __attribute__((weak, alias("__is_sata_supported")));
+
 /
  *
  * This is the next part if the initialization sequence: we are now
@@ -1105,8 +1115,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif
 
 #if defined(CONFIG_CMD_SATA)
-   puts ("SATA:  ");
-   sata_initialize ();
+   if (is_sata_supported()) {
+   puts("SATA:  ");
+   sata_initialize();
+   }
 #endif
 
 #ifdef CONFIG_LAST_STAGE_INIT
-- 
1.5.4

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Re: [U-Boot] [PATCH 2/2] Leave x86emu op code tables in default section

2008-10-09 Thread Jin Zhengxiong-R64188
 > -Original Message-
> From: [EMAIL PROTECTED] 
> [mailto:[EMAIL PROTECTED] On Behalf Of Swarthout 
> Edward L-SWARTHOU
> Sent: Thursday, October 09, 2008 2:27 PM
> To: u-boot@lists.denx.de
> Cc: Swarthout Edward L-SWARTHOU
> Subject: [U-Boot] [PATCH 2/2] Leave x86emu op code tables in 
> default section
> 
> Forcing the tables into got2 caused extra relocation when 
> using -mrelocatable.
> This patch requires any board defining CONFIG_BIOSEMU to use 
> -mrelocatable.
> 
> Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]>
> ---
> 
> The only boards which define CONFIG_BIOSEMU are:
> MPC8536DS, MPC8572DS, MPC8544DS, HPC8641HPCN, and sequoia.
> I've tested this patch on the 8572 and 8544 boards.
> 
Ack, Tested on 8536DS board.

Jason
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Re: [U-Boot] [PATCH 08/13 v3] ARM: OMAP3: Add NAND support

2008-10-09 Thread Dirk Behme

Scott Wood wrote:

[EMAIL PROTECTED] wrote:


+unsigned char cs;
+volatile unsigned long gpmc_cs_base_add;



Make these static.  gpmc_cs_base_add should be a pointer, not "unsigned 
long".  Volatile isn't needed since you use I/O accessors, and 
definitely isn't needed on the address itself.


Changed in attachment.


+/*
+ * omap_nand_hwcontrol - Set the address pointers corretly for the
+ *following address/data/command operation
+ */
+static void omap_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+unsigned int ctrl)
+{
+register struct nand_chip *this = mtd->priv;
+
+/* Point the IO_ADDR to DATA and ADDRESS registers instead
+   of chip address */
+switch (ctrl) {
+case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
+this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
+this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+break;
+case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
+this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR;
+this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+break;
+case NAND_CTRL_CHANGE | NAND_NCE:
+this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+break;
+}



IO_ADDR_R never seems to change; you can leave it out of here and 
omap_nand_wait.


Yes, thanks. Removed in attachment.


+/*
+ * omap_nand_wait - called primarily after a program/erase operation
+ *so that we access NAND again only after the device
+ *is ready again.
+ * @mtd:MTD device structure
+ * @chip:nand_chip structure
+ */
+static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+register struct nand_chip *this = mtd->priv;
+int status = 0;
+
+this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
+this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+/* Send the status command and loop until the device is free */
+while (!(status & 0x40)) {
+writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
+status = readb(this->IO_ADDR_R);
+}



Maybe should just do this, to avoid changing client-visible state:
writeb(NAND_CMD_STATUS, &gpmc_cs_base_add[GPMC_NAND_CMD]);

No need for the "& 0xFF".


Modified.


+/* Init ECC Control Register */
+/* Clear all ECC  | Enable Reg1 */
+val = ((0x0001 << 8) | 0x0001);
+writel(val, GPMC_BASE + GPMC_ECC_CONTROL);
+writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG);



Symbolic constants for the bit values would be nice.


Added. Hope you like them ;)


+/*
+ *  omap_calculate_ecc - Generate non-inverted ECC bytes.
+ *
+ *  Using noninverted ECC can be considered ugly since writing a blank
+ *  page ie. padding will clear the ECC bytes. This is no problem as
+ *  long nobody is trying to write data on the seemingly unused page.
+ *  Reading an erased page will produce an ECC mismatch between
+ *  generated and read ECC bytes that has to be dealt with separately.



Where is it dealt with separately?


We already talked about this and extended the comment. To my 
understanding this special handling can't be done in 
omap_calculate_ecc() as it is called from generic NAND code and 
doesn't know if ECC it calculates is correct or not?


Do you have any proposals where and how to handle this?

Any propsals from OMAP experts?

Easiest short term solution would be to add a "FIXME" to comment?


+unsigned long val = 0x0;



Unnecessary initialization.


Removed.


+unsigned long reg;
+
+/* Start Reading from HW ECC1_Result = 0x200 */
+reg = (unsigned long) (GPMC_BASE + GPMC_ECC1_RESULT);
+val = readl(reg);



readl() takes a pointer.  ARM gets away without a warning here because 
it uses macros rather than inline functions, but it's bad practice.


Helper variable removed.


+/* Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required */
+reg = (unsigned long) (GPMC_BASE + GPMC_ECC_CONFIG);
+writel(0x000, reg);



Likewise.


Ditto.


+void omap_nand_switch_ecc(int hardware)
+{
+struct nand_chip *nand;
+
+if (nand_curr_device < 0 ||
+nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+!nand_info[nand_curr_device].name) {
+printf("Error: Can't switch ecc, no devices available\n");
+return;
+}
+
+nand = (&nand_info[nand_curr_device])->priv;
+
+if (!hardware) {
+nand->ecc.mode = NAND_ECC_SOFT;
+nand->ecc.layout = &sw_nand_oob_64;
+nand->ecc.size = 256;/* set default eccsize */
+nand->ecc.bytes = 3;
+nand->ecc.steps = 8;
+nand->ecc.hwctl = 0;
+nand->ecc.calculate = nand_calculate_ecc;
+nand->ecc.correct = nand_correct_data;
+} else {
+nand->ecc.mode = NAND_ECC_HW;
+nand->ecc.layout = &hw_nand_oob_64;
+nand->ecc.size =