Re: [Mesa-dev] [PATCH] r600/sb: Fix constant-logical-operand warning.
On Fri, 12 Oct 2018 at 07:16, Vinson Lee wrote:
>
> sb/sb_bc_parser.cpp:620:27: warning: use of logical '&&' with constant
> operand [-Wconstant-logical-operand]
> if (cf->bc.op_ptr->flags && FF_GDS)
> ^ ~~
> sb/sb_bc_parser.cpp:620:27: note: use '&' for a bitwise operation
> if (cf->bc.op_ptr->flags && FF_GDS)
> ^~
> &
> sb/sb_bc_parser.cpp:620:27: note: remove constant to silence this warning
> if (cf->bc.op_ptr->flags && FF_GDS)
> ~^
>
> Fixes: da977ad90747 ("r600/sb: start adding GDS support")
> Signed-off-by: Vinson Lee
Oops,
Reviewed-by: Dave Airlie
(not currently used as sb is disabled for tess shaders).
Dave.
> ---
> src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> index eafc1cb8ec..90e6df745a 100644
> --- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> +++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
> @@ -617,7 +617,7 @@ int bc_parser::decode_fetch_clause(cf_node* cf) {
> int r;
> unsigned i = cf->bc.addr << 1, cnt = cf->bc.count + 1;
>
> - if (cf->bc.op_ptr->flags && FF_GDS)
> + if (cf->bc.op_ptr->flags & FF_GDS)
> cf->subtype = NST_GDS_CLAUSE;
> else
> cf->subtype = NST_TEX_CLAUSE;
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH] i965: consider a 'base level' when calculating width0, height0, depth0
Hi,
Thanks for your advices.
I will be on vacation from 13.10.2018 till 20.10.2018
so I will try to do it after vacation.
Thanks,
Andrii.
On Thu, Oct 11, 2018 at 6:10 PM Rafael Antognolli <
rafael.antogno...@intel.com> wrote:
> On Thu, Oct 11, 2018 at 03:12:08PM +0300, andrey simiklit wrote:
> > Hi,
> >
> > Thanks for reviewing.
> > This 'simple reproducer' just can cause assertion
> > in the debug mesa version but I don't know
> > how to check things which cause it using opengl api at the moment.
> > I mean it can be some internal mesa things inaccessible outside
> > but anyway I am going to try to do it.
>
> I don't think you need to check for the assertion. You can simply write
> the piglit test that does the same thing as your simple reproducer does,
> and if the test causes an assertion, then if I'm not wrong piglit will
> report that test as a "crash". So we would have coverage. And if your
> test gets to the end of the execution without crashing, you can assume
> it's a pass.
>
> You probably can write some comments by the end of the test stating that
> if it has reached that point, then things should be fine.
>
> As an extra thing, I think the test could additionally check that
> everything rendered correctly (check some colors from the framebuffer).
>
> Anyway, just some ideas.
>
> Thanks,
> Rafael
>
> > Regards,
> > Andrii.
> > On Mon, Oct 8, 2018 at 11:46 PM Rafael Antognolli <
> rafael.antogno...@intel.com>
> > wrote:
> >
> > On Tue, Oct 02, 2018 at 07:16:01PM +0300, asimiklit.w...@gmail.com
> wrote:
> > > From: Andrii Simiklit
> > >
> > > I guess that when we calculating the width0, height0, depth0
> > > to use for function 'intel_miptree_create' we need to consider
> > > the 'base level' like it is done in the
> > 'intel_miptree_create_for_teximage'
> > > function.
> >
> > Hi Andrii, this makes sense to me. I'm also not familiar with this
> code,
> > so I'm not sure this is the right way to solve the issue, but at
> least
> > it's a way.
> >
> > You added a simple test case in the bug, do you think you could make
> > that a piglit test?
> >
> >
> > Thanks,
> > Rafael
> >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107987
> > > Signed-off-by: Andrii Simiklit
> > > ---
> > > .../drivers/dri/i965/intel_tex_validate.c | 26
> ++-
> > > 1 file changed, 25 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> b/src/mesa/
> > drivers/dri/i965/intel_tex_validate.c
> > > index 72ce83c7ce..37aa8f43ec 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> > > @@ -119,8 +119,32 @@ intel_finalize_mipmap_tree(struct brw_context
> *brw,
> > > /* May need to create a new tree:
> > > */
> > > if (!intelObj->mt) {
> > > + const unsigned level = firstImage->base.Base.Level;
> > >intel_get_image_dims(&firstImage->base.Base, &width,
> &height, &
> > depth);
> > > -
> > > + /* Figure out image dimensions at start level. */
> > > + switch(intelObj->base.Target) {
> > > + case GL_TEXTURE_2D_MULTISAMPLE:
> > > + case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
> > > + case GL_TEXTURE_RECTANGLE:
> > > + case GL_TEXTURE_EXTERNAL_OES:
> > > + assert(level == 0);
> > > + break;
> > > + case GL_TEXTURE_3D:
> > > + depth = depth << level;
> > > + /* Fall through */
> > > + case GL_TEXTURE_2D:
> > > + case GL_TEXTURE_2D_ARRAY:
> > > + case GL_TEXTURE_CUBE_MAP:
> > > + case GL_TEXTURE_CUBE_MAP_ARRAY:
> > > + height = height << level;
> > > + /* Fall through */
> > > + case GL_TEXTURE_1D:
> > > + case GL_TEXTURE_1D_ARRAY:
> > > + width = width << level;
> > > + break;
> > > + default:
> > > + unreachable("Unexpected target");
> > > + }
> > >perf_debug("Creating new %s %dx%dx%d %d-level miptree to
> handle "
> > > "finalized texture miptree.\n",
> > >
> _mesa_get_format_name(firstImage->base.Base.TexFormat),
> > > --
> > > 2.17.1
> > >
> > > ___
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> >
>
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>
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Re: [Mesa-dev] [PATCH] loader/dri3: Also wait for front buffer fence if we triggered it
On 2018-10-11 10:40 p.m., Mike Lothian wrote: > I'm still seeing weird graphical corruptions in chrome and sometimes when > playing video > > It's especially noticeable when in inbox.google.com > > I might be suffering from a different issue however If reverting aefac10fecc9 "loader/dri3: Only wait for back buffer fences in dri3_get_buffer" doesn't help, it's indeed a different issue. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v4 5/5] loader/dri3: Enable adaptive sync via _VARIABLE_REFRESH property
On 2018-10-11 6:43 p.m., Nicholas Kazlauskas wrote:
> The DDX driver can be notified of adaptive sync suitability by
> flagging the application's window with the _VARIABLE_REFRESH property.
>
> This property is set on the first swap the application performs
> when adaptive_sync_enable is set to true in the drirc.
>
> It's performed here instead of when the loader is initialized for
> two reasons:
>
> (1) The window's drawable can be missing during loader init.
> This can be observed during the Unigine Superposition benchmark.
>
> (2) Adaptive sync will only be enabled closer to when the application
> actually begins rendering.
>
> If adaptive_sync_enable is false then the _VARIABLE_REFRESH property
> is deleted on loader init.
>
> The property is only managed on the glx DRI3 backend for now. This
> should cover most common applications and games on modern hardware.
>
> Vulkan support can be implemented in a similar manner but would likely
> require splitting the function out into a common helper function.
>
> Signed-off-by: Nicholas Kazlauskas
> ---
> src/loader/loader_dri3_helper.c | 58 -
> src/loader/loader_dri3_helper.h | 2 ++
> 2 files changed, 59 insertions(+), 1 deletion(-)
>
> diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
> index f641a34e6d..d4ff5abe41 100644
> --- a/src/loader/loader_dri3_helper.c
> +++ b/src/loader/loader_dri3_helper.c
> @@ -101,6 +101,39 @@ get_xcb_visualtype_for_depth(struct loader_dri3_drawable
> *draw, int depth)
> return NULL;
> }
>
> +/* Sets the adaptive sync window property state. */
> +static void
> +set_adaptive_sync_property(xcb_connection_t *conn,
> + xcb_window_t window,
> + uint32_t state)
> +{
> + static char const name[] = "_VARIABLE_REFRESH";
> + xcb_intern_atom_cookie_t cookie;
> + xcb_intern_atom_reply_t* reply;
> +
> + cookie = xcb_intern_atom(conn, 0, sizeof(name), name);
> + reply = xcb_intern_atom_reply(conn, cookie, NULL);
> + if (reply == NULL)
> + return;
> +
> + if (state)
> + xcb_change_property(conn,
> +XCB_PROP_MODE_REPLACE,
> +window,
> +reply->atom,
> +XCB_ATOM_CARDINAL,
> +32,
> +1,
> +&state);
The indentation of the second and later parameters doesn't seem to line
up with the opening parenthesis. Also, we usually put as many arguments
on the same line as can fit within ~80 columns.
> + else
> + xcb_delete_property(conn,
> + window,
> + reply->atom);
If the drawable isn't actually a window (can also be a pixmap), these
requests will raise a BadWindow protocol error. An easy way to deal with
that:
cookie = xcb_change/delete_property_checked(conn, ...);
xcb_discard_reply(conn, cookie.sequence);
Maybe also change the parameter of this function to xcb_drawable_t draw.
> + xcb_flush(conn);
This isn't necessary, the Property request will be processed before a
buffer swap anyway.
> - if (draw->ext->config)
> + if (draw->ext->config) {
>draw->ext->config->configQueryi(draw->dri_screen,
>"vblank_mode", &vblank_mode);
>
> + draw->ext->config->configQueryb(draw->dri_screen,
> + "adaptive_sync_enable",
> + &adaptive_sync_enable);
> +
> + draw->adaptive_sync_enable = adaptive_sync_enable;
> +
> + if (!adaptive_sync_enable)
> + set_adaptive_sync_property(conn,
> +(xcb_window_t)draw->drawable,
> +false);
This should be after the if (draw->ext->config) block:
if (!draw->adaptive_sync_enable)
set_adaptive_sync_property(conn, draw->drawable, false);
> diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
> index 0d18181312..86f994cb2a 100644
> --- a/src/loader/loader_dri3_helper.h
> +++ b/src/loader/loader_dri3_helper.h
> @@ -156,6 +156,8 @@ struct loader_dri3_drawable {
> xcb_special_event_t *special_event;
>
> bool first_init;
> + bool adaptive_sync_enable;
BTW, I think the option should be called just "adaptive_sync" instead of
"adaptive_sync_enable". But I can live with the latter.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[Mesa-dev] [Bug 107765] [regression] Batman Arkham City crashes with DXVK under wine
https://bugs.freedesktop.org/show_bug.cgi?id=107765 --- Comment #4 from Samuel Pitoiset --- Does this branch help ? https://cgit.freedesktop.org/~hakzsam/mesa/log/?h=radv_r32g32b32_btoi -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH libdrm] xf86drmHash: remove redundant zero init
On Thursday, 2018-10-11 19:18:10 -0400, mesa-dev-boun...@lists.freedesktop.org wrote: > From: Rob Clark > > drmMalloc() is already calloc() Sounds very much like an implementation detail, but everything relies on it already, so... Reviewed-by: Eric Engestrom > > Signed-off-by: Rob Clark > --- > Small micro-optimization that I noticed while doing some perf work.. > I should probably look at promoting amdgpu's handle_table to core > libdrm and replacing a couple of libdrm_freedreno's xf86drmHash > tables over to that. There is still at least one hashtable (in > some libdrm_freedreno patches I'm working on finalizing) where > handle_table would not be appropriate (ie. key is a ptr).. but the > answer there might be importing a better hashtable implementation > into libdrm. > > Related note, once I land a libdrm_freedreno patchset (hopefully > tomorrow or over the weekend), I'll have interest in making a > libdrm release so I can start landing mesa patches that will > depend on that.. so if anyone else wants me to wait a few days > so they can push something before the next libdrm release, please > let me know. > > xf86drmHash.c | 5 - > 1 file changed, 5 deletions(-) > > diff --git a/xf86drmHash.c b/xf86drmHash.c > index b2fa414e..39900e7e 100644 > --- a/xf86drmHash.c > +++ b/xf86drmHash.c > @@ -109,12 +109,7 @@ void *drmHashCreate(void) > table = drmMalloc(sizeof(*table)); > if (!table) return NULL; > table->magic= HASH_MAGIC; > -table->entries = 0; > -table->hits = 0; > -table->partials = 0; > -table->misses = 0; > > -for (i = 0; i < HASH_SIZE; i++) table->buckets[i] = NULL; > return table; > } > > -- > 2.17.1 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: do not support blitting surfaces for R32G32B32 formats
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_formats.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index a7aa819e2b..59bc46d2fc 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -667,6 +667,13 @@ radv_physical_device_get_format_properties(struct
radv_physical_device *physical
linear |=
VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
tiled |=
VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
+
+ /* Don't support blitting for R32G32B32 formats. */
+ if (format == VK_FORMAT_R32G32B32_SFLOAT ||
+ format == VK_FORMAT_R32G32B32_UINT ||
+ format == VK_FORMAT_R32G32B32_SINT) {
+ linear &= ~VK_FORMAT_FEATURE_BLIT_SRC_BIT;
+ }
}
if (radv_is_colorbuffer_format_supported(format, &blendable)) {
linear |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT;
--
2.19.1
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[Mesa-dev] [PATCH] glsl/linker: validate attribute aliasing before optimizations
Patch does a 'dry run' of assign_attribute_or_color_locations before
optimizations to catch cases where we have aliasing of unused attributes
which is forbidden by the GLSL ES 3.x specifications.
We need to run this pass before unused attributes may be removed and with
attribute binding information from program, therefore we re-use existing
pass in linker rather than attempt to write another one.
This fixes WebGL2 test 'gl-bindAttribLocation-aliasing-inactive' and
Piglit test 'gles-3.0-attribute-aliasing'.
Signed-off-by: Tapani Pälli
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106833
---
src/compiler/glsl/linker.cpp | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 2f4c8860547..905d4b3cbed 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -2709,7 +2709,8 @@ static bool
assign_attribute_or_color_locations(void *mem_ctx,
gl_shader_program *prog,
struct gl_constants *constants,
-unsigned target_index)
+unsigned target_index,
+bool do_assignment)
{
/* Maximum number of generic locations. This corresponds to either the
* maximum number of draw buffers or the maximum number of generic
@@ -3072,6 +3073,9 @@ assign_attribute_or_color_locations(void *mem_ctx,
num_attr++;
}
+ if (!do_assignment)
+ return true;
+
if (target_index == MESA_SHADER_VERTEX) {
unsigned total_attribs_size =
util_bitcount(used_locations & SAFE_MASK_FROM_INDEX(max_index)) +
@@ -4780,12 +4784,12 @@ link_varyings_and_uniforms(unsigned first, unsigned
last,
}
if (!assign_attribute_or_color_locations(mem_ctx, prog, &ctx->Const,
-MESA_SHADER_VERTEX)) {
+MESA_SHADER_VERTEX, true)) {
return false;
}
if (!assign_attribute_or_color_locations(mem_ctx, prog, &ctx->Const,
-MESA_SHADER_FRAGMENT)) {
+MESA_SHADER_FRAGMENT, true)) {
return false;
}
@@ -5162,6 +5166,27 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
lower_tess_level(prog->_LinkedShaders[i]);
}
+ /* Section 13.46 (Vertex Attribute Aliasing) of the OpenGL ES 3.2
+ * specification says:
+ *
+ *"In general, the behavior of GLSL ES should not depend on compiler
+ *optimizations which might be implementation-dependent. Name
matching
+ *rules in most languages, including C++ from which GLSL ES is
derived,
+ *are based on declarations rather than use.
+ *
+ *RESOLUTION: The existence of aliasing is determined by declarations
+ *present after preprocessing."
+ *
+ * Because of this rule, we do a 'dry-run' of attribute assignment for
+ * vertex shader inputs here.
+ */
+ if (i == MESA_SHADER_VERTEX) {
+ if (!assign_attribute_or_color_locations(mem_ctx, prog, &ctx->Const,
+ MESA_SHADER_VERTEX, false)) {
+goto done;
+ }
+ }
+
/* Call opts before lowering const arrays to uniforms so we can const
* propagate any elements accessed directly.
*/
--
2.17.1
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Re: [Mesa-dev] [PATCH] radv: do not support blitting surfaces for R32G32B32 formats
Reviewed-by: Bas Nieuwenhuizen
On Fri, Oct 12, 2018 at 2:03 PM Samuel Pitoiset
wrote:
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_formats.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
> index a7aa819e2b..59bc46d2fc 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -667,6 +667,13 @@ radv_physical_device_get_format_properties(struct
> radv_physical_device *physical
> linear |=
> VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
> tiled |=
> VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
> }
> +
> + /* Don't support blitting for R32G32B32 formats. */
> + if (format == VK_FORMAT_R32G32B32_SFLOAT ||
> + format == VK_FORMAT_R32G32B32_UINT ||
> + format == VK_FORMAT_R32G32B32_SINT) {
> + linear &= ~VK_FORMAT_FEATURE_BLIT_SRC_BIT;
> + }
> }
> if (radv_is_colorbuffer_format_supported(format, &blendable))
> {
> linear |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
> VK_FORMAT_FEATURE_BLIT_DST_BIT;
> --
> 2.19.1
>
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Re: [Mesa-dev] [PATCH v4 5/5] loader/dri3: Enable adaptive sync via _VARIABLE_REFRESH property
On 10/12/2018 05:25 AM, Michel Dänzer wrote:
On 2018-10-11 6:43 p.m., Nicholas Kazlauskas wrote:
The DDX driver can be notified of adaptive sync suitability by
flagging the application's window with the _VARIABLE_REFRESH property.
This property is set on the first swap the application performs
when adaptive_sync_enable is set to true in the drirc.
It's performed here instead of when the loader is initialized for
two reasons:
(1) The window's drawable can be missing during loader init.
This can be observed during the Unigine Superposition benchmark.
(2) Adaptive sync will only be enabled closer to when the application
actually begins rendering.
If adaptive_sync_enable is false then the _VARIABLE_REFRESH property
is deleted on loader init.
The property is only managed on the glx DRI3 backend for now. This
should cover most common applications and games on modern hardware.
Vulkan support can be implemented in a similar manner but would likely
require splitting the function out into a common helper function.
Signed-off-by: Nicholas Kazlauskas
---
src/loader/loader_dri3_helper.c | 58 -
src/loader/loader_dri3_helper.h | 2 ++
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index f641a34e6d..d4ff5abe41 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -101,6 +101,39 @@ get_xcb_visualtype_for_depth(struct loader_dri3_drawable
*draw, int depth)
return NULL;
}
+/* Sets the adaptive sync window property state. */
+static void
+set_adaptive_sync_property(xcb_connection_t *conn,
+ xcb_window_t window,
+ uint32_t state)
+{
+ static char const name[] = "_VARIABLE_REFRESH";
+ xcb_intern_atom_cookie_t cookie;
+ xcb_intern_atom_reply_t* reply;
+
+ cookie = xcb_intern_atom(conn, 0, sizeof(name), name);
+ reply = xcb_intern_atom_reply(conn, cookie, NULL);
+ if (reply == NULL)
+ return;
+
+ if (state)
+ xcb_change_property(conn,
+XCB_PROP_MODE_REPLACE,
+window,
+reply->atom,
+XCB_ATOM_CARDINAL,
+32,
+1,
+&state);
The indentation of the second and later parameters doesn't seem to line
up with the opening parenthesis. Also, we usually put as many arguments
on the same line as can fit within ~80 columns.
Noted, will fix.
+ else
+ xcb_delete_property(conn,
+ window,
+ reply->atom);
If the drawable isn't actually a window (can also be a pixmap), these
requests will raise a BadWindow protocol error. An easy way to deal with
that:
cookie = xcb_change/delete_property_checked(conn, ...);
xcb_discard_reply(conn, cookie.sequence);
Maybe also change the parameter of this function to xcb_drawable_t draw.
I've seen this happen for a few applications I've tested, actually. This
seems like a reasonable solution.
+ xcb_flush(conn);
This isn't necessary, the Property request will be processed before a
buffer swap anyway.
It's not necessary for setting the value at least. I'm not sure about
deleting the property, but there should be a flush at some point?
- if (draw->ext->config)
+ if (draw->ext->config) {
draw->ext->config->configQueryi(draw->dri_screen,
"vblank_mode", &vblank_mode);
+ draw->ext->config->configQueryb(draw->dri_screen,
+ "adaptive_sync_enable",
+ &adaptive_sync_enable);
+
+ draw->adaptive_sync_enable = adaptive_sync_enable;
+
+ if (!adaptive_sync_enable)
+ set_adaptive_sync_property(conn,
+(xcb_window_t)draw->drawable,
+false);
This should be after the if (draw->ext->config) block:
if (!draw->adaptive_sync_enable)
set_adaptive_sync_property(conn, draw->drawable, false);
diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
index 0d18181312..86f994cb2a 100644
--- a/src/loader/loader_dri3_helper.h
+++ b/src/loader/loader_dri3_helper.h
@@ -156,6 +156,8 @@ struct loader_dri3_drawable {
xcb_special_event_t *special_event;
bool first_init;
+ bool adaptive_sync_enable;
BTW, I think the option should be called just "adaptive_sync" instead of
"adaptive_sync_enable". But I can live with the latter.
I think this was mostly just following the convention set by previously
proposed patches. I'm open to shortening this.
Nicholas Kazlauskas
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Re: [Mesa-dev] [PATCH libdrm] xf86drmHash: remove redundant zero init
On Fri, 12 Oct 2018 at 00:18, Rob Clark wrote: > > From: Rob Clark > > drmMalloc() is already calloc() > > Signed-off-by: Rob Clark For the patch Reviewed-by: Emil Velikov > --- > Small micro-optimization that I noticed while doing some perf work.. > I should probably look at promoting amdgpu's handle_table to core > libdrm and replacing a couple of libdrm_freedreno's xf86drmHash > tables over to that. There is still at least one hashtable (in > some libdrm_freedreno patches I'm working on finalizing) where > handle_table would not be appropriate (ie. key is a ptr).. but the > answer there might be importing a better hashtable implementation > into libdrm. > Please remember to nuke some of the existing hash implementations, if you want to add new one. The more (nuked) the better. > Related note, once I land a libdrm_freedreno patchset (hopefully > tomorrow or over the weekend), I'll have interest in making a > libdrm release so I can start landing mesa patches that will > depend on that.. so if anyone else wants me to wait a few days > so they can push something before the next libdrm release, please > let me know. > There's nothing urgent on my end. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] anv/android: we need git_sha1.h in include paths
On Thu, 11 Oct 2018 at 18:35, Tapani Pälli wrote: > On 10/11/18 2:22 PM, Eric Engestrom wrote: > > On Thursday, 2018-10-11 08:16:52 +0300, Tapani Pälli wrote: > >> ping ... this fixes Android build as anv_device.c started to include > >> "git_sha1.h" but build does not currently pass the path to this header. > > > > I don't know much about the android build system; is this the right way > > to add a -I include path? > > I consider this the cleanest way and this is how it's done elsewhere in > build. > It's one of the cleanest way indeed. The concept of "dependency" is iffy, so a dummy static library is the best thing AFAICT. Fwiw: Reviewed-by: Emil Velikov -Emil P.S. Don't be afraid to CC/ping me on patches like these. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 108113] [vulkancts] r32g32b32 transfer operations not implemented
https://bugs.freedesktop.org/show_bug.cgi?id=108113 Samuel Pitoiset changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #3 from Samuel Pitoiset --- Blit fails should be fixed with https://cgit.freedesktop.org/mesa/mesa/commit/?id=2c139e2cdff6e4b4b257949b687a2ff06ba976bd Closing as all reported fails are now fixed! -- You are receiving this mail because: You are the QA Contact for the bug. You are on the CC list for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV
https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #20 from Samuel Pitoiset --- Faces issue fixed with the possible patch reported here https://bugs.llvm.org/show_bug.cgi?id=37744#c2 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: drop old DXVK GPU hangs workaround by removing amdgpu-skip-threshold
Tested with Hellblade and LLVM 6, 7 and master, no hangs so far.
Maybe some NIR changes fixed the issue as a side effect.
This should reduce code size a little bit.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 3e3eb96a53..12019e96cd 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -520,9 +520,8 @@ static void radv_init_llvm_target()
*
* "mesa" is the prefix for error messages.
*/
- const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
- "-amdgpu-skip-threshold=1" };
- LLVMParseCommandLineOptions(3, argv, NULL);
+ const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
+ LLVMParseCommandLineOptions(2, argv, NULL);
}
static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
--
2.19.1
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[Mesa-dev] [PATCH 3/3] appveyor: Cache pip's cache files.
It should speed up the Python packages installation. --- appveyor.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/appveyor.yml b/appveyor.yml index a4e942c14ca..ccb84fd3403 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -33,7 +33,9 @@ branches: # - https://www.appveyor.com/blog/2014/06/04/shallow-clone-for-git-repositories clone_depth: 100 +# https://www.appveyor.com/docs/build-cache/ cache: +- '%LOCALAPPDATA%\pip\Cache -> appveyor.yml' - win_flex_bison-2.5.15.zip - llvm-5.0.1-msvc2017-mtd.7z -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] appveyor: Update to newer Mako/winflexbison versions.
As that's what most people are bound to use. --- appveyor.yml | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/appveyor.yml b/appveyor.yml index 66f8354bd66..a4e942c14ca 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -34,7 +34,7 @@ branches: clone_depth: 100 cache: -- win_flex_bison-2.5.9.zip +- win_flex_bison-2.5.15.zip - llvm-5.0.1-msvc2017-mtd.7z os: Visual Studio 2017 @@ -45,7 +45,7 @@ init: - git config --global core.autocrlf true environment: - WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip + WINFLEXBISON_VERSION: 2.5.15 LLVM_ARCHIVE: llvm-5.0.1-msvc2017-mtd.7z install: @@ -55,7 +55,7 @@ install: - python --version - python -m pip --version # Install Mako -- python -m pip install Mako==1.0.6 +- python -m pip install Mako==1.0.7 # Install pywin32 extensions, needed by SCons - python -m pip install pypiwin32 # Install python wheels, necessary to install SCons via pip @@ -64,7 +64,8 @@ install: - python -m pip install scons==3.0.1 - scons --version # Install flex/bison -- if not exist "%WINFLEXBISON_ARCHIVE%" appveyor DownloadFile "https://downloads.sourceforge.net/project/winflexbison/old_versions/%WINFLEXBISON_ARCHIVE%"; +- set WINFLEXBISON_ARCHIVE=win_flex_bison-%WINFLEXBISON_VERSION%.zip +- if not exist "%WINFLEXBISON_ARCHIVE%" appveyor DownloadFile "https://github.com/lexxmark/winflexbison/releases/download/v%WINFLEXBISON_VERSION%/%WINFLEXBISON_ARCHIVE%"; - 7z x -y -owinflexbison\ "%WINFLEXBISON_ARCHIVE%" > nul - set Path=%CD%\winflexbison;%Path% - win_flex --version -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] appveyor: Update to MSVC 2017.
That's what we (and I suppose most people out there) are using now. --- appveyor.yml | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/appveyor.yml b/appveyor.yml index 73be3c57df8..66f8354bd66 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -35,9 +35,9 @@ clone_depth: 100 cache: - win_flex_bison-2.5.9.zip -- llvm-5.0.1-msvc2015-mtd.7z +- llvm-5.0.1-msvc2017-mtd.7z -os: Visual Studio 2015 +os: Visual Studio 2017 init: # Appveyor defaults core.autocrlf to input instead of the default (true), but @@ -46,7 +46,7 @@ init: environment: WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip - LLVM_ARCHIVE: llvm-5.0.1-msvc2015-mtd.7z + LLVM_ARCHIVE: llvm-5.0.1-msvc2017-mtd.7z install: # Check git config @@ -61,7 +61,7 @@ install: # Install python wheels, necessary to install SCons via pip - python -m pip install wheel # Install SCons -- python -m pip install scons==2.5.1 +- python -m pip install scons==3.0.1 - scons --version # Install flex/bison - if not exist "%WINFLEXBISON_ARCHIVE%" appveyor DownloadFile "https://downloads.sourceforge.net/project/winflexbison/old_versions/%WINFLEXBISON_ARCHIVE%"; @@ -76,10 +76,10 @@ install: - set LLVM=%CD%\llvm build_script: -- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.0 llvm=1 +- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.1 llvm=1 after_build: -- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.0 llvm=1 check +- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.1 llvm=1 check # It's possible to setup notification here, as described in -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v5 2/5] util: Add adaptive_sync driconf option
This option lets the user decide whether mesa should notify the
window manager / DDX driver that the current application is adaptive
sync capable.
It's off by default.
Signed-off-by: Nicholas Kazlauskas
---
src/util/xmlpool/t_options.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index e0a30f5fd1..80ddf0e203 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -210,6 +210,11 @@ DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_ADAPTIVE_SYNC(def) \
+DRI_CONF_OPT_BEGIN_B(adaptive_sync,def) \
+DRI_CONF_DESC(en,gettext("Adapt the monitor sync to the application
performance (when possible)")) \
+DRI_CONF_OPT_END
+
#define DRI_CONF_MESA_GLTHREAD(def) \
DRI_CONF_OPT_BEGIN_B(mesa_glthread, def) \
DRI_CONF_DESC(en,gettext("Enable offloading GL driver work to a
separate thread")) \
--
2.19.1
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[Mesa-dev] [PATCH v5 1/5] util: Get program name based on path when possible
Some programs start with the path and command line arguments in
argv[0] (program_invocation_name). Chromium is an example of
an application using mesa that does this.
This tries to query the real path for the symbolic link /proc/self/exe
to find the program name instead. It only uses the realpath if it
was a prefix of the invocation to avoid breaking wine programs.
Signed-off-by: Nicholas Kazlauskas
---
src/util/u_process.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/util/u_process.c b/src/util/u_process.c
index 5e5927678d..a1667e7807 100644
--- a/src/util/u_process.c
+++ b/src/util/u_process.c
@@ -41,8 +41,29 @@ static const char *
__getProgramName()
{
char * arg = strrchr(program_invocation_name, '/');
- if (arg)
+ if (arg) {
+ /* If the / character was found this is likely a linux path or
+ * an invocation path for a 64-bit wine program.
+ *
+ * However, some programs pass command line arguments into argv[0].
+ * Strip these arguments out by using the realpath only if it was
+ * a prefix of the invocation name.
+ */
+ static char *path;
+
+ if (!path)
+ path = realpath("/proc/self/exe", NULL);
+
+ if (path && strncmp(path, program_invocation_name, strlen(path)) == 0) {
+ /* This shouldn't be null because path is a a prefix,
+ * but check it anyway since path is static. */
+ char * name = strrchr(path, '/');
+ if (name)
+return name + 1;
+ }
+
return arg+1;
+ }
/* If there was no '/' at all we likely have a windows like path from
* a wine application.
--
2.19.1
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[Mesa-dev] [PATCH v5 0/5] Mesa integration for DRM variable refresh rate API
These patches are part of a proposed new interface for supporting variable refresh rate via DRM properties. It adds a new option for supporting adaptive sync to drirc along with the implementation of notifying the window manager/DDX of the support via a window property. The option is enabled by default for radeonsi so included is an initial blacklist of applications that shouldn't have this option enabled. In order to catch some of these applications a patch to the program name detection was needed to ignore arguments for some Linux applications. === Changes from v4 === * "adaptive_sync_enable" shortened to now "adaptive_sync" * Reordered patches for more logical bisection * Replaced suspicious pointer arithmetic in get program name path to better clarify intent * Errors are now discarded when setting/destroying variable refresh property * Updated formatting in dri3 loader patch === Changes from v3 === * Blacklist updated to include more desktop environments * Variable refresh property is now deleted when adaptive_sync_enable is false during loader init - this should resolve a potential issue with reusing windows with blacklisted applications. === Changes from v2 === * A patch to add the option to the drirc was missing from the v2 patchset. That patch is now included in v3. * The method to fix program name detection for Chromium based applications for the drirc was modified to not break detection for 32-bit/64-bit WINE applications. === Adaptive sync and variable refresh rate === Adaptive sync is part of the DisplayPort specification and allows for graphics adapters to drive displays with varying frame timings. Variable refresh rate (VRR) is essentially the same, but defined for HDMI. === Use cases for variable refresh rate === Variable frame (flip) timings don't align well with fixed refresh rate displays. This results in stuttering, tearing and/or input lag. By adjusting the display refresh rate dynamically these issues can be reduced or eliminated. However, not all content is suitable for dynamic refresh adaptation. The user may experience "flickering" from differences in panel luminance at different refresh rates. Content that flips at an infrequent rate or demand is more likely to cause large changes in refresh rate that result in flickering. Userland needs a way to let the driver know when the screen content is suitable for variable refresh rates. === DRM API to support variable refresh rates === This patch introduces a new API via atomic properties on the DRM connector and CRTC. The drm_connector has one new optional boolean property: * bool vrr_capable - set by the driver if the hardware is capable of supporting variable refresh rates The drm_crtc has one new default boolean property: * bool vrr_enabled - set by userspace indicating that variable refresh rate should be enabled == Overview for DRM driver developers === Driver developers can attach the "vrr_capable" property by calling drm_connector_attach_vrr_capable_property(). This should be done on connectors that could be capable of supporting variable refresh rates (such as DP or HDMI). The "vrr_capable" can then be updated accordingly by calling drm_connector_set_vrr_capable_property(). The "vrr_enabled" property can be checked from the drm_crtc_state object. === Overview for Userland developers == The "vrr_enabled" property on the CRTC should be set to true when the CRTC is suitable for variable refresh rates. To demonstrate the suitability of the API for variable refresh and dynamic adaptation there are additional patches using this API that implement adaptive variable refresh across kernel and userland projects: * DRM (dri-devel) * amdgpu DRM kernel driver (amd-gfx) * xf86-video-amdgpu (https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu) * mesa (mesa-dev) These patches enable adaptive variable refresh on X for AMD hardware. Support for variable refresh is disabled by default in xf86-video-amdgpu and will require additional user configuration. The patches have been tested as working on upstream userland with the GNOME desktop environment under a single monitor setup. They also work on KDE in a single monitor setup with the compositor disabled. The patches require that suitable applications flip via the Present extension to xf86-video-amdgpu for the entire Screen. Some compositors may interfere with this if they are unable to unredirect the window. Full implementation details for these changes can be reviewed in their respective mailing lists and the xf86-video-amdgpu GitLab. === Previous discussions === These patches are based upon feedback from previous threads on the subject. These are linked below for reference: https://lists.freedesktop.org/archives/amd-gfx/2018-April/021047.html https://lists.freedesktop.org/archives/dri-devel/2017-October/155207.html https://lists.freedesktop.org/archives/dri-devel/2018-September/189404.html https://lists.freedesktop.org
[Mesa-dev] [PATCH v5 3/5] drirc: Initial blacklist for adaptive sync
Applications that don't present at a predictable rate (ie. not games) shouldn't have adapative sync enabled. This list covers some of the common desktop compositors, web browsers and video players. Signed-off-by: Nicholas Kazlauskas --- src/util/00-mesa-defaults.conf | 82 ++ 1 file changed, 82 insertions(+) diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index a937c46d05..8e9a87d603 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -21,6 +21,8 @@ Application bugs worked around in this file: built-ins (specifically gl_VertexID), which causes the vertex shaders to fail to compile. +* Applications that are not suitable for adapative sync are blacklisted here. + TODO: document the other workarounds. --> @@ -314,6 +316,86 @@ TODO: document the other workarounds. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v5 5/5] radeonsi: Enable adaptive_sync by default for radeon
It's better to let most applications make use of adaptive sync
by default. Problematic applications can be placed on the blacklist
or the user can manually disable the feature.
Signed-off-by: Nicholas Kazlauskas
---
src/gallium/drivers/radeonsi/driinfo_radeonsi.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index 8c5078c13f..cbf3bb01fb 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,4 +1,8 @@
// DriConf options specific to radeonsi
+DRI_CONF_SECTION_QUALITY
+DRI_CONF_ADAPTIVE_SYNC("true")
+DRI_CONF_SECTION_END
+
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
--
2.19.1
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[Mesa-dev] [PATCH v5 4/5] loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property
The DDX driver can be notified of adaptive sync suitability by
flagging the application's window with the _VARIABLE_REFRESH property.
This property is set on the first swap the application performs
when adaptive_sync is set to true in the drirc.
It's performed here instead of when the loader is initialized for
two reasons:
(1) The window's drawable can be missing during loader init.
This can be observed during the Unigine Superposition benchmark.
(2) Adaptive sync will only be enabled closer to when the application
actually begins rendering.
If adaptive_sync is false then the _VARIABLE_REFRESH property
is deleted on loader init.
The property is only managed on the glx DRI3 backend for now. This
should cover most common applications and games on modern hardware.
Vulkan support can be implemented in a similar manner but would likely
require splitting the function out into a common helper function.
Signed-off-by: Nicholas Kazlauskas
---
src/loader/loader_dri3_helper.c | 47 -
src/loader/loader_dri3_helper.h | 2 ++
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index f641a34e6d..dad0ede624 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -101,6 +101,32 @@ get_xcb_visualtype_for_depth(struct loader_dri3_drawable
*draw, int depth)
return NULL;
}
+/* Sets the adaptive sync window property state. */
+static void
+set_adaptive_sync_property(xcb_connection_t *conn, xcb_drawable_t drawable,
+ uint32_t state)
+{
+ static char const name[] = "_VARIABLE_REFRESH";
+ xcb_intern_atom_cookie_t cookie;
+ xcb_intern_atom_reply_t* reply;
+ xcb_void_cookie_t check;
+
+ cookie = xcb_intern_atom(conn, 0, sizeof(name), name);
+ reply = xcb_intern_atom_reply(conn, cookie, NULL);
+ if (reply == NULL)
+ return;
+
+ if (state)
+ check = xcb_change_property_checked(conn, XCB_PROP_MODE_REPLACE,
+ drawable, reply->atom,
+ XCB_ATOM_CARDINAL, 32, 1, &state);
+ else
+ check = xcb_delete_property_checked(conn, drawable, reply->atom);
+
+ xcb_discard_reply(conn, check.sequence);
+ free(reply);
+}
+
/* Get red channel mask for given drawable at given depth. */
static unsigned int
dri3_get_red_mask_for_depth(struct loader_dri3_drawable *draw, int depth)
@@ -318,6 +344,7 @@ loader_dri3_drawable_init(xcb_connection_t *conn,
xcb_get_geometry_reply_t *reply;
xcb_generic_error_t *error;
GLint vblank_mode = DRI_CONF_VBLANK_DEF_INTERVAL_1;
+ unsigned char adaptive_sync;
int swap_interval;
draw->conn = conn;
@@ -331,16 +358,28 @@ loader_dri3_drawable_init(xcb_connection_t *conn,
draw->have_back = 0;
draw->have_fake_front = 0;
draw->first_init = true;
+ draw->adaptive_sync = false;
+ draw->adaptive_sync_active = false;
draw->cur_blit_source = -1;
draw->back_format = __DRI_IMAGE_FORMAT_NONE;
mtx_init(&draw->mtx, mtx_plain);
cnd_init(&draw->event_cnd);
- if (draw->ext->config)
+ if (draw->ext->config) {
draw->ext->config->configQueryi(draw->dri_screen,
"vblank_mode", &vblank_mode);
+ draw->ext->config->configQueryb(draw->dri_screen,
+ "adaptive_sync",
+ &adaptive_sync);
+
+ draw->adaptive_sync = adaptive_sync;
+
+ if (!adaptive_sync)
+ set_adaptive_sync_property(conn, draw->drawable, false);
+ }
+
switch (vblank_mode) {
case DRI_CONF_VBLANK_NEVER:
case DRI_CONF_VBLANK_DEF_INTERVAL_0:
@@ -879,6 +918,12 @@ loader_dri3_swap_buffers_msc(struct loader_dri3_drawable
*draw,
back = dri3_find_back_alloc(draw);
mtx_lock(&draw->mtx);
+
+ if (draw->adaptive_sync && !draw->adaptive_sync_active) {
+ set_adaptive_sync_property(draw->conn, draw->drawable, true);
+ draw->adaptive_sync_active = true;
+ }
+
if (draw->is_different_gpu && back) {
/* Update the linear buffer before presenting the pixmap */
(void) loader_dri3_blit_image(draw,
diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
index 0d18181312..663ce3c0e2 100644
--- a/src/loader/loader_dri3_helper.h
+++ b/src/loader/loader_dri3_helper.h
@@ -156,6 +156,8 @@ struct loader_dri3_drawable {
xcb_special_event_t *special_event;
bool first_init;
+ bool adaptive_sync;
+ bool adaptive_sync_active;
int swap_interval;
struct loader_dri3_extensions *ext;
--
2.19.1
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Re: [Mesa-dev] [PATCH 1/7] intel/ir: Don't allow allocating zero registers
Patches 1 through 5 and 7 are
Reviewed-by: Ian Romanick
Patch 6 is
Acked-by: Ian Romanick
Someone more familiar with those bits should look at patch 6.
On 10/11/2018 02:32 PM, Jason Ekstrand wrote:
> This simple check helps catch bugs early that can end up propagating
> into later stages of the compile and triggering strange asserts.
> ---
> src/intel/compiler/brw_ir_allocator.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/compiler/brw_ir_allocator.h
> b/src/intel/compiler/brw_ir_allocator.h
> index b1237ed38e7..9f124645ba2 100644
> --- a/src/intel/compiler/brw_ir_allocator.h
> +++ b/src/intel/compiler/brw_ir_allocator.h
> @@ -47,6 +47,7 @@ namespace brw {
>unsigned
>allocate(unsigned size)
>{
> + assert(size > 0);
> if (capacity <= count) {
> capacity = MAX2(16, capacity * 2);
> sizes = (unsigned *)realloc(sizes, capacity * sizeof(unsigned));
>
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[Mesa-dev] [PATCH v2 00/32] intel/isl: Add support for Yf and Ys texturing
This series adds support for the Yf and Ys formats. I've had it kicking around for a while but got bogged down debugging a CNL miptail issue. I decided yesterday to give it a rebase and I'm sending it out again. This time, Ys actually works thanks to anv's ability to enforce 64K alignments of buffers. I do not expect the final anv patch to actually get merged this time around as I've been told by various people that Yf and Ys don't actually help performance that much. They are, however, required for sparse texturing so I'd like to get the ISL patches merged so they can stop bitrotting. This series passes jenkins both as-is and with a hack to disable Ys and fall back to Yf. There are still some bugs with Yf miptails on CNL but I don't think they affect Ys so we can sort them out later. Most of the patches have already been reviewed by Topi (thanks!) so it's just one patch in the middle (Disallow Yf and Ys for 1D depth surfaces) and some of the ones towards the end that need review. Jason Ekstrand (32): intel/isl: Add a isl_surf_get_image_offset_B_tile_el helper intel/blorp: Use isl_surf_get_image_offset_B_tile_el in ccs_ambiguate intel/isl: Make the offset helpers four dimensional intel/isl: Make tile logical extents four dimensional intel/isl: Use a 4D physical total extent for size calculations intel/isl: Expose isl_tiling_get_info intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_GEN9_Yf/s intel/isl: Add gen10 variants of Yf and Ys tiling intel/isl: Implement correct tile size calculations for Ys/Yf intel/isl: Use the tile size for computing standard Y alignments intel/isl: Use ISL_DIM_LAYOUT_GEN9_1D for Yf/Ys intel/isl: Disallow Yf and Ys for 1D depth surfaces intel/isl: Use the depth field of phys_level0_sa for GEN4_2D 3D surfaces intel/isl: Fill out the correct phys_total_extent for Ys/Yf intel/isl: Support Yf/Ys in isl_surf_get_image_offset_sa intel/isl: Pull the uncompressed surface view code from anv intel/blorp: Adjust the compressed copy rectangle before convert_to_single_slice intel/blorp: Use isl_surf_get_uncompressed_surf intel/isl: Support Ys and Yf in isl_surf_get_uncompressed_surf intel/isl: Don't compute image tiling data for Yf/Ys tiling intel/isl: Support Yf/Ys tiling in surf_fill_state intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz intel/isl: Allow Yf and Ys tiling intel/isl: Add initial data-structure support for miptails intel/isl: Add a max_miptail_levels field to isl_tile_info intel/isl: Add support for computing offsets with miptails intel/isl: Add units to view dimensions in isl_surf_get_uncompressed_surf intel/isl: Support miptails in isl_surf_get_uncompressed_surf intel/isl: Disallow CCS on 3D surfaces with miptails intel/isl: Start using miptails anv: Enable support for Yf and Ys tiled images anv/image: Wrap an error return in vk_error src/intel/Makefile.isl.am | 9 +- src/intel/blorp/blorp_blit.c | 69 +- src/intel/blorp/blorp_clear.c | 8 +- src/intel/isl/isl.c | 935 -- src/intel/isl/isl.h | 145 ++- src/intel/isl/isl_drm.c | 6 +- src/intel/isl/isl_emit_depth_stencil.c| 23 +- src/intel/isl/isl_gen7.c | 25 +- src/intel/isl/isl_gen9.c | 85 +- src/intel/isl/isl_storage_image.c | 17 +- src/intel/isl/isl_surface_state.c | 32 +- src/intel/isl/meson.build | 11 + .../tests/isl_surf_get_image_offset_test.c| 4 +- src/intel/isl/tests/isl_tile_std_y_test.c | 201 src/intel/vulkan/anv_device.c | 6 +- src/intel/vulkan/anv_image.c | 47 +- src/mesa/drivers/dri/i965/intel_blit.c| 12 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 +- 18 files changed, 1357 insertions(+), 299 deletions(-) create mode 100644 src/intel/isl/tests/isl_tile_std_y_test.c -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 02/32] intel/blorp: Use isl_surf_get_image_offset_B_tile_el in ccs_ambiguate
Reviewed-by: Topi Pohjolainen --- src/intel/blorp/blorp_clear.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 5b575dccc22..dd974df35d2 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -1086,12 +1086,8 @@ blorp_ccs_ambiguate(struct blorp_batch *batch, } uint32_t offset_B, x_offset_el, y_offset_el; - isl_surf_get_image_offset_el(surf->aux_surf, level, layer, z, -&x_offset_el, &y_offset_el); - isl_tiling_get_intratile_offset_el(surf->aux_surf->tiling, aux_fmtl->bpb, - surf->aux_surf->row_pitch_B, - x_offset_el, y_offset_el, - &offset_B, &x_offset_el, &y_offset_el); + isl_surf_get_image_offset_B_tile_el(surf->aux_surf, level, layer, z, + &offset_B, &x_offset_el, &y_offset_el); params.dst.addr.offset += offset_B; const uint32_t width_px = -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 04/32] intel/isl: Make tile logical extents four dimensional
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 36
src/intel/isl/isl.h | 2 +-
2 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a53fbf3da02..6bc96e86cb5 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -164,7 +164,8 @@ isl_tiling_get_info(enum isl_tiling tiling,
struct isl_tile_info *tile_info)
{
const uint32_t bs = format_bpb / 8;
- struct isl_extent2d logical_el, phys_B;
+ struct isl_extent4d logical_el;
+ struct isl_extent2d phys_B;
if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
/* It is possible to have non-power-of-two formats in a tiled buffer.
@@ -181,25 +182,25 @@ isl_tiling_get_info(enum isl_tiling tiling,
switch (tiling) {
case ISL_TILING_LINEAR:
assert(bs > 0);
- logical_el = isl_extent2d(1, 1);
+ logical_el = isl_extent4d(1, 1, 1, 1);
phys_B = isl_extent2d(bs, 1);
break;
case ISL_TILING_X:
assert(bs > 0);
- logical_el = isl_extent2d(512 / bs, 8);
+ logical_el = isl_extent4d(512 / bs, 8, 1, 1);
phys_B = isl_extent2d(512, 8);
break;
case ISL_TILING_Y0:
assert(bs > 0);
- logical_el = isl_extent2d(128 / bs, 32);
+ logical_el = isl_extent4d(128 / bs, 32, 1, 1);
phys_B = isl_extent2d(128, 32);
break;
case ISL_TILING_W:
assert(bs == 1);
- logical_el = isl_extent2d(64, 64);
+ logical_el = isl_extent4d(64, 64, 1, 1);
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
*
*"If the surface is a stencil buffer (and thus has Tile Mode set
@@ -222,7 +223,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
unsigned height = 1 << (6 - (ffs(bs) / 2) + (2 * is_Ys));
- logical_el = isl_extent2d(width / bs, height);
+ logical_el = isl_extent4d(width / bs, height, 1, 1);
phys_B = isl_extent2d(width, height);
break;
}
@@ -233,7 +234,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
* Y-tiling but actually has two HiZ columns per Y-tiled column.
*/
assert(bs == 16);
- logical_el = isl_extent2d(16, 16);
+ logical_el = isl_extent4d(16, 16, 1, 1);
phys_B = isl_extent2d(128, 32);
break;
@@ -256,7 +257,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
* is 128x256 elements.
*/
assert(format_bpb == 1 || format_bpb == 2);
- logical_el = isl_extent2d(128, 256 / format_bpb);
+ logical_el = isl_extent4d(128, 256 / format_bpb, 1, 1);
phys_B = isl_extent2d(128, 32);
break;
@@ -2307,7 +2308,10 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling
tiling,
struct isl_tile_info tile_info;
isl_tiling_get_info(tiling, bpb, &tile_info);
+ /* Pitches must make sense with the tiling */
assert(row_pitch_B % tile_info.phys_extent_B.width == 0);
+ assert(array_pitch_el_rows % tile_info.logical_extent_el.d == 0);
+ assert(array_pitch_el_rows % tile_info.logical_extent_el.a == 0);
/* For non-power-of-two formats, we need the address to be both tile and
* element-aligned. The easiest way to achieve this is to work with a tile
@@ -2324,14 +2328,22 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling
tiling,
/* Compute the offset into the tile */
*x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w;
*y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h;
- assert(total_z_offset_el == 0);
- assert(total_array_offset == 0);
- *z_offset_el = 0;
- *array_offset = 0;
+ *z_offset_el = total_z_offset_el % tile_info.logical_extent_el.d;
+ *array_offset = total_array_offset % tile_info.logical_extent_el.a;
/* Compute the offset of the tile in units of whole tiles */
uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w;
uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h;
+ uint32_t z_offset_tl = total_z_offset_el / tile_info.logical_extent_el.d;
+ uint32_t a_offset_tl = total_array_offset / tile_info.logical_extent_el.a;
+
+ /* Compute an array pitch in number of tiles */
+ uint32_t array_pitch_tl_rows =
+ array_pitch_el_rows / MAX2(tile_info.logical_extent_el.d,
+ tile_info.logical_extent_el.a);
+
+ /* Add the Z and array offset to the Y offset to get a 2D offset */
+ y_offset_tl += (z_offset_tl + a_offset_tl) * array_pitch_tl_rows;
*base_address_offset =
y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 2476a22161a..474d1d543c9 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1075,7 +1075,7 @@ struct isl_tile_info {
* The exact value of this field depends heavily on the bits-per-block of
* the format being used.
*
[Mesa-dev] [PATCH v2 03/32] intel/isl: Make the offset helpers four dimensional
We need to do this in order to handle Yf and Ys tiling because they use
a four-dimensional tile instead of laying everything out in two
dimensions.
Reviewed-by: Topi Pohjolainen
---
src/intel/blorp/blorp_blit.c | 8 ++-
src/intel/isl/isl.c | 52 ---
src/intel/isl/isl.h | 37 ++---
src/intel/isl/isl_storage_image.c | 6 ++-
.../tests/isl_surf_get_image_offset_test.c| 4 +-
src/mesa/drivers/dri/i965/intel_blit.c| 7 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++-
7 files changed, 98 insertions(+), 23 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index ae3e3c50930..8b8f76dec06 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2108,11 +2108,15 @@ shrink_surface_params(const struct isl_device *dev,
*/
x_offset_sa = (uint32_t)*x0 * px_size_sa.w + info->tile_x_sa;
y_offset_sa = (uint32_t)*y0 * px_size_sa.h + info->tile_y_sa;
+ uint32_t tile_z_sa, tile_a;
isl_tiling_get_intratile_offset_sa(info->surf.tiling,
info->surf.format,
info->surf.row_pitch_B,
- x_offset_sa, y_offset_sa,
+ info->surf.array_pitch_el_rows,
+ x_offset_sa, y_offset_sa, 0, 0,
&byte_offset,
- &info->tile_x_sa, &info->tile_y_sa);
+ &info->tile_x_sa, &info->tile_y_sa,
+ &tile_z_sa, &tile_a);
+ assert(tile_z_sa == 0 && tile_a == 0);
info->addr.offset += byte_offset;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index ffcede1ef61..a53fbf3da02 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2093,7 +2093,9 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
uint32_t *x_offset_sa,
- uint32_t *y_offset_sa)
+ uint32_t *y_offset_sa,
+ uint32_t *z_offset_sa,
+ uint32_t *array_offset)
{
assert(level < surf->levels);
assert(logical_array_layer < surf->logical_level0_px.array_len);
@@ -2104,21 +2106,29 @@ isl_surf_get_image_offset_sa(const struct isl_surf
*surf,
case ISL_DIM_LAYOUT_GEN9_1D:
get_image_offset_sa_gen9_1d(surf, level, logical_array_layer,
x_offset_sa, y_offset_sa);
+ *z_offset_sa = 0;
+ *array_offset = 0;
break;
case ISL_DIM_LAYOUT_GEN4_2D:
get_image_offset_sa_gen4_2d(surf, level, logical_array_layer
+ logical_z_offset_px,
x_offset_sa, y_offset_sa);
+ *z_offset_sa = 0;
+ *array_offset = 0;
break;
case ISL_DIM_LAYOUT_GEN4_3D:
get_image_offset_sa_gen4_3d(surf, level, logical_array_layer +
logical_z_offset_px,
x_offset_sa, y_offset_sa);
+ *z_offset_sa = 0;
+ *array_offset = 0;
break;
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
get_image_offset_sa_gen6_stencil_hiz(surf, level, logical_array_layer +
logical_z_offset_px,
x_offset_sa, y_offset_sa);
+ *z_offset_sa = 0;
+ *array_offset = 0;
break;
default:
@@ -2132,7 +2142,9 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
uint32_t *x_offset_el,
- uint32_t *y_offset_el)
+ uint32_t *y_offset_el,
+ uint32_t *z_offset_el,
+ uint32_t *array_offset)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
@@ -2141,15 +2153,18 @@ isl_surf_get_image_offset_el(const struct isl_surf
*surf,
assert(logical_z_offset_px
< isl_minify(surf->logical_level0_px.depth, level));
- uint32_t x_offset_sa, y_offset_sa;
+ uint32_t x_offset_sa, y_offset_sa, z_offset_sa;
isl_surf_get_image_offset_sa(surf, level,
logical_array_layer,
logical_z_offset_px,
&x_offset_sa,
-&y_offset_sa);
+&y_offset_sa,
+&z_offset_sa,
+array_offset);
*x_offset_el = x_offset_sa / fmtl->bw;
*y_offset_el = y_o
[Mesa-dev] [PATCH v2 01/32] intel/isl: Add a isl_surf_get_image_offset_B_tile_el helper
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 45 -
src/intel/isl/isl.h | 20
2 files changed, 52 insertions(+), 13 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 359293cfcb2..ffcede1ef61 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2163,20 +2163,13 @@ isl_surf_get_image_offset_B_tile_sa(const struct
isl_surf *surf,
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- uint32_t total_x_offset_el, total_y_offset_el;
- isl_surf_get_image_offset_el(surf, level, logical_array_layer,
-logical_z_offset_px,
-&total_x_offset_el,
-&total_y_offset_el);
-
uint32_t x_offset_el, y_offset_el;
- isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb,
- surf->row_pitch_B,
- total_x_offset_el,
- total_y_offset_el,
- offset_B,
- &x_offset_el,
- &y_offset_el);
+ isl_surf_get_image_offset_B_tile_el(surf, level,
+ logical_array_layer,
+ logical_z_offset_px,
+ offset_B,
+ &x_offset_el,
+ &y_offset_el);
if (x_offset_sa) {
*x_offset_sa = x_offset_el * fmtl->bw;
@@ -2191,6 +2184,32 @@ isl_surf_get_image_offset_B_tile_sa(const struct
isl_surf *surf,
}
}
+void
+isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
+uint32_t level,
+uint32_t logical_array_layer,
+uint32_t logical_z_offset_px,
+uint32_t *offset_B,
+uint32_t *x_offset_el,
+uint32_t *y_offset_el)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
+
+ uint32_t total_x_offset_el, total_y_offset_el;
+ isl_surf_get_image_offset_el(surf, level, logical_array_layer,
+logical_z_offset_px,
+&total_x_offset_el,
+&total_y_offset_el);
+
+ isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb,
+ surf->row_pitch_B,
+ total_x_offset_el,
+ total_y_offset_el,
+ offset_B,
+ x_offset_el,
+ y_offset_el);
+}
+
void
isl_surf_get_image_surf(const struct isl_device *dev,
const struct isl_surf *surf,
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index d53c69adbde..df3f2f75d63 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1983,6 +1983,26 @@ isl_surf_get_image_offset_B_tile_sa(const struct
isl_surf *surf,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa);
+/**
+ * Calculate the offset, in bytes and intratile surface elements, to a
+ * subimage in the surface.
+ *
+ * This is equivalent to calling isl_surf_get_image_offset_el, passing the
+ * result to isl_tiling_get_intratile_offset_el.
+ *
+ * @invariant level < surface levels
+ * @invariant logical_array_layer < logical array length of surface
+ * @invariant logical_z_offset_px < logical depth of surface at level
+ */
+void
+isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
+uint32_t level,
+uint32_t logical_array_layer,
+uint32_t logical_z_offset_px,
+uint32_t *offset_B,
+uint32_t *x_offset_el,
+uint32_t *y_offset_el);
+
/**
* Create an isl_surf that represents a particular subimage in the surface.
*
--
2.19.1
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[Mesa-dev] [PATCH v2 05/32] intel/isl: Use a 4D physical total extent for size calculations
With Yf and Ys tiling, everything is actually four dimensional because
we can have multiple depth or multisampled array slices in the same
tile. This commit just enhances the calculations so they can handle it.
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 73 ++---
1 file changed, 55 insertions(+), 18 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6bc96e86cb5..a805facb1ae 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -992,7 +992,7 @@ isl_calc_phys_total_extent_el_gen4_2d(
const struct isl_extent4d *phys_level0_sa,
enum isl_array_pitch_span array_pitch_span,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *total_extent_el)
+ struct isl_extent4d *phys_total_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1005,10 +1005,12 @@ isl_calc_phys_total_extent_el_gen4_2d(
image_align_sa, phys_level0_sa,
array_pitch_span,
&phys_slice0_sa);
- *total_extent_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
.h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
isl_assert_div(phys_slice0_sa.h, fmtl->bh),
+ .d = 1,
+ .a = 1,
};
}
@@ -1023,7 +1025,7 @@ isl_calc_phys_total_extent_el_gen4_3d(
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *phys_total_el)
+ struct isl_extent4d *phys_total_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1070,9 +1072,11 @@ isl_calc_phys_total_extent_el_gen4_3d(
*/
*array_pitch_el_rows =
isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
- *phys_total_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(total_w, fmtl->bw),
.h = isl_assert_div(total_h, fmtl->bh),
+ .d = 1,
+ .a = 1,
};
}
@@ -1088,7 +1092,7 @@ isl_calc_phys_total_extent_el_gen6_stencil_hiz(
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *phys_total_el)
+ struct isl_extent4d *phys_total_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1131,9 +1135,11 @@ isl_calc_phys_total_extent_el_gen6_stencil_hiz(
*array_pitch_el_rows =
isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
- *phys_total_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
.h = isl_assert_div(total_h, fmtl->bh),
+ .d = 1,
+ .a = 1,
};
}
@@ -1148,7 +1154,7 @@ isl_calc_phys_total_extent_el_gen9_1d(
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *phys_total_el)
+ struct isl_extent4d *phys_total_el)
{
MAYBE_UNUSED const struct isl_format_layout *fmtl =
isl_format_get_layout(info->format);
@@ -1168,9 +1174,11 @@ isl_calc_phys_total_extent_el_gen9_1d(
}
*array_pitch_el_rows = 1;
- *phys_total_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(slice_w, fmtl->bw),
.h = phys_level0_sa->array_len,
+ .d = 1,
+ .a = 1,
};
}
@@ -1188,7 +1196,7 @@ isl_calc_phys_total_extent_el(const struct isl_device
*dev,
const struct isl_extent4d *phys_level0_sa,
enum isl_array_pitch_span array_pitch_span,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *total_extent_el)
+ struct isl_extent4d *phys_total_el)
{
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
@@ -1196,14 +1204,14 @@ isl_calc_phys_total_extent_el(const struct isl_device
*dev,
isl_calc_phys_total_extent_el_gen9_1d(dev, info,
image_align_sa, phys_level0_sa,
array_pitch_el_rows,
-total_extent_el);
+phys_total_el);
return;
case ISL_DIM_LAYOUT_GEN4_2D:
isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout,
image_align_sa, phys_level0_sa,
array_pitch_span,
array_pitch_el_rows,
-
[Mesa-dev] [PATCH v2 10/32] intel/isl: Use the tile size for computing standard Y alignments
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl_gen9.c | 85 +---
1 file changed, 9 insertions(+), 76 deletions(-)
diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c
index 8e460430a1c..f9d391ab67d 100644
--- a/src/intel/isl/isl_gen9.c
+++ b/src/intel/isl/isl_gen9.c
@@ -25,77 +25,6 @@
#include "isl_gen9.h"
#include "isl_priv.h"
-/**
- * Calculate the surface's subimage alignment, in units of surface samples,
- * for the standard tiling formats Yf and Ys.
- */
-static void
-gen9_calc_std_image_alignment_sa(const struct isl_device *dev,
- const struct isl_surf_init_info *restrict
info,
- enum isl_tiling tiling,
- enum isl_msaa_layout msaa_layout,
- struct isl_extent3d *align_sa)
-{
- const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
- assert(isl_tiling_is_std_y(tiling));
-
- const uint32_t bpb = fmtl->bpb;
- const uint32_t is_Ys = tiling == ISL_TILING_GEN9_Ys;
-
- switch (info->dim) {
- case ISL_SURF_DIM_1D:
- /* See the Skylake BSpec > Memory Views > Common Surface Formats >
Surface
- * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
- */
- *align_sa = (struct isl_extent3d) {
- .w = 1 << (12 - (ffs(bpb) - 4) + (4 * is_Ys)),
- .h = 1,
- .d = 1,
- };
- return;
- case ISL_SURF_DIM_2D:
- /* See the Skylake BSpec > Memory Views > Common Surface Formats >
- * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
- * Requirements.
- */
- *align_sa = (struct isl_extent3d) {
- .w = 1 << (6 - ((ffs(bpb) - 4) / 2) + (4 * is_Ys)),
- .h = 1 << (6 - ((ffs(bpb) - 3) / 2) + (4 * is_Ys)),
- .d = 1,
- };
-
- if (is_Ys) {
- /* FINISHME(chadv): I don't trust this code. Untested. */
- isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__);
-
- switch (msaa_layout) {
- case ISL_MSAA_LAYOUT_NONE:
- case ISL_MSAA_LAYOUT_INTERLEAVED:
-break;
- case ISL_MSAA_LAYOUT_ARRAY:
-align_sa->w >>= (ffs(info->samples) - 0) / 2;
-align_sa->h >>= (ffs(info->samples) - 1) / 2;
-break;
- }
- }
- return;
-
- case ISL_SURF_DIM_3D:
- /* See the Skylake BSpec > Memory Views > Common Surface Formats >
Surface
- * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
- */
- *align_sa = (struct isl_extent3d) {
- .w = 1 << (4 - ((ffs(bpb) - 2) / 3) + (4 * is_Ys)),
- .h = 1 << (4 - ((ffs(bpb) - 4) / 3) + (2 * is_Ys)),
- .d = 1 << (4 - ((ffs(bpb) - 3) / 3) + (2 * is_Ys)),
- };
- return;
- }
-
- unreachable("bad isl_surface_type");
-}
-
void
isl_gen9_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict
info,
@@ -166,11 +95,15 @@ isl_gen9_choose_image_alignment_el(const struct isl_device
*dev,
*/
if (isl_tiling_is_std_y(tiling)) {
- struct isl_extent3d image_align_sa;
- gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout,
- &image_align_sa);
-
- *image_align_el = isl_extent3d_sa_to_el(info->format, image_align_sa);
+ /* Ys and Yf tiled images are aligned to the tile size */
+ struct isl_tile_info tile_info;
+ isl_tiling_get_info(tiling, info->dim, fmtl->bpb,
+ info->samples, &tile_info);
+ *image_align_el = (struct isl_extent3d) {
+ .w = tile_info.logical_extent_el.w,
+ .h = tile_info.logical_extent_el.h,
+ .d = tile_info.logical_extent_el.d,
+ };
return;
}
--
2.19.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 08/32] intel/isl: Add gen10 variants of Yf and Ys tiling
---
src/intel/isl/isl.c | 9 +++--
src/intel/isl/isl.h | 12 ++--
src/intel/isl/isl_drm.c | 2 ++
src/intel/isl/isl_gen7.c | 8 +++-
src/intel/isl/isl_surface_state.c | 2 ++
5 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 392c15ca3fb..3ffc6f627b2 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -218,8 +218,11 @@ isl_tiling_get_info(enum isl_tiling tiling,
break;
case ISL_TILING_GEN9_Yf:
- case ISL_TILING_GEN9_Ys: {
- bool is_Ys = tiling == ISL_TILING_GEN9_Ys;
+ case ISL_TILING_GEN9_Ys:
+ case ISL_TILING_GEN10_Yf:
+ case ISL_TILING_GEN10_Ys: {
+ bool is_Ys = tiling == ISL_TILING_GEN9_Ys ||
+ tiling == ISL_TILING_GEN10_Ys;
assert(bs > 0);
unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
@@ -375,7 +378,9 @@ isl_surf_choose_tiling(const struct isl_device *dev,
CHOOSE(ISL_TILING_LINEAR);
}
+ CHOOSE(ISL_TILING_GEN10_Ys);
CHOOSE(ISL_TILING_GEN9_Ys);
+ CHOOSE(ISL_TILING_GEN10_Yf);
CHOOSE(ISL_TILING_GEN9_Yf);
CHOOSE(ISL_TILING_Y0);
CHOOSE(ISL_TILING_X);
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 1c7990f2dc7..200bfbfa85b 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -462,6 +462,8 @@ enum isl_tiling {
ISL_TILING_Y0, /**< Legacy Y tiling */
ISL_TILING_GEN9_Yf, /**< Standard 4K tiling. The 'f' means "four". */
ISL_TILING_GEN9_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
+ ISL_TILING_GEN10_Yf, /**< Standard 4K tiling. The 'f' means "four". */
+ ISL_TILING_GEN10_Ys, /**< Standard 64K tiling. The 's' means "sixty-four".
*/
ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
};
@@ -477,6 +479,8 @@ typedef uint32_t isl_tiling_flags_t;
#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
#define ISL_TILING_GEN9_Yf_BIT(1u << ISL_TILING_GEN9_Yf)
#define ISL_TILING_GEN9_Ys_BIT(1u << ISL_TILING_GEN9_Ys)
+#define ISL_TILING_GEN10_Yf_BIT (1u << ISL_TILING_GEN10_Yf)
+#define ISL_TILING_GEN10_Ys_BIT (1u << ISL_TILING_GEN10_Ys)
#define ISL_TILING_HIZ_BIT(1u << ISL_TILING_HIZ)
#define ISL_TILING_CCS_BIT(1u << ISL_TILING_CCS)
#define ISL_TILING_ANY_MASK (~0u)
@@ -485,11 +489,15 @@ typedef uint32_t isl_tiling_flags_t;
/** Any Y tiling, including legacy Y tiling. */
#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
ISL_TILING_GEN9_Yf_BIT | \
- ISL_TILING_GEN9_Ys_BIT)
+ ISL_TILING_GEN9_Ys_BIT | \
+ ISL_TILING_GEN10_Yf_BIT | \
+ ISL_TILING_GEN10_Ys_BIT)
/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
#define ISL_TILING_STD_Y_MASK (ISL_TILING_GEN9_Yf_BIT | \
- ISL_TILING_GEN9_Ys_BIT)
+ ISL_TILING_GEN9_Ys_BIT | \
+ ISL_TILING_GEN10_Yf_BIT | \
+ ISL_TILING_GEN10_Ys_BIT)
/** @} */
/**
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 62fdd22d10d..03f433a1058 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -46,6 +46,8 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
case ISL_TILING_W:
case ISL_TILING_GEN9_Yf:
case ISL_TILING_GEN9_Ys:
+ case ISL_TILING_GEN10_Yf:
+ case ISL_TILING_GEN10_Ys:
case ISL_TILING_HIZ:
case ISL_TILING_CCS:
return I915_TILING_NONE;
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 91cea299abc..f6f7e1ba7dc 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -197,16 +197,22 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
/* Clear flags unsupported on this hardware */
- if (ISL_DEV_GEN(dev) < 9) {
+ if (ISL_DEV_GEN(dev) != 9) {
*flags &= ~ISL_TILING_GEN9_Yf_BIT;
*flags &= ~ISL_TILING_GEN9_Ys_BIT;
}
+ if (ISL_DEV_GEN(dev) < 10) {
+ *flags &= ~ISL_TILING_GEN10_Yf_BIT;
+ *flags &= ~ISL_TILING_GEN10_Ys_BIT;
+ }
/* And... clear the Yf and Ys bits anyway because Anvil doesn't support
* them yet.
*/
*flags &= ~ISL_TILING_GEN9_Yf_BIT; /* FINISHME[SKL]: Support Yf */
*flags &= ~ISL_TILING_GEN9_Ys_BIT; /* FINISHME[SKL]: Support Ys */
+ *flags &= ~ISL_TILING_GEN10_Yf_BIT; /* FINISHME[SKL]: Support Yf */
+ *flags &= ~ISL_TILING_GEN10_Ys_BIT; /* FINISHME[SKL]: Support Ys */
if (isl_surf_usage_is_depth(info->usage)) {
/* Depth requires Y. */
diff --git a/src/intel/isl/i
[Mesa-dev] [PATCH v2 07/32] intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_GEN9_Yf/s
The Yf and Ys tilings change a bit between gen9 and gen10 so we have to
be able to distinguish between them.
---
src/intel/isl/isl.c | 12 ++--
src/intel/isl/isl.h | 16
src/intel/isl/isl_drm.c | 4 ++--
src/intel/isl/isl_gen7.c | 8
src/intel/isl/isl_gen9.c | 2 +-
src/intel/isl/isl_surface_state.c | 4 ++--
6 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index d6beee987b5..392c15ca3fb 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -217,9 +217,9 @@ isl_tiling_get_info(enum isl_tiling tiling,
phys_B = isl_extent2d(128, 32);
break;
- case ISL_TILING_Yf:
- case ISL_TILING_Ys: {
- bool is_Ys = tiling == ISL_TILING_Ys;
+ case ISL_TILING_GEN9_Yf:
+ case ISL_TILING_GEN9_Ys: {
+ bool is_Ys = tiling == ISL_TILING_GEN9_Ys;
assert(bs > 0);
unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
@@ -375,8 +375,8 @@ isl_surf_choose_tiling(const struct isl_device *dev,
CHOOSE(ISL_TILING_LINEAR);
}
- CHOOSE(ISL_TILING_Ys);
- CHOOSE(ISL_TILING_Yf);
+ CHOOSE(ISL_TILING_GEN9_Ys);
+ CHOOSE(ISL_TILING_GEN9_Yf);
CHOOSE(ISL_TILING_Y0);
CHOOSE(ISL_TILING_X);
CHOOSE(ISL_TILING_W);
@@ -715,7 +715,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
- if (tiling == ISL_TILING_Ys && info->samples > 1)
+ if (tiling == ISL_TILING_GEN9_Ys && info->samples > 1)
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
switch (msaa_layout) {
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 4f8d38e22fb..1c7990f2dc7 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -460,8 +460,8 @@ enum isl_tiling {
ISL_TILING_W,
ISL_TILING_X,
ISL_TILING_Y0, /**< Legacy Y tiling */
- ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
- ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
+ ISL_TILING_GEN9_Yf, /**< Standard 4K tiling. The 'f' means "four". */
+ ISL_TILING_GEN9_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
};
@@ -475,8 +475,8 @@ typedef uint32_t isl_tiling_flags_t;
#define ISL_TILING_W_BIT (1u << ISL_TILING_W)
#define ISL_TILING_X_BIT (1u << ISL_TILING_X)
#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
-#define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
-#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
+#define ISL_TILING_GEN9_Yf_BIT(1u << ISL_TILING_GEN9_Yf)
+#define ISL_TILING_GEN9_Ys_BIT(1u << ISL_TILING_GEN9_Ys)
#define ISL_TILING_HIZ_BIT(1u << ISL_TILING_HIZ)
#define ISL_TILING_CCS_BIT(1u << ISL_TILING_CCS)
#define ISL_TILING_ANY_MASK (~0u)
@@ -484,12 +484,12 @@ typedef uint32_t isl_tiling_flags_t;
/** Any Y tiling, including legacy Y tiling. */
#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
- ISL_TILING_Yf_BIT | \
- ISL_TILING_Ys_BIT)
+ ISL_TILING_GEN9_Yf_BIT | \
+ ISL_TILING_GEN9_Ys_BIT)
/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
-#define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
- ISL_TILING_Ys_BIT)
+#define ISL_TILING_STD_Y_MASK (ISL_TILING_GEN9_Yf_BIT | \
+ ISL_TILING_GEN9_Ys_BIT)
/** @} */
/**
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index e16d7b63917..62fdd22d10d 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -44,8 +44,8 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
return I915_TILING_Y;
case ISL_TILING_W:
- case ISL_TILING_Yf:
- case ISL_TILING_Ys:
+ case ISL_TILING_GEN9_Yf:
+ case ISL_TILING_GEN9_Ys:
case ISL_TILING_HIZ:
case ISL_TILING_CCS:
return I915_TILING_NONE;
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index a9db21fba52..91cea299abc 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -198,15 +198,15 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
/* Clear flags unsupported on this hardware */
if (ISL_DEV_GEN(dev) < 9) {
- *flags &= ~ISL_TILING_Yf_BIT;
- *flags &= ~ISL_TILING_Ys_BIT;
+ *flags &= ~ISL_TILING_GEN9_Yf_BIT;
+ *flags &= ~ISL_TILING_GEN9_Ys_BIT;
}
/* And... clear the Yf and Ys bits anyway because Anvil doesn't support
[Mesa-dev] [PATCH v2 06/32] intel/isl: Expose isl_tiling_get_info
While we're moving things around, we also add dim and sample count
parameters. They are not used yet but the layout of Yf and Ys tiles are
dependent on these parameters.
Reviewed-by: Topi Pohjolainen
---
src/intel/blorp/blorp_blit.c | 5 +++--
src/intel/isl/isl.c| 21 ++---
src/intel/isl/isl.h| 15 +--
src/mesa/drivers/dri/i965/intel_blit.c | 5 +++--
4 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 8b8f76dec06..0ba08d9 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2109,8 +2109,9 @@ shrink_surface_params(const struct isl_device *dev,
x_offset_sa = (uint32_t)*x0 * px_size_sa.w + info->tile_x_sa;
y_offset_sa = (uint32_t)*y0 * px_size_sa.h + info->tile_y_sa;
uint32_t tile_z_sa, tile_a;
- isl_tiling_get_intratile_offset_sa(info->surf.tiling,
- info->surf.format,
info->surf.row_pitch_B,
+ isl_tiling_get_intratile_offset_sa(info->surf.tiling, info->surf.dim,
+ info->surf.format, info->surf.samples,
+ info->surf.row_pitch_B,
info->surf.array_pitch_el_rows,
x_offset_sa, y_offset_sa, 0, 0,
&byte_offset,
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a805facb1ae..d6beee987b5 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -158,9 +158,11 @@ isl_device_get_sample_counts(struct isl_device *dev)
/**
* @param[out] info is written only on success
*/
-static void
+void
isl_tiling_get_info(enum isl_tiling tiling,
+enum isl_surf_dim dim,
uint32_t format_bpb,
+uint32_t samples,
struct isl_tile_info *tile_info)
{
const uint32_t bs = format_bpb / 8;
@@ -175,7 +177,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
*/
assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0);
assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
- isl_tiling_get_info(tiling, format_bpb / 3, tile_info);
+ isl_tiling_get_info(tiling, dim, format_bpb / 3, samples, tile_info);
return;
}
@@ -1432,7 +1434,7 @@ isl_surf_init_s(const struct isl_device *dev,
return false;
struct isl_tile_info tile_info;
- isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
+ isl_tiling_get_info(tiling, info->dim, fmtl->bpb, info->samples,
&tile_info);
const enum isl_dim_layout dim_layout =
isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
@@ -1591,7 +1593,8 @@ isl_surf_get_tile_info(const struct isl_surf *surf,
struct isl_tile_info *tile_info)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
- isl_tiling_get_info(surf->tiling, fmtl->bpb, tile_info);
+ isl_tiling_get_info(surf->tiling, surf->dim, fmtl->bpb,
+ surf->samples, tile_info);
}
bool
@@ -2042,7 +2045,7 @@ get_image_offset_sa_gen6_stencil_hiz(const struct
isl_surf *surf,
isl_surf_get_image_alignment_sa(surf);
struct isl_tile_info tile_info;
- isl_tiling_get_info(surf->tiling, fmtl->bpb, &tile_info);
+ isl_surf_get_tile_info(surf, &tile_info);
const struct isl_extent2d tile_extent_sa = {
.w = tile_info.logical_extent_el.w * fmtl->bw,
.h = tile_info.logical_extent_el.h * fmtl->bh,
@@ -2258,7 +2261,8 @@ isl_surf_get_image_offset_B_tile_el(const struct isl_surf
*surf,
&total_array_offset);
uint32_t z_offset_el, array_offset;
- isl_tiling_get_intratile_offset_el(surf->tiling, fmtl->bpb,
+ isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
+ fmtl->bpb, surf->samples,
surf->row_pitch_B,
surf->array_pitch_el_rows,
total_x_offset_el,
@@ -2317,7 +2321,9 @@ isl_surf_get_image_surf(const struct isl_device *dev,
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
+ enum isl_surf_dim dim,
uint32_t bpb,
+ uint32_t samples,
uint32_t row_pitch_B,
uint32_t array_pitch_el_rows,
uint32_t total_x_offset_el,
@@ -2332,6 +2338,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
{
if (tiling == ISL_TILING_LINEAR) {
assert(bpb % 8 == 0);
+ assert(samples == 1);
assert(total_z_offset_el == 0 && total_array_offset == 0);
*base_address_offset = total_y_offset_el * row_pitch_B +
[Mesa-dev] [PATCH v2 09/32] intel/isl: Implement correct tile size calculations for Ys/Yf
The tile size calculations use a clever bit of math to make them short
and simple. We add unit tests to assert that they identically match the
tables in the PRM.
---
src/intel/Makefile.isl.am | 9 +-
src/intel/isl/isl.c | 66 ++-
src/intel/isl/meson.build | 11 ++
src/intel/isl/tests/isl_tile_std_y_test.c | 201 ++
4 files changed, 281 insertions(+), 6 deletions(-)
create mode 100644 src/intel/isl/tests/isl_tile_std_y_test.c
diff --git a/src/intel/Makefile.isl.am b/src/intel/Makefile.isl.am
index f51294468cd..56d5404a056 100644
--- a/src/intel/Makefile.isl.am
+++ b/src/intel/Makefile.isl.am
@@ -75,7 +75,9 @@ isl/isl_format_layout.c: isl/gen_format_layout.py \
# Tests
#
-check_PROGRAMS += isl/tests/isl_surf_get_image_offset_test
+check_PROGRAMS += \
+ isl/tests/isl_surf_get_image_offset_test \
+ isl/tests/isl_tile_std_y_test
TESTS += $(check_PROGRAMS)
@@ -85,6 +87,11 @@ isl_tests_isl_surf_get_image_offset_test_LDADD = \
$(top_builddir)/src/util/libmesautil.la \
-lm
+isl_tests_isl_tile_std_y_test_LDADD = \
+ common/libintel_common.la \
+ isl/libisl.la \
+ -lm
+
#
EXTRA_DIST += \
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 3ffc6f627b2..21d2babdb56 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -223,13 +223,69 @@ isl_tiling_get_info(enum isl_tiling tiling,
case ISL_TILING_GEN10_Ys: {
bool is_Ys = tiling == ISL_TILING_GEN9_Ys ||
tiling == ISL_TILING_GEN10_Ys;
+ assert(format_bpb >= 8);
- assert(bs > 0);
- unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
- unsigned height = 1 << (6 - (ffs(bs) / 2) + (2 * is_Ys));
+ switch (dim) {
+ case ISL_SURF_DIM_1D:
+ /* See the SKL PRM under Memory Views > Common Surface Formats >
+ * Surface Layout and Tiling > 1D Surfaces > 1D Alignment
+ * Requirements.
+ *
+ * The BSpec claims that 1D images cannot be tiled. This is wrong.
+ */
+ logical_el = (struct isl_extent4d) {
+.w = 1 << (12 - (ffs(format_bpb) - 4) + (4 * is_Ys)),
+.h = 1,
+.d = 1,
+.a = 1,
+ };
+ break;
+
+ case ISL_SURF_DIM_2D:
+ /* See the BSpec Memory Data Formats » Common Surface Formats »
+ * Surface Layout and Tiling [SKL+] » 2D Surfaces SKL+ » 2D/CUBE
+ * Alignment Requirement [SKL+]
+ *
+ * Or, look in the SKL PRM under Memory Views > Common Surface
+ * Formats > Surface Layout and Tiling > 2D Surfaces > 2D/CUBE
+ * Alignment Requirements.
+ */
+ logical_el = (struct isl_extent4d) {
+.w = 1 << (6 - ((ffs(format_bpb) - 4) / 2) + (2 * is_Ys)),
+.h = 1 << (6 - ((ffs(format_bpb) - 3) / 2) + (2 * is_Ys)),
+.d = 1,
+.a = 1,
+ };
+
+ if (samples > 1 && tiling != ISL_TILING_GEN9_Yf) {
+logical_el.w >>= (ffs(samples) - 0) / 2;
+logical_el.h >>= (ffs(samples) - 1) / 2;
+logical_el.a = samples;
+ }
+ break;
+
+ case ISL_SURF_DIM_3D:
+ /* See the BSpec Memory Data Formats » Common Surface Formats »
+ * Surface Layout and Tiling [SKL+] » 3D Surfaces SKL+ » 3D Alignment
+ * Requirements [SKL+]
+ *
+ * Or, look in the SKL PRM under Memory Views > Common Surface
+ * Formats > Surface Layout and Tiling > 3D Surfaces > 3D Alignment
+ * Requirements.
+ */
+ logical_el = (struct isl_extent4d) {
+.w = 1 << (4 - ((ffs(format_bpb) - 2) / 3) + (2 * is_Ys)),
+.h = 1 << (4 - ((ffs(format_bpb) - 4) / 3) + (1 * is_Ys)),
+.d = 1 << (4 - ((ffs(format_bpb) - 3) / 3) + (1 * is_Ys)),
+.a = 1,
+ };
+ break;
+ }
+
+ uint32_t tile_size_B = is_Ys ? (1 << 16) : (1 << 12);
- logical_el = isl_extent4d(width / bs, height, 1, 1);
- phys_B = isl_extent2d(width, height);
+ phys_B.w = logical_el.width * bs;
+ phys_B.h = tile_size_B / phys_B.w;
break;
}
diff --git a/src/intel/isl/meson.build b/src/intel/isl/meson.build
index 62cde190e6e..305a61dc92f 100644
--- a/src/intel/isl/meson.build
+++ b/src/intel/isl/meson.build
@@ -98,4 +98,15 @@ if with_tests
link_with : [libisl, libintel_dev, libmesa_util],
)
)
+
+ test(
+'isl_tile_std_y',
+executable(
+ 'isl_tile_std_y_test',
+ 'tests/isl_tile_std_y_test.c',
+ dependencies : dep_m,
+ include_directories : [inc_common, inc_intel],
+ link_with : [libisl, libintel_dev],
+)
+ )
endif
diff --git a/src/intel/isl/tests/isl_tile_std_y_test.c
b/src/intel
[Mesa-dev] [PATCH v2 11/32] intel/isl: Use ISL_DIM_LAYOUT_GEN9_1D for Yf/Ys
Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 21d2babdb56..58091795a26 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -696,8 +696,10 @@ isl_surf_choose_dim_layout(const struct isl_device *dev, * * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used. + * Yf and Ys tiled surfaces are considered to be linear for the + * purposes of handling 1D surfaces. */ - if (tiling == ISL_TILING_LINEAR) + if (tiling == ISL_TILING_LINEAR || isl_tiling_is_std_y(tiling)) return ISL_DIM_LAYOUT_GEN9_1D; else return ISL_DIM_LAYOUT_GEN4_2D; -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 13/32] intel/isl: Use the depth field of phys_level0_sa for GEN4_2D 3D surfaces
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 18 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++--
2 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 58091795a26..970d437f2e7 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -845,21 +845,10 @@ isl_calc_phys_level0_extent_sa(const struct isl_device
*dev,
unreachable("bad isl_dim_layout");
case ISL_DIM_LAYOUT_GEN4_2D:
- assert(ISL_DEV_GEN(dev) >= 9);
-
+ case ISL_DIM_LAYOUT_GEN4_3D:
*phys_level0_sa = (struct isl_extent4d) {
.w = isl_align_npot(info->width, fmtl->bw),
.h = isl_align_npot(info->height, fmtl->bh),
-.d = 1,
-.a = info->depth,
- };
- break;
-
- case ISL_DIM_LAYOUT_GEN4_3D:
- assert(ISL_DEV_GEN(dev) < 9);
- *phys_level0_sa = (struct isl_extent4d) {
-.w = isl_align(info->width, fmtl->bw),
-.h = isl_align(info->height, fmtl->bh),
.d = info->depth,
.a = 1,
};
@@ -986,8 +975,6 @@ isl_calc_phys_slice0_extent_sa_gen4_2d(
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
- assert(phys_level0_sa->depth == 1);
-
if (info->levels == 1) {
/* Do not pad the surface to the image alignment. Instead, pad it only
* to the pixel format's block alignment.
@@ -1070,9 +1057,10 @@ isl_calc_phys_total_extent_el_gen4_2d(
image_align_sa, phys_level0_sa,
array_pitch_span,
&phys_slice0_sa);
+ uint32_t array_len = MAX(phys_level0_sa->d, phys_level0_sa->a);
*phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
- .h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
+ .h = *array_pitch_el_rows * (array_len - 1) +
isl_assert_div(phys_slice0_sa.h, fmtl->bh),
.d = 1,
.a = 1,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 88d28c20807..36d080129fa 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -444,13 +444,10 @@ get_num_phys_layers(const struct isl_surf *surf, unsigned
level)
/* In case of physical dimensions one needs to consider also the layout.
* See isl_calc_phys_level0_extent_sa().
*/
- if (surf->dim != ISL_SURF_DIM_3D)
+ if (surf->dim == ISL_SURF_DIM_3D)
+ return minify(surf->phys_level0_sa.depth, level);
+ else
return surf->phys_level0_sa.array_len;
-
- if (surf->dim_layout == ISL_DIM_LAYOUT_GEN4_2D)
- return minify(surf->phys_level0_sa.array_len, level);
-
- return minify(surf->phys_level0_sa.depth, level);
}
/** \brief Assert that the level and layer are valid for the miptree. */
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 12/32] intel/isl: Disallow Yf and Ys for 1D depth surfaces
---
src/intel/isl/isl_gen7.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index f6f7e1ba7dc..fe420e4fbd8 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -217,6 +217,15 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
if (isl_surf_usage_is_depth(info->usage)) {
/* Depth requires Y. */
*flags &= ISL_TILING_ANY_Y_MASK;
+
+ /* The Yf and Ys tilings for 1D can't be easily faked as a 2D surface
+ * because there's no calculable qpitch.
+ *
+ * TODO: In theory, on could fake it with surface offset tricks but
+ * that's currently being left as an exercise to the reader.
+ */
+ if (info->dim == ISL_SURF_DIM_1D)
+ *flags &= ~ISL_TILING_STD_Y_MASK;
}
/* Separate stencil requires W tiling, and W tiling requires separate
--
2.19.1
___
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[Mesa-dev] [PATCH v2 15/32] intel/isl: Support Yf/Ys in isl_surf_get_image_offset_sa
All that's really needed here is to handle the array offsetting by using
an Z or array offset instead of the Y offset.
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 45 ++---
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 3ea2a4f8247..a118da56c17 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2009,7 +2009,9 @@ static void
get_image_offset_sa_gen4_2d(const struct isl_surf *surf,
uint32_t level, uint32_t logical_array_layer,
uint32_t *x_offset_sa,
-uint32_t *y_offset_sa)
+uint32_t *y_offset_sa,
+uint32_t *z_offset_sa,
+uint32_t *array_offset)
{
assert(level < surf->levels);
if (surf->dim == ISL_SURF_DIM_3D)
@@ -2026,8 +2028,21 @@ get_image_offset_sa_gen4_2d(const struct isl_surf *surf,
const uint32_t phys_layer = logical_array_layer *
(surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1);
- uint32_t x = 0;
- uint32_t y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
+ uint32_t x = 0, y;
+ if (isl_tiling_is_std_y(surf->tiling)) {
+ y = 0;
+ if (surf->dim == ISL_SURF_DIM_3D) {
+ *z_offset_sa = logical_array_layer;
+ *array_offset = 0;
+ } else {
+ *z_offset_sa = 0;
+ *array_offset = phys_layer;
+ }
+ } else {
+ y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
+ *z_offset_sa = 0;
+ *array_offset = 0;
+ }
for (uint32_t l = 0; l < level; ++l) {
if (l == 1) {
@@ -2167,7 +2182,9 @@ static void
get_image_offset_sa_gen9_1d(const struct isl_surf *surf,
uint32_t level, uint32_t layer,
uint32_t *x_offset_sa,
-uint32_t *y_offset_sa)
+uint32_t *y_offset_sa,
+uint32_t *z_offset_sa,
+uint32_t *array_offset)
{
assert(level < surf->levels);
assert(layer < surf->phys_level0_sa.array_len);
@@ -2189,7 +2206,15 @@ get_image_offset_sa_gen9_1d(const struct isl_surf *surf,
}
*x_offset_sa = x;
- *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf);
+ *z_offset_sa = 0;
+ if (surf->tiling == ISL_TILING_LINEAR) {
+ *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf);
+ *array_offset = 0;
+ } else {
+ assert(isl_tiling_is_std_y(surf->tiling));
+ *y_offset_sa = 0;
+ *array_offset = layer;
+ }
}
/**
@@ -2218,16 +2243,14 @@ isl_surf_get_image_offset_sa(const struct isl_surf
*surf,
switch (surf->dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
get_image_offset_sa_gen9_1d(surf, level, logical_array_layer,
- x_offset_sa, y_offset_sa);
- *z_offset_sa = 0;
- *array_offset = 0;
+ x_offset_sa, y_offset_sa,
+ z_offset_sa, array_offset);
break;
case ISL_DIM_LAYOUT_GEN4_2D:
get_image_offset_sa_gen4_2d(surf, level, logical_array_layer
+ logical_z_offset_px,
- x_offset_sa, y_offset_sa);
- *z_offset_sa = 0;
- *array_offset = 0;
+ x_offset_sa, y_offset_sa,
+ z_offset_sa, array_offset);
break;
case ISL_DIM_LAYOUT_GEN4_3D:
get_image_offset_sa_gen4_3d(surf, level, logical_array_layer +
--
2.19.1
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[Mesa-dev] [PATCH v2 16/32] intel/isl: Pull the uncompressed surface view code from anv
This adds a helper isl_surf_get_uncompressed_surf for creating a surface
which provides an uncompressed view into a compressed surface. The code
is basically a direct port of the uncompressed surface code from the
Vulkan driver which, in turn, was a port from BLORP.
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 75
src/intel/isl/isl.h | 29 ++
src/intel/vulkan/anv_image.c | 34 ++--
3 files changed, 107 insertions(+), 31 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a118da56c17..b8af8ad1176 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2414,6 +2414,81 @@ isl_surf_get_image_surf(const struct isl_device *dev,
assert(ok);
}
+void
+isl_surf_get_uncompressed_surf(const struct isl_device *dev,
+ const struct isl_surf *surf,
+ const struct isl_view *view,
+ struct isl_surf *ucompr_surf,
+ struct isl_view *ucompr_view,
+ uint32_t *offset_B,
+ uint32_t *x_offset_el,
+ uint32_t *y_offset_el)
+{
+ const struct isl_format_layout *fmtl =
+ isl_format_get_layout(surf->format);
+
+ assert(fmtl->bw > 1 || fmtl->bh > 1 || fmtl->bd > 1);
+ assert(isl_format_is_compressed(surf->format));
+ assert(!isl_format_is_compressed(view->format));
+ assert(isl_format_get_layout(view->format)->bpb == fmtl->bpb);
+ assert(view->levels == 1);
+
+ const uint32_t view_width =
+ isl_minify(surf->logical_level0_px.width, view->base_level);
+ const uint32_t view_height =
+ isl_minify(surf->logical_level0_px.height, view->base_level);
+
+ const uint32_t ucompr_width = isl_align_div_npot(view_width, fmtl->bw);
+ const uint32_t ucompr_height = isl_align_div_npot(view_height, fmtl->bh);
+
+ {
+ /* For legacy tilings, we just make a new 2D surface which represents
+ * the single slice of the main surface. Due to hardware restrictions
+ * with intratile offsets, we can only handle a single slice.
+ */
+ assert(view->array_len == 1);
+
+ uint32_t x_offset_sa, y_offset_sa;
+ isl_surf_get_image_surf(dev, surf,
+ view->base_level,
+ surf->dim == ISL_SURF_DIM_3D ?
+ 0 : view->base_array_layer,
+ surf->dim == ISL_SURF_DIM_3D ?
+ view->base_array_layer : 0,
+ ucompr_surf,
+ offset_B, &x_offset_sa, &y_offset_sa);
+
+ ucompr_surf->format = view->format;
+
+ /* We're making an uncompressed view here. The image dimensions
+ * need to be scaled down by the block size.
+ */
+ assert(ucompr_surf->logical_level0_px.width == view_width);
+ assert(ucompr_surf->logical_level0_px.height == view_height);
+ assert(ucompr_surf->logical_level0_px.depth == 1);
+ assert(ucompr_surf->logical_level0_px.array_len = 1);
+ ucompr_surf->logical_level0_px.width = ucompr_width;
+ ucompr_surf->logical_level0_px.height = ucompr_height;
+
+ assert(ucompr_surf->phys_level0_sa.width % fmtl->bw == 0);
+ assert(ucompr_surf->phys_level0_sa.height % fmtl->bh == 0);
+ assert(ucompr_surf->phys_level0_sa.depth == 1);
+ assert(ucompr_surf->phys_level0_sa.array_len == 1);
+ ucompr_surf->phys_level0_sa.width /= fmtl->bw;
+ ucompr_surf->phys_level0_sa.height /= fmtl->bh;
+
+ *x_offset_el = isl_assert_div(x_offset_sa, fmtl->bw);
+ *y_offset_el = isl_assert_div(y_offset_sa, fmtl->bh);
+
+ /* The newly created image represents the one subimage we're referencing
+ * with this view so it only has one array slice and miplevel.
+ */
+ *ucompr_view = *view;
+ ucompr_view->base_array_layer = 0;
+ ucompr_view->base_level = 0;
+ }
+}
+
void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
enum isl_surf_dim dim,
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 200bfbfa85b..213f5b408e2 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -2045,6 +2045,35 @@ isl_surf_get_image_surf(const struct isl_device *dev,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa);
+/**
+ * Create an isl_surf that is an uncompressed view of a compressed isl_surf
+ *
+ * The incoming surface must have a compressed format. The incoming view must
+ * be a valid view for the given surface with the exception that it's format
+ * is an umcompressed format with the same bpb as the surface format. The
+ * incoming view must have isl_view::levels == 1.
+ *
+ * When the function returns, the resulting combination of uncompressed_surf
+ * and uncompressed_view will be a v
[Mesa-dev] [PATCH v2 17/32] intel/blorp: Adjust the compressed copy rectangle before convert_to_single_slice
It doesn't matter for the actual copy rectangle and this makes the
asserts a bit nicer as we don't need to bother with the intratile
offsets because there aren't any yet.
---
src/intel/blorp/blorp_blit.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 0ba08d9..dd43b8643b9 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2454,22 +2454,16 @@ blorp_surf_convert_to_uncompressed(const struct
isl_device *isl_dev,
assert(fmtl->bw > 1 || fmtl->bh > 1);
- /* This is a compressed surface. We need to convert it to a single
-* slice (because compressed layouts don't perfectly match uncompressed
-* ones with the same bpb) and divide x, y, width, and height by the
-* block size.
-*/
- blorp_surf_convert_to_single_slice(isl_dev, info);
+ /* This should be the first modification made to the surface */
+ assert(info->tile_x_sa == 0 && info->tile_y_sa == 0);
if (width && height) {
-#ifndef NDEBUG
- uint32_t right_edge_px = info->tile_x_sa + *x + *width;
- uint32_t bottom_edge_px = info->tile_y_sa + *y + *height;
- assert(*width % fmtl->bw == 0 ||
- right_edge_px == info->surf.logical_level0_px.width);
- assert(*height % fmtl->bh == 0 ||
- bottom_edge_px == info->surf.logical_level0_px.height);
-#endif
+ UNUSED const uint32_t level_width =
+ minify(info->surf.logical_level0_px.width, info->view.base_level);
+ UNUSED const uint32_t level_height =
+ minify(info->surf.logical_level0_px.height, info->view.base_level);
+ assert(*width % fmtl->bw == 0 || *x + *width == level_width);
+ assert(*height % fmtl->bh == 0 || *y + *height == level_height);
*width = DIV_ROUND_UP(*width, fmtl->bw);
*height = DIV_ROUND_UP(*height, fmtl->bh);
}
@@ -2481,6 +2475,13 @@ blorp_surf_convert_to_uncompressed(const struct
isl_device *isl_dev,
*y /= fmtl->bh;
}
+ /* This is a compressed surface. We need to convert it to a single
+* slice (because compressed layouts don't perfectly match uncompressed
+* ones with the same bpb) and divide x, y, width, and height by the
+* block size.
+*/
+ blorp_surf_convert_to_single_slice(isl_dev, info);
+
info->surf.logical_level0_px.width =
DIV_ROUND_UP(info->surf.logical_level0_px.width, fmtl->bw);
info->surf.logical_level0_px.height =
--
2.19.1
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[Mesa-dev] [PATCH v2 14/32] intel/isl: Fill out the correct phys_total_extent for Ys/Yf
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us. We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 51 -
1 file changed, 36 insertions(+), 15 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 970d437f2e7..3ea2a4f8247 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1057,14 +1057,24 @@ isl_calc_phys_total_extent_el_gen4_2d(
image_align_sa, phys_level0_sa,
array_pitch_span,
&phys_slice0_sa);
- uint32_t array_len = MAX(phys_level0_sa->d, phys_level0_sa->a);
- *phys_total_el = (struct isl_extent4d) {
- .w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
- .h = *array_pitch_el_rows * (array_len - 1) +
- isl_assert_div(phys_slice0_sa.h, fmtl->bh),
- .d = 1,
- .a = 1,
- };
+
+ if (isl_tiling_is_std_y(tile_info->tiling)) {
+ *phys_total_el = (struct isl_extent4d) {
+ .w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
+ .h = isl_assert_div(phys_slice0_sa.h, fmtl->bh),
+ .d = isl_assert_div(phys_level0_sa->depth, fmtl->bd),
+ .a = phys_level0_sa->array_len,
+ };
+ } else {
+ uint32_t array_len = MAX(phys_level0_sa->d, phys_level0_sa->a);
+ *phys_total_el = (struct isl_extent4d) {
+ .w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
+ .h = *array_pitch_el_rows * (array_len - 1) +
+ isl_assert_div(phys_slice0_sa.h, fmtl->bh),
+ .d = 1,
+ .a = 1,
+ };
+ }
}
/**
@@ -1204,6 +1214,7 @@ static void
isl_calc_phys_total_extent_el_gen9_1d(
const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info,
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
@@ -1227,12 +1238,22 @@ isl_calc_phys_total_extent_el_gen9_1d(
}
*array_pitch_el_rows = 1;
- *phys_total_el = (struct isl_extent4d) {
- .w = isl_assert_div(slice_w, fmtl->bw),
- .h = phys_level0_sa->array_len,
- .d = 1,
- .a = 1,
- };
+ if (tile_info->tiling == ISL_TILING_LINEAR) {
+ *phys_total_el = (struct isl_extent4d) {
+ .w = isl_assert_div(slice_w, fmtl->bw),
+ .h = phys_level0_sa->array_len,
+ .d = 1,
+ .a = 1,
+ };
+ } else {
+ assert(isl_tiling_is_std_y(tile_info->tiling));
+ *phys_total_el = (struct isl_extent4d) {
+ .w = isl_assert_div(slice_w, fmtl->bw),
+ .h = 1,
+ .d = 1,
+ .a = phys_level0_sa->array_len,
+ };
+ }
}
/**
@@ -1254,7 +1275,7 @@ isl_calc_phys_total_extent_el(const struct isl_device
*dev,
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
- isl_calc_phys_total_extent_el_gen9_1d(dev, info,
+ isl_calc_phys_total_extent_el_gen9_1d(dev, info, tile_info,
image_align_sa, phys_level0_sa,
array_pitch_el_rows,
phys_total_el);
--
2.19.1
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[Mesa-dev] [PATCH v2 18/32] intel/blorp: Use isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen
---
src/intel/blorp/blorp_blit.c | 41 ++--
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index dd43b8643b9..170c2e66106 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2475,30 +2475,29 @@ blorp_surf_convert_to_uncompressed(const struct
isl_device *isl_dev,
*y /= fmtl->bh;
}
- /* This is a compressed surface. We need to convert it to a single
-* slice (because compressed layouts don't perfectly match uncompressed
-* ones with the same bpb) and divide x, y, width, and height by the
-* block size.
-*/
- blorp_surf_convert_to_single_slice(isl_dev, info);
-
- info->surf.logical_level0_px.width =
- DIV_ROUND_UP(info->surf.logical_level0_px.width, fmtl->bw);
- info->surf.logical_level0_px.height =
- DIV_ROUND_UP(info->surf.logical_level0_px.height, fmtl->bh);
+ /* We only want one level and slice */
+ info->view.levels = 1;
+ info->view.array_len = 1;
- assert(info->surf.phys_level0_sa.width % fmtl->bw == 0);
- assert(info->surf.phys_level0_sa.height % fmtl->bh == 0);
- info->surf.phys_level0_sa.width /= fmtl->bw;
- info->surf.phys_level0_sa.height /= fmtl->bh;
+ if (info->surf.dim == ISL_SURF_DIM_3D) {
+ /* Roll the Z offset into the image view */
+ info->view.base_array_layer += info->z_offset;
+ info->z_offset = 0;
+ }
- assert(info->tile_x_sa % fmtl->bw == 0);
- assert(info->tile_y_sa % fmtl->bh == 0);
- info->tile_x_sa /= fmtl->bw;
- info->tile_y_sa /= fmtl->bh;
+ uint32_t offset_B;
+ isl_surf_get_uncompressed_surf(isl_dev, &info->surf, &info->view,
+ &info->surf, &info->view, &offset_B,
+ &info->tile_x_sa, &info->tile_y_sa);
+ info->addr.offset += offset_B;
- /* It's now an uncompressed surface so we need an uncompressed format */
- info->surf.format = get_copy_format_for_bpb(isl_dev, fmtl->bpb);
+ /* BLORP doesn't use the actual intratile offsets. Instead, it needs the
+* surface to be a bit bigger and we offset the vertices instead.
+*/
+ info->surf.logical_level0_px.w += info->tile_x_sa;
+ info->surf.logical_level0_px.h += info->tile_y_sa;
+ info->surf.phys_level0_sa.w += info->tile_x_sa;
+ info->surf.phys_level0_sa.h += info->tile_y_sa;
}
void
--
2.19.1
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[Mesa-dev] [PATCH v2 20/32] intel/isl: Don't compute image tiling data for Yf/Ys tiling
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl_storage_image.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/isl/isl_storage_image.c
b/src/intel/isl/isl_storage_image.c
index d9c45505a14..93805bb98ea 100644
--- a/src/intel/isl/isl_storage_image.c
+++ b/src/intel/isl/isl_storage_image.c
@@ -240,6 +240,17 @@ isl_surf_fill_image_param(const struct isl_device *dev,
view->array_len :
isl_minify(surf->logical_level0_px.d, view->base_level);
+ if (isl_tiling_is_std_y(surf->tiling)) {
+ /* The shader code for doing manual tiling calculations doesn't support
+ * Yf or Ys tiling. Fortunately, we never need it on gen9 where Yf and
+ * Ys were added.
+ */
+ assert(ISL_DEV_GEN(dev) >= 9);
+ assert(isl_has_matching_typed_storage_image_format(dev->info,
+ view->format));
+ return;
+ }
+
uint32_t tile_z_el, phys_array_layer;
isl_surf_get_image_offset_el(surf, view->base_level,
surf->dim == ISL_SURF_DIM_3D ?
--
2.19.1
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[Mesa-dev] [PATCH v2 19/32] intel/isl: Support Ys and Yf in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl.c | 47 -
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index b8af8ad1176..3d0741bc207 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2441,7 +2441,52 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
const uint32_t ucompr_width = isl_align_div_npot(view_width, fmtl->bw);
const uint32_t ucompr_height = isl_align_div_npot(view_height, fmtl->bh);
- {
+ if (isl_tiling_is_std_y(surf->tiling)) {
+ /* Offset to the given miplevel. Because we're using standard tilings
+ * with no miptail, arrays and 3D textures should just work so long as
+ * we have the right array stride in the end.
+ */
+ isl_surf_get_image_offset_B_tile_el(surf, view->base_level, 0, 0,
+ offset_B, x_offset_el, y_offset_el);
+ /* Ys and Yf should have no intratile X or Y offset */
+ assert(*x_offset_el == 0 && *y_offset_el == 0);
+
+ /* Save off the array pitch */
+ const uint32_t array_pitch_el_rows = surf->array_pitch_el_rows;
+
+ const uint32_t view_depth =
+ isl_minify(surf->logical_level0_px.depth, view->base_level);
+ const uint32_t ucompr_depth = isl_align_div_npot(view_depth, fmtl->bd);
+
+ bool ok UNUSED;
+ ok = isl_surf_init(dev, ucompr_surf,
+ .dim = surf->dim,
+ .format = view->format,
+ .width = ucompr_width,
+ .height = ucompr_height,
+ .depth = ucompr_depth,
+ .levels = 1,
+ .array_len = surf->logical_level0_px.array_len,
+ .samples = surf->samples,
+ .row_pitch_B = surf->row_pitch_B,
+ .usage = surf->usage,
+ .tiling_flags = (1u << surf->tiling));
+ assert(ok);
+
+ /* Use the array pitch from the original surface. This way 2D arrays
+ * and 3D textures should work properly, just with one LOD.
+ */
+ assert(ucompr_surf->array_pitch_el_rows <= array_pitch_el_rows);
+ ucompr_surf->array_pitch_el_rows = array_pitch_el_rows;
+
+ /* The newly created image represents only the one miplevel so we
+ * need to adjust the view accordingly. Because we offset it to
+ * miplevel but used a Z and array slice of 0, the array range can be
+ * left alone.
+ */
+ *ucompr_view = *view;
+ ucompr_view->base_level = 0;
+ } else {
/* For legacy tilings, we just make a new 2D surface which represents
* the single slice of the main surface. Due to hardware restrictions
* with intratile offsets, we can only handle a single slice.
--
2.19.1
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[Mesa-dev] [PATCH v2 23/32] intel/isl: Allow Yf and Ys tiling
They are both implemented in ISL now. Instead of disabling them in ISL,
we disable them in the two dirvers.
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl_gen7.c | 8
src/intel/vulkan/anv_image.c | 3 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index fe420e4fbd8..51958f7e2d5 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -206,14 +206,6 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*flags &= ~ISL_TILING_GEN10_Ys_BIT;
}
- /* And... clear the Yf and Ys bits anyway because Anvil doesn't support
-* them yet.
-*/
- *flags &= ~ISL_TILING_GEN9_Yf_BIT; /* FINISHME[SKL]: Support Yf */
- *flags &= ~ISL_TILING_GEN9_Ys_BIT; /* FINISHME[SKL]: Support Ys */
- *flags &= ~ISL_TILING_GEN10_Yf_BIT; /* FINISHME[SKL]: Support Yf */
- *flags &= ~ISL_TILING_GEN10_Ys_BIT; /* FINISHME[SKL]: Support Ys */
-
if (isl_surf_usage_is_depth(info->usage)) {
/* Depth requires Y. */
*flags &= ISL_TILING_ANY_Y_MASK;
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 388f9410564..82ce43ef2b9 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -120,6 +120,9 @@ choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info,
if (isl_mod_info)
flags &= 1 << isl_mod_info->tiling;
+ /* We don't support Yf or Ys tiling yet */
+ flags &= ISL_TILING_STD_Y_MASK;
+
assert(flags);
return flags;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 36d080129fa..cfeb4d67d29 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -573,6 +573,11 @@ make_surface(struct brw_context *brw, GLenum target,
mesa_format format,
num_samples, width0, height0, depth0,
first_level, last_level, mt);
+ /* We don't support Yf or Ys in i965 yet because we use the blitter too
+* much and it can't handle them.
+*/
+ tiling_flags &= ~ISL_TILING_STD_Y_MASK;
+
struct isl_surf_init_info init_info = {
.dim = get_isl_surf_dim(target),
.format = translate_tex_format(brw, format, false),
--
2.19.1
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[Mesa-dev] [PATCH v2 24/32] intel/isl: Add initial data-structure support for miptails
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code. We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.
---
src/intel/isl/isl.c| 1 +
src/intel/isl/isl.h| 11 +++
src/intel/isl/isl_emit_depth_stencil.c | 2 +-
src/intel/isl/isl_surface_state.c | 5 +
4 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 3d0741bc207..4a8380ad540 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1653,6 +1653,7 @@ isl_surf_init_s(const struct isl_device *dev,
.row_pitch_B = row_pitch_B,
.array_pitch_el_rows = array_pitch_el_rows,
.array_pitch_span = array_pitch_span,
+ .miptail_start_level = 15,
.usage = info->usage,
};
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 213f5b408e2..4fb212e33d5 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1145,6 +1145,9 @@ struct isl_surf_init_info {
/** Lower bound for isl_surf::alignment, in bytes. */
uint32_t min_alignment_B;
+ /** Lower bound for where to start the miptail */
+ uint32_t min_miptail_start_level;
+
/**
* Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
* will fail if this is misaligned or out of bounds.
@@ -1219,6 +1222,14 @@ struct isl_surf {
enum isl_array_pitch_span array_pitch_span;
+ /**
+* Level at which the miptail starts.
+*
+* This value is inclusive in the sense that the miptail contains this
+* level.
+*/
+ uint32_t miptail_start_level;
+
/** Copy of isl_surf_init_info::usage. */
isl_surf_usage_flags_t usage;
};
diff --git a/src/intel/isl/isl_emit_depth_stencil.c
b/src/intel/isl/isl_emit_depth_stencil.c
index b07da781be8..c1a40ee20f0 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -115,7 +115,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device
*dev, void *batch,
/* We don't use miptails yet. The PRM recommends that you set "Mip Tail
* Start LOD" to 15 to prevent the hardware from trying to use them.
*/
- db.MipTailStartLOD = 15;
+ db.MipTailStartLOD = info->depth_surf->miptail_start_level;
#elif GEN_GEN >= 7
/* Gen7+ depth is always Y-tiled. We don't even have a bit for it */
#else
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index abd4767acd7..b3e51d6f5e0 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -423,10 +423,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev,
void *state,
}
#if GEN_GEN >= 9
- /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
-* Start LOD" to 15 to prevent the hardware from trying to use them.
-*/
- s.MipTailStartLOD = 15;
+ s.MipTailStartLOD = info->surf->miptail_start_level;
#endif
#if GEN_GEN >= 6
--
2.19.1
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[Mesa-dev] [PATCH v2 22/32] intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl_emit_depth_stencil.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/intel/isl/isl_emit_depth_stencil.c
b/src/intel/isl/isl_emit_depth_stencil.c
index 9cf5a476687..b07da781be8 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -58,6 +58,16 @@ static const uint32_t isl_to_gen_ds_surftype[] = {
[ISL_SURF_DIM_3D] = SURFTYPE_3D,
};
+#if GEN_GEN >= 9
+static const uint8_t isl_tiling_to_gen_trmode[] = {
+ [ISL_TILING_Y0] = NONE,
+ [ISL_TILING_GEN9_Yf]= TILEYF,
+ [ISL_TILING_GEN9_Ys]= TILEYS,
+ [ISL_TILING_GEN10_Yf] = TILEYF,
+ [ISL_TILING_GEN10_Ys] = TILEYS,
+};
+#endif
+
void
isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
const struct
isl_depth_stencil_hiz_emit_info *restrict info)
@@ -97,7 +107,18 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device
*dev, void *batch,
db.DepthBufferMOCS = info->mocs;
#endif
-#if GEN_GEN <= 6
+#if GEN_GEN >= 9
+ /* Gen9+ depth is always Y-tiled but it may be Y0, Yf, or Ys. */
+ assert(isl_tiling_is_any_y(info->depth_surf->tiling));
+ db.TiledResourceMode =
isl_tiling_to_gen_trmode[info->depth_surf->tiling];
+
+ /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
+ * Start LOD" to 15 to prevent the hardware from trying to use them.
+ */
+ db.MipTailStartLOD = 15;
+#elif GEN_GEN >= 7
+ /* Gen7+ depth is always Y-tiled. We don't even have a bit for it */
+#else
db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ?
TILEWALK_YMAJOR :
TILEWALK_XMAJOR;
--
2.19.1
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[Mesa-dev] [PATCH v2 21/32] intel/isl: Support Yf/Ys tiling in surf_fill_state
Reviewed-by: Topi Pohjolainen
---
src/intel/isl/isl_surface_state.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index 26cb2a87c55..abd4767acd7 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -78,6 +78,16 @@ static const uint8_t isl_to_gen_tiling[] = {
};
#endif
+#if GEN_GEN >= 9
+static const uint8_t isl_tiling_to_gen_trmode[] = {
+ [ISL_TILING_Y0] = NONE,
+ [ISL_TILING_GEN9_Yf]= TILEYF,
+ [ISL_TILING_GEN9_Ys]= TILEYS,
+ [ISL_TILING_GEN10_Yf] = TILEYF,
+ [ISL_TILING_GEN10_Ys] = TILEYS,
+};
+#endif
+
#if GEN_GEN >= 7
static const uint32_t isl_to_gen_multisample_layout[] = {
[ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
@@ -416,7 +426,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev,
void *state,
/* We don't use miptails yet. The PRM recommends that you set "Mip Tail
* Start LOD" to 15 to prevent the hardware from trying to use them.
*/
- s.TiledResourceMode = NONE;
s.MipTailStartLOD = 15;
#endif
@@ -442,7 +451,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev,
void *state,
ISL_ARRAY_PITCH_SPAN_COMPACT;
#endif
-#if GEN_GEN >= 8
+#if GEN_GEN >= 9
+ s.TileMode = isl_to_gen_tiling[info->surf->tiling];
+ if (isl_tiling_is_std_y(info->surf->tiling)) {
+ /* 1D Yf/Ys is supposed to have a tile mode of linear */
+ if (info->surf->dim == ISL_SURF_DIM_1D)
+ s.TileMode = LINEAR;
+ s.TiledResourceMode = isl_tiling_to_gen_trmode[info->surf->tiling];
+ }
+#elif GEN_GEN >= 8
s.TileMode = isl_to_gen_tiling[info->surf->tiling];
#else
s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
--
2.19.1
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[Mesa-dev] [PATCH v2 28/32] intel/isl: Support miptails in isl_surf_get_uncompressed_surf
---
src/intel/isl/isl.c | 45 +++--
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 88de1407375..df4fb94a6fe 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2657,11 +2657,22 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
const uint32_t view_height_el = isl_align_div_npot(view_height_px,
fmtl->bh);
if (isl_tiling_is_std_y(surf->tiling)) {
- /* Offset to the given miplevel. Because we're using standard tilings
- * with no miptail, arrays and 3D textures should just work so long as
- * we have the right array stride in the end.
+ /* If the requested level is not part of the miptail, we just ofset to
+ * the requested level. Because we're using standard tilings and aren't
+ * in the miptail, arrays and 3D textures should just work so long as we
+ * have the right array stride in the end.
+ *
+ * If the requested level is in the miptail, we instead offset to the
+ * base of the miptail. Because offsets into the miptail are fixed by
+ * the tiling and don't depend on the actual size of the image, we can
+ * set the level in the view to offset into the miptail regardless of
+ * the fact minification yields different results for the compressed and
+ * uncompressed surface.
*/
- isl_surf_get_image_offset_B_tile_el(surf, view->base_level, 0, 0,
+ const uint32_t base_level =
+ MIN(view->base_level, surf->miptail_start_level);
+
+ isl_surf_get_image_offset_B_tile_el(surf, base_level, 0, 0,
offset_B, x_offset_el, y_offset_el);
/* Ys and Yf should have no intratile X or Y offset */
assert(*x_offset_el == 0 && *y_offset_el == 0);
@@ -2674,16 +2685,31 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
const uint32_t view_depth_el =
isl_align_div_npot(view_depth_px, fmtl->bd);
+ /* We need to compute the size of the uncompressed surface we will
+ * create. If we're not in the miptail, it is just the view size in
+ * surface elements. If we are in a miptail, we need a size that will
+ * minify to the view size in surface elements. This may not be the
+ * same as the size of base_level.
+ */
+ const uint32_t ucompr_level = view->base_level - base_level;
+ struct isl_extent3d ucompr_surf_extent_el = {
+ .w = (view_width_el > 1) ? view_width_el << ucompr_level : 1,
+ .h = (view_height_el > 1) ? view_height_el << ucompr_level : 1,
+ .d = (view_depth_el > 1) ? view_depth_el << ucompr_level : 1,
+ };
+
bool ok UNUSED;
ok = isl_surf_init(dev, ucompr_surf,
.dim = surf->dim,
.format = view->format,
- .width = view_width_el,
- .height = view_height_el,
- .depth = view_depth_el,
- .levels = 1,
+ .width = ucompr_surf_extent_el.width,
+ .height = ucompr_surf_extent_el.height,
+ .depth = ucompr_surf_extent_el.depth,
+ .levels = view->base_level - base_level + 1,
.array_len = surf->logical_level0_px.array_len,
.samples = surf->samples,
+ .min_miptail_start_level =
+ surf->miptail_start_level - base_level,
.row_pitch_B = surf->row_pitch_B,
.usage = surf->usage,
.tiling_flags = (1u << surf->tiling));
@@ -2692,7 +2718,6 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
/* Use the array pitch from the original surface. This way 2D arrays
* and 3D textures should work properly, just with one LOD.
*/
- assert(ucompr_surf->array_pitch_el_rows <= array_pitch_el_rows);
ucompr_surf->array_pitch_el_rows = array_pitch_el_rows;
/* The newly created image represents only the one miplevel so we
@@ -2701,7 +2726,7 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
* left alone.
*/
*ucompr_view = *view;
- ucompr_view->base_level = 0;
+ ucompr_view->base_level -= base_level;
} else {
/* For legacy tilings, we just make a new 2D surface which represents
* the single slice of the main surface. Due to hardware restrictions
--
2.19.1
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[Mesa-dev] [PATCH v2 31/32] anv: Enable support for Yf and Ys tiled images
---
src/intel/vulkan/anv_device.c | 6 --
src/intel/vulkan/anv_image.c | 12
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 6a24d1086d8..7f7778fd81d 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2126,11 +2126,13 @@ anv_vma_alloc(struct anv_device *device, struct anv_bo
*bo)
pthread_mutex_lock(&device->vma_mutex);
+ uint32_t align = bo->size >= (64 << 10) ? (64 << 10) : (4 << 10);
+
bo->offset = 0;
if (bo->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS &&
device->vma_hi_available >= bo->size) {
- uint64_t addr = util_vma_heap_alloc(&device->vma_hi, bo->size, 4096);
+ uint64_t addr = util_vma_heap_alloc(&device->vma_hi, bo->size, align);
if (addr) {
bo->offset = gen_canonical_address(addr);
assert(addr == gen_48b_address(bo->offset));
@@ -2139,7 +2141,7 @@ anv_vma_alloc(struct anv_device *device, struct anv_bo
*bo)
}
if (bo->offset == 0 && device->vma_lo_available >= bo->size) {
- uint64_t addr = util_vma_heap_alloc(&device->vma_lo, bo->size, 4096);
+ uint64_t addr = util_vma_heap_alloc(&device->vma_lo, bo->size, align);
if (addr) {
bo->offset = gen_canonical_address(addr);
assert(addr == gen_48b_address(bo->offset));
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 82ce43ef2b9..93f42dc98f9 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -93,7 +93,8 @@ choose_isl_surf_usage(VkImageCreateFlags vk_create_flags,
}
static isl_tiling_flags_t
-choose_isl_tiling_flags(const struct anv_image_create_info *anv_info,
+choose_isl_tiling_flags(struct anv_device *device,
+const struct anv_image_create_info *anv_info,
const struct isl_drm_modifier_info *isl_mod_info,
bool legacy_scanout)
{
@@ -120,8 +121,11 @@ choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info,
if (isl_mod_info)
flags &= 1 << isl_mod_info->tiling;
- /* We don't support Yf or Ys tiling yet */
- flags &= ISL_TILING_STD_Y_MASK;
+ /* Ys tiling requires softpin so that we can ensure Ys-tiled images are
+* aligned to 64K rather than 4K.
+*/
+ if (!device->instance->physicalDevice.use_softpin)
+ flags &= ~(ISL_TILING_GEN9_Ys_BIT | ISL_TILING_GEN10_Ys_BIT);
assert(flags);
@@ -604,7 +608,7 @@ anv_image_create(VkDevice _device,
assert(format != NULL);
const isl_tiling_flags_t isl_tiling_flags =
- choose_isl_tiling_flags(create_info, isl_mod_info,
+ choose_isl_tiling_flags(device, create_info, isl_mod_info,
image->needs_set_tiling);
image->n_planes = format->n_planes;
--
2.19.1
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[Mesa-dev] [PATCH v2 25/32] intel/isl: Add a max_miptail_levels field to isl_tile_info
---
src/intel/isl/isl.c | 5 +
src/intel/isl/isl.h | 7 +++
2 files changed, 12 insertions(+)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 4a8380ad540..3657b11ee00 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -181,6 +181,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
return;
}
+ uint32_t max_miptail_levels = 0;
switch (tiling) {
case ISL_TILING_LINEAR:
assert(bs > 0);
@@ -239,6 +240,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
.d = 1,
.a = 1,
};
+ max_miptail_levels = is_Ys ? 16 : 12;
break;
case ISL_SURF_DIM_2D:
@@ -262,6 +264,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
logical_el.h >>= (ffs(samples) - 1) / 2;
logical_el.a = samples;
}
+ max_miptail_levels = is_Ys ? 16 - ffs(samples) : 11;
break;
case ISL_SURF_DIM_3D:
@@ -279,6 +282,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
.d = 1 << (4 - ((ffs(format_bpb) - 3) / 3) + (1 * is_Ys)),
.a = 1,
};
+ max_miptail_levels = is_Ys ? 16 : 12;
break;
}
@@ -331,6 +335,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
.format_bpb = format_bpb,
.logical_extent_el = logical_el,
.phys_extent_B = phys_B,
+ .max_miptail_levels = max_miptail_levels,
};
}
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 4fb212e33d5..0bcb7edc899 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1085,6 +1085,13 @@ struct isl_tile_info {
*/
struct isl_extent4d logical_extent_el;
+ /** The maximum number of miplevels that will fit in the miptail.
+*
+* This does not guarantee that the given number of miplevels will fit in
+* the miptail as that is also dependent on the size of the miplevels.
+*/
+ uint32_t max_miptail_levels;
+
/** The physical size of the tile in bytes and rows of bytes
*
* This field determines how the tiles of a surface are physically layed
--
2.19.1
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[Mesa-dev] [PATCH v2 32/32] anv/image: Wrap an error return in vk_error
--- src/intel/vulkan/anv_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 93f42dc98f9..17727695001 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -362,7 +362,7 @@ make_surface(const struct anv_device *dev, .tiling_flags = tiling_flags); if (!ok) - return VK_ERROR_OUT_OF_DEVICE_MEMORY; + return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY); image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE; -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 27/32] intel/isl: Add units to view dimensions in isl_surf_get_uncompressed_surf
---
src/intel/isl/isl.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c86390bf851..88de1407375 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2648,13 +2648,13 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
assert(isl_format_get_layout(view->format)->bpb == fmtl->bpb);
assert(view->levels == 1);
- const uint32_t view_width =
+ const uint32_t view_width_px =
isl_minify(surf->logical_level0_px.width, view->base_level);
- const uint32_t view_height =
+ const uint32_t view_height_px =
isl_minify(surf->logical_level0_px.height, view->base_level);
- const uint32_t ucompr_width = isl_align_div_npot(view_width, fmtl->bw);
- const uint32_t ucompr_height = isl_align_div_npot(view_height, fmtl->bh);
+ const uint32_t view_width_el = isl_align_div_npot(view_width_px, fmtl->bw);
+ const uint32_t view_height_el = isl_align_div_npot(view_height_px,
fmtl->bh);
if (isl_tiling_is_std_y(surf->tiling)) {
/* Offset to the given miplevel. Because we're using standard tilings
@@ -2669,17 +2669,18 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
/* Save off the array pitch */
const uint32_t array_pitch_el_rows = surf->array_pitch_el_rows;
- const uint32_t view_depth =
+ const uint32_t view_depth_px =
isl_minify(surf->logical_level0_px.depth, view->base_level);
- const uint32_t ucompr_depth = isl_align_div_npot(view_depth, fmtl->bd);
+ const uint32_t view_depth_el =
+ isl_align_div_npot(view_depth_px, fmtl->bd);
bool ok UNUSED;
ok = isl_surf_init(dev, ucompr_surf,
.dim = surf->dim,
.format = view->format,
- .width = ucompr_width,
- .height = ucompr_height,
- .depth = ucompr_depth,
+ .width = view_width_el,
+ .height = view_height_el,
+ .depth = view_depth_el,
.levels = 1,
.array_len = surf->logical_level0_px.array_len,
.samples = surf->samples,
@@ -2723,12 +2724,12 @@ isl_surf_get_uncompressed_surf(const struct isl_device
*dev,
/* We're making an uncompressed view here. The image dimensions
* need to be scaled down by the block size.
*/
- assert(ucompr_surf->logical_level0_px.width == view_width);
- assert(ucompr_surf->logical_level0_px.height == view_height);
+ assert(ucompr_surf->logical_level0_px.width == view_width_px);
+ assert(ucompr_surf->logical_level0_px.height == view_height_px);
assert(ucompr_surf->logical_level0_px.depth == 1);
assert(ucompr_surf->logical_level0_px.array_len = 1);
- ucompr_surf->logical_level0_px.width = ucompr_width;
- ucompr_surf->logical_level0_px.height = ucompr_height;
+ ucompr_surf->logical_level0_px.width = view_width_el;
+ ucompr_surf->logical_level0_px.height = view_height_el;
assert(ucompr_surf->phys_level0_sa.width % fmtl->bw == 0);
assert(ucompr_surf->phys_level0_sa.height % fmtl->bh == 0);
--
2.19.1
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[Mesa-dev] [PATCH v2 30/32] intel/isl: Start using miptails
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.
---
src/intel/isl/isl.c | 165 ++--
1 file changed, 161 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 2513d2e73d1..8677f8edcbc 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1026,6 +1026,130 @@ isl_get_miptail_level_offset_el(enum isl_tiling tiling,
}
}
+static uint32_t
+isl_choose_miptail_start_level(const struct isl_device *dev,
+ const struct isl_surf_init_info *restrict info,
+ const struct isl_tile_info *tile_info)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+
+ if (tile_info->max_miptail_levels == 0)
+ return info->levels;
+
+ assert(isl_tiling_is_std_y(tile_info->tiling));
+
+ if (info->samples > 1) {
+ /* In theory, miptails work for multisampled images, but we don't
+ * support mipmapped multisampling.
+ */
+ assert(info->levels == 1);
+ return info->levels;
+ }
+
+ uint32_t max_miptail_levels = tile_info->max_miptail_levels;
+
+ if (info->dim == ISL_SURF_DIM_3D && fmtl->bpb > 32) {
+ /* On Sky Lake, the render engine does not properly handle the higher
+ * slots in the 3D miptail layout for 64 and 128 bpb formats.
+ * Specifically, any attempt to render into slot 6 or higher may end you
+ * up in the wrong spot. To work around this issue, we limit the
+ * miptail to 2 levels for Yf and 6 levels for Ys.
+ */
+ if (tile_info->tiling == ISL_TILING_GEN9_Yf) {
+ max_miptail_levels = 2;
+ } else if (tile_info->tiling == ISL_TILING_GEN9_Ys) {
+ max_miptail_levels = 6;
+ }
+ }
+
+ /* Start with the minimum number of levels that will fit in the tile */
+ uint32_t min_miptail_start =
+ info->levels > max_miptail_levels ? info->levels - max_miptail_levels :
0;
+
+ /* Account for the specified minimum */
+ min_miptail_start = MAX(min_miptail_start, info->min_miptail_start_level);
+
+ struct isl_extent3d level0_extent_el = {
+ .w = isl_align_div_npot(info->width, fmtl->bw),
+ .h = isl_align_div_npot(info->height, fmtl->bh),
+ .d = isl_align_div_npot(info->depth, fmtl->bd),
+ };
+
+ /* In the SKL PRM entry for RENDER_SURFACE_STATE::Mip Tail Start LOD, there
+* is a table of maximum sizes for the first level of the miptail.
+*/
+ struct isl_extent3d miptail_level0_extent_el;
+ if (info->dim == ISL_SURF_DIM_1D) {
+ /* For 1D, it's just 1/4 of the tile width */
+ miptail_level0_extent_el = (struct isl_extent3d) {
+ .w = tile_info->logical_extent_el.w / 4,
+ .h = 1,
+ .d = 1,
+ };
+ } else {
+ /* For 2D and 3D images, it's just the distance from the offset of the
+ * first level to the corner of the tile.
+ */
+ uint32_t level0_x_offset_el, level0_y_offset_el, level0_z_offset_el;
+ isl_get_miptail_level_offset_el(tile_info->tiling, info->dim,
+ fmtl->bpb, info->samples,
+ 0, /* level */
+ &level0_x_offset_el,
+ &level0_y_offset_el,
+ &level0_z_offset_el);
+ miptail_level0_extent_el = (struct isl_extent3d) {
+ .w = tile_info->logical_extent_el.w - level0_x_offset_el,
+ .h = tile_info->logical_extent_el.h - level0_y_offset_el,
+ .d = tile_info->logical_extent_el.d - level0_z_offset_el,
+ };
+ }
+
+ /* For determining whether or not all miplevels past a certain point will
+* fit, we can just compare the first LOD of the miptail with the minified
+* first LOD of the surface. This is not normally valid, however there are
+* three facts that we have working in our favor:
+*
+* 1) All dimensions of the first LOD of the miptail are powers of two
+* 2) The miptail levels decrease in size by at most a factor of two in
+* each dimension at each step.
+* 3) Each miptail level is non-empty
+*
+* For 1D images, (2) above is true only because miptail_level0_extent_el
+* is chosen such that it starts off only half-filling the available space.
+* At row 6 in the offset table, the space available drops by a factor of 4
+* instead of 2. This is ok because we only choose to fill half of the
+* available space for the first several levels.
+*
+* As an example, suppose that some LOD of the main surface has width W
+* and it fits in the first LOD of the miptail which has width 2^p.
+* Then
+*
+* ciel(W / fmtl->bw) <= 2^p
+* W / fmtl->bw <= 2^p
+* W <=
[Mesa-dev] [PATCH v2 29/32] intel/isl: Disallow CCS on 3D surfaces with miptails
--- src/intel/isl/isl.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index df4fb94a6fe..2513d2e73d1 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2006,6 +2006,25 @@ isl_surf_get_ccs_surf(const struct isl_device *dev, if (isl_format_is_compressed(surf->format)) return false; + /* From the workarounds section in the SKL PRM: +* +*"RCC cacheline is composed of X-adjacent 64B fragments instead of +*memory adjacent. This causes a single 128B cacheline to straddle +*multiple LODs inside the TYF MIPtail for 3D surfaces (beyond a +*certain slot number), leading to corruption when CCS is enabled for +*these LODs and RT is later bound as texture. WA: If +*RENDER_SURFACE_STATE.Surface Type = 3D and +*RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE and +*RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS, Set the value +*of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip that larger than +*those present in the surface (i.e. 15)" +* +* We simply disallow CCS on 3D surfaces with miptails. +*/ + if (surf->dim == ISL_SURF_DIM_3D && + surf->miptail_start_level < surf->levels) + return false; + /* TODO: More conditions where it can fail. */ enum isl_format ccs_format; -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 26/32] intel/isl: Add support for computing offsets with miptails
Unfortunately, there is no nice way to calculate miptail offsets in
closed form. Instead, we just copy the tables from the PRM directly
verbatim.
---
src/intel/isl/isl.c | 217 +++-
1 file changed, 213 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 3657b11ee00..c86390bf851 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -863,6 +863,169 @@ isl_calc_phys_level0_extent_sa(const struct isl_device
*dev,
}
}
+static const uint16_t std_y_1d_miptail_offset_el[] = {
+/* 128 bpb */
+ 2048,
+ 1024,
+ 512,
+ 256,
+ 128,
+ 64,
+ 48,
+ 32,
+ 28,
+ 24,
+ 20,
+ 16,
+ 12,
+ 8,
+ 4,
+ 0,
+};
+
+static const uint8_t gen9_std_y_2d_miptail_offset_el[][5][2] = {
+/* 128 bpb64 bpb32 bpb16 bpb 8 bpb */
+ { {32, 0}, {64, 0}, {64, 0}, {128, 0}, {128, 0} },
+ { { 0, 32}, { 0, 32}, { 0, 64}, { 0, 64}, { 0,128} },
+ { {16, 0}, {32, 0}, {32, 0}, { 64, 0}, { 64, 0} },
+ { { 0, 16}, { 0, 16}, { 0, 32}, { 0, 32}, { 0, 64} },
+ { { 8, 0}, {16, 0}, {16, 0}, { 32, 0}, { 32, 0} },
+ { { 4, 8}, { 8, 8}, { 8, 16}, { 16, 16}, { 16, 32} },
+ { { 0, 12}, { 0, 12}, { 0, 24}, { 0, 24}, { 0, 48} },
+ { { 0, 8}, { 0, 8}, { 0, 16}, { 0, 16}, { 0, 32} },
+ { { 4, 4}, { 8, 4}, { 8, 8}, { 16, 8}, { 16, 16} },
+ { { 4, 0}, { 8, 0}, { 8, 0}, { 16, 0}, { 16, 0} },
+ { { 0, 4}, { 0, 4}, { 0, 8}, { 0, 8}, { 0, 16} },
+ { { 3, 0}, { 6, 0}, { 4, 4}, { 8, 4}, { 0, 12} },
+ { { 2, 0}, { 4, 0}, { 4, 0}, { 8, 0}, { 0, 8} },
+ { { 1, 0}, { 2, 0}, { 0, 4}, { 0, 4}, { 0, 4} },
+ { { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0} },
+};
+
+static const uint8_t gen10_std_y_2d_miptail_offset_el[][5][2] = {
+/* 128 bpb64 bpb32 bpb16 bpb 8 bpb */
+ { {32, 0}, {64, 0}, {64, 0}, {128, 0}, {128, 0} },
+ { { 0, 32}, { 0, 32}, { 0, 64}, { 0, 64}, { 0, 128} },
+ { {16, 0}, {32, 0}, {32, 0}, { 64, 0}, { 64, 0} },
+ { { 0, 16}, { 0, 16}, { 0, 32}, { 0, 32}, { 0, 64} },
+ { { 8, 0}, {16, 0}, {16, 0}, { 32, 0}, { 32, 0} },
+ { { 4, 8}, { 8, 8}, { 8, 16}, { 16, 16}, { 16, 32} },
+ { { 0, 12}, { 0, 12}, { 0, 24}, { 0, 24}, { 0, 48} },
+ { { 0, 8}, { 0, 8}, { 0, 16}, { 0, 16}, { 0, 32} },
+ { { 4, 4}, { 8, 4}, { 8, 8}, { 16, 8}, { 16, 16} },
+ { { 4, 0}, { 8, 0}, { 8, 0}, { 16, 0}, { 16, 0} },
+ { { 0, 4}, { 0, 4}, { 0, 8}, { 0, 8}, { 0, 16} },
+ { { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0} },
+ { { 1, 0}, { 2, 0}, { 0, 4}, { 0, 4}, { 0, 4} },
+ { { 2, 0}, { 4, 0}, { 4, 0}, { 8, 0}, { 0, 8} },
+ { { 3, 0}, { 6, 0}, { 4, 4}, { 8, 4}, { 0, 12} },
+};
+
+static const uint8_t gen9_std_y_3d_miptail_offset_el[][5][3] = {
+/*128 bpb 64 bpb 32 bpb16 bpb8 bpb */
+ { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0} },
+ { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0} },
+ { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16} },
+ { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0} },
+ { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0} },
+ { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8} },
+ { {3, 0, 0}, { 6, 0, 0}, { 4, 4, 0}, { 0, 4, 4}, { 0, 4, 4} },
+ { {2, 0, 0}, { 4, 0, 0}, { 0, 4, 0}, { 0, 4, 0}, { 0, 4, 0} },
+ { {1, 0, 3}, { 2, 0, 3}, { 4, 0, 3}, { 0, 0, 7}, { 0, 0, 7} },
+ { {1, 0, 2}, { 2, 0, 2}, { 4, 0, 2}, { 0, 0, 6}, { 0, 0, 6} },
+ { {1, 0, 1}, { 2, 0, 1}, { 4, 0, 1}, { 0, 0, 5}, { 0, 0, 5} },
+ { {1, 0, 0}, { 2, 0, 0}, { 4, 0, 0}, { 0, 0, 4}, { 0, 0, 4} },
+ { {0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3} },
+ { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2} },
+ { {0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1} },
+ { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0} },
+};
+
+static const uint8_t gen10_std_y_3d_miptail_offset_el[][5][3] = {
+/*128 bpb 64 bpb 32 bpb16 bpb8 bpb */
+ { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0} },
+ { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0} },
+ { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16} },
+ { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0} },
+ { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0} },
+ { {2, 0, 4}, { 4, 0, 4}, { 4, 0, 4}, { 4, 0, 8}, { 8, 0, 8} },
+ { {0, 2, 4}, { 0, 2, 4}, { 0, 4, 4}, { 0, 4, 8}, { 0, 4, 8} },
+ { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8} },
+ { {2, 2, 0}, { 4, 2, 0}, { 4, 4, 0}, { 4, 4, 0}, { 8, 4, 0} },
+ { {2, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 8, 0, 0} },
+ { {0, 2, 0}, { 0, 2, 0}, { 0,
[Mesa-dev] [Bug 107765] [regression] Batman Arkham City crashes with DXVK under wine
https://bugs.freedesktop.org/show_bug.cgi?id=107765 --- Comment #5 from farmboy0+freedesk...@googlemail.com --- With the patch applied to mesa git wine crashes now with: Unhandled exception: assertion failed in 32-bit code (0xf7f99b09). Register dump: CS:0023 SS:002b DS:002b ES:002b FS:0063 GS:006b EIP:f7f99b09 ESP:12aef0d0 EBP:12aef0fc EFLAGS:0246( - -- I Z- -P- ) EAX: EBX:0002 ECX:12aef0fc EDX: ESI:0008 EDI: Stack dump: 0x12aef0d0: 12aef0fc 12aef0fc f7b8456a 0x12aef0e0: f7f94fcc d4a00018 0006 0x12aef0f0: f7b59fb0 07188f72 12aef120 0x12aef100: f6fd6de0 12aef2ac 2570ba00 0x12aef110: 12aef17c 12aef2ac f7bd6d39 f7bd321b 0x12aef120: e6a7c680 d4a00018 0001 cb40d8a8 Backtrace: =>0 0xf7f99b09 __kernel_vsyscall+0x9() in [vdso].so (0x12aef0fc) 1 0xf7b8456a gsignal+0xc9() in libc.so.6 (0x12aef0fc) 2 0xf7b85fcf abort+0x15e() in libc.so.6 (0xf7cde7de) 3 0xf7b7b7ed in libc.so.6 (+0x257ec) (0xf7cde7de) 4 0xf7b7b887 __assert_fail+0x56() in libc.so.6 (0x01e6) 5 0xe5999051 in libvulkan_radeon.so (+0x7f050) (0x0004) 6 0xe599fc9d in libvulkan_radeon.so (+0x85c9c) (0x12aef8c8) 7 0xe596693f in libvulkan_radeon.so (+0x4c93e) (0x12aef8c8) 8 0xe59830f9 in libvulkan_radeon.so (+0x690f8) (0xd4abea50) 9 0xf04ec424 wine_vkCmdCopyImage+0x73(commandBuffer=, srcImage=, srcImageLayout=, dstImage=, dstImageLayout=, regionCount=, pRegions=) [/mnt/work/Repositories/wine/dlls/winevulkan/vulkan_thunks.c:1400] in winevulkan (0x12aefce8) 10 0x6a5a792a in d3d11 (+0x67929) (0x12aefde8) 11 0x6a545a5c in d3d11 (+0x5a5b) (0x12aefea8) 12 0x6a610618 in d3d11 (+0xd0617) (0x12aefeec) 13 0x7bc852c9 call_thread_func+0xf8() [/mnt/work/Repositories/wine/dlls/ntdll/signal_i386.c:2654] in ntdll (0x12aeffdc) 14 0x7bc81d56 call_thread_entry+0x9() in ntdll (0x12aeffec) 0xf7f99b09 __kernel_vsyscall+0x9 in [vdso].so: popl %ebp -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object
https://bugs.freedesktop.org/show_bug.cgi?id=105731 --- Comment #5 from Marcel Heinz --- Created attachment 142005 --> https://bugs.freedesktop.org/attachment.cgi?id=142005&action=edit updated reproduced code -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object
https://bugs.freedesktop.org/show_bug.cgi?id=105731 Marcel Heinz changed: What|Removed |Added Attachment #142005|updated reproduced code |updated reproducer code description|| --- Comment #6 from Marcel Heinz --- Comment on attachment 142005 --> https://bugs.freedesktop.org/attachment.cgi?id=142005 updated reproducer code The bugfix from https://patchwork.freedesktop.org/patch/246171/ did solve the issue for my first reproducer, the issue is not completely resolved. This is an updated version of the reproducer code, which triggers the issue again. The only changes are that there are now _two_ VS outputs which are not written to, but both are used in the fragment shader: -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 105731] linker error "fragment shader input ... has no matching output in the previous stage" when previous stage's output declaration in a separate shader object
https://bugs.freedesktop.org/show_bug.cgi?id=105731 Marcel Heinz changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|FIXED |--- --- Comment #7 from Marcel Heinz --- Reopened bug because bug was not completely resolved. See the second attachment with the updated reproducer code for another case to tirgger the issue. -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: Allow physical device interfaces to be included in device extensions
According to the Vulkan spec:
"Vulkan 1.0 initially required all new physical-device-level extension
functionality to be structured within an instance extension. In order
to avoid using an instance extension, which often requires loader
support, physical-device-level extension functionality may be
implemented within device extensions"
The code that checks for enabled extension APIs currently only passes
functions with VkDevice or VkCommandBuffer as their first
argument. This patch extends that to also allow functions with
VkPhysicalDevice parameters, in support of the above quote from the
Vulkan spec.
Signed-off-by: Keith Packard
---
src/amd/vulkan/radv_entrypoints_gen.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py
b/src/amd/vulkan/radv_entrypoints_gen.py
index 377b544c2aa..69e6fc3e0eb 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -352,7 +352,7 @@ class Entrypoint(EntrypointBase):
self.return_type = return_type
self.params = params
self.guard = guard
-self.device_command = len(params) > 0 and (params[0].type ==
'VkDevice' or params[0].type == 'VkQueue' or params[0].type ==
'VkCommandBuffer')
+self.device_command = len(params) > 0 and (params[0].type ==
'VkPhysicalDevice' or params[0].type == 'VkDevice' or params[0].type ==
'VkQueue' or params[0].type == 'VkCommandBuffer')
def prefixed_name(self, prefix):
assert self.name.startswith('vk')
--
2.19.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/5] compiler/types: Serialize/deserialize subpass input types correctly
They have glsl_sampler_dim enum values of 8 and 9 which don't work when you & them with 0x7. Fortunately, we have plenty of bits. --- src/compiler/glsl_types.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp index 70bce6ace8e..d3cfcf24dd8 100644 --- a/src/compiler/glsl_types.cpp +++ b/src/compiler/glsl_types.cpp @@ -2175,14 +2175,14 @@ decode_type_from_blob(struct blob_reader *blob) case GLSL_TYPE_INT64: return glsl_type::get_instance(base_type, (u >> 4) & 0x0f, u & 0x0f); case GLSL_TYPE_SAMPLER: - return glsl_type::get_sampler_instance((enum glsl_sampler_dim) ((u >> 4) & 0x07), + return glsl_type::get_sampler_instance((enum glsl_sampler_dim) ((u >> 4) & 0x0f), (u >> 3) & 0x01, (u >> 2) & 0x01, (glsl_base_type) ((u >> 0) & 0x03)); case GLSL_TYPE_SUBROUTINE: return glsl_type::get_subroutine_instance(blob_read_string(blob)); case GLSL_TYPE_IMAGE: - return glsl_type::get_image_instance((enum glsl_sampler_dim) ((u >> 3) & 0x07), + return glsl_type::get_image_instance((enum glsl_sampler_dim) ((u >> 3) & 0x0f), (u >> 2) & 0x01, (glsl_base_type) ((u >> 0) & 0x03)); case GLSL_TYPE_ATOMIC_UINT: -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/5] anv/pipeline_cache: Add support for caching NIR
---
src/intel/vulkan/anv_pipeline_cache.c | 100 ++
src/intel/vulkan/anv_private.h| 18 +
2 files changed, 118 insertions(+)
diff --git a/src/intel/vulkan/anv_pipeline_cache.c
b/src/intel/vulkan/anv_pipeline_cache.c
index 3efa427279d..2add9e06b20 100644
--- a/src/intel/vulkan/anv_pipeline_cache.c
+++ b/src/intel/vulkan/anv_pipeline_cache.c
@@ -26,6 +26,7 @@
#include "util/debug.h"
#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
+#include "nir/nir_serialize.h"
#include "anv_private.h"
struct anv_shader_bin *
@@ -211,6 +212,18 @@ shader_bin_key_compare_func(const void *void_a, const void
*void_b)
return memcmp(a->data, b->data, a->size) == 0;
}
+static uint32_t
+sha1_hash_func(const void *sha1)
+{
+ return _mesa_hash_data(sha1, 20);
+}
+
+static bool
+sha1_compare_func(const void *sha1_a, const void *sha1_b)
+{
+ return memcmp(sha1_a, sha1_b, 20) == 0;
+}
+
void
anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
struct anv_device *device,
@@ -222,6 +235,8 @@ anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
if (cache_enabled) {
cache->cache = _mesa_hash_table_create(NULL, shader_bin_key_hash_func,
shader_bin_key_compare_func);
+ cache->nir_cache = _mesa_hash_table_create(NULL, sha1_hash_func,
+ sha1_compare_func);
} else {
cache->cache = NULL;
}
@@ -644,3 +659,88 @@ anv_device_upload_kernel(struct anv_device *device,
return bin;
}
+
+struct serialized_nir {
+ unsigned char sha1_key[20];
+ size_t size;
+ char data[0];
+};
+
+struct nir_shader *
+anv_device_search_for_nir(struct anv_device *device,
+ struct anv_pipeline_cache *cache,
+ const nir_shader_compiler_options *nir_options,
+ unsigned char sha1_key[20],
+ void *mem_ctx)
+{
+ if (cache) {
+ const struct serialized_nir *snir = NULL;
+
+ pthread_mutex_lock(&cache->mutex);
+ struct hash_entry *entry =
+ _mesa_hash_table_search(cache->nir_cache, sha1_key);
+ if (entry)
+ snir = entry->data;
+ pthread_mutex_unlock(&cache->mutex);
+
+ if (snir) {
+ struct blob_reader blob;
+ blob_reader_init(&blob, snir->data, snir->size);
+
+ nir_shader *nir = nir_deserialize(mem_ctx, nir_options, &blob);
+ if (blob.overrun) {
+ralloc_free(nir);
+ } else {
+return nir;
+ }
+ }
+ }
+
+ return NULL;
+}
+
+void
+anv_device_upload_nir(struct anv_device *device,
+ struct anv_pipeline_cache *cache,
+ const struct nir_shader *nir,
+ unsigned char sha1_key[20])
+{
+ if (cache) {
+ pthread_mutex_lock(&cache->mutex);
+ struct hash_entry *entry =
+ _mesa_hash_table_search(cache->nir_cache, sha1_key);
+ pthread_mutex_unlock(&cache->mutex);
+ if (entry)
+ return;
+
+ struct blob blob;
+ blob_init(&blob);
+
+ nir_serialize(&blob, nir);
+ if (blob.out_of_memory) {
+ blob_finish(&blob);
+ return;
+ }
+
+ pthread_mutex_lock(&cache->mutex);
+ /* Because ralloc isn't thread-safe, we have to do all this inside the
+ * lock. We could unlock for the big memcpy but it's probably not worth
+ * the hassle.
+ */
+ entry = _mesa_hash_table_search(cache->nir_cache, sha1_key);
+ if (entry) {
+ pthread_mutex_unlock(&cache->mutex);
+ return;
+ }
+
+ struct serialized_nir *snir =
+ ralloc_size(cache->nir_cache, sizeof(*snir) + blob.size);
+ memcpy(snir->sha1_key, sha1_key, 20);
+ snir->size = blob.size;
+ memcpy(snir->data, blob.data, blob.size);
+
+ _mesa_hash_table_insert(cache->nir_cache, snir->sha1_key, snir);
+
+ pthread_mutex_unlock(&cache->mutex);
+ }
+}
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 5b4c286bf38..19f673f1563 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -932,6 +932,8 @@ struct anv_pipeline_cache {
struct anv_device * device;
pthread_mutex_t mutex;
+ struct hash_table * nir_cache;
+
struct hash_table * cache;
};
@@ -971,6 +973,22 @@ anv_device_upload_kernel(struct anv_device *device,
uint32_t prog_data_size,
const struct anv_pipeline_bind_map *bind_map);
+struct nir_shader;
+struct nir_shader_compiler_options;
+
+struct nir_shader *
+anv_device_search_for_nir(struct anv_device *device,
+ struct anv_pipeline_cache *cache,
+ const struct nir_shader_compiler_options
*nir_options,
+
[Mesa-dev] [PATCH 2/5] anv/pipeline: Hash shader modules and spec constants separately
The stuff hashed by anv_pipeline_hash_shader is exactly the inputs to
anv_shader_compile_to_nir so it can be used for NIR caching.
---
src/intel/vulkan/anv_pipeline.c | 54 -
1 file changed, 39 insertions(+), 15 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 4e3ae9d094d..481921840f3 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -391,6 +391,8 @@ struct anv_pipeline_stage {
const char *entrypoint;
const VkSpecializationInfo *spec_info;
+ unsigned char shader_sha1[20];
+
union brw_any_prog_key key;
struct {
@@ -408,20 +410,27 @@ struct anv_pipeline_stage {
};
static void
-anv_pipeline_hash_shader(struct mesa_sha1 *ctx,
- struct anv_pipeline_stage *stage)
+anv_pipeline_hash_shader(const struct anv_shader_module *module,
+ const char *entrypoint,
+ gl_shader_stage stage,
+ const VkSpecializationInfo *spec_info,
+ unsigned char *sha1_out)
{
- _mesa_sha1_update(ctx, stage->module->sha1, sizeof(stage->module->sha1));
- _mesa_sha1_update(ctx, stage->entrypoint, strlen(stage->entrypoint));
- _mesa_sha1_update(ctx, &stage->stage, sizeof(stage->stage));
- if (stage->spec_info) {
- _mesa_sha1_update(ctx, stage->spec_info->pMapEntries,
-stage->spec_info->mapEntryCount *
-sizeof(*stage->spec_info->pMapEntries));
- _mesa_sha1_update(ctx, stage->spec_info->pData,
-stage->spec_info->dataSize);
+ struct mesa_sha1 ctx;
+ _mesa_sha1_init(&ctx);
+
+ _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
+ _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
+ _mesa_sha1_update(&ctx, &stage, sizeof(stage));
+ if (spec_info) {
+ _mesa_sha1_update(&ctx, spec_info->pMapEntries,
+spec_info->mapEntryCount *
+sizeof(*spec_info->pMapEntries));
+ _mesa_sha1_update(&ctx, spec_info->pData,
+spec_info->dataSize);
}
- _mesa_sha1_update(ctx, &stage->key, brw_prog_key_size(stage->stage));
+
+ _mesa_sha1_final(&ctx, sha1_out);
}
static void
@@ -440,8 +449,11 @@ anv_pipeline_hash_graphics(struct anv_pipeline *pipeline,
_mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
- if (stages[s].entrypoint)
- anv_pipeline_hash_shader(&ctx, &stages[s]);
+ if (stages[s].entrypoint) {
+ _mesa_sha1_update(&ctx, stages[s].shader_sha1,
+ sizeof(stages[s].shader_sha1));
+ _mesa_sha1_update(&ctx, &stages[s].key, brw_prog_key_size(s));
+ }
}
_mesa_sha1_final(&ctx, sha1_out);
@@ -459,7 +471,9 @@ anv_pipeline_hash_compute(struct anv_pipeline *pipeline,
if (layout)
_mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
- anv_pipeline_hash_shader(&ctx, stage);
+ _mesa_sha1_update(&ctx, stage->shader_sha1,
+ sizeof(stage->shader_sha1));
+ _mesa_sha1_update(&ctx, &stage->key.cs, sizeof(stage->key.cs));
_mesa_sha1_final(&ctx, sha1_out);
}
@@ -865,6 +879,11 @@ anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline,
stages[stage].module = anv_shader_module_from_handle(sinfo->module);
stages[stage].entrypoint = sinfo->pName;
stages[stage].spec_info = sinfo->pSpecializationInfo;
+ anv_pipeline_hash_shader(stages[stage].module,
+ stages[stage].entrypoint,
+ stage,
+ stages[stage].spec_info,
+ stages[stage].shader_sha1);
const struct gen_device_info *devinfo = &pipeline->device->info;
switch (stage) {
@@ -1115,6 +1134,11 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
.stage = MESA_SHADER_COMPUTE,
}
};
+ anv_pipeline_hash_shader(stage.module,
+stage.entrypoint,
+MESA_SHADER_COMPUTE,
+stage.spec_info,
+stage.shader_sha1);
struct anv_shader_bin *bin = NULL;
--
2.19.1
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[Mesa-dev] [PATCH 0/5] anv: Add a NIR cache
This patch series adds a simple NIR shader cache that sits right after spirv_to_nir and brw_preprocess_nir and before linking. This should help alleviate some of the added overhead of link-time optimization since most of the NIR-level optimization is now cached prior to linking. I have no numbers to back this series up; just intuition. Jason Ekstrand (5): anv/pipeline: Move wpos and input attachment lowering to lower_nir anv/pipeline: Hash shader modules and spec constants separately compiler/types: Serialize/deserialize subpass input types correctly anv/pipeline_cache: Add support for caching NIR anv/pipeline: Cache the pre-lowered NIR src/compiler/glsl_types.cpp | 4 +- src/intel/vulkan/anv_pipeline.c | 118 ++ src/intel/vulkan/anv_pipeline_cache.c | 100 ++ src/intel/vulkan/anv_private.h| 18 4 files changed, 204 insertions(+), 36 deletions(-) -- 2.19.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/5] anv/pipeline: Move wpos and input attachment lowering to lower_nir
This lets us make anv_pipeline_compile_to_nir take a device instead of a
pipeline.
---
src/intel/vulkan/anv_pipeline.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index be05c11f45d..4e3ae9d094d 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -97,15 +97,13 @@ static const uint64_t stage_to_debug[] = {
* we can't do that yet because we don't have the ability to copy nir.
*/
static nir_shader *
-anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
+anv_shader_compile_to_nir(struct anv_device *device,
void *mem_ctx,
const struct anv_shader_module *module,
const char *entrypoint_name,
gl_shader_stage stage,
const VkSpecializationInfo *spec_info)
{
- const struct anv_device *device = pipeline->device;
-
const struct brw_compiler *compiler =
device->instance->physicalDevice.compiler;
const nir_shader_compiler_options *nir_options =
@@ -209,9 +207,6 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
NIR_PASS_V(nir, nir_remove_dead_variables,
nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
- if (stage == MESA_SHADER_FRAGMENT)
- NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
-
NIR_PASS_V(nir, nir_propagate_invariant);
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
entry_point->impl, true, false);
@@ -221,9 +216,6 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
nir = brw_preprocess_nir(compiler, nir);
- if (stage == MESA_SHADER_FRAGMENT)
- NIR_PASS_V(nir, anv_nir_lower_input_attachments);
-
return nir;
}
@@ -484,6 +476,11 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
struct brw_stage_prog_data *prog_data = &stage->prog_data.base;
nir_shader *nir = stage->nir;
+ if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+ NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
+ NIR_PASS_V(nir, anv_nir_lower_input_attachments);
+ }
+
NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
NIR_PASS_V(nir, anv_nir_lower_push_constants);
@@ -969,7 +966,7 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
.sampler_to_descriptor = stages[s].sampler_to_descriptor
};
- stages[s].nir = anv_shader_compile_to_nir(pipeline, pipeline_ctx,
+ stages[s].nir = anv_shader_compile_to_nir(pipeline->device, pipeline_ctx,
stages[s].module,
stages[s].entrypoint,
stages[s].stage,
@@ -1137,7 +1134,7 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
void *mem_ctx = ralloc_context(NULL);
- stage.nir = anv_shader_compile_to_nir(pipeline, mem_ctx,
+ stage.nir = anv_shader_compile_to_nir(pipeline->device, mem_ctx,
stage.module,
stage.entrypoint,
stage.stage,
--
2.19.1
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[Mesa-dev] [PATCH 5/5] anv/pipeline: Cache the pre-lowered NIR
This adds a second level of caching for the pre-lowered NIR that's only
based off of the shader module, entrypoint and specialization constants.
This is enough for spirv_to_nir as well as our first round of lowering
and optimization. Caching at this level should allow for faster shader
recompiles due to state changes.
The NIR caching does not get serialized to disk via either the
VkPipelineCache serialization mechanism or the transparent on-disk
cache. We could but it's usually not that expensive to fall back to
SPIR-V for the odd cache miss especially if it only happens once for
several misses and it simplifies the cache.
---
src/intel/vulkan/anv_pipeline.c | 49 ++---
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 481921840f3..cb204f62902 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -478,6 +478,41 @@ anv_pipeline_hash_compute(struct anv_pipeline *pipeline,
_mesa_sha1_final(&ctx, sha1_out);
}
+static nir_shader *
+anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
+ struct anv_pipeline_cache *cache,
+ void *mem_ctx,
+ struct anv_pipeline_stage *stage)
+{
+ const struct brw_compiler *compiler =
+ pipeline->device->instance->physicalDevice.compiler;
+ const nir_shader_compiler_options *nir_options =
+ compiler->glsl_compiler_options[stage->stage].NirOptions;
+ nir_shader *nir;
+
+ nir = anv_device_search_for_nir(pipeline->device, cache,
+ nir_options,
+ stage->shader_sha1,
+ mem_ctx);
+ if (nir) {
+ assert(nir->info.stage == stage->stage);
+ return nir;
+ }
+
+ nir = anv_shader_compile_to_nir(pipeline->device,
+ mem_ctx,
+ stage->module,
+ stage->entrypoint,
+ stage->stage,
+ stage->spec_info);
+ if (nir) {
+ anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_sha1);
+ return nir;
+ }
+
+ return NULL;
+}
+
static void
anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
void *mem_ctx,
@@ -985,11 +1020,9 @@ anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline,
.sampler_to_descriptor = stages[s].sampler_to_descriptor
};
- stages[s].nir = anv_shader_compile_to_nir(pipeline->device, pipeline_ctx,
-stages[s].module,
-stages[s].entrypoint,
-stages[s].stage,
-stages[s].spec_info);
+ stages[s].nir = anv_pipeline_stage_get_nir(pipeline, cache,
+ pipeline_ctx,
+ &stages[s]);
if (stages[s].nir == NULL) {
result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
goto fail;
@@ -1158,11 +1191,7 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
void *mem_ctx = ralloc_context(NULL);
- stage.nir = anv_shader_compile_to_nir(pipeline->device, mem_ctx,
-stage.module,
-stage.entrypoint,
-stage.stage,
-stage.spec_info);
+ stage.nir = anv_pipeline_stage_get_nir(pipeline, cache, mem_ctx, &stage);
if (stage.nir == NULL) {
ralloc_free(mem_ctx);
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
--
2.19.1
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[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV
https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #21 from Thomas Crider --- Can confirm @Samuel Pitoiset v2 of that llvm patch fixes the face issue! Just got around to testing it today, working well -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
