Re: [Intel-wired-lan] [PATCH iwl-next v2 00/12] Add support for Rx timestamping for both ice and iavf drivers.
On 3/27/2024 3:50 PM, Jakub Kicinski wrote: On Wed, 27 Mar 2024 09:25:31 -0400 Mateusz Polchlopek wrote: v2: - fixed warning related to wrong specifier to dev_err_once in commit 7 - fixed warnings related to unused variables in commit 9 You posted this yesterday and got no feedback. You're not posting to the list just to get the code build tested, right? There's a lot of code getting posted, give people more time to take a look. v2 feels a bit rushed. You are right, it was a bit rush, sorry for that. I will remember for the future
[Intel-wired-lan] [PATCH v2 iwl-next 00/12] Introduce ETH56G PHY model for E825C products
E825C products have a different PHY model than E822, E823 and E810 products. This PHY is ETH56G and its support is necessary to have functional PTP stack for E825C products. Grzegorz Nitka (2): ice: Add NAC Topology device capability parser ice: Adjust PTP init for 2x50G E825C devices Jacob Keller (2): ice: Introduce helper to get tmr_cmd_reg values ice: Introduce ice_get_base_incval() helper Karol Kolacinski (4): ice: Introduce ice_ptp_hw struct ice: Add PHY OFFSET_READY register clearing ice: Change CGU regs struct to anonymous ice: Support 2XNAC configuration using auxbus Michal Michalik (1): ice: Add support for E825-C TS PLL handling Sergey Temerkhanov (3): ice: Implement Tx interrupt enablement functions ice: Move CGU block ice: Introduce ETH56G PHY model for E825C products drivers/net/ethernet/intel/ice/ice.h | 23 +- .../net/ethernet/intel/ice/ice_adminq_cmd.h |1 + drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 77 +- drivers/net/ethernet/intel/ice/ice_common.c | 58 +- drivers/net/ethernet/intel/ice/ice_common.h |2 + .../net/ethernet/intel/ice/ice_hw_autogen.h |4 + drivers/net/ethernet/intel/ice/ice_ptp.c | 263 +- drivers/net/ethernet/intel/ice/ice_ptp.h |1 + .../net/ethernet/intel/ice/ice_ptp_consts.h | 402 ++ drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 3656 + drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 284 +- drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 10 +- drivers/net/ethernet/intel/ice/ice_type.h | 60 +- 13 files changed, 3907 insertions(+), 934 deletions(-) base-commit: a81f6acc75e74f8b5502e4fa7ede177623de2035 -- 2.43.0
[Intel-wired-lan] [PATCH v2 iwl-next 01/12] ice: Introduce ice_ptp_hw struct
Create new ice_ptp_hw struct and use it for all HW and PTP-related
fields from struct ice_hw.
Replace definitions with struct fields, which values are set accordingly
to a specific device.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_common.c | 24
drivers/net/ethernet/intel/ice/ice_common.h | 1 +
drivers/net/ethernet/intel/ice/ice_ptp.c| 22 ++--
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 128 +++-
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 +-
drivers/net/ethernet/intel/ice/ice_type.h | 17 +--
6 files changed, 120 insertions(+), 76 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index 5c4dec3efe8f..80995a11c596 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -233,6 +233,30 @@ bool ice_is_e810t(struct ice_hw *hw)
return false;
}
+/**
+ * ice_is_e822
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E822 based, false if not.
+ */
+bool ice_is_e822(struct ice_hw *hw)
+{
+ switch (hw->device_id) {
+ case ICE_DEV_ID_E822C_BACKPLANE:
+ case ICE_DEV_ID_E822C_QSFP:
+ case ICE_DEV_ID_E822C_SFP:
+ case ICE_DEV_ID_E822C_10G_BASE_T:
+ case ICE_DEV_ID_E822C_SGMII:
+ case ICE_DEV_ID_E822L_BACKPLANE:
+ case ICE_DEV_ID_E822L_SFP:
+ case ICE_DEV_ID_E822L_10G_BASE_T:
+ case ICE_DEV_ID_E822L_SGMII:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* ice_is_e823
* @hw: pointer to the hardware structure
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h
b/drivers/net/ethernet/intel/ice/ice_common.h
index ffb22c7ce28b..70f57340eb0d 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -249,6 +249,7 @@ void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
bool ice_is_e810t(struct ice_hw *hw);
+bool ice_is_e822(struct ice_hw *hw);
bool ice_is_e823(struct ice_hw *hw);
bool ice_is_e825c(struct ice_hw *hw);
int
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 0f17fc1181d2..8150f949dfd3 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -813,7 +813,7 @@ static enum ice_tx_tstamp_work
ice_ptp_tx_tstamp_owner(struct ice_pf *pf)
}
mutex_unlock(&pf->ptp.ports_owner.lock);
- for (i = 0; i < ICE_MAX_QUAD; i++) {
+ for (i = 0; i < ICE_GET_QUAD_NUM(pf->hw.ptp.num_lports); i++) {
u64 tstamp_ready;
int err;
@@ -1027,7 +1027,7 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct
ice_ptp_tx *tx)
static int
ice_ptp_init_tx_e82x(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
{
- tx->block = port / ICE_PORTS_PER_QUAD;
+ tx->block = ICE_GET_QUAD_NUM(port);
tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E82X;
tx->len = INDEX_PER_PORT_E82X;
tx->has_ready_bitmap = 1;
@@ -1229,7 +1229,7 @@ static u64 ice_base_incval(struct ice_pf *pf)
*/
static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
{
- int quad = port->port_num / ICE_PORTS_PER_QUAD;
+ int quad = ICE_GET_QUAD_NUM(port->port_num);
int offs = port->port_num % ICE_PORTS_PER_QUAD;
struct ice_pf *pf;
struct ice_hw *hw;
@@ -1429,7 +1429,7 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool
linkup)
if (pf->ptp.state != ICE_PTP_READY)
return;
- if (WARN_ON_ONCE(port >= ICE_NUM_EXTERNAL_PORTS))
+ if (WARN_ON_ONCE(port >= hw->ptp.num_lports))
return;
ptp_port = &pf->ptp.port;
@@ -1439,7 +1439,7 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool
linkup)
/* Update cached link status for this port immediately */
ptp_port->link_up = linkup;
- switch (hw->phy_model) {
+ switch (hw->ptp.phy_model) {
case ICE_PHY_E810:
/* Do not reconfigure E810 PHY */
return;
@@ -1468,7 +1468,7 @@ static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf,
bool ena, u32 threshold)
ice_ptp_reset_ts_memory(hw);
- for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
+ for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {
err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
&val);
if (err)
@@ -1953,7 +1953,7 @@ ice_ptp_settime64(struct ptp_clock_info *info, const
struct timespec64 *ts)
ice_ptp_enable_all_clkout(pf);
/* Recalibrate and re-enable timestamp blocks for E822/E823 */
- if (hw->phy_model == ICE_PHY_E82X)
+
[Intel-wired-lan] [PATCH v2 iwl-next 02/12] ice: Introduce helper to get tmr_cmd_reg values
From: Jacob Keller
Multiple places in the driver code need to convert enum ice_ptp_tmr_cmd
values into register bits for both the main timer and the PHY port
timers. The main MAC register has one bit scheme for timer commands,
while the PHY commands use a different scheme.
The E810 and E830 devices use the same scheme for port commands as used
for the main timer. However, E822 and ETH56G hardware has a separate
scheme used by the PHY.
Introduce helper functions to convert the timer command enumeration into
the register values, reducing some code duplication, and making it
easier to later refactor the individual port write commands.
Signed-off-by: Jacob Keller
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 140
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 2 +-
2 files changed, 89 insertions(+), 53 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index e86ca6cada79..c892b966c3b8 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -227,40 +227,114 @@ static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
}
/**
- * ice_ptp_src_cmd - Prepare source timer for a timer command
- * @hw: pointer to HW structure
+ * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
+ * @hw: pointer to HW struct
* @cmd: Timer command
*
- * Prepare the source timer for an upcoming timer sync command.
+ * Returns: the source timer command register value for the given PTP timer
+ * command.
*/
-void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
+static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw,
+ enum ice_ptp_tmr_cmd cmd)
{
- u32 cmd_val;
- u8 tmr_idx;
+ u32 cmd_val, tmr_idx;
+
+ switch (cmd) {
+ case ICE_PTP_INIT_TIME:
+ cmd_val = GLTSYN_CMD_INIT_TIME;
+ break;
+ case ICE_PTP_INIT_INCVAL:
+ cmd_val = GLTSYN_CMD_INIT_INCVAL;
+ break;
+ case ICE_PTP_ADJ_TIME:
+ cmd_val = GLTSYN_CMD_ADJ_TIME;
+ break;
+ case ICE_PTP_ADJ_TIME_AT_TIME:
+ cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
+ break;
+ case ICE_PTP_NOP:
+ case ICE_PTP_READ_TIME:
+ cmd_val = GLTSYN_CMD_READ_TIME;
+ break;
+ default:
+ dev_warn(ice_hw_to_dev(hw),
+"Ignoring unrecognized timer command %u\n", cmd);
+ cmd_val = 0;
+ }
tmr_idx = ice_get_ptp_src_clock_index(hw);
- cmd_val = tmr_idx << SEL_CPK_SRC;
+
+ return tmr_idx | cmd_val << SEL_CPK_SRC;
+}
+
+/**
+ * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
+ * @hw: pointer to HW struct
+ * @cmd: Timer command
+ *
+ * Note that some hardware families use a different command register value for
+ * the PHY ports, while other hardware families use the same register values
+ * as the source timer.
+ *
+ * Returns: the PHY port timer command register value for the given PTP timer
+ * command.
+ */
+static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw,
+ enum ice_ptp_tmr_cmd cmd)
+{
+ u32 cmd_val, tmr_idx;
+
+ /* Certain hardware families share the same register values for the
+* port register and source timer register.
+*/
+ switch (hw->ptp.phy_model) {
+ case ICE_PHY_E810:
+ return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810;
+ default:
+ break;
+ }
switch (cmd) {
case ICE_PTP_INIT_TIME:
- cmd_val |= GLTSYN_CMD_INIT_TIME;
+ cmd_val = PHY_CMD_INIT_TIME;
break;
case ICE_PTP_INIT_INCVAL:
- cmd_val |= GLTSYN_CMD_INIT_INCVAL;
+ cmd_val = PHY_CMD_INIT_INCVAL;
break;
case ICE_PTP_ADJ_TIME:
- cmd_val |= GLTSYN_CMD_ADJ_TIME;
+ cmd_val = PHY_CMD_ADJ_TIME;
break;
case ICE_PTP_ADJ_TIME_AT_TIME:
- cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
+ cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
break;
case ICE_PTP_READ_TIME:
- cmd_val |= GLTSYN_CMD_READ_TIME;
+ cmd_val = PHY_CMD_READ_TIME;
break;
case ICE_PTP_NOP:
+ cmd_val = 0;
break;
+ default:
+ dev_warn(ice_hw_to_dev(hw),
+"Ignoring unrecognized timer command %u\n", cmd);
+ cmd_val = 0;
}
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+
+ return tmr_idx | cmd_val << SEL_PHY_SRC;
+}
+
+/**
+ * ice_ptp_src_cmd - Prepare source timer for a timer command
+ * @hw: pointer to HW structur
[Intel-wired-lan] [PATCH v2 iwl-next 03/12] ice: Implement Tx interrupt enablement functions
From: Sergey Temerkhanov
Introduce functions enabling/disabling Tx TS interrupts
for the E822 and ETH56G PHYs
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 63 ++---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 31 ++
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 +-
3 files changed, 63 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 8150f949dfd3..3019988a43c8 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1457,42 +1457,43 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port,
bool linkup)
* @ena: bool value to enable or disable interrupt
* @threshold: Minimum number of packets at which intr is triggered
*
- * Utility function to enable or disable Tx timestamp interrupt and threshold
+ * Utility function to configure all the PHY interrupt settings, including
+ * whether the PHY interrupt is enabled, and what threshold to use. Also
+ * configures The E82X timestamp owner to react to interrupts from all PHYs.
*/
static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32
threshold)
{
+ struct device *dev = ice_pf_to_dev(pf);
struct ice_hw *hw = &pf->hw;
- int err = 0;
- int quad;
- u32 val;
ice_ptp_reset_ts_memory(hw);
- for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {
- err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
-&val);
- if (err)
- break;
-
- if (ena) {
- val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
- val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
- val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,
- threshold);
- } else {
- val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
+ switch (hw->ptp.phy_model) {
+ case ICE_PHY_E82X: {
+ int quad;
+
+ for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);
+quad++) {
+ int err;
+
+ err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);
+ if (err) {
+ dev_err(dev, "Failed to configure PHY interrupt
for quad %d, err %d\n",
+ quad, err);
+ return err;
+ }
}
- err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
- val);
- if (err)
- break;
+ return 0;
+ }
+ case ICE_PHY_E810:
+ return 0;
+ case ICE_PHY_UNSUP:
+ default:
+ dev_warn(dev, "%s: Unexpected PHY model %d\n", __func__,
+hw->ptp.phy_model);
+ return -EOPNOTSUPP;
}
-
- if (err)
- dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
- err);
- return err;
}
/**
@@ -3010,12 +3011,10 @@ static int ice_ptp_init_owner(struct ice_pf *pf)
/* Release the global hardware lock */
ice_ptp_unlock(hw);
- if (!ice_is_e810(hw)) {
- /* Enable quad interrupts */
- err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
- if (err)
- goto err_exit;
- }
+ /* Configure PHY interrupt settings */
+ err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
+ if (err)
+ goto err_exit;
/* Ensure we have a clock device */
err = ice_ptp_create_clock(pf);
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index c892b966c3b8..12f04ad263c5 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2715,6 +2715,37 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8
quad, u64 *tstamp_ready)
return 0;
}
+/**
+ * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
+ * @hw: pointer to the HW struct
+ * @quad: the timestamp quad
+ * @ena: enable or disable interrupt
+ * @threshold: interrupt threshold
+ *
+ * Configure TX timestamp interrupt for the specified quad
+ */
+
+int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
+{
+ int err;
+ u32 val;
+
+ err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
+ if (err)
+ return err;
+
+ val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
+ if (ena) {
+ val |= Q_REG_TX_MEM_GBL_CFG_INTR_E
[Intel-wired-lan] [PATCH v2 iwl-next 04/12] ice: Add PHY OFFSET_READY register clearing
Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 11 ---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 32 +
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 +
3 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 3019988a43c8..7980482bbf56 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1930,11 +1930,14 @@ ice_ptp_settime64(struct ptp_clock_info *info, const
struct timespec64 *ts)
struct ice_hw *hw = &pf->hw;
int err;
- /* For Vernier mode, we need to recalibrate after new settime
-* Start with disabling timestamp block
+ /* For Vernier mode on E82X, we need to recalibrate after new settime.
+* Start with marking timestamps as invalid.
*/
- if (pf->ptp.port.link_up)
- ice_ptp_port_phy_stop(&pf->ptp.port);
+ if (hw->ptp.phy_model == ICE_PHY_E82X) {
+ err = ice_ptp_clear_phy_offset_ready_e82x(hw);
+ if (err)
+ dev_warn(ice_pf_to_dev(pf), "Failed to mark timestamps
as invalid before settime\n");
+ }
if (!ice_ptp_lock(hw)) {
err = -EBUSY;
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 12f04ad263c5..6967a918ab5e 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2405,6 +2405,38 @@ int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8
port)
return 0;
}
+/**
+ * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY
registers
+ * @hw: pointer to the HW struct
+ *
+ * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
+ * and received timestamps as invalid.
+ */
+int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
+{
+ u8 port;
+
+ for (port = 0; port < hw->ptp.num_lports; port++) {
+ int err;
+
+ err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
+ if (err) {
+ dev_warn(ice_hw_to_dev(hw),
+"Failed to clear PHY TX_OFFSET_READY
register\n");
+ return err;
+ }
+
+ err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
+ if (err) {
+ dev_warn(ice_hw_to_dev(hw),
+"Failed to clear PHY RX_OFFSET_READY
register\n");
+ return err;
+ }
+ }
+
+ return 0;
+}
+
/**
* ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
* @hw: pointer to the HW struct
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 5645b20a9f87..5223e17d2806 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -208,6 +208,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time);
int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
+int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
void ice_ptp_reset_ts_memory(struct ice_hw *hw);
--
2.43.0
[Intel-wired-lan] [PATCH v2 iwl-next 05/12] ice: Move CGU block
From: Sergey Temerkhanov
Move CGU block to the beginning of ice_ptp_hw.c
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 986 ++--
1 file changed, 492 insertions(+), 494 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 6967a918ab5e..be1613f069d5 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -226,6 +226,287 @@ static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
}
+/**
+ * ice_read_cgu_reg_e82x - Read a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to read
+ * @val: storage for register value read
+ *
+ * Read the contents of a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ int err;
+
+ cgu_msg.opcode = ice_sbq_msg_rd;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+
+ err = ice_sbq_rw_reg(hw, &cgu_msg);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x,
err %d\n",
+ addr, err);
+ return err;
+ }
+
+ *val = cgu_msg.data;
+
+ return err;
+}
+
+/**
+ * ice_write_cgu_reg_e82x - Write a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to write
+ * @val: value to write into the register
+ *
+ * Write the specified value to a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ int err;
+
+ cgu_msg.opcode = ice_sbq_msg_wr;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+ cgu_msg.data = val;
+
+ err = ice_sbq_rw_reg(hw, &cgu_msg);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register
0x%04x, err %d\n",
+ addr, err);
+ return err;
+ }
+
+ return err;
+}
+
+/**
+ * ice_clk_freq_str - Convert time_ref_freq to string
+ * @clk_freq: Clock frequency
+ *
+ * Convert the specified TIME_REF clock frequency to a string.
+ */
+static const char *ice_clk_freq_str(u8 clk_freq)
+{
+ switch ((enum ice_time_ref_freq)clk_freq) {
+ case ICE_TIME_REF_FREQ_25_000:
+ return "25 MHz";
+ case ICE_TIME_REF_FREQ_122_880:
+ return "122.88 MHz";
+ case ICE_TIME_REF_FREQ_125_000:
+ return "125 MHz";
+ case ICE_TIME_REF_FREQ_153_600:
+ return "153.6 MHz";
+ case ICE_TIME_REF_FREQ_156_250:
+ return "156.25 MHz";
+ case ICE_TIME_REF_FREQ_245_760:
+ return "245.76 MHz";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_clk_src_str - Convert time_ref_src to string
+ * @clk_src: Clock source
+ *
+ * Convert the specified clock source to its string name.
+ */
+static const char *ice_clk_src_str(u8 clk_src)
+{
+ switch ((enum ice_clk_src)clk_src) {
+ case ICE_CLK_SRC_TCX0:
+ return "TCX0";
+ case ICE_CLK_SRC_TIME_REF:
+ return "TIME_REF";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
+ * @hw: pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCX0)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the PLL which drives the PTP hardware clock.
+ */
+static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
+ enum ice_time_ref_freq clk_freq,
+ enum ice_clk_src clk_src)
+{
+ union tspll_ro_bwm_lf bwm_lf;
+ union nac_cgu_dword19 dw19;
+ union nac_cgu_dword22 dw22;
+ union nac_cgu_dword24 dw24;
+ union nac_cgu_dword9 dw9;
+ int err;
+
+ if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
+clk_freq);
+ return -EINVAL;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
+clk_src);
+ return -EINVAL;
+ }
+
+ if (clk_src == ICE_CLK_SRC_TCX0 &&
+ clk_freq != ICE_TIME_REF_FREQ_25_000) {
+ dev_warn(ice_hw_to_dev(hw),
+"TCX0 only supports 25 MHz
[Intel-wired-lan] [PATCH v2 iwl-next 06/12] ice: Introduce ice_get_base_incval() helper
From: Jacob Keller
Add a new helper for getting base clock increment value for specific HW.
Signed-off-by: Jacob Keller
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 7 +--
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 12
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 7980482bbf56..cd2dab7b4c44 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1210,12 +1210,7 @@ static u64 ice_base_incval(struct ice_pf *pf)
struct ice_hw *hw = &pf->hw;
u64 incval;
- if (ice_is_e810(hw))
- incval = ICE_PTP_NOMINAL_INCVAL_E810;
- else if (ice_e82x_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
- incval = ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
- else
- incval = UNKNOWN_INCVAL_E82X;
+ incval = ice_get_base_incval(hw);
dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of
0x%016llx\n",
incval);
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 5223e17d2806..d477d334b1d8 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -285,6 +285,18 @@ int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8
*base_idx, u8 *pin_num);
int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
unsigned long *caps);
+static inline u64 ice_get_base_incval(struct ice_hw *hw)
+{
+ switch (hw->ptp.phy_model) {
+ case ICE_PHY_E810:
+ return ICE_PTP_NOMINAL_INCVAL_E810;
+ case ICE_PHY_E82X:
+ return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
+ default:
+ return 0;
+ }
+}
+
#define PFTSYN_SEM_BYTES 4
#define ICE_PTP_CLOCK_INDEX_0 0x00
--
2.43.0
[Intel-wired-lan] [PATCH v2 iwl-next 08/12] ice: Change CGU regs struct to anonymous
Simplify the code by using anonymous struct in CGU registers instead of
naming each structure 'field'.
Suggested-by: Przemek Kitszel
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 12 ++---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 44 +--
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
index 57abd52386d0..36aeb10eefb7 100644
--- a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
+++ b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
@@ -23,7 +23,7 @@ union nac_cgu_dword9 {
u32 clk_synce0_amp : 2;
u32 one_pps_out_amp : 2;
u32 misc24 : 12;
- } field;
+ };
u32 val;
};
@@ -39,7 +39,7 @@ union nac_cgu_dword19 {
u32 japll_ndivratio : 4;
u32 japll_iref_ndivratio : 3;
u32 misc27 : 1;
- } field;
+ };
u32 val;
};
@@ -63,7 +63,7 @@ union nac_cgu_dword22 {
u32 fdpllclk_sel_div2 : 1;
u32 time1588clk_sel_div2 : 1;
u32 misc3 : 1;
- } field;
+ };
u32 val;
};
@@ -77,7 +77,7 @@ union nac_cgu_dword24 {
u32 ext_synce_sel : 1;
u32 ref1588_ck_div : 4;
u32 time_ref_sel : 1;
- } field;
+ };
u32 val;
};
@@ -92,7 +92,7 @@ union tspll_cntr_bist_settings {
u32 i_plllock_cnt_6_0 : 7;
u32 i_plllock_cnt_10_7 : 4;
u32 reserved200 : 4;
- } field;
+ };
u32 val;
};
@@ -109,7 +109,7 @@ union tspll_ro_bwm_lf {
u32 afcdone_cri : 1;
u32 feedfwrdgain_cal_cri_7_0 : 8;
u32 m2fbdivmod_cri_7_0 : 8;
- } field;
+ };
u32 val;
};
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 83359cc4c01c..6b0b15324433 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -385,14 +385,14 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src
%s, clk_freq %s, PLL %s\n",
- dw24.field.ts_pll_enable ? "enabled" : "disabled",
- ice_clk_src_str(dw24.field.time_ref_sel),
- ice_clk_freq_str(dw9.field.time_ref_freq_sel),
- bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
+ dw24.ts_pll_enable ? "enabled" : "disabled",
+ ice_clk_src_str(dw24.time_ref_sel),
+ ice_clk_freq_str(dw9.time_ref_freq_sel),
+ bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
/* Disable the PLL before changing the clock source or frequency */
- if (dw24.field.ts_pll_enable) {
- dw24.field.ts_pll_enable = 0;
+ if (dw24.ts_pll_enable) {
+ dw24.ts_pll_enable = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
if (err)
@@ -400,7 +400,7 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
}
/* Set the frequency */
- dw9.field.time_ref_freq_sel = clk_freq;
+ dw9.time_ref_freq_sel = clk_freq;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
if (err)
return err;
@@ -410,8 +410,8 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
if (err)
return err;
- dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
- dw19.field.tspll_ndivratio = 1;
+ dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
+ dw19.tspll_ndivratio = 1;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
if (err)
@@ -422,8 +422,8 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
if (err)
return err;
- dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
- dw22.field.time1588clk_sel_div2 = 0;
+ dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
+ dw22.time1588clk_sel_div2 = 0;
err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
if (err)
@@ -434,16 +434,16 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
if (err)
return err;
- dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
- dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
- dw24.field.time_ref_sel = clk_src;
+ dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
+ dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
+ dw24.time_ref_sel = clk_src;
er
[Intel-wired-lan] [PATCH v2 iwl-next 07/12] ice: Introduce ETH56G PHY model for E825C products
From: Sergey Temerkhanov
E825C products feature a new PHY model - ETH56G.
Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
analogous to E82X and E810 ones with addition of a few HW-specific
functionalities for ETH56G like one-step timestamping.
It ensures correct PTP initialization and operation for E825C products.
Co-developed-by: Jacob Keller
Signed-off-by: Jacob Keller
Co-developed-by: Michal Michalik
Signed-off-by: Michal Michalik
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Co-developed-by: Karol Kolacinski
Signed-off-by: Karol Kolacinski
---
V1 -> V2: Adjusted bitslip calculation
drivers/net/ethernet/intel/ice/ice_common.c |3 +-
drivers/net/ethernet/intel/ice/ice_common.h |1 +
drivers/net/ethernet/intel/ice/ice_ptp.c | 99 +-
drivers/net/ethernet/intel/ice/ice_ptp.h |1 +
.../net/ethernet/intel/ice/ice_ptp_consts.h | 315 +++
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 1879 +++--
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 239 ++-
drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 10 +-
drivers/net/ethernet/intel/ice/ice_type.h | 20 +-
9 files changed, 2413 insertions(+), 154 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index 80995a11c596..7d3098e19bc0 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -3059,8 +3059,7 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw)
* If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
* If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
*/
-static u16
-ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
+u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
{
u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h
b/drivers/net/ethernet/intel/ice/ice_common.h
index 70f57340eb0d..86cc1df469dd 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -262,6 +262,7 @@ int
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
bool *value, struct ice_sq_cd *cd);
bool ice_is_100m_speed_supported(struct ice_hw *hw);
+u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high);
int
ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
struct ice_sq_cd *cd);
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index cd2dab7b4c44..e2d4632d564c 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1013,6 +1013,26 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct
ice_ptp_tx *tx)
tx->len = 0;
}
+/**
+ * ice_ptp_init_tx_eth56g - Initialize tracking for Tx timestamps
+ * @pf: Board private structure
+ * @tx: the Tx tracking structure to initialize
+ * @port: the port this structure tracks
+ *
+ * Initialize the Tx timestamp tracker for this port. ETH56G PHYs
+ * have independent memory blocks for all ports.
+ */
+static int
+ice_ptp_init_tx_eth56g(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
+{
+ tx->block = port;
+ tx->offset = 0;
+ tx->len = INDEX_PER_PORT_ETH56G;
+ tx->has_ready_bitmap = 1;
+
+ return ice_ptp_alloc_tx_tracker(tx);
+}
+
/**
* ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps
* @pf: Board private structure
@@ -1343,10 +1363,19 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
mutex_lock(&ptp_port->ps_lock);
- kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
+ switch (hw->ptp.phy_model) {
+ case ICE_PHY_ETH56G:
+ err = ice_stop_phy_timer_eth56g(hw, port, true);
+ break;
+ case ICE_PHY_E82X:
+ kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
- err = ice_stop_phy_timer_e82x(hw, port, true);
- if (err)
+ err = ice_stop_phy_timer_e82x(hw, port, true);
+ break;
+ default:
+ err = -ENODEV;
+ }
+ if (err && err != -EBUSY)
dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down,
err %d\n",
port, err);
@@ -1380,27 +1409,39 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
mutex_lock(&ptp_port->ps_lock);
- kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
+ switch (hw->ptp.phy_model) {
+ case ICE_PHY_ETH56G:
+ err = ice_start_phy_timer_eth56g(hw, port);
+ break;
+ case ICE_PHY_E82X:
+ /* Start the PHY timer in Vernier mode */
+ kthread_cancel_delayed_work_
[Intel-wired-lan] [PATCH v2 iwl-next 09/12] ice: Add support for E825-C TS PLL handling
From: Michal Michalik
The CGU layout of E825-C is a little different than E822/E823. Add
support the new hardware adding relevant functions.
Signed-off-by: Michal Michalik
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 65 +
.../net/ethernet/intel/ice/ice_ptp_consts.h | 87 +++
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 245 +-
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 22 ++
drivers/net/ethernet/intel/ice/ice_type.h | 2 +-
5 files changed, 408 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
index 36aeb10eefb7..10d9d74f3545 100644
--- a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
+++ b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
@@ -27,6 +27,17 @@ union nac_cgu_dword9 {
u32 val;
};
+#define NAC_CGU_DWORD16_E825C 0x40
+union nac_cgu_dword16_e825c {
+ struct {
+ u32 synce_remndr : 6;
+ u32 synce_phlmt_en : 1;
+ u32 misc13 : 17;
+ u32 tspll_ck_refclkfreq : 8;
+ };
+ u32 val;
+};
+
#define NAC_CGU_DWORD19 0x4c
union nac_cgu_dword19 {
struct {
@@ -67,6 +78,22 @@ union nac_cgu_dword22 {
u32 val;
};
+#define NAC_CGU_DWORD23_E825C 0x5C
+union nac_cgu_dword23_e825c {
+ struct {
+ u32 cgupll_fbdiv_intgr : 10;
+ u32 ux56pll_fbdiv_intgr : 10;
+ u32 misc20 : 4;
+ u32 ts_pll_enable : 1;
+ u32 time_sync_tspll_align_sel : 1;
+ u32 ext_synce_sel : 1;
+ u32 ref1588_ck_div : 4;
+ u32 time_ref_sel : 1;
+
+ };
+ u32 val;
+};
+
#define NAC_CGU_DWORD24 0x60
union nac_cgu_dword24 {
struct {
@@ -113,4 +140,42 @@ union tspll_ro_bwm_lf {
u32 val;
};
+#define TSPLL_RO_LOCK_E825C 0x3f0
+union tspll_ro_lock_e825c {
+ struct {
+ u32 bw_freqov_high_cri_7_0 : 8;
+ u32 bw_freqov_high_cri_9_8 : 2;
+ u32 reserved455 : 1;
+ u32 plllock_gain_tran_cri : 1;
+ u32 plllock_true_lock_cri : 1;
+ u32 pllunlock_flag_cri : 1;
+ u32 afcerr_cri : 1;
+ u32 afcdone_cri : 1;
+ u32 feedfwrdgain_cal_cri_7_0 : 8;
+ u32 reserved462 : 8;
+ };
+ u32 val;
+};
+
+#define TSPLL_BW_TDC_E825C 0x31c
+union tspll_bw_tdc_e825c {
+ struct {
+ u32 i_tdc_offset_lock_1_0 : 2;
+ u32 i_bbthresh1_2_0 : 3;
+ u32 i_bbthresh2_2_0 : 3;
+ u32 i_tdcsel_1_0 : 2;
+ u32 i_tdcovccorr_en_h : 1;
+ u32 i_divretimeren : 1;
+ u32 i_bw_ampmeas_window : 1;
+ u32 i_bw_lowerbound_2_0 : 3;
+ u32 i_bw_upperbound_2_0 : 3;
+ u32 i_bw_mode_1_0 : 2;
+ u32 i_ft_mode_sel_2_0 : 3;
+ u32 i_bwphase_4_0 : 5;
+ u32 i_plllock_sel_1_0 : 2;
+ u32 i_afc_divratio : 1;
+ };
+ u32 val;
+};
+
#endif /* _ICE_CGU_REGS_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
index ef180936f60c..9a22ac05987f 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
@@ -470,6 +470,93 @@ const struct ice_cgu_pll_params_e82x
e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
},
};
+const
+struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
+ /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x19,
+ /* tspll_ndivratio */
+ 1,
+ /* tspll_fbdiv_intgr */
+ 320,
+ /* tspll_fbdiv_frac */
+ 0,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x29,
+ /* tspll_ndivratio */
+ 3,
+ /* tspll_fbdiv_intgr */
+ 195,
+ /* tspll_fbdiv_frac */
+ 1342177280,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x3E,
+ /* tspll_ndivratio */
+ 2,
+ /* tspll_fbdiv_intgr */
+ 128,
+ /* tspll_fbdiv_frac */
+ 0,
+ /* ref1588_ck_div */
+ 0,
+ },
+
+ /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
+ {
+ /* tspll_ck_refclkfreq */
+ 0x33,
+ /* tspll_ndivratio */
+ 3
[Intel-wired-lan] [PATCH v2 iwl-next 10/12] ice: Add NAC Topology device capability parser
From: Grzegorz Nitka
Add new device capability ICE_AQC_CAPS_NAC_TOPOLOGY which allows to
determine the mode of operation (1 or 2 NAC).
Define a new structure to store data from new capability and
corresponding parser code.
Co-developed-by: Prathisna Padmasanan
Signed-off-by: Prathisna Padmasanan
Signed-off-by: Grzegorz Nitka
Reviewed-by: Pawel Kaminski
Reviewed-by: Mateusz Polchlopek
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
.../net/ethernet/intel/ice/ice_adminq_cmd.h | 1 +
drivers/net/ethernet/intel/ice/ice_common.c | 31 +++
drivers/net/ethernet/intel/ice/ice_type.h | 10 ++
3 files changed, 42 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
index 540c0bdca936..8eaf030a29c9 100644
--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
@@ -121,6 +121,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT0x0077
#define ICE_AQC_CAPS_NVM_MGMT 0x0080
+#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
#define ICE_AQC_CAPS_FW_LAG_SUPPORT0x0092
#define ICE_AQC_BIT_ROCEV2_LAG 0x01
#define ICE_AQC_BIT_SRIOV_LAG 0x02
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index 7d3098e19bc0..3b20a9a2935c 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -2577,6 +2577,34 @@ ice_parse_sensor_reading_cap(struct ice_hw *hw, struct
ice_hw_dev_caps *dev_p,
dev_p->supported_sensors);
}
+/**
+ * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap
+ * @hw: pointer to the HW struct
+ * @dev_p: pointer to device capabilities structure
+ * @cap: capability element to parse
+ *
+ * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities.
+ */
+static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw,
+ struct ice_hw_dev_caps *dev_p,
+ struct ice_aqc_list_caps_elem *cap)
+{
+ dev_p->nac_topo.mode = le32_to_cpu(cap->number);
+ dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M;
+
+ dev_info(ice_hw_to_dev(hw),
+"PF is configured in %s mode with IP instance ID %d\n",
+(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ?
+"primary" : "secondary", dev_p->nac_topo.id);
+
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n",
+ !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M));
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n",
+ !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M));
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n",
+ dev_p->nac_topo.id);
+}
+
/**
* ice_parse_dev_caps - Parse device capabilities
* @hw: pointer to the HW struct
@@ -2628,6 +2656,9 @@ ice_parse_dev_caps(struct ice_hw *hw, struct
ice_hw_dev_caps *dev_p,
case ICE_AQC_CAPS_SENSOR_READING:
ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]);
break;
+ case ICE_AQC_CAPS_NAC_TOPOLOGY:
+ ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]);
+ break;
default:
/* Don't list common capabilities as unknown */
if (!found)
diff --git a/drivers/net/ethernet/intel/ice/ice_type.h
b/drivers/net/ethernet/intel/ice/ice_type.h
index 2baf305a0c95..948c4bdbb206 100644
--- a/drivers/net/ethernet/intel/ice/ice_type.h
+++ b/drivers/net/ethernet/intel/ice/ice_type.h
@@ -372,6 +372,15 @@ struct ice_ts_dev_info {
u8 ts_ll_int_read;
};
+#define ICE_NAC_TOPO_PRIMARY_M BIT(0)
+#define ICE_NAC_TOPO_DUAL_MBIT(1)
+#define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0)
+
+struct ice_nac_topology {
+ u32 mode;
+ u8 id;
+};
+
/* Function specific capabilities */
struct ice_hw_func_caps {
struct ice_hw_common_caps common_cap;
@@ -393,6 +402,7 @@ struct ice_hw_dev_caps {
u32 num_flow_director_fltr; /* Number of FD filters available */
struct ice_ts_dev_info ts_dev_info;
u32 num_funcs;
+ struct ice_nac_topology nac_topo;
/* bitmap of supported sensors
* bit 0 - internal temperature sensor
* bit 31:1 - Reserved
--
2.43.0
[Intel-wired-lan] [PATCH v2 iwl-next 11/12] ice: Support 2XNAC configuration using auxbus
There are E825C products featuring 2 NACs. Those have only one source
clock on the primary NAC.
For those devices, there
should be only one clock controller on the primary NAC. All PFs from
both NACs should connect as auxiliary devices to the auxiliary driver on
the primary NAC.
Reviewed-by: Igor Bagnucki
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice.h| 23 +++-
drivers/net/ethernet/intel/ice/ice_ptp.c| 62 +++--
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 28 --
drivers/net/ethernet/intel/ice/ice_type.h | 2 +
4 files changed, 101 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice.h
b/drivers/net/ethernet/intel/ice/ice.h
index 67a3236ab1fc..b8319851bef1 100644
--- a/drivers/net/ethernet/intel/ice/ice.h
+++ b/drivers/net/ethernet/intel/ice/ice.h
@@ -197,8 +197,6 @@
#define ice_pf_to_dev(pf) (&((pf)->pdev->dev))
-#define ice_pf_src_tmr_owned(pf)
((pf)->hw.func_caps.ts_func_info.src_tmr_owned)
-
enum ice_feature {
ICE_F_DSCP,
ICE_F_PHY_RCLK,
@@ -1010,4 +1008,25 @@ static inline void ice_clear_rdma_cap(struct ice_pf *pf)
}
extern const struct xdp_metadata_ops ice_xdp_md_ops;
+
+/**
+ * ice_pf_src_tmr_owned - check if PF is owner of source timer
+ * @pf: Board private structure
+ */
+static inline bool ice_pf_src_tmr_owned(struct ice_pf *pf)
+{
+ if (pf->hw.ptp.phy_model == ICE_PHY_ETH56G && !pf->hw.ptp.primary_nac)
+ return false;
+ else
+ return pf->hw.func_caps.ts_func_info.src_tmr_owned;
+}
+
+/**
+ * ice_is_primary - check if PF is on a primary NAC
+ * @pf: Board private structure
+ */
+static inline bool ice_is_primary(struct ice_pf *pf)
+{
+ return pf->hw.dev_caps.nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M;
+}
#endif /* _ICE_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index e2d4632d564c..811830eab385 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -373,6 +373,9 @@ ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct
ptp_system_timestamp *sts)
u32 hi, lo, lo2;
u8 tmr_idx;
+ if (!hw->ptp.primary_nac)
+ hw = hw->ptp.primary_hw;
+
tmr_idx = ice_get_ptp_src_clock_index(hw);
guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
/* Read the system timestamp pre PHC read */
@@ -2675,6 +2678,31 @@ static void ice_ptp_periodic_work(struct kthread_work
*work)
msecs_to_jiffies(err ? 10 : 500));
}
+/**
+ * ice_ptp_prepare_rebuild_sec - Prepare second NAC for PTP reset or rebuild
+ * @pf: Board private structure
+ * @rebuild: rebuild if true, prepare if false
+ * @reset_type: the reset type being performed
+ */
+static void ice_ptp_prepare_rebuild_sec(struct ice_pf *pf, bool rebuild,
+ enum ice_reset_req reset_type)
+{
+ struct ice_ptp_port *port;
+
+ mutex_lock(&pf->ptp.ports_owner.lock);
+ list_for_each_entry(port, &pf->ptp.ports_owner.ports, list_member) {
+ struct ice_pf *peer_pf = ptp_port_to_pf(port);
+
+ if (!peer_pf->hw.ptp.primary_nac) {
+ if (rebuild)
+ ice_ptp_rebuild(peer_pf, reset_type);
+ else
+ ice_ptp_prepare_for_reset(peer_pf, reset_type);
+ }
+ }
+ mutex_unlock(&pf->ptp.ports_owner.lock);
+}
+
/**
* ice_ptp_prepare_for_reset - Prepare PTP for reset
* @pf: Board private structure
@@ -2683,6 +2711,7 @@ static void ice_ptp_periodic_work(struct kthread_work
*work)
void ice_ptp_prepare_for_reset(struct ice_pf *pf, enum ice_reset_req
reset_type)
{
struct ice_ptp *ptp = &pf->ptp;
+ struct ice_hw *hw = &pf->hw;
u8 src_tmr;
if (ptp->state != ICE_PTP_READY)
@@ -2698,15 +2727,18 @@ void ice_ptp_prepare_for_reset(struct ice_pf *pf, enum
ice_reset_req reset_type)
if (reset_type == ICE_RESET_PFR)
return;
+ if (ice_pf_src_tmr_owned(pf) && ice_is_e825c(hw))
+ ice_ptp_prepare_rebuild_sec(pf, false, reset_type);
+
ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
/* Disable periodic outputs */
ice_ptp_disable_all_clkout(pf);
- src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
+ src_tmr = ice_get_ptp_src_clock_index(hw);
/* Disable source clock */
- wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
+ wr32(hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
/* Acquire PHC and system timer to restore after reset */
ptp->reset_time = ktime_get_real_ns();
@@ -2802,6 +2834,9 @@ void ice_ptp_rebuild(struct ice_pf *pf, enum
ice_reset_req reset_type)
err = ice_ptp_rebuild_o
[Intel-wired-lan] [PATCH v2 iwl-next 12/12] ice: Adjust PTP init for 2x50G E825C devices
From: Grzegorz Nitka
>From FW/HW perspective, 2 port topology in E825C devices requires
merging of 2 port mapping internally to CPK and breakout mapping
externally to CPK. As a consequence, it requires different port
numbering from PTP code perspective.
For that topology, pf_id can not be used to index PTP ports. Even if
the 2nd port is identified as port with pf_id = 1, all PHY operations
need to be performed as it was port 2. Thus, special mapping is needed
for the 2nd port.
This change adds detection of 2x50G topology and applies 'custom'
mapping on the 2nd port.
Signed-off-by: Grzegorz Nitka
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
.../net/ethernet/intel/ice/ice_hw_autogen.h | 4
drivers/net/ethernet/intel/ice/ice_ptp.c | 5
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 23 +++
drivers/net/ethernet/intel/ice/ice_type.h | 9
4 files changed, 41 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
index cfac1d432c15..26260eed852d 100644
--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
@@ -157,6 +157,8 @@
#define GLGEN_RTRIG_CORER_MBIT(0)
#define GLGEN_RTRIG_GLOBR_MBIT(1)
#define GLGEN_STAT 0x000B612C
+#define GLGEN_SWITCH_MODE_CONFIG 0x000B81E0
+#define GLGEN_SWITCH_MODE_CONFIG_SELECT_25X4_ON_SINGLE_QUAD_M BIT(2)
#define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4))
#define PFGEN_CTRL 0x00091000
#define PFGEN_CTRL_PFSWR_M BIT(0)
@@ -177,6 +179,8 @@
#define GLINT_CTL_ITR_GRAN_50_MICE_M(0xF, 24)
#define GLINT_CTL_ITR_GRAN_25_S28
#define GLINT_CTL_ITR_GRAN_25_MICE_M(0xF, 28)
+#define GLGEN_MAC_LINK_TOPO0x000B81DC
+#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_MGENMASK(1, 0)
#define GLINT_DYN_CTL(_INT)(0x0016 + ((_INT) * 4))
#define GLINT_DYN_CTL_INTENA_M BIT(0)
#define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 811830eab385..73898aa08dc5 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1472,6 +1472,8 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool
linkup)
return;
ptp_port = &pf->ptp.port;
+ if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
+ port *= 2;
if (WARN_ON_ONCE(ptp_port->port_num != port))
return;
@@ -3329,6 +3331,9 @@ void ice_ptp_init(struct ice_pf *pf)
}
ptp->port.port_num = hw->pf_id;
+ if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
+ ptp->port.port_num = hw->pf_id * 2;
+
err = ice_ptp_init_port(pf, &ptp->port);
if (err)
goto err;
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index c64e66ceab40..34c9a9489708 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2466,6 +2466,27 @@ static int ice_get_phy_tx_tstamp_ready_eth56g(struct
ice_hw *hw, u8 port,
return 0;
}
+/**
+ * ice_is_muxed_topo - detect breakout 2x50G topology for E825C
+ * @hw: pointer to the HW struct
+ *
+ * Returns: true if it's 2x50 breakout topology, false otherwise
+ */
+static bool ice_is_muxed_topo(struct ice_hw *hw)
+{
+ u8 link_topo;
+ bool mux;
+ u32 val;
+
+ val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);
+ mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_SELECT_25X4_ON_SINGLE_QUAD_M,
+ val);
+ val = rd32(hw, GLGEN_MAC_LINK_TOPO);
+ link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val);
+
+ return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS);
+}
+
/**
* ice_ptp_init_phy_e825c - initialize PHY parameters
* @hw: pointer to the HW struct
@@ -2498,6 +2519,8 @@ static void ice_ptp_init_phy_e825c(struct ice_hw *hw)
return;
}
}
+
+ ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw);
}
/* E822 family functions
diff --git a/drivers/net/ethernet/intel/ice/ice_type.h
b/drivers/net/ethernet/intel/ice/ice_type.h
index e019dad56819..c5b2ad113d1a 100644
--- a/drivers/net/ethernet/intel/ice/ice_type.h
+++ b/drivers/net/ethernet/intel/ice/ice_type.h
@@ -851,6 +851,14 @@ enum ice_phy_model {
ICE_PHY_ETH56G,
};
+/* Global Link Topology */
+enum ice_global_link_topo {
+ ICE_LINK_TOPO_UP_TO_2_LINKS,
+ ICE_LINK_TOPO_UP_TO_4_LINKS,
+ ICE_LINK_TOPO_UP_TO_8_LINKS,
+ ICE_LINK_TOPO_RESERVED,
+};
+
struct ice_ptp_hw {
en
Re: [Intel-wired-lan] [PATCH net-next v2 0/3] compiler_types: add Endianness-dependent __counted_by_{le, be}
On 3/27/24 15:22, Alexander Lobakin wrote:
Some structures contain flexible arrays at the end and the counter for
them, but the counter has explicit Endianness and thus __counted_by()
can't be used directly.
To increase test coverage for potential problems without breaking
anything, introduce __counted_by_{le,be} defined depending on platform's
Endianness to either __counted_by() when applicable or noop otherwise.
The first user will be virtchnl2.h from idpf just as example with 9 flex
structures having Little Endian counters.
Maybe it would be a good idea to introduce such attributes on compiler
level if possible, but for now let's stop on what we have.
Alexander Lobakin (3):
compiler_types: add Endianness-dependent __counted_by_{le,be}
idpf: make virtchnl2.h self-contained
idpf: sprinkle __counted_by{,_le}() in the virtchnl2 header
Documentation/conf.py | 2 ++
scripts/kernel-doc | 1 +
include/linux/compiler_types.h | 11 ++
drivers/net/ethernet/intel/idpf/idpf_txrx.h | 2 ++
drivers/net/ethernet/intel/idpf/virtchnl2.h | 24 ++---
5 files changed, 28 insertions(+), 12 deletions(-)
---
From v1[0]:
* fix compilation of #2 (Jakub);
* pick Acked-bys (Gustavo).
From RFC[1]:
* teach kdoc new attributes (Simon, Kees);
* add Acked-by (Kees);
* fix a couple typos;
* send to net-next (Kees).
[0]
https://lore.kernel.org/netdev/20240326164116.645718-1-aleksander.loba...@intel.com
[1]
https://lore.kernel.org/netdev/20240318130354.2713265-1-aleksander.loba...@intel.com
nice,
Reviewed-by: Przemek Kitszel
Re: [Intel-wired-lan] [iwl-next v1 1/3] ice: move ice_devlink.[ch] to devlink folder
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Swiatkowski
> Sent: Tuesday, March 26, 2024 3:05 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Loktionov, Aleksandr ;
> net...@vger.kernel.org; Michal Swiatkowski
>
> Subject: [Intel-wired-lan] [iwl-next v1 1/3] ice: move ice_devlink.[ch] to
> devlink folder
>
> Only moving whole files, fixing Makefile and bunch of includes.
>
> Some changes to ice_devlink file was done even in representor part (Tx
> topology), so keep it as final patch to not mess up with rebasing.
>
> After moving to devlink folder there is no need to have such long name for
> these files. Rename them to simple devlink.
>
> Reviewed-by: Aleksandr Loktionov
> Signed-off-by: Michal Swiatkowski
> ---
> drivers/net/ethernet/intel/ice/Makefile| 3 ++-
> .../ethernet/intel/ice/{ice_devlink.c => devlink/devlink.c}| 2 +-
> .../ethernet/intel/ice/{ice_devlink.h => devlink/devlink.h}| 0
> drivers/net/ethernet/intel/ice/ice_dcb_lib.c | 2 +-
> drivers/net/ethernet/intel/ice/ice_eswitch.c | 2 +-
> drivers/net/ethernet/intel/ice/ice_lib.c | 2 +-
> drivers/net/ethernet/intel/ice/ice_main.c | 2 +-
> drivers/net/ethernet/intel/ice/ice_repr.c | 2 +-
> 8 files changed, 8 insertions(+), 7 deletions(-) rename
> drivers/net/ethernet/intel/ice/{ice_devlink.c => devlink/devlink.c} (99%)
> rename drivers/net/ethernet/intel/ice/{ice_devlink.h => devlink/devlink.h}
> (100%)
>
Tested-by: Pucha Himasekhar Reddy (A
Contingent worker at Intel)
Re: [Intel-wired-lan] [iwl-next v1 2/3] ice: move devlink port code to a separate file
> -Original Message- > From: Intel-wired-lan On Behalf Of > Michal Swiatkowski > Sent: Tuesday, March 26, 2024 3:05 AM > To: intel-wired-...@lists.osuosl.org > Cc: Drewek, Wojciech ; net...@vger.kernel.org; > Michal Swiatkowski ; Piotr Raczynski > ; Kitszel, Przemyslaw > > Subject: [Intel-wired-lan] [iwl-next v1 2/3] ice: move devlink port code to a > separate file > > From: Piotr Raczynski > > Keep devlink related code in a separate file. More devlink port code and > handlers will be added here for other port operations. > > Remove no longer needed include of our devlink.h in ice_lib.c. > > Reviewed-by: Przemek Kitszel > Reviewed-by: Wojciech Drewek > Signed-off-by: Piotr Raczynski > Signed-off-by: Michal Swiatkowski > --- > drivers/net/ethernet/intel/ice/Makefile | 1 + > .../net/ethernet/intel/ice/devlink/devlink.c | 423 - > .../ethernet/intel/ice/devlink/devlink_port.c | 430 ++ > .../ethernet/intel/ice/devlink/devlink_port.h | 12 + > drivers/net/ethernet/intel/ice/ice_lib.c | 1 - > drivers/net/ethernet/intel/ice/ice_main.c | 1 + > drivers/net/ethernet/intel/ice/ice_repr.c | 1 + > 7 files changed, 445 insertions(+), 424 deletions(-) create mode 100644 > drivers/net/ethernet/intel/ice/devlink/devlink_port.c > create mode 100644 drivers/net/ethernet/intel/ice/devlink/devlink_port.h > Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel)
Re: [Intel-wired-lan] [iwl-next v1 3/3] ice: hold devlink lock for whole init/cleanup
> -Original Message- > From: Intel-wired-lan On Behalf Of > Michal Swiatkowski > Sent: Tuesday, March 26, 2024 3:05 AM > To: intel-wired-...@lists.osuosl.org > Cc: Drewek, Wojciech ; net...@vger.kernel.org; > Jiri Pirko ; Michal Swiatkowski > > Subject: [Intel-wired-lan] [iwl-next v1 3/3] ice: hold devlink lock for whole > init/cleanup > > Simplify devlink lock code in driver by taking it for whole init/cleanup > path. Instead of calling devlink functions that taking lock call the lockless > versions. > > Suggested-by: Jiri Pirko > Reviewed-by: Jesse Brandeburg > Reviewed-by: Wojciech Drewek > Signed-off-by: Michal Swiatkowski > --- > .../net/ethernet/intel/ice/devlink/devlink.c | 32 +-- > drivers/net/ethernet/intel/ice/ice_main.c | 7 ++-- > 2 files changed, 19 insertions(+), 20 deletions(-) Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel)
Re: [Intel-wired-lan] [PATCH v2 iwl-next 03/12] ice: Implement Tx interrupt enablement functions
Hi,
> > +/**
> > + * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
> > + * @hw: pointer to the HW struct
> > + * @quad: the timestamp quad
> > + * @ena: enable or disable interrupt
> > + * @threshold: interrupt threshold
> > + *
> > + * Configure TX timestamp interrupt for the specified quad
> > + */
> > +
> > +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8
> > threshold)
> > +{
> > + int err;
> > + u32 val;
>
> Reverse Christmas trees.
In this case, both lines are same length (15 columns).
Thanks,
Karol
Re: [Intel-wired-lan] [PATCH net-next v2] net: remove gfp_mask from napi_alloc_skb()
On Tue, Mar 26, 2024 at 09:02:12PM -0700, Jakub Kicinski wrote: > __napi_alloc_skb() is napi_alloc_skb() with the added flexibility > of choosing gfp_mask. This is a NAPI function, so GFP_ATOMIC is > implied. The only practical choice the caller has is whether to > set __GFP_NOWARN. But that's a false choice, too, allocation failures > in atomic context will happen, and printing warnings in logs, > effectively for a packet drop, is both too much and very likely > non-actionable. > > This leads me to a conclusion that most uses of napi_alloc_skb() > are simply misguided, and should use __GFP_NOWARN in the first > place. We also have a "standard" way of reporting allocation > failures via the queue stat API (qstats::rx-alloc-fail). > > The direct motivation for this patch is that one of the drivers > used at Meta calls napi_alloc_skb() (so prior to this patch without > __GFP_NOWARN), and the resulting OOM warning is the top networking > warning in our fleet. > > Reviewed-by: Alexander Lobakin > Signed-off-by: Jakub Kicinski Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2] igc: Add MQPRIO offload support
On Tue, Mar 26, 2024 at 02:34:54PM +0100, Kurt Kanzenbach wrote:
> Add support for offloading MQPRIO. The hardware has four priorities as well
> as four queues. Each queue must be a assigned with a unique priority.
>
> However, the priorities are only considered in TSN Tx mode. There are two
> TSN Tx modes. In case of MQPRIO the Qbv capability is not required.
> Therefore, use the legacy TSN Tx mode, which performs strict priority
> arbitration.
>
> Example for mqprio with hardware offload:
>
> |tc qdisc replace dev ${INTERFACE} handle 100 parent root mqprio num_tc 4 \
> | map 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 \
> | queues 1@0 1@1 1@2 1@3 \
> | hw 1
>
> The mqprio Qdisc also allows to configure the `preemptible_tcs'. However,
> frame preemption is not supported yet.
>
> Tested on Intel i225 and implemented by following data sheet section 7.5.2,
> Transmit Scheduling.
>
> Signed-off-by: Kurt Kanzenbach
...
> diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h
> b/drivers/net/ethernet/intel/igc/igc_defines.h
> index 5f92b3c7c3d4..73502a0b4df7 100644
> --- a/drivers/net/ethernet/intel/igc/igc_defines.h
> +++ b/drivers/net/ethernet/intel/igc/igc_defines.h
> @@ -547,6 +547,15 @@
>
> #define IGC_MAX_SR_QUEUES2
>
> +#define IGC_TXARB_TXQ_PRIO_0_SHIFT 0
> +#define IGC_TXARB_TXQ_PRIO_1_SHIFT 2
> +#define IGC_TXARB_TXQ_PRIO_2_SHIFT 4
> +#define IGC_TXARB_TXQ_PRIO_3_SHIFT 6
> +#define IGC_TXARB_TXQ_PRIO_0_MASKGENMASK(1, 0)
> +#define IGC_TXARB_TXQ_PRIO_1_MASKGENMASK(3, 2)
> +#define IGC_TXARB_TXQ_PRIO_2_MASKGENMASK(5, 4)
> +#define IGC_TXARB_TXQ_PRIO_3_MASKGENMASK(7, 6)
> +
> /* Receive Checksum Control */
> #define IGC_RXCSUM_CRCOFL0x0800 /* CRC32 offload enable */
> #define IGC_RXCSUM_PCSD 0x2000 /* packet checksum
> disabled */
> diff --git a/drivers/net/ethernet/intel/igc/igc_main.c
> b/drivers/net/ethernet/intel/igc/igc_main.c
...
> diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c
> b/drivers/net/ethernet/intel/igc/igc_tsn.c
...
> @@ -106,7 +109,26 @@ static int igc_tsn_disable_offload(struct igc_adapter
> *adapter)
> wr32(IGC_QBVCYCLET_S, 0);
> wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
>
> + /* Reset mqprio TC configuration. */
> + netdev_reset_tc(adapter->netdev);
> +
> + /* Restore the default Tx arbitration: Priority 0 has the highest
> + * priority and is assigned to queue 0 and so on and so forth.
> + */
> + txarb = rd32(IGC_TXARB);
> + txarb &= ~(IGC_TXARB_TXQ_PRIO_0_MASK |
> +IGC_TXARB_TXQ_PRIO_1_MASK |
> +IGC_TXARB_TXQ_PRIO_2_MASK |
> +IGC_TXARB_TXQ_PRIO_3_MASK);
> +
> + txarb |= 0x00 << IGC_TXARB_TXQ_PRIO_0_SHIFT;
> + txarb |= 0x01 << IGC_TXARB_TXQ_PRIO_1_SHIFT;
> + txarb |= 0x02 << IGC_TXARB_TXQ_PRIO_2_SHIFT;
> + txarb |= 0x03 << IGC_TXARB_TXQ_PRIO_3_SHIFT;
> + wr32(IGC_TXARB, txarb);
Hi Kurt,
It looks like the above would be a good candidate for using FIELD_PREP,
in which case the _SHIFT #defines can likely be removed.
Also, the logic above seems to be replicated in igc_tsn_enable_offload.
Perhaps a helper is appropriate.
> +
> adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;
> + adapter->flags &= ~IGC_FLAG_TSN_LEGACY_ENABLED;
>
> return 0;
> }
> @@ -123,6 +145,50 @@ static int igc_tsn_enable_offload(struct igc_adapter
> *adapter)
> wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);
> wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN);
>
> + if (adapter->strict_priority_enable) {
> + u32 txarb;
> + int err;
> +
> + err = netdev_set_num_tc(adapter->netdev, adapter->num_tc);
> + if (err)
> + return err;
> +
> + for (i = 0; i < adapter->num_tc; i++) {
> + err = netdev_set_tc_queue(adapter->netdev, i, 1,
> + adapter->queue_per_tc[i]);
> + if (err)
> + return err;
> + }
> +
> + /* In case the card is configured with less than four queues. */
> + for (; i < IGC_MAX_TX_QUEUES; i++)
> + adapter->queue_per_tc[i] = i;
> +
> + /* Configure queue priorities according to the user provided
> + * mapping.
> + */
> + txarb = rd32(IGC_TXARB);
> + txarb &= ~(IGC_TXARB_TXQ_PRIO_0_MASK |
> +IGC_TXARB_TXQ_PRIO_1_MASK |
> +IGC_TXARB_TXQ_PRIO_2_MASK |
> +IGC_TXARB_TXQ_PRIO_3_MASK);
> + txarb |= adapter->queue_per_tc[3] << IGC_TXARB_TXQ_PRIO_0_SHIFT;
> + txarb |= adapter->queue_per_tc[2] << IGC_TXARB_TXQ_PRIO_1_SHIFT;
> + txarb |= adapter->queue_per_tc[1] << IGC_TXARB_TXQ_PRIO_2_SHIFT;
> + txarb |= adapter->queue_per_tc[0] << IGC_TXARB_TXQ_PRIO_3_SHIFT;
> + wr32(IGC_TXA
Re: [Intel-wired-lan] [PATCH net-next v2] net: remove gfp_mask from napi_alloc_skb()
On Thu, Mar 28, 2024 at 12:32 PM Simon Horman wrote: > > On Tue, Mar 26, 2024 at 09:02:12PM -0700, Jakub Kicinski wrote: > > __napi_alloc_skb() is napi_alloc_skb() with the added flexibility > > of choosing gfp_mask. This is a NAPI function, so GFP_ATOMIC is > > implied. The only practical choice the caller has is whether to > > set __GFP_NOWARN. But that's a false choice, too, allocation failures > > in atomic context will happen, and printing warnings in logs, > > effectively for a packet drop, is both too much and very likely > > non-actionable. > > > > This leads me to a conclusion that most uses of napi_alloc_skb() > > are simply misguided, and should use __GFP_NOWARN in the first > > place. We also have a "standard" way of reporting allocation > > failures via the queue stat API (qstats::rx-alloc-fail). > > > > The direct motivation for this patch is that one of the drivers > > used at Meta calls napi_alloc_skb() (so prior to this patch without > > __GFP_NOWARN), and the resulting OOM warning is the top networking > > warning in our fleet. > > > > Reviewed-by: Alexander Lobakin > > Signed-off-by: Jakub Kicinski > > Reviewed-by: Simon Horman Reviewed-by: Eric Dumazet
[Intel-wired-lan] [tnguy-next-queue:main] BUILD SUCCESS 2a702c2e57908e7bb5c814afeac577a14815c2f2
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git main branch HEAD: 2a702c2e57908e7bb5c814afeac577a14815c2f2 Merge tag 'for-netdev' of https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next elapsed time: 1239m configs tested: 102 configs skipped: 3 The following configs have been built successfully. More configs may be tested in the coming days. tested configs: alpha allnoconfig gcc alphaallyesconfig gcc alpha defconfig gcc arc allmodconfig gcc arc allnoconfig gcc arc allyesconfig gcc arc defconfig gcc arm allmodconfig gcc arm allnoconfig clang arm allyesconfig gcc arm defconfig clang arm64allmodconfig clang arm64 allnoconfig gcc arm64allyesconfig clang arm64 defconfig gcc csky allmodconfig gcc csky allnoconfig gcc csky allyesconfig gcc cskydefconfig gcc hexagon allmodconfig clang hexagon allnoconfig clang hexagon allyesconfig clang hexagon defconfig clang i386 allmodconfig gcc i386 allnoconfig gcc i386 allyesconfig gcc i386 buildonly-randconfig-001-20240328 gcc i386 buildonly-randconfig-002-20240328 gcc i386 buildonly-randconfig-003-20240328 clang i386 buildonly-randconfig-004-20240328 gcc i386 buildonly-randconfig-005-20240328 gcc i386 buildonly-randconfig-006-20240328 gcc i386defconfig clang i386 randconfig-001-20240328 clang i386 randconfig-002-20240328 clang i386 randconfig-003-20240328 clang i386 randconfig-004-20240328 clang i386 randconfig-005-20240328 gcc i386 randconfig-006-20240328 gcc i386 randconfig-011-20240328 clang i386 randconfig-012-20240328 clang i386 randconfig-013-20240328 clang i386 randconfig-014-20240328 clang i386 randconfig-015-20240328 clang i386 randconfig-016-20240328 clang loongarchallmodconfig gcc loongarch allnoconfig gcc loongarch defconfig gcc m68k allmodconfig gcc m68k allnoconfig gcc m68k allyesconfig gcc m68kdefconfig gcc microblaze allmodconfig gcc microblazeallnoconfig gcc microblaze allyesconfig gcc microblaze defconfig gcc mips allnoconfig gcc mips allyesconfig gcc nios2allmodconfig gcc nios2 allnoconfig gcc nios2allyesconfig gcc nios2 defconfig gcc openrisc allnoconfig gcc openrisc allyesconfig gcc openriscdefconfig gcc parisc allmodconfig gcc pariscallnoconfig gcc parisc allyesconfig gcc parisc defconfig gcc parisc64defconfig gcc powerpc allmodconfig gcc powerpc allnoconfig gcc powerpc allyesconfig clang riscvallmodconfig clang riscv allnoconfig gcc riscvallyesconfig clang riscv defconfig clang s390 allmodconfig clang s390 allnoconfig clang s390 allyesconfig gcc s390defconfig clang sh allmodconfig gcc shallnoconfig gcc sh allyesconfig gcc sh
[Intel-wired-lan] [PATCH RFC 04/10] mm: page_frag: add '_va' suffix to page_frag API
Currently most of the API for page_frag API is returning
'virtual address' as output or expecting 'virtual address'
as input, in order to differentiate the API handling between
'virtual address' and 'struct page', add '_va' suffix to the
corresponding API mirroring the page_pool_alloc_va() API of
the page_pool.
Signed-off-by: Yunsheng Lin
---
drivers/net/ethernet/google/gve/gve_rx.c | 4 ++--
drivers/net/ethernet/intel/ice/ice_txrx.c | 2 +-
drivers/net/ethernet/intel/ice/ice_txrx.h | 2 +-
drivers/net/ethernet/intel/ice/ice_txrx_lib.c | 2 +-
.../net/ethernet/intel/ixgbevf/ixgbevf_main.c | 4 ++--
.../marvell/octeontx2/nic/otx2_common.c | 2 +-
drivers/net/ethernet/mediatek/mtk_wed_wo.c| 4 ++--
drivers/nvme/host/tcp.c | 8 +++
drivers/nvme/target/tcp.c | 22 -
drivers/vhost/net.c | 6 ++---
include/linux/page_frag_cache.h | 24 ++-
include/linux/skbuff.h| 2 +-
kernel/bpf/cpumap.c | 2 +-
mm/page_frag_alloc.c | 10
net/core/skbuff.c | 15 ++--
net/core/xdp.c| 2 +-
net/rxrpc/txbuf.c | 15 ++--
net/sunrpc/svcsock.c | 4 ++--
18 files changed, 67 insertions(+), 63 deletions(-)
diff --git a/drivers/net/ethernet/google/gve/gve_rx.c
b/drivers/net/ethernet/google/gve/gve_rx.c
index 20f5a9e7fae9..58091de93430 100644
--- a/drivers/net/ethernet/google/gve/gve_rx.c
+++ b/drivers/net/ethernet/google/gve/gve_rx.c
@@ -687,7 +687,7 @@ static int gve_xdp_redirect(struct net_device *dev, struct
gve_rx_ring *rx,
total_len = headroom + SKB_DATA_ALIGN(len) +
SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- frame = page_frag_alloc(&rx->page_cache, total_len, GFP_ATOMIC);
+ frame = page_frag_alloc_va(&rx->page_cache, total_len, GFP_ATOMIC);
if (!frame) {
u64_stats_update_begin(&rx->statss);
rx->xdp_alloc_fails++;
@@ -700,7 +700,7 @@ static int gve_xdp_redirect(struct net_device *dev, struct
gve_rx_ring *rx,
err = xdp_do_redirect(dev, &new, xdp_prog);
if (err)
- page_frag_free(frame);
+ page_frag_free_va(frame);
return err;
}
diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.c
b/drivers/net/ethernet/intel/ice/ice_txrx.c
index 97d41d6ebf1f..87f23995b657 100644
--- a/drivers/net/ethernet/intel/ice/ice_txrx.c
+++ b/drivers/net/ethernet/intel/ice/ice_txrx.c
@@ -126,7 +126,7 @@ ice_unmap_and_free_tx_buf(struct ice_tx_ring *ring, struct
ice_tx_buf *tx_buf)
dev_kfree_skb_any(tx_buf->skb);
break;
case ICE_TX_BUF_XDP_TX:
- page_frag_free(tx_buf->raw_buf);
+ page_frag_free_va(tx_buf->raw_buf);
break;
case ICE_TX_BUF_XDP_XMIT:
xdp_return_frame(tx_buf->xdpf);
diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h
b/drivers/net/ethernet/intel/ice/ice_txrx.h
index af955b0e5dc5..65ad1757824f 100644
--- a/drivers/net/ethernet/intel/ice/ice_txrx.h
+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h
@@ -148,7 +148,7 @@ static inline int ice_skb_pad(void)
* @ICE_TX_BUF_DUMMY: dummy Flow Director packet, unmap and kfree()
* @ICE_TX_BUF_FRAG: mapped skb OR &xdp_buff frag, only unmap DMA
* @ICE_TX_BUF_SKB: &sk_buff, unmap and consume_skb(), update stats
- * @ICE_TX_BUF_XDP_TX: &xdp_buff, unmap and page_frag_free(), stats
+ * @ICE_TX_BUF_XDP_TX: &xdp_buff, unmap and page_frag_free_va(), stats
* @ICE_TX_BUF_XDP_XMIT: &xdp_frame, unmap and xdp_return_frame(), stats
* @ICE_TX_BUF_XSK_TX: &xdp_buff on XSk queue, xsk_buff_free(), stats
*/
diff --git a/drivers/net/ethernet/intel/ice/ice_txrx_lib.c
b/drivers/net/ethernet/intel/ice/ice_txrx_lib.c
index f8f1d2bdc1be..312f351ac601 100644
--- a/drivers/net/ethernet/intel/ice/ice_txrx_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_txrx_lib.c
@@ -279,7 +279,7 @@ ice_clean_xdp_tx_buf(struct device *dev, struct ice_tx_buf
*tx_buf,
switch (tx_buf->type) {
case ICE_TX_BUF_XDP_TX:
- page_frag_free(tx_buf->raw_buf);
+ page_frag_free_va(tx_buf->raw_buf);
break;
case ICE_TX_BUF_XDP_XMIT:
xdp_return_frame_bulk(tx_buf->xdpf, bq);
diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
index 9c960017a6de..f781c5f202c9 100644
--- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
+++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
@@ -303,7 +303,7 @@ static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector
*q_vector,
/* free the skb */
if (ring_is_xdp(tx_ring))
- page_frag_free(tx_buffer->data);
+
[Intel-wired-lan] [tnguy-next-queue:dev-queue] BUILD SUCCESS a81f6acc75e74f8b5502e4fa7ede177623de2035
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue.git dev-queue branch HEAD: a81f6acc75e74f8b5502e4fa7ede177623de2035 igc: Remove redundant runtime resume for ethtool ops elapsed time: 893m configs tested: 123 configs skipped: 3 The following configs have been built successfully. More configs may be tested in the coming days. tested configs: alpha allnoconfig gcc alphaallyesconfig gcc alpha defconfig gcc arc allmodconfig gcc arc allnoconfig gcc arc allyesconfig gcc arc defconfig gcc arc randconfig-001-20240328 gcc arc randconfig-002-20240328 gcc arm allmodconfig gcc arm allnoconfig clang arm allyesconfig gcc arm defconfig clang arm randconfig-001-20240328 gcc arm randconfig-002-20240328 gcc arm randconfig-003-20240328 gcc arm randconfig-004-20240328 gcc arm64allmodconfig clang arm64 allnoconfig gcc arm64allyesconfig clang arm64 defconfig gcc arm64 randconfig-001-20240328 gcc arm64 randconfig-002-20240328 gcc arm64 randconfig-003-20240328 gcc arm64 randconfig-004-20240328 gcc csky allmodconfig gcc csky allnoconfig gcc csky allyesconfig gcc cskydefconfig gcc csky randconfig-001-20240328 gcc csky randconfig-002-20240328 gcc hexagon allmodconfig clang hexagon allnoconfig clang hexagon allyesconfig clang hexagon defconfig clang hexagon randconfig-001-20240328 clang hexagon randconfig-002-20240328 clang i386 allmodconfig gcc i386 allnoconfig gcc i386 allyesconfig gcc i386defconfig clang loongarchallmodconfig gcc loongarch allnoconfig gcc loongarch defconfig gcc loongarch randconfig-001-20240328 gcc loongarch randconfig-002-20240328 gcc m68k allmodconfig gcc m68k allnoconfig gcc m68k allyesconfig gcc m68kdefconfig gcc microblaze allmodconfig gcc microblazeallnoconfig gcc microblaze allyesconfig gcc microblaze defconfig gcc mips allnoconfig gcc mips allyesconfig gcc nios2allmodconfig gcc nios2 allnoconfig gcc nios2allyesconfig gcc nios2 defconfig gcc nios2 randconfig-001-20240328 gcc nios2 randconfig-002-20240328 gcc openrisc allnoconfig gcc openrisc allyesconfig gcc openriscdefconfig gcc parisc allmodconfig gcc pariscallnoconfig gcc parisc allyesconfig gcc parisc defconfig gcc pariscrandconfig-001-20240328 gcc pariscrandconfig-002-20240328 gcc parisc64defconfig gcc powerpc allmodconfig gcc powerpc allnoconfig gcc powerpc allyesconfig clang powerpc randconfig-001-20240328 clang powerpc randconfig-002-20240328 clang powerpc randconfig-003-20240328 clang powerpc64 randconfig-001-20240328 clang powerpc64 randconfig-002-20240328 gcc powerpc64 randconfig-003-20240328 gcc riscvallmodconfig clang riscv allnoconfig gcc riscvallyesconfig clang riscv defconfig clang riscv
[Intel-wired-lan] [tnguy-net-queue:dev-queue] BUILD SUCCESS 94366cbc5324f77fcd7dc56b85432fc25a4ca0ee
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue.git dev-queue branch HEAD: 94366cbc5324f77fcd7dc56b85432fc25a4ca0ee ice: Fix freeing uninitialized pointers elapsed time: 922m configs tested: 145 configs skipped: 3 The following configs have been built successfully. More configs may be tested in the coming days. tested configs: alpha allnoconfig gcc alphaallyesconfig gcc alpha defconfig gcc arc allmodconfig gcc arc allnoconfig gcc arc allyesconfig gcc arc defconfig gcc arc randconfig-001-20240328 gcc arc randconfig-002-20240328 gcc arm allmodconfig gcc arm allnoconfig clang arm allyesconfig gcc arm defconfig clang arm randconfig-001-20240328 gcc arm randconfig-002-20240328 gcc arm randconfig-003-20240328 gcc arm randconfig-004-20240328 gcc arm64allmodconfig clang arm64 allnoconfig gcc arm64 defconfig gcc arm64 randconfig-001-20240328 gcc arm64 randconfig-002-20240328 gcc arm64 randconfig-003-20240328 gcc arm64 randconfig-004-20240328 gcc csky allmodconfig gcc csky allnoconfig gcc csky allyesconfig gcc cskydefconfig gcc csky randconfig-001-20240328 gcc csky randconfig-002-20240328 gcc hexagon allmodconfig clang hexagon allnoconfig clang hexagon allyesconfig clang hexagon defconfig clang hexagon randconfig-001-20240328 clang hexagon randconfig-002-20240328 clang i386 allmodconfig gcc i386 allnoconfig gcc i386 allyesconfig gcc i386 buildonly-randconfig-001-20240328 gcc i386 buildonly-randconfig-002-20240328 gcc i386 buildonly-randconfig-003-20240328 clang i386 buildonly-randconfig-004-20240328 gcc i386 buildonly-randconfig-005-20240328 gcc i386 buildonly-randconfig-006-20240328 gcc i386defconfig clang i386 randconfig-001-20240328 clang i386 randconfig-002-20240328 clang i386 randconfig-003-20240328 clang i386 randconfig-004-20240328 clang i386 randconfig-005-20240328 gcc i386 randconfig-006-20240328 gcc i386 randconfig-011-20240328 clang i386 randconfig-012-20240328 clang i386 randconfig-013-20240328 clang i386 randconfig-014-20240328 clang i386 randconfig-015-20240328 clang i386 randconfig-016-20240328 clang loongarchallmodconfig gcc loongarch allnoconfig gcc loongarch defconfig gcc loongarch randconfig-001-20240328 gcc loongarch randconfig-002-20240328 gcc m68k allmodconfig gcc m68k allnoconfig gcc m68k allyesconfig gcc m68kdefconfig gcc microblaze allmodconfig gcc microblazeallnoconfig gcc microblaze allyesconfig gcc microblaze defconfig gcc mips allnoconfig gcc mips allyesconfig gcc nios2allmodconfig gcc nios2 allnoconfig gcc nios2allyesconfig gcc nios2 defconfig gcc nios2 randconfig-001-20240328 gcc nios2 randconfig-002-20240328 gcc openrisc allnoconfig gcc openrisc allyesconfig gcc openriscdefconfig gcc parisc allmodconfig gcc pariscallnoconfig gcc parisc allyesconfig gcc parisc
Re: [Intel-wired-lan] [PATCH v2 iwl-next 03/12] ice: Implement Tx interrupt enablement functions
On Thu, Mar 28, 2024 at 3:04 PM Karol Kolacinski
wrote:
>
> From: Sergey Temerkhanov
>
> Introduce functions enabling/disabling Tx TS interrupts
> for the E822 and ETH56G PHYs
>
> Signed-off-by: Sergey Temerkhanov
> Reviewed-by: Przemek Kitszel
> Reviewed-by: Arkadiusz Kubalewski
> Signed-off-by: Karol Kolacinski
> ---
> drivers/net/ethernet/intel/ice/ice_ptp.c| 63 ++---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 31 ++
> drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 +-
> 3 files changed, 63 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c
> b/drivers/net/ethernet/intel/ice/ice_ptp.c
> index 8150f949dfd3..3019988a43c8 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
> @@ -1457,42 +1457,43 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port,
> bool linkup)
> * @ena: bool value to enable or disable interrupt
> * @threshold: Minimum number of packets at which intr is triggered
> *
> - * Utility function to enable or disable Tx timestamp interrupt and threshold
> + * Utility function to configure all the PHY interrupt settings, including
> + * whether the PHY interrupt is enabled, and what threshold to use. Also
> + * configures The E82X timestamp owner to react to interrupts from all PHYs.
> */
> static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32
> threshold)
> {
> + struct device *dev = ice_pf_to_dev(pf);
> struct ice_hw *hw = &pf->hw;
> - int err = 0;
> - int quad;
> - u32 val;
>
> ice_ptp_reset_ts_memory(hw);
>
> - for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {
> - err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
> -&val);
> - if (err)
> - break;
> -
> - if (ena) {
> - val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> - val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
> - val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,
> - threshold);
> - } else {
> - val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> + switch (hw->ptp.phy_model) {
> + case ICE_PHY_E82X: {
> + int quad;
> +
> + for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports);
> +quad++) {
> + int err;
> +
> + err = ice_phy_cfg_intr_e82x(hw, quad, ena, threshold);
> + if (err) {
> + dev_err(dev, "Failed to configure PHY
> interrupt for quad %d, err %d\n",
> + quad, err);
> + return err;
> + }
> }
>
> - err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
> - val);
> - if (err)
> - break;
> + return 0;
> + }
> + case ICE_PHY_E810:
> + return 0;
> + case ICE_PHY_UNSUP:
> + default:
> + dev_warn(dev, "%s: Unexpected PHY model %d\n", __func__,
> +hw->ptp.phy_model);
> + return -EOPNOTSUPP;
> }
> -
> - if (err)
> - dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
> - err);
> - return err;
> }
>
> /**
> @@ -3010,12 +3011,10 @@ static int ice_ptp_init_owner(struct ice_pf *pf)
> /* Release the global hardware lock */
> ice_ptp_unlock(hw);
>
> - if (!ice_is_e810(hw)) {
> - /* Enable quad interrupts */
> - err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
> - if (err)
> - goto err_exit;
> - }
> + /* Configure PHY interrupt settings */
> + err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
> + if (err)
> + goto err_exit;
>
> /* Ensure we have a clock device */
> err = ice_ptp_create_clock(pf);
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index c892b966c3b8..12f04ad263c5 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -2715,6 +2715,37 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8
> quad, u64 *tstamp_ready)
> return 0;
> }
>
> +/**
> + * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
> + * @hw: pointer to the HW struct
> + * @quad: the timestamp quad
> + * @ena: enable or disable interrupt
> + * @threshold: interrupt threshold
> + *
> + * Configure TX timestamp interrupt for the specified quad
> + */
> +
> +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad,
[Intel-wired-lan] [tnguy-net-queue:1GbE] BUILD SUCCESS 861e8086029e003305750b4126ecd6617465f5c7
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue.git 1GbE branch HEAD: 861e8086029e003305750b4126ecd6617465f5c7 e1000e: move force SMBUS from enable ulp function to avoid PHY loss issue elapsed time: 1244m configs tested: 161 configs skipped: 3 The following configs have been built successfully. More configs may be tested in the coming days. tested configs: alpha allnoconfig gcc alphaallyesconfig gcc alpha defconfig gcc arc allmodconfig gcc arc allnoconfig gcc arc allyesconfig gcc arc defconfig gcc arc haps_hs_smp_defconfig gcc arc randconfig-001-20240328 gcc arc randconfig-002-20240328 gcc arm allmodconfig gcc arm allnoconfig clang arm allyesconfig gcc arm defconfig clang arm ixp4xx_defconfig gcc arm moxart_defconfig gcc arm multi_v4t_defconfig clang arm randconfig-001-20240328 gcc arm randconfig-002-20240328 gcc arm randconfig-003-20240328 gcc arm randconfig-004-20240328 gcc arm s5pv210_defconfig gcc arm sama5_defconfig gcc arm64allmodconfig clang arm64 allnoconfig gcc arm64 defconfig gcc arm64 randconfig-001-20240328 gcc arm64 randconfig-002-20240328 gcc arm64 randconfig-003-20240328 gcc arm64 randconfig-004-20240328 gcc csky allmodconfig gcc csky allnoconfig gcc csky allyesconfig gcc cskydefconfig gcc csky randconfig-001-20240328 gcc csky randconfig-002-20240328 gcc hexagon allmodconfig clang hexagon allnoconfig clang hexagon allyesconfig clang hexagon defconfig clang hexagon randconfig-001-20240328 clang hexagon randconfig-002-20240328 clang i386 allmodconfig gcc i386 allnoconfig gcc i386 allyesconfig gcc i386 buildonly-randconfig-001-20240328 gcc i386 buildonly-randconfig-002-20240328 gcc i386 buildonly-randconfig-003-20240328 clang i386 buildonly-randconfig-004-20240328 gcc i386 buildonly-randconfig-005-20240328 gcc i386 buildonly-randconfig-006-20240328 gcc i386defconfig clang i386 randconfig-001-20240328 clang i386 randconfig-002-20240328 clang i386 randconfig-003-20240328 clang i386 randconfig-004-20240328 clang i386 randconfig-005-20240328 gcc i386 randconfig-006-20240328 gcc i386 randconfig-011-20240328 clang i386 randconfig-012-20240328 clang i386 randconfig-013-20240328 clang i386 randconfig-014-20240328 clang i386 randconfig-015-20240328 clang i386 randconfig-016-20240328 clang loongarchallmodconfig gcc loongarch allnoconfig gcc loongarch defconfig gcc loongarch randconfig-001-20240328 gcc loongarch randconfig-002-20240328 gcc m68k allmodconfig gcc m68k allnoconfig gcc m68k allyesconfig gcc m68k amcore_defconfig gcc m68kdefconfig gcc microblaze allmodconfig gcc microblazeallnoconfig gcc microblaze allyesconfig gcc microblaze defconfig gcc mips allnoconfig gcc mips allyesconfig gcc mips ath25_defconfig clang mips gcw0_defconfig clang mips ip22_defconfig gcc mips ip32_defconfig clang mips loongson1c_defconfig gcc mips
Re: [Intel-wired-lan] [PATCH net] i40e: Fix VF MAC filter removal
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Brett Creeley
> Sent: Thursday, March 14, 2024 4:54 PM
> To: ivecera ; net...@vger.kernel.org
> Cc: moderated list:INTEL ETHERNET DRIVERS l...@lists.osuosl.org>; open list ; Loktionov,
> Aleksandr ; Eric Dumazet
> ; Nguyen, Anthony L
> ; ho...@kernel.org; Jakub Kicinski
> ; Paolo Abeni ; David S. Miller
>
> Subject: Re: [Intel-wired-lan] [PATCH net] i40e: Fix VF MAC filter removal
>
> On 3/13/2024 6:56 AM, Ivan Vecera wrote:
> > Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> >
> >
> > Commit 73d9629e1c8c ("i40e: Do not allow untrusted VF to remove
> > administratively set MAC") fixed an issue where untrusted VF was
> > allowed to remove its own MAC address although this was assigned
> > administratively from PF. Unfortunately the introduced check is wrong
> > because it causes that MAC filters for other MAC addresses including
> > multi-cast ones are not removed.
> >
> >
> > if (ether_addr_equal(addr, vf->default_lan_addr.addr) &&
> > i40e_can_vf_change_mac(vf))
> > was_unimac_deleted = true;
> > else
> > continue;
> >
> > if (i40e_del_mac_filter(vsi, al->list[i].addr)) {
> > ...
> >
> >
> > The else path with `continue` effectively skips any MAC filter removal
> > except one for primary MAC addr when VF is allowed to do so.
> > Fix the check condition so the `continue` is only done for primary MAC
> > address.
> >
> > Fixes: 73d9629e1c8c ("i40e: Do not allow untrusted VF to remove
> > administratively set MAC")
> > Signed-off-by: Ivan Vecera
> > ---
> > drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> > b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> > index b34c71770887..10267a300770 100644
> > --- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> > +++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> > @@ -3143,11 +3143,12 @@ static int i40e_vc_del_mac_addr_msg(struct
> i40e_vf *vf, u8 *msg)
> > /* Allow to delete VF primary MAC only if it was not set
> > * administratively by PF or if VF is trusted.
> > */
> > - if (ether_addr_equal(addr, vf->default_lan_addr.addr) &&
> > - i40e_can_vf_change_mac(vf))
> > - was_unimac_deleted = true;
> > - else
> > - continue;
> > + if (ether_addr_equal(addr, vf->default_lan_addr.addr)) {
> > + if (i40e_can_vf_change_mac(vf))
> > + was_unimac_deleted = true;
> > + else
> > + continue;
> > + }
>
> Seems okay to me.
>
> Reviewed-by: Brett Creeley
>
> >
> > if (i40e_del_mac_filter(vsi, al->list[i].addr)) {
> > ret = -EINVAL;
> > --
> > 2.43.0
> >
> >
Tested-by: Rafal Romanowski
Re: [Intel-wired-lan] [PATCH iwl-next v2 2/7] i40e: Refactor argument of several client notification functions
On Wed, Mar 27, 2024 at 08:57:28AM +0100, Ivan Vecera wrote:
> Commit 0ef2d5afb12d ("i40e: KISS the client interface") simplified
> the client interface so in practice it supports only one client
> per i40e netdev. But we have still 2 notification functions that
> uses as parameter a pointer to VSI of netdevice associated with
> the client. After the mentioned commit only possible and used
> VSI is the main (LAN) VSI.
> So refactor these functions so they are called with PF pointer argument
> and the associated VSI (LAN) is taken inside them.
>
> Reviewed-by: Michal Schmidt
> Signed-off-by: Ivan Vecera
Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2 1/7] i40e: Remove flags field from i40e_veb
On Wed, Mar 27, 2024 at 08:57:27AM +0100, Ivan Vecera wrote: > The field is initialized always to zero and it is never read. > Remove it. > > Reviewed-by: Michal Schmidt > Reviewed-by: Aleksandr Loktionov > Reviewed-by: Kalesh AP > Signed-off-by: Ivan Vecera Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2 3/7] i40e: Refactor argument of i40e_detect_recover_hung()
On Wed, Mar 27, 2024 at 08:57:29AM +0100, Ivan Vecera wrote:
> Commit 07d44190a389 ("i40e/i40evf: Detect and recover hung queue
> scenario") changes i40e_detect_recover_hung() argument type from
> i40e_pf* to i40e_vsi* to be shareable by both i40e and i40evf.
> Because the i40evf does not exist anymore and the function is
> exclusively used by i40e we can revert this change.
>
> Reviewed-by: Michal Schmidt
> Signed-off-by: Ivan Vecera
Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2 4/7] i40e: Add helper to access main VSI
On Wed, Mar 27, 2024 at 08:57:30AM +0100, Ivan Vecera wrote: > Add simple helper i40e_pf_get_main_vsi(pf) to access main VSI > that replaces pattern 'pf->vsi[pf->lan_vsi]' > > Reviewed-by: Michal Schmidt > Signed-off-by: Ivan Vecera Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2 5/7] i40e: Consolidate checks whether given VSI is main
On Wed, Mar 27, 2024 at 08:57:31AM +0100, Ivan Vecera wrote: > In the driver code there are 3 types of checks whether given > VSI is main or not: > 1. vsi->type ==/!= I40E_VSI_MAIN > 2. vsi ==/!= pf->vsi[pf->lan_vsi] > 3. vsi->seid ==/!= pf->vsi[pf->lan_vsi]->seid > > All of them are equivalent and can be consolidated. Convert cases > 2 and 3 to case 1. > > Reviewed-by: Michal Schmidt > Signed-off-by: Ivan Vecera Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2 6/7] i40e: Add helper to access main VEB
On Wed, Mar 27, 2024 at 08:57:32AM +0100, Ivan Vecera wrote: > Add a helper to access main VEB: > > i40e_pf_get_main_veb(pf) replaces 'pf->veb[pf->lan_veb]' > > Reviewed-by: Michal Schmidt > Reviewed-by: Aleksandr Loktionov > Signed-off-by: Ivan Vecera Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v2 7/7] i40e: Add and use helper to reconfigure TC for given VSI
On Wed, Mar 27, 2024 at 08:57:33AM +0100, Ivan Vecera wrote: > Add helper i40e_vsi_reconfig_tc(vsi) that configures TC > for given VSI using previously stored TC bitmap. > > Effectively replaces open-coded patterns: > > enabled_tc = vsi->tc_config.enabled_tc; > vsi->tc_config.enabled_tc = 0; > i40e_vsi_config_tc(vsi, enabled_tc); > > Reviewed-by: Michal Schmidt > Signed-off-by: Ivan Vecera Reviewed-by: Simon Horman
Re: [Intel-wired-lan] [PATCH iwl-next v3] ice: Reset VF on Tx MDD event
On Tue, Mar 26, 2024 at 05:44:55PM +0100, Marcin Szycik wrote: > In cases when VF sends malformed packets that are classified as malicious, > sometimes it causes Tx queue to freeze. This frozen queue can be stuck > for several minutes being unusable. This behavior can be reproduced with > a faulty userspace app running on VF. > > When Malicious Driver Detection event occurs and the mdd-auto-reset-vf > private flag is set, perform a graceful VF reset to quickly bring VF back > to operational state. Add a log message to notify about the cause of > the reset. Add a helper for this to be reused for both TX and RX events. > > Reviewed-by: Wojciech Drewek > Co-developed-by: Liang-Min Wang > Signed-off-by: Liang-Min Wang > Signed-off-by: Marcin Szycik Hi Marcin, If I read this correctly then a reset may be performed for several different conditions - values of different registers - for a VF as checked in a for loop. I am wondering if multiple resets could occur for the same VF within an iteration of the for loop - because more than one of the conditions is met. And, if so, is this ok?
Re: [Intel-wired-lan] [PATCH iwl-next v1 2/2] ice: update E830 device ids and comments
On 3/26/2024 9:36 AM, Paul Greenwalt wrote: Update existing E830 device ids and comments to align with new naming 'C' for 100G and 'CC' for 200G. Reviewed-by: Wojciech Drewek Signed-off-by: Paul Greenwalt --- ... diff --git a/drivers/net/ethernet/intel/ice/ice_devids.h b/drivers/net/ethernet/intel/ice/ice_devids.h index c37b2b450b02..9a1bc434f167 100644 --- a/drivers/net/ethernet/intel/ice/ice_devids.h +++ b/drivers/net/ethernet/intel/ice/ice_devids.h @@ -16,14 +16,14 @@ #define ICE_DEV_ID_E823L_1GBE 0x124F /* Intel(R) Ethernet Connection E823-L for QSFP */ #define ICE_DEV_ID_E823L_QSFP 0x151D -/* Intel(R) Ethernet Controller E830-C for backplane */ -#define ICE_DEV_ID_E830_BACKPLANE 0x12D1 -/* Intel(R) Ethernet Controller E830-C for QSFP */ -#define ICE_DEV_ID_E830_QSFP56 0x12D2 -/* Intel(R) Ethernet Controller E830-C for SFP */ -#define ICE_DEV_ID_E830_SFP0x12D3 -/* Intel(R) Ethernet Controller E830-C for SFP-DD */ -#define ICE_DEV_ID_E830_SFP_DD 0x12D4 +/* Intel(R) Ethernet Controller E830-CC for backplane */ +#define ICE_DEV_ID_E830CC_BACKPLANE0x12D1 +/* Intel(R) Ethernet Controller E830-CC for QSFP */ +#define ICE_DEV_ID_E830CC_QSFP56 0x12D2 +/* Intel(R) Ethernet Controller E830-CC for SFP */ +#define ICE_DEV_ID_E830CC_SFP 0x12D3 +/* Intel(R) Ethernet Controller E830-CC for SFP-DD */ +#define ICE_DEV_ID_E83CC0_SFP_DD 0x12D4 This doesn't compile; there's a stray '0' here. ../drivers/net/ethernet/intel/ice/ice_common.c:166:14: error: ‘ICE_DEV_ID_E830CC_SFP_DD’ undeclared (first use in this function); did you mean ‘ICE_DEV_ID_E83CC0_SFP_DD’? 166 | case ICE_DEV_ID_E830CC_SFP_DD: | ^~~~ | ICE_DEV_ID_E83CC0_SFP_DD ... /* Intel(R) Ethernet Controller E830-C for backplane */ #define ICE_DEV_ID_E830C_BACKPLANE0x12D5 /* Intel(R) Ethernet Controller E830-C for QSFP */
Re: [Intel-wired-lan] [PATCH iwl-next v1 2/2] ice: update E830 device ids and comments
> On Mar 28, 2024, at 2:16 PM, Tony Nguyen wrote: > >> +/* Intel(R) Ethernet Controller E830-CC for SFP-DD */ >> +#define ICE_DEV_ID_E83CC0_SFP_DD 0x12D4 > > This doesn't compile; there's a stray '0' here. Not stray, just mispositioned in the definition above. > ../drivers/net/ethernet/intel/ice/ice_common.c:166:14: error: > ‘ICE_DEV_ID_E830CC_SFP_DD’ undeclared (first use in this function); did you > mean ‘ICE_DEV_ID_E83CC0_SFP_DD’? > 166 | case ICE_DEV_ID_E830CC_SFP_DD: > | ^~~~ > | ICE_DEV_ID_E83CC0_SFP_DD > > ... -- Mark Rustad (he/him), Ethernet Products Group, Intel Corporation
Re: [Intel-wired-lan] [PATCH net-next v8 0/6] ice: Support 5 layer Tx scheduler topology
On 3/26/2024 7:30 AM, Mateusz Polchlopek wrote: For performance reasons there is a need to have support for selectable Tx scheduler topology. Currently firmware supports only the default 9-layer and 5-layer topology. This patch series enables switch from default to 5-layer topology, if user decides to opt-in. This no longer applies after Michal S' series was applied https://lore.kernel.org/intel-wired-lan/20240325213433.829161-1-michal.swiatkow...@linux.intel.com/ Can you please rebase and resend? Thanks, Tony
Re: [Intel-wired-lan] [PATCH iwl-next v1 2/2] ice: update E830 device ids and comments
On 3/28/2024 2:37 PM, Rustad, Mark D wrote: On Mar 28, 2024, at 2:16 PM, Tony Nguyen wrote: +/* Intel(R) Ethernet Controller E830-CC for SFP-DD */ +#define ICE_DEV_ID_E83CC0_SFP_DD 0x12D4 This doesn't compile; there's a stray '0' here. Not stray, just mispositioned in the definition above. Missed the missing 0. Yea, mispositioned. Thanks Mark :) ../drivers/net/ethernet/intel/ice/ice_common.c:166:14: error: ‘ICE_DEV_ID_E830CC_SFP_DD’ undeclared (first use in this function); did you mean ‘ICE_DEV_ID_E83CC0_SFP_DD’? 166 | case ICE_DEV_ID_E830CC_SFP_DD: | ^~~~ | ICE_DEV_ID_E83CC0_SFP_DD ...
[Intel-wired-lan] [PATCH iwl-next v3 1/2] ice: add additional E830 device ids
Add support for additional E830 device ids which are supported by the
driver:
- 0x12D5: Intel(R) Ethernet Controller E830-C for backplane
- 0x12D8: Intel(R) Ethernet Controller E830-C for QSFP
- 0x12DA: Intel(R) Ethernet Controller E830-C for SFP
- 0x12DC: Intel(R) Ethernet Controller E830-XXV for backplane
- 0x12DD: Intel(R) Ethernet Controller E830-XXV for QSFP
- 0x12DE: Intel(R) Ethernet Controller E830-XXV for SFP
Reviewed-by: Wojciech Drewek
Signed-off-by: Paul Greenwalt
---
v1 -> v2: add device ids and strings to commit message. Rearrange device
ids in order.
---
drivers/net/ethernet/intel/ice/ice_common.c | 6 ++
drivers/net/ethernet/intel/ice/ice_devids.h | 12
drivers/net/ethernet/intel/ice/ice_main.c | 6 ++
3 files changed, 24 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index f4ac3c30b124..acfae3cd5b6c 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -164,6 +164,12 @@ static int ice_set_mac_type(struct ice_hw *hw)
case ICE_DEV_ID_E830_QSFP56:
case ICE_DEV_ID_E830_SFP:
case ICE_DEV_ID_E830_SFP_DD:
+ case ICE_DEV_ID_E830C_BACKPLANE:
+ case ICE_DEV_ID_E830_XXV_BACKPLANE:
+ case ICE_DEV_ID_E830C_QSFP:
+ case ICE_DEV_ID_E830_XXV_QSFP:
+ case ICE_DEV_ID_E830C_SFP:
+ case ICE_DEV_ID_E830_XXV_SFP:
hw->mac_type = ICE_MAC_E830;
break;
default:
diff --git a/drivers/net/ethernet/intel/ice/ice_devids.h
b/drivers/net/ethernet/intel/ice/ice_devids.h
index 9dfae9bce758..c37b2b450b02 100644
--- a/drivers/net/ethernet/intel/ice/ice_devids.h
+++ b/drivers/net/ethernet/intel/ice/ice_devids.h
@@ -24,6 +24,18 @@
#define ICE_DEV_ID_E830_SFP0x12D3
/* Intel(R) Ethernet Controller E830-C for SFP-DD */
#define ICE_DEV_ID_E830_SFP_DD 0x12D4
+/* Intel(R) Ethernet Controller E830-C for backplane */
+#define ICE_DEV_ID_E830C_BACKPLANE 0x12D5
+/* Intel(R) Ethernet Controller E830-C for QSFP */
+#define ICE_DEV_ID_E830C_QSFP 0x12D8
+/* Intel(R) Ethernet Controller E830-C for SFP */
+#define ICE_DEV_ID_E830C_SFP 0x12DA
+/* Intel(R) Ethernet Controller E830-XXV for backplane */
+#define ICE_DEV_ID_E830_XXV_BACKPLANE 0x12DC
+/* Intel(R) Ethernet Controller E830-XXV for QSFP */
+#define ICE_DEV_ID_E830_XXV_QSFP 0x12DD
+/* Intel(R) Ethernet Controller E830-XXV for SFP */
+#define ICE_DEV_ID_E830_XXV_SFP0x12DE
/* Intel(R) Ethernet Controller E810-C for backplane */
#define ICE_DEV_ID_E810C_BACKPLANE 0x1591
/* Intel(R) Ethernet Controller E810-C for QSFP */
diff --git a/drivers/net/ethernet/intel/ice/ice_main.c
b/drivers/net/ethernet/intel/ice/ice_main.c
index 3dea0d4c767c..2f198bf3d8b1 100644
--- a/drivers/net/ethernet/intel/ice/ice_main.c
+++ b/drivers/net/ethernet/intel/ice/ice_main.c
@@ -5695,6 +5695,12 @@ static const struct pci_device_id ice_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_QSFP56) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_SFP) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_SFP_DD) },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830C_BACKPLANE), },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_XXV_BACKPLANE), },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830C_QSFP), },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_XXV_QSFP), },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830C_SFP), },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_XXV_SFP), },
/* required last entry */
{}
};
--
2.41.0
[Intel-wired-lan] [PATCH iwl-next v3 2/2] ice: update E830 device ids and comments
Update existing E830 device ids and comments to align with new naming 'C'
for 100G and 'CC' for 200G.
Reviewed-by: Wojciech Drewek
Signed-off-by: Paul Greenwalt
---
v2 -> v3: fix compiler error
---
drivers/net/ethernet/intel/ice/ice_common.c | 8
drivers/net/ethernet/intel/ice/ice_devids.h | 16
drivers/net/ethernet/intel/ice/ice_main.c | 8
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index acfae3cd5b6c..199049e08a78 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -160,10 +160,10 @@ static int ice_set_mac_type(struct ice_hw *hw)
case ICE_DEV_ID_E825C_SGMII:
hw->mac_type = ICE_MAC_GENERIC_3K_E825;
break;
- case ICE_DEV_ID_E830_BACKPLANE:
- case ICE_DEV_ID_E830_QSFP56:
- case ICE_DEV_ID_E830_SFP:
- case ICE_DEV_ID_E830_SFP_DD:
+ case ICE_DEV_ID_E830CC_BACKPLANE:
+ case ICE_DEV_ID_E830CC_QSFP56:
+ case ICE_DEV_ID_E830CC_SFP:
+ case ICE_DEV_ID_E830CC_SFP_DD:
case ICE_DEV_ID_E830C_BACKPLANE:
case ICE_DEV_ID_E830_XXV_BACKPLANE:
case ICE_DEV_ID_E830C_QSFP:
diff --git a/drivers/net/ethernet/intel/ice/ice_devids.h
b/drivers/net/ethernet/intel/ice/ice_devids.h
index c37b2b450b02..34fd604132f5 100644
--- a/drivers/net/ethernet/intel/ice/ice_devids.h
+++ b/drivers/net/ethernet/intel/ice/ice_devids.h
@@ -16,14 +16,14 @@
#define ICE_DEV_ID_E823L_1GBE 0x124F
/* Intel(R) Ethernet Connection E823-L for QSFP */
#define ICE_DEV_ID_E823L_QSFP 0x151D
-/* Intel(R) Ethernet Controller E830-C for backplane */
-#define ICE_DEV_ID_E830_BACKPLANE 0x12D1
-/* Intel(R) Ethernet Controller E830-C for QSFP */
-#define ICE_DEV_ID_E830_QSFP56 0x12D2
-/* Intel(R) Ethernet Controller E830-C for SFP */
-#define ICE_DEV_ID_E830_SFP0x12D3
-/* Intel(R) Ethernet Controller E830-C for SFP-DD */
-#define ICE_DEV_ID_E830_SFP_DD 0x12D4
+/* Intel(R) Ethernet Controller E830-CC for backplane */
+#define ICE_DEV_ID_E830CC_BACKPLANE0x12D1
+/* Intel(R) Ethernet Controller E830-CC for QSFP */
+#define ICE_DEV_ID_E830CC_QSFP56 0x12D2
+/* Intel(R) Ethernet Controller E830-CC for SFP */
+#define ICE_DEV_ID_E830CC_SFP 0x12D3
+/* Intel(R) Ethernet Controller E830-CC for SFP-DD */
+#define ICE_DEV_ID_E830CC_SFP_DD 0x12D4
/* Intel(R) Ethernet Controller E830-C for backplane */
#define ICE_DEV_ID_E830C_BACKPLANE 0x12D5
/* Intel(R) Ethernet Controller E830-C for QSFP */
diff --git a/drivers/net/ethernet/intel/ice/ice_main.c
b/drivers/net/ethernet/intel/ice/ice_main.c
index 2f198bf3d8b1..3c76c3ffe7a4 100644
--- a/drivers/net/ethernet/intel/ice/ice_main.c
+++ b/drivers/net/ethernet/intel/ice/ice_main.c
@@ -5691,10 +5691,10 @@ static const struct pci_device_id ice_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E825C_QSFP), },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E825C_SFP), },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E825C_SGMII), },
- { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_BACKPLANE) },
- { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_QSFP56) },
- { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_SFP) },
- { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_SFP_DD) },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830CC_BACKPLANE) },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830CC_QSFP56) },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830CC_SFP) },
+ { PCI_VDEVICE(INTEL, ICE_DEV_ID_E830CC_SFP_DD) },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830C_BACKPLANE), },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830_XXV_BACKPLANE), },
{ PCI_VDEVICE(INTEL, ICE_DEV_ID_E830C_QSFP), },
--
2.41.0
Re: [Intel-wired-lan] [PATCH net-next v2] net: remove gfp_mask from napi_alloc_skb()
Hello: This patch was applied to netdev/net-next.git (main) by Jakub Kicinski : On Tue, 26 Mar 2024 21:02:12 -0700 you wrote: > __napi_alloc_skb() is napi_alloc_skb() with the added flexibility > of choosing gfp_mask. This is a NAPI function, so GFP_ATOMIC is > implied. The only practical choice the caller has is whether to > set __GFP_NOWARN. But that's a false choice, too, allocation failures > in atomic context will happen, and printing warnings in logs, > effectively for a packet drop, is both too much and very likely > non-actionable. > > [...] Here is the summary with links: - [net-next,v2] net: remove gfp_mask from napi_alloc_skb() https://git.kernel.org/netdev/net-next/c/6e9b01909a81 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
Re: [Intel-wired-lan] [PATCH net-next v2 0/3] compiler_types: add Endianness-dependent __counted_by_{le, be}
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski :
On Wed, 27 Mar 2024 15:22:38 +0100 you wrote:
> Some structures contain flexible arrays at the end and the counter for
> them, but the counter has explicit Endianness and thus __counted_by()
> can't be used directly.
>
> To increase test coverage for potential problems without breaking
> anything, introduce __counted_by_{le,be} defined depending on platform's
> Endianness to either __counted_by() when applicable or noop otherwise.
> The first user will be virtchnl2.h from idpf just as example with 9 flex
> structures having Little Endian counters.
>
> [...]
Here is the summary with links:
- [net-next,v2,1/3] compiler_types: add Endianness-dependent
__counted_by_{le,be}
https://git.kernel.org/netdev/net-next/c/ca7e324e8ad3
- [net-next,v2,2/3] idpf: make virtchnl2.h self-contained
https://git.kernel.org/netdev/net-next/c/c00d33f1fc79
- [net-next,v2,3/3] idpf: sprinkle __counted_by{,_le}() in the virtchnl2
header
https://git.kernel.org/netdev/net-next/c/93d24acfa05e
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
Re: [Intel-wired-lan] [PATCH iwl-next v2 3/7] i40e: Refactor argument of i40e_detect_recover_hung()
On Wed, Mar 27, 2024 at 1:28 PM Ivan Vecera wrote:
>
> Commit 07d44190a389 ("i40e/i40evf: Detect and recover hung queue
> scenario") changes i40e_detect_recover_hung() argument type from
> i40e_pf* to i40e_vsi* to be shareable by both i40e and i40evf.
> Because the i40evf does not exist anymore and the function is
> exclusively used by i40e we can revert this change.
>
> Reviewed-by: Michal Schmidt
> Signed-off-by: Ivan Vecera
Reviewed-by: Kalesh AP
> ---
> drivers/net/ethernet/intel/i40e/i40e_main.c | 2 +-
> drivers/net/ethernet/intel/i40e/i40e_txrx.c | 10 ++
> drivers/net/ethernet/intel/i40e/i40e_txrx.h | 2 +-
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c
> b/drivers/net/ethernet/intel/i40e/i40e_main.c
> index 7fed7fb69d4e..1ba28893f49e 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_main.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
> @@ -11274,7 +11274,7 @@ static void i40e_service_task(struct work_struct
> *work)
> return;
>
> if (!test_bit(__I40E_RECOVERY_MODE, pf->state)) {
> - i40e_detect_recover_hung(pf->vsi[pf->lan_vsi]);
> + i40e_detect_recover_hung(pf);
> i40e_sync_filters_subtask(pf);
> i40e_reset_subtask(pf);
> i40e_handle_mdd_event(pf);
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c
> b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
> index 1a12b732818e..e35a08de16b2 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
> @@ -860,13 +860,15 @@ u32 i40e_get_tx_pending(struct i40e_ring *ring, bool
> in_sw)
>
> /**
> * i40e_detect_recover_hung - Function to detect and recover hung_queues
> - * @vsi: pointer to vsi struct with tx queues
> + * @pf: pointer to PF struct
> *
> - * VSI has netdev and netdev has TX queues. This function is to check each of
> - * those TX queues if they are hung, trigger recovery by issuing SW
> interrupt.
> + * LAN VSI has netdev and netdev has TX queues. This function is to check
> + * each of those TX queues if they are hung, trigger recovery by issuing
> + * SW interrupt.
> **/
> -void i40e_detect_recover_hung(struct i40e_vsi *vsi)
> +void i40e_detect_recover_hung(struct i40e_pf *pf)
> {
> + struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
> struct i40e_ring *tx_ring = NULL;
> struct net_device *netdev;
> unsigned int i;
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h
> b/drivers/net/ethernet/intel/i40e/i40e_txrx.h
> index 2cdc7de6301c..7c26c9a2bf65 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h
> +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h
> @@ -470,7 +470,7 @@ void i40e_free_rx_resources(struct i40e_ring *rx_ring);
> int i40e_napi_poll(struct napi_struct *napi, int budget);
> void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector);
> u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw);
> -void i40e_detect_recover_hung(struct i40e_vsi *vsi);
> +void i40e_detect_recover_hung(struct i40e_pf *pf);
> int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
> bool __i40e_chk_linearize(struct sk_buff *skb);
> int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
> --
> 2.43.0
>
>
--
Regards,
Kalesh A P
smime.p7s
Description: S/MIME Cryptographic Signature
Re: [Intel-wired-lan] [PATCH net-next v4 1/3] ice: add ice_adapter for shared data across PFs on the same NIC
> -Original Message- > From: Intel-wired-lan On Behalf Of > Michal Schmidt > Sent: Tuesday, March 26, 2024 4:51 AM > To: intel-wired-...@lists.osuosl.org > Cc: Jiri Pirko ; Temerkhanov, Sergey > ; net...@vger.kernel.org; Richard Cochran > ; Kubalewski, Arkadiusz > ; Kolacinski, Karol > ; Marcin Szycik ; > Nguyen, Anthony L ; Kitszel, Przemyslaw > ; Keller, Jacob E > Subject: [Intel-wired-lan] [PATCH net-next v4 1/3] ice: add ice_adapter for > shared data across PFs on the same NIC > > There is a need for synchronization between ice PFs on the same physical > adapter. > > Add a "struct ice_adapter" for holding data shared between PFs of the same > multifunction PCI device. The struct is refcounted - each ice_pf holds a > reference to it. > > Its first use will be for PTP. I expect it will be useful also to improve the > ugliness that is ice_prot_id_tbl. > > Reviewed-by: Przemek Kitszel > Signed-off-by: Michal Schmidt > --- > drivers/net/ethernet/intel/ice/Makefile | 3 +- > drivers/net/ethernet/intel/ice/ice.h | 2 + > drivers/net/ethernet/intel/ice/ice_adapter.c | 114 +++ > drivers/net/ethernet/intel/ice/ice_adapter.h | 22 > drivers/net/ethernet/intel/ice/ice_main.c| 8 ++ > 5 files changed, 148 insertions(+), 1 deletion(-) create mode 100644 > drivers/net/ethernet/intel/ice/ice_adapter.c > create mode 100644 drivers/net/ethernet/intel/ice/ice_adapter.h > Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel)
Re: [Intel-wired-lan] [PATCH net-next v4 2/3] ice: avoid the PTP hardware semaphore in gettimex64 path
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Michal Schmidt
> Sent: Tuesday, March 26, 2024 4:51 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: Jiri Pirko ; Temerkhanov, Sergey
> ; net...@vger.kernel.org; Richard Cochran
> ; Kubalewski, Arkadiusz
> ; Kolacinski, Karol
> ; Marcin Szycik ;
> Nguyen, Anthony L ; Kitszel, Przemyslaw
> ; Keller, Jacob E
> Subject: [Intel-wired-lan] [PATCH net-next v4 2/3] ice: avoid the PTP
> hardware semaphore in gettimex64 path
>
> The PTP hardware semaphore (PFTSYN_SEM) is used to synchronize operations
> that program the PTP timers. The operations involve issuing commands to the
> sideband queue. The E810 does not have a hardware sideband queue, so the
> admin queue is used. The admin queue is slow.
> I have observed delays in hundreds of milliseconds waiting for ice_sq_done.
>
> When phc2sys reads the time from the ice PTP clock and PFTSYN_SEM is held by
> a task performing one of the slow operations, ice_ptp_lock can easily time
> out. phc2sys gets -EBUSY and the kernel prints:
> ice :XX:YY.0: PTP failed to get time These messages appear once every
> few seconds, causing log spam.
>
> The E810 datasheet recommends an algorithm for reading the upper 64 bits of
> the GLTSYN_TIME register. It matches what's implemented in
> ice_ptp_read_src_clk_reg. It is robust against wrap-around, but not
> necessarily against the concurrent setting of the register (with
> GLTSYN_CMD_{INIT,ADJ}_TIME commands). Perhaps that's why
> ice_ptp_gettimex64 also takes PFTSYN_SEM.
>
> The race with time setters can be prevented without relying on the PTP
> hardware semaphore. Using the "ice_adapter" from the previous patch, we can
> have a common spinlock for the PFs that share the clock hardware.
> It will protect the reading and writing to the GLTSYN_TIME register.
> The writing is performed indirectly, by the hardware, as a result of the
> driver writing GLTSYN_CMD_SYNC in ice_ptp_exec_tmr_cmd. I wasn't sure if the
> ice_flush there is enough to make sure GLTSYN_TIME has been updated, but it
> works well in my testing.
>
> My test code can be seen here:
> https://gitlab.com/mschmidt2/linux/-/commits/ice-ptp-host-side-lock-10
> It consists of:
> - kernel threads reading the time in a busy loop and looking at the
>deltas between consecutive values, reporting new maxima.
> - a shell script that sets the time repeatedly;
> - a bpftrace probe to produce a histogram of the measured deltas.
> Without the spinlock ptp_gltsyn_time_lock, it is easy to see tearing.
> Deltas in the [2G, 4G) range appear in the histograms.
> With the spinlock added, there is no tearing and the biggest delta I saw was
> in the range [1M, 2M), that is under 2 ms.
>
> Reviewed-by: Jacob Keller
> Reviewed-by: Przemek Kitszel
> Signed-off-by: Michal Schmidt
> ---
> drivers/net/ethernet/intel/ice/ice_adapter.c | 2 ++
> drivers/net/ethernet/intel/ice/ice_adapter.h | 6 ++
> drivers/net/ethernet/intel/ice/ice_ptp.c | 8 +---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 3 +++
> 4 files changed, 12 insertions(+), 7 deletions(-)
>
Tested-by: Pucha Himasekhar Reddy (A
Contingent worker at Intel)
Re: [Intel-wired-lan] [PATCH net-next v4 3/3] ice: fold ice_ptp_read_time into ice_ptp_gettimex64
> -Original Message- > From: Intel-wired-lan On Behalf Of > Michal Schmidt > Sent: Tuesday, March 26, 2024 4:51 AM > To: intel-wired-...@lists.osuosl.org > Cc: Jiri Pirko ; Temerkhanov, Sergey > ; net...@vger.kernel.org; Richard Cochran > ; Kubalewski, Arkadiusz > ; Kolacinski, Karol > ; Marcin Szycik ; > Nguyen, Anthony L ; Kitszel, Przemyslaw > ; Keller, Jacob E > Subject: [Intel-wired-lan] [PATCH net-next v4 3/3] ice: fold > ice_ptp_read_time into ice_ptp_gettimex64 > > This is a cleanup. It is unnecessary to have this function just to call > another function. > > Reviewed-by: Przemek Kitszel > Signed-off-by: Michal Schmidt > --- > drivers/net/ethernet/intel/ice/ice_ptp.c | 25 +++- > 1 file changed, 3 insertions(+), 22 deletions(-) > Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel)
