from:"Umesh Kalappa"

[Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-18 Thread Umesh Kalappa

Hi Nagy/Ramana,

Please help us to review the attached patch and do let me know your comments .

No regress in the  gcc.target  suite for arm target.

Thank you
~Umesh

On Tue, Jul 17, 2018 at 4:01 PM, Umesh Kalappa  wrote:
> Will do, thanks.
> Thanks
>
> On Tue, Jul 17, 2018, 3:24 PM Ramana Radhakrishnan
>  wrote:
>>
>> On Tue, Jul 17, 2018 at 10:41 AM, Umesh Kalappa
>>  wrote:
>> > Hi Nagy,
>> >
>> > Please  help us with your comments on the attached patch for the issue
>> > (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86512)
>> >
>> > Thank you and waiting for your inputs on the same.
>>
>>
>> Patches should be sent to gcc-patches@gcc.gnu.org with a clear
>> description of what the patch hopes to
>> achieve and why this is correct, how was it tested and if a regression
>> test needs to be added - add one please.
>> Please read https://gcc.gnu.org/contribute.html before sending a patch.
>>
>> This is the wrong list to send patches to.
>>
>> regards
>> Ramana
>> > ~Umesh
>> >
>> > On Fri, Jul 13, 2018 at 1:22 PM, Umesh Kalappa
>> >  wrote:
>> >> Thank you and issue  raised at
>> >> gcc-patches@gcc.gnu.org
>> >>
>> >> ~Umesh
>> >>
>> >> On Thu, Jul 12, 2018 at 9:33 PM, Szabolcs Nagy 
>> >> wrote:
>> >>> On 12/07/18 16:20, Umesh Kalappa wrote:
>> >>>>
>> >>>> Hi everyone,
>> >>>>
>> >>>> we have our source base ,that was compiled for armv7 on gcc8.1 with
>> >>>> soft-float and for following input
>> >>>>
>> >>>> a=0x0010
>> >>>> b=0x0001
>> >>>>
>> >>>>   result = a - b ;
>> >>>>
>> >>>> we are getting the result as "0x000e" and with
>> >>>> -mhard-float (disabled the flush to zero mode ) we are getting the
>> >>>> result as ""0x000f" as expected.
>> >>>>
>> >>>
>> >>> please submit it as a bug report to bugzilla
>> >>>
>> >>>
>> >>>> while debugging the soft-float code,we see that ,the compiler calls
>> >>>> the intrinsic "__aeabi_dsub" with arm calling conventions i.e passing
>> >>>> "a" in r0 and r1 registers and respectively for "b".
>> >>>>
>> >>>> we are investigating the routine "__aeabi_dsub" that comes from
>> >>>> libgcc
>> >>>> for incorrect result  and meanwhile we would like to know that
>> >>>>
>> >>>> a)do libgcc routines/intrinsic for float operations support or
>> >>>> consider the subnormal values ? ,if so how we can enable the same.
>> >>>>
>> >>>> Thank you
>> >>>> ~Umesh
>> >>>>
>> >>>


pr86512.patch
Description: Binary data

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-20 Thread Umesh Kalappa

Reminder !!!

~Umesh


On Wed, Jul 18, 2018 at 6:01 PM, Umesh Kalappa  wrote:
> Hi Nagy/Ramana,
>
> Please help us to review the attached patch and do let me know your comments .
>
> No regress in the  gcc.target  suite for arm target.
>
> Thank you
> ~Umesh
>
> On Tue, Jul 17, 2018 at 4:01 PM, Umesh Kalappa  
> wrote:
>> Will do, thanks.
>> Thanks
>>
>> On Tue, Jul 17, 2018, 3:24 PM Ramana Radhakrishnan
>>  wrote:
>>>
>>> On Tue, Jul 17, 2018 at 10:41 AM, Umesh Kalappa
>>>  wrote:
>>> > Hi Nagy,
>>> >
>>> > Please  help us with your comments on the attached patch for the issue
>>> > (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86512)
>>> >
>>> > Thank you and waiting for your inputs on the same.
>>>
>>>
>>> Patches should be sent to gcc-patches@gcc.gnu.org with a clear
>>> description of what the patch hopes to
>>> achieve and why this is correct, how was it tested and if a regression
>>> test needs to be added - add one please.
>>> Please read https://gcc.gnu.org/contribute.html before sending a patch.
>>>
>>> This is the wrong list to send patches to.
>>>
>>> regards
>>> Ramana
>>> > ~Umesh
>>> >
>>> > On Fri, Jul 13, 2018 at 1:22 PM, Umesh Kalappa
>>> >  wrote:
>>> >> Thank you and issue  raised at
>>> >> gcc-patches@gcc.gnu.org
>>> >>
>>> >> ~Umesh
>>> >>
>>> >> On Thu, Jul 12, 2018 at 9:33 PM, Szabolcs Nagy 
>>> >> wrote:
>>> >>> On 12/07/18 16:20, Umesh Kalappa wrote:
>>> >>>>
>>> >>>> Hi everyone,
>>> >>>>
>>> >>>> we have our source base ,that was compiled for armv7 on gcc8.1 with
>>> >>>> soft-float and for following input
>>> >>>>
>>> >>>> a=0x0010
>>> >>>> b=0x0001
>>> >>>>
>>> >>>>   result = a - b ;
>>> >>>>
>>> >>>> we are getting the result as "0x000e" and with
>>> >>>> -mhard-float (disabled the flush to zero mode ) we are getting the
>>> >>>> result as ""0x000f" as expected.
>>> >>>>
>>> >>>
>>> >>> please submit it as a bug report to bugzilla
>>> >>>
>>> >>>
>>> >>>> while debugging the soft-float code,we see that ,the compiler calls
>>> >>>> the intrinsic "__aeabi_dsub" with arm calling conventions i.e passing
>>> >>>> "a" in r0 and r1 registers and respectively for "b".
>>> >>>>
>>> >>>> we are investigating the routine "__aeabi_dsub" that comes from
>>> >>>> libgcc
>>> >>>> for incorrect result  and meanwhile we would like to know that
>>> >>>>
>>> >>>> a)do libgcc routines/intrinsic for float operations support or
>>> >>>> consider the subnormal values ? ,if so how we can enable the same.
>>> >>>>
>>> >>>> Thank you
>>> >>>> ~Umesh
>>> >>>>
>>> >>>

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-20 Thread Umesh Kalappa

Thank you all for your comments .

Wilco,
We tried some of the normalisation numbers and the fix works and please
could you help us with the input ,where  if you see that fix breaks down.

Thank you again
~Umesh
On Fri, Jul 20, 2018, 7:07 PM Wilco Dijkstra  wrote:

> Hi Umesh,
>
> Looking at your patch, this would break all results which need to be
> normalized.
>
>
> Index: libgcc/config/arm/ieee754-df.S
> ===
> --- libgcc/config/arm/ieee754-df.S  (revision 262850)
> +++ libgcc/config/arm/ieee754-df.S  (working copy)
> @@ -203,8 +203,11 @@
>  #endif
>
> @ Determine how to normalize the result.
> +   @ if result is denormal i.e (exp)=0,then don't normalise the
> result,
>  LSYM(Lad_p):
> cmp xh, #0x0010
> +   blt LSYM(Lad_e)
> +   cmp xh, #0x0010
> bcc LSYM(Lad_a)
> cmp xh, #0x0020
> bcc LSYM(Lad_e)
>
> It seems Lad_a doesn't correctly handle the case where the result is a
> denormal. For this case
> the result is correct so nothing else needs to be done. This requires an
> explicit test that the
> exponent is zero - other cases still need to be renormalized as usual.
> This code looks overly
> complex so any change will require extensive testing of all the corner
> cases.
>
> Wilco
>

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-23 Thread Umesh Kalappa

Thank you Wilco for the inputs and we agree that the  fix break down
for the case.

Meanwhile ,attached patch will take care the inputs and we are testing
the patch vigorously ,would you recommended any test-suite out there
for the same ?

Thank you
~Umesh


On Fri, Jul 20, 2018 at 10:04 PM, Wilco Dijkstra  wrote:
> Umesh Kalappa wrote:
>
>> We tried some of the normalisation numbers and the fix works and please
>> could you help us with the input ,where  if you see that fix breaks down.
>
> Well try any set of inputs which require normalisation. You'll find these no
> longer get normalised and so will get incorrect results. Try basic cases like
> 1.0 - 0.75 which I think will return 0.625...
>
> A basic test would be to run old vs new on a large set of inputs to verify
> there aren't any obvious differences.
>
> Wilco
>


pr86512.patch
Description: Binary data

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-23 Thread Umesh Kalappa

Hi Richard,

We tested on the SP and yes the problem persist on the SP too and
attached patch will fix the both SP and DP issues for the  denormal
resultant.
We bootstrapped the compiler ,look ok to us with minimal testing ,

Any floating point test-suite to test for the attached patch ? any
recommendations or inputs  ?

Thank you again
~Umesh


On Mon, Jul 23, 2018 at 3:28 PM, Richard Earnshaw (lists)
 wrote:
> So why is this only changing the double-precision implementation?
> Surely, a problem like this will normally be common to both SP and DP
> floating-point computations.
>
> R.
>
> On 23/07/18 08:46, Umesh Kalappa wrote:
>> Thank you Wilco for the inputs and we agree that the  fix break down
>> for the case.
>>
>> Meanwhile ,attached patch will take care the inputs and we are testing
>> the patch vigorously ,would you recommended any test-suite out there
>> for the same ?
>>
>> Thank you
>> ~Umesh
>>
>>
>> On Fri, Jul 20, 2018 at 10:04 PM, Wilco Dijkstra  
>> wrote:
>>> Umesh Kalappa wrote:
>>>
>>>> We tried some of the normalisation numbers and the fix works and please
>>>> could you help us with the input ,where  if you see that fix breaks down.
>>>
>>> Well try any set of inputs which require normalisation. You'll find these no
>>> longer get normalised and so will get incorrect results. Try basic cases 
>>> like
>>> 1.0 - 0.75 which I think will return 0.625...
>>>
>>> A basic test would be to run old vs new on a large set of inputs to verify
>>> there aren't any obvious differences.
>>>
>>> Wilco
>>>
>>>
>>> pr86512.patch
>>>
>>>
>>> Index: libgcc/config/arm/ieee754-df.S
>>> ===
>>> --- libgcc/config/arm/ieee754-df.S   (revision 262850)
>>> +++ libgcc/config/arm/ieee754-df.S   (working copy)
>>> @@ -203,6 +203,7 @@
>>>  #endif
>>>
>>>  @ Determine how to normalize the result.
>>> +@ if result is denormal i.e (exp)=0,then don't normalise the result,
>>>  LSYM(Lad_p):
>>>  cmp xh, #0x0010
>>>  bcc LSYM(Lad_a)
>>> @@ -235,6 +236,8 @@
>>>
>>>  @ Result must be shifted left and exponent adjusted.
>>>  LSYM(Lad_a):
>>> +cmp r4,#0x0
>>> +beq LSYM(Lad_e)
>>>  movsip, ip, lsl #1
>>>  adcsxl, xl, xl
>>>  adc xh, xh, xh
>>> Index: gcc/testsuite/gcc.target/arm/pr86512.c
>>> ===
>>> --- gcc/testsuite/gcc.target/arm/pr86512.c   (nonexistent)
>>> +++ gcc/testsuite/gcc.target/arm/pr86512.c   (working copy)
>>> @@ -0,0 +1,28 @@
>>> +/* { dg-do run } */
>>> +/* { dg-options "-O0 -msoft-float" } */
>>> +
>>> +#include
>>> +#include
>>> +
>>> +typedef union
>>> +{
>>> +double d;
>>> +uint64_t i;
>>> +} u;
>>> +
>>> +int main()
>>> +{
>>> +  u smallestPositiveNormal, smallesPositiveSubnormal, expectedResult, 
>>> result;
>>> +
>>> +  smallesPositiveSubnormal.i = 1;
>>> +
>>> +  smallestPositiveNormal.i = 0x0010;
>>> +  expectedResult.i = 0x000f;
>>> +  result.d = smallestPositiveNormal.d - smallesPositiveSubnormal.d;
>>> +
>>> +  if (result.i != expectedResult.i)
>>> +abort();
>>> +
>>> +  return 0;
>>> +}
>>> +
>


pr86512.patch
Description: Binary data

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-24 Thread Umesh Kalappa

Thank you All for the suggestions  and we tried runing the GCC
testsuite and found that no regression with the fix and also ran the
our regressions base for conformance with no regress.

Is ok for commit with below  Changelog ?
+++ libgcc/ChangeLog(working copy)
@@ -1,3 +1,9 @@
+2018-07-18  Umesh Kalappa 
+
+   PR libgcc/86512
+   * config/arm/ieee754-df.S :Don't normalise the denormal result.
+   * config/arm/ieee754-sf.S:Likewise.
+
+
+++ gcc/testsuite/ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2018-07-18  Umesh Kalappa 
+
+   PR libgcc/86512
+   * gcc.target/arm/pr86512.c :New test.
+

On Mon, Jul 23, 2018 at 5:24 PM, Wilco Dijkstra  wrote:
> Umesh Kalappa wrote:
>
>> We tested on the SP and yes the problem persist on the SP too and
>> attached patch will fix the both SP and DP issues for the  denormal
>> resultant.
>
> The patch now looks correct to me (but I can't approve).
>
>> We bootstrapped the compiler ,look ok to us with minimal testing ,
>>
>> Any floating point test-suite to test for the attached patch ? any
>> recommendations or inputs  ?
>
> Running the GCC regression tests would be required since a bootstrap isn't
> useful for this kind of change. Assuming you use Linux, building and running
> GLIBC with the changed GCC would give additional test coverage as it tests
> all the math library functions.
>
> I don't know of any IEEE conformance testsuites in the GNU world, which is
> why I'm suggesting running some targeted and randomized tests. You could
> use the generic soft-float code in libgcc/soft-fp/adddf3.c to compare the 
> outputs.
>
>
>>>> Index: libgcc/config/arm/ieee754-df.S
>>>> ===
>>>> --- libgcc/config/arm/ieee754-df.S   (revision 262850)
>>>> +++ libgcc/config/arm/ieee754-df.S   (working copy)
>>>> @@ -203,6 +203,7 @@
>>>>  #endif
>>>>
>>>>  @ Determine how to normalize the result.
>>>> +@ if result is denormal i.e (exp)=0,then don't normalise the result,
>
> Use a standard sentence here, eg. like:
>
> If exp is zero and the mantissa unnormalized, return a denormal.
>
> Wilco
>


pr86512.patch
Description: Binary data

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

2018-07-25 Thread Umesh Kalappa

Hi,

Any more suggestions or comments on the patch ?

Thank you
~Umesh

On Tue, Jul 24, 2018, 2:08 PM Umesh Kalappa 
wrote:

> Thank you All for the suggestions  and we tried runing the GCC
> testsuite and found that no regression with the fix and also ran the
> our regressions base for conformance with no regress.
>
> Is ok for commit with below  Changelog ?
> +++ libgcc/ChangeLog(working copy)
> @@ -1,3 +1,9 @@
> +2018-07-18  Umesh Kalappa 
> +
> +   PR libgcc/86512
> +   * config/arm/ieee754-df.S :Don't normalise the denormal result.
> +   * config/arm/ieee754-sf.S:Likewise.
> +
> +
> +++ gcc/testsuite/ChangeLog     (working copy)
> @@ -1,3 +1,8 @@
> +2018-07-18  Umesh Kalappa 
> +
> +   PR libgcc/86512
> +   * gcc.target/arm/pr86512.c :New test.
> +
>
> On Mon, Jul 23, 2018 at 5:24 PM, Wilco Dijkstra 
> wrote:
> > Umesh Kalappa wrote:
> >
> >> We tested on the SP and yes the problem persist on the SP too and
> >> attached patch will fix the both SP and DP issues for the  denormal
> >> resultant.
> >
> > The patch now looks correct to me (but I can't approve).
> >
> >> We bootstrapped the compiler ,look ok to us with minimal testing ,
> >>
> >> Any floating point test-suite to test for the attached patch ? any
> >> recommendations or inputs  ?
> >
> > Running the GCC regression tests would be required since a bootstrap
> isn't
> > useful for this kind of change. Assuming you use Linux, building and
> running
> > GLIBC with the changed GCC would give additional test coverage as it
> tests
> > all the math library functions.
> >
> > I don't know of any IEEE conformance testsuites in the GNU world, which
> is
> > why I'm suggesting running some targeted and randomized tests. You could
> > use the generic soft-float code in libgcc/soft-fp/adddf3.c to compare
> the outputs.
> >
> >
> >>>> Index: libgcc/config/arm/ieee754-df.S
> >>>> ===
> >>>> --- libgcc/config/arm/ieee754-df.S   (revision 262850)
> >>>> +++ libgcc/config/arm/ieee754-df.S   (working copy)
> >>>> @@ -203,6 +203,7 @@
> >>>>  #endif
> >>>>
> >>>>  @ Determine how to normalize the result.
> >>>> +@ if result is denormal i.e (exp)=0,then don't normalise the
> result,
> >
> > Use a standard sentence here, eg. like:
> >
> > If exp is zero and the mantissa unnormalized, return a denormal.
> >
> > Wilco
> >
>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762

2018-12-11 Thread Umesh Kalappa

Hi All,

Please find the attached patch for the subjected issue .

Do please let me know your thoughts and comments on the same .

Thank you
~Umesh


pr84762.patch
Description: Binary data

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762

2018-12-11 Thread Umesh Kalappa

Thank you Jakub for the information.

Will make a note of it.

Umesh



On Tue, Dec 11, 2018, 17:58 Jakub Jelinek  On Tue, Dec 11, 2018 at 05:30:48PM +0530, Umesh Kalappa wrote:
> > Hi All,
> >
> > Please find the attached patch for the subjected issue .
> >
> > Do please let me know your thoughts and comments on the same .
>
> Not a patch review (will defer that to rs6000 maintainers), but
> some comments on gcc-patches patch submissions.
>
> The subject should ideally start with [PATCH] or similar,
> then have some short summary of what the patch is about and if
> it fixes some PR, just PR something/12345 reference,
> the subjects you are posting like:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762
> don't say anything relevant except for the PR 84762 number,
> so anyone reading gcc-patches needs to open that bug in order to even find
> out if it is something for him or somebody else.
>
> If you are sending a patch for an area that has some maintainer(s),
> usually you should either mention those maintainers in To: (and CC:
> gcc-patches) or To: gcc-patches, CC: the maintainers, to draw their
> attention.  See MAINTAINERS file in GCC tree.
>
> The mail body should start with a short explanation of what the problem is
> and how are you solving it, again, so that people don't have to jump to
> bugzilla to find out (of course, short is enough, no need to duplicate
> dozens of comments from the PR), should include information on what
> target(s) it has been bootstrapped/regtested.  And, it is always better if
> it is the patch author that posts it, or is at least CCed so that he can
> answer review questions.
>
> Thanks.
>
> Jakub
>

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762

2018-12-11 Thread Umesh Kalappa

Thank you Segher, will work on your suggestions.

Umesh

On Tue, Dec 11, 2018, 19:23 Segher Boessenkool  Hi Umesh,
>
> On Tue, Dec 11, 2018 at 05:30:48PM +0530, Umesh Kalappa wrote:
> > Please find the attached patch for the subjected issue .
> >
> > Do please let me know your thoughts and comments on the same .
>
> First of all: do you have a copyright assignment with the FSF?
>
> Second: please don't send application/octet-stream attachments.
>
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index ee5f183..d1c0edb 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,14 @@
> +2018-12-06  Lokesh Janghel  
> +
> +PR target/84762
> +* config/rs6000/rs6000.c (rs6000_return_in_msb): Retrun in svr4
> for
> +small struct value.
> +(rs6000_option_override_internal): Modify the condition for aix or
> +svr4.
> +   * config/rs6000/rs6000.opt : Modify the -msvr4-struct-return
> option.
> +   * config/rs6000/rs6000-opts.h : Add enum for svr4 option (Big
> endian
> +   and Little endian).
>
> The changelog should not be part of the patch, but written before it.
> Not as diff, just as the text it is.
>
> Indent is one tab.  Not a tab and a space, not nine spaces.
>
> There shouldn't be trailing spaces.
>
> There should not be a space before a colon.
>
> "Modify XYZ." means that you should have "(XYZ): Modify." instead; but
> you probably can say more than just "Modify", too.  Like, _what_ have you
> changed about it :-)
>
> s/retrun/return/
>
> The changelog should mention everything you change.  I haven't checked
> if it does here, but all the testcases are missing (those have their own
> changelog, in gcc/testsuite/ChangeLog).
>
> +/* Return small structs in register,
> +   gnu: LSB-aligned,
> +   standard: MSB-aligned*/
>
> This should end with dot space space */
>
> +enum rs6000_svr4_struct_return {
> +  SVR4_STRUCT_RETURN_GNU=1,
> +  SVR4_STRUCT_RETURN_STD
> +};
>
> I think a simple boolean would be easier?
>
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 2765263..4751b61 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -4632,7 +4632,8 @@ rs6000_option_override_internal (bool global_init_p)
>/* Set aix_struct_return last, after the ABI is determined.
>  If -maix-struct-return or -msvr4-struct-return was explicitly
>  used, don't override with the ABI default.  */
> -  if (!global_options_set.x_aix_struct_return)
> +  if (!global_options_set.x_aix_struct_return
> +  && !rs6000_current_svr4_struct_return)
> aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
>
> Why this change?
>
>  static bool
>  rs6000_return_in_msb (const_tree valtype)
>  {
> -  return (DEFAULT_ABI == ABI_ELFv2
> - && BYTES_BIG_ENDIAN
> +  return ((DEFAULT_ABI == ABI_ELFv2
> +  || (DEFAULT_ABI == ABI_V4
> +  && rs6000_current_svr4_struct_return == SVR4_STRUCT_RETURN_STD))
> + && BYTES_BIG_ENDIAN
>   && AGGREGATE_TYPE_P (valtype)
>   && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
>   == PAD_UPWARD));
>
> Indents are with tabs, not eight spaces.  There never should be tabs
> after spaces though.
>
> Please write this as
>
>   if (DEFAULT_ABI == ABI_ELFv2
>   && BYTES_BIG_ENDIAN
>   && AGGREGATE_TYPE_P (valtype)
>   && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
>   == PAD_UPWARD))
> return true;
>
>   if (DEFAULT_ABI == ABI_V4
>   && rs6000_current_svr4_struct_return == SVR4_STRUCT_RETURN_STD
>   && BYTES_BIG_ENDIAN
>   && AGGREGATE_TYPE_P (valtype)
>   && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
>   == PAD_UPWARD))
> return true;
>
>   return false;
>
> But, on the other hand, you should do this in rs6000_function_arg_padding
> instead I think.
>
> -msvr4-struct-return
> -Target Report RejectNegative Var(aix_struct_return,0) Save
> -Return small structures in registers (SVR4 default).
> +msvr4-struct-return=
> +Target RejectNegative Joined Enum(rs6000_svr4_struct_return)
> Var(rs6000_current_svr4_struct_return)
> +-msvr4-struct-return=[standard,gnu] Return small structures in registers
> (SVR4 default).
> +
> +Enum
> +Name(rs6000_svr4_struct_return) Type(enum rs6000_svr4_struct_return)
> +
> +EnumValue
> +Enum(rs6000_svr4_struct_return) String(standar

Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

2018-11-12 Thread Umesh Kalappa

Hi All,

the following patch fix the subjected issue

Index: gcc/cp/parser.c
===
--- gcc/cp/parser.c (revision 266026)
+++ gcc/cp/parser.c (working copy)
@@ -24615,6 +24615,8 @@
 {
   tree expr;
   cp_lexer_consume_token (parser->lexer);
+
+  inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);

   if (cp_lexer_peek_token (parser->lexer)->type == CPP_OPEN_PAREN)
{


ok to commit along the testcase with changelog update ?

Thank you
~Umesh

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

2018-11-14 Thread Umesh Kalappa

Thank you Jason and Marek for the suggestions .

Attached patch(pr86512.patch)  along the Changelog .

and also please note tested the patch for x86_64 only with "make -k
check-gcc RUNTESTFLAGS=dg.exp=g++.dg" and see no regressions.

We are runing the make check-gcc(x86_64) and will let know for any regressions .

Meanwhile ,Please let us know your thoughts on the patch.

Thank you
~Umesh

On Wed, Nov 14, 2018 at 2:55 AM Jason Merrill  wrote:
>
> On Tue, Nov 13, 2018 at 10:40 AM Marek Polacek  wrote:
> > On Tue, Nov 13, 2018 at 11:49:55AM +0530, Umesh Kalappa wrote:
> > > Hi All,
> > >
> > > the following patch fix the subjected issue
> > >
> > > Index: gcc/cp/parser.c
> > > ===
> > > --- gcc/cp/parser.c (revision 266026)
> > > +++ gcc/cp/parser.c (working copy)
> > > @@ -24615,6 +24615,8 @@
> > >  {
> > >tree expr;
> > >cp_lexer_consume_token (parser->lexer);
> > > +
> > > +  inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
> > >
> > >if (cp_lexer_peek_token (parser->lexer)->type == CPP_OPEN_PAREN)
> > > {
> > >
> > >
> > > ok to commit along the testcase with changelog update ?
> >
> > Thanks for the patch.
> >
> > Please also include the testcase along with the patch (and I think it should
> > also test noexcept in a template).  Please also include a ChangeLog entry
> > in the patch submission.
> >
> > Can you describe how this patch has been tested?
> >
> > Further, wouldn't it be better to call inject_this_parameter inside the
> > CPP_OPEN_PAREN block?  If noexcept doesn't have any expression, then it
> > can't refer to "this".
>
> Agreed, thanks.  You also need to restore the old
> current_class_{ptr,ref} at the end of the noexcept-specifier.
>
> Jason


pr86512.patch
Description: Binary data

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

2018-11-14 Thread Umesh Kalappa

>>We are runing the make check-gcc(x86_64) and will let know for any 
>>regressions .
No regress found .

~Umesh
On Wed, Nov 14, 2018 at 5:18 PM Umesh Kalappa  wrote:
>
> Thank you Jason and Marek for the suggestions .
>
> Attached patch(pr86512.patch)  along the Changelog .
>
> and also please note tested the patch for x86_64 only with "make -k
> check-gcc RUNTESTFLAGS=dg.exp=g++.dg" and see no regressions.
>
> We are runing the make check-gcc(x86_64) and will let know for any 
> regressions .
>
> Meanwhile ,Please let us know your thoughts on the patch.
>
> Thank you
> ~Umesh
>
> On Wed, Nov 14, 2018 at 2:55 AM Jason Merrill  wrote:
> >
> > On Tue, Nov 13, 2018 at 10:40 AM Marek Polacek  wrote:
> > > On Tue, Nov 13, 2018 at 11:49:55AM +0530, Umesh Kalappa wrote:
> > > > Hi All,
> > > >
> > > > the following patch fix the subjected issue
> > > >
> > > > Index: gcc/cp/parser.c
> > > > ===
> > > > --- gcc/cp/parser.c (revision 266026)
> > > > +++ gcc/cp/parser.c (working copy)
> > > > @@ -24615,6 +24615,8 @@
> > > >  {
> > > >tree expr;
> > > >cp_lexer_consume_token (parser->lexer);
> > > > +
> > > > +  inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
> > > >
> > > >if (cp_lexer_peek_token (parser->lexer)->type == CPP_OPEN_PAREN)
> > > > {
> > > >
> > > >
> > > > ok to commit along the testcase with changelog update ?
> > >
> > > Thanks for the patch.
> > >
> > > Please also include the testcase along with the patch (and I think it 
> > > should
> > > also test noexcept in a template).  Please also include a ChangeLog entry
> > > in the patch submission.
> > >
> > > Can you describe how this patch has been tested?
> > >
> > > Further, wouldn't it be better to call inject_this_parameter inside the
> > > CPP_OPEN_PAREN block?  If noexcept doesn't have any expression, then it
> > > can't refer to "this".
> >
> > Agreed, thanks.  You also need to restore the old
> > current_class_{ptr,ref} at the end of the noexcept-specifier.
> >
> > Jason

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

2018-11-14 Thread Umesh Kalappa

My bad Marek and thank you for pointing that out.

Please find the attached correct one (pr52869.patch) .

~Umesh


pr52869.patch
Description: Binary data

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

2018-11-15 Thread Umesh Kalappa

Thank you Marek  for the inputs .
>>In the future, if using diff, please also use the -p option.
We are using svn diif  and other comments are addressed .

please let us know  your take on the  revised attached patch .

Thank you
~Umesh
On Thu, Nov 15, 2018 at 12:23 AM Marek Polacek  wrote:
>
> On Wed, Nov 14, 2018 at 09:55:39PM +0530, Umesh Kalappa wrote:
> > My bad Marek and thank you for pointing that out.
> >
> > Please find the attached correct one (pr52869.patch) .
>
> Index: gcc/cp/ChangeLog
> ===
> --- gcc/cp/ChangeLog(revision 266026)
> +++ gcc/cp/ChangeLog(working copy)
> @@ -1,3 +1,9 @@
> +2018-11-14  Kamlesh Kumar  
> +
> +   PR c++/52869
> +   *parser.c () :  restore the old current_class_{ptr,ref} by
> +   inject_this_parameter().
> +
>
> So the correct CL entry would look like
>
> 2018-11-14  Kamlesh Kumar  
>
> DR 1207
> PR c++/52869
> * parser.c (cp_parser_noexcept_specification_opt): Call
> inject_this_parameter.
>
> or so.
>
> Index: gcc/cp/parser.c
> ===
> --- gcc/cp/parser.c (revision 266026)
> +++ gcc/cp/parser.c (working copy)
> @@ -24615,11 +24615,24 @@
>  {
>tree expr;
>cp_lexer_consume_token (parser->lexer);
> -
> +
>
> You're adding whitespaces where they shouldn't be.  Let's avoid changes like 
> these.
>
>if (cp_lexer_peek_token (parser->lexer)->type == CPP_OPEN_PAREN)
> {
>   matching_parens parens;
>   parens.consume_open (parser);
> +
> + if (current_class_type)
> +  inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
> +  else
> +{
> +  /*clear the current_class_ptr for non class type , like
> +   int foo() noexcept(*this)
> +   {
> + return 1;
> +   }
> + */
> +current_class_ptr = NULL_TREE;
> +}
>
> I don't believe that's what Jason meant by restoring; I think you want
>
>   tree save_ccp = current_class_ptr;
>   tree save_ccr = current_class_ref;
>
>   inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
>
>   [...]
>
>   current_class_ptr = save_ccp;
>   current_class_ref = save_ccr;
>
> In the future, if using diff, please also use the -p option.
>
> Index: gcc/testsuite/ChangeLog
> ===
> --- gcc/testsuite/ChangeLog (revision 266026)
> +++ gcc/testsuite/ChangeLog (working copy)
> @@ -1,3 +1,8 @@
> +2018-11-14  Kamlesh Kumar  
> +
> +   PR g++.dg/52869
> +   * g++.dg/pr52869.C: New.
>
> Should be "PR c++/52869".
>
> Index: gcc/testsuite/g++.dg/pr52869.C
> ===
> --- gcc/testsuite/g++.dg/pr52869.C  (nonexistent)
> +++ gcc/testsuite/g++.dg/pr52869.C  (working copy)
>
> Maybe move the test to testsuite/g++.dg/DRs?
>
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -g" } */
>
> Why these options?  I don't think you need -g.
>
> +struct S {
> +void f() { }
> +void g() noexcept(noexcept(f())) { }
> +void h() noexcept(noexcept(this->f())) { }
> +};
> +
> +struct Nyan {
> +   constexpr Nyan &operator++() noexcept { return *this; }
> +   constexpr void omg() noexcept(noexcept(++*this)) {}
> +};
>
> I was hoping you'd add also a test with 'this' in noexcept in a class 
> template.
>
> This test doesn't compile on all dialects:
> FAIL: g++.dg/pr52869.C  -std=gnu++98 (test for excess errors)
> FAIL: g++.dg/pr52869.C  -std=gnu++11 (test for excess errors)
>
> You can run just the new test in all dialects using:
> GXX_TESTSUITE_STDS=98,11,14,17,2a make check-c++ RUNTESTFLAGS=dg.exp=pr52869.C
>
> The noexcept specifier is only in C++11 and newer I think.
>
> +template< typename T >
> +T sine( T const& a, T const& b ) noexcept
> +{
> +static_assert( noexcept( T(a / sqrt(a * a  + b * b)) ), "throwing expr" 
> );
> +return a / sqrt(a * a  + b * b);
> +}
> +
> +int foo() noexcept
> +{
> +  return 1;
> +}
> +
>
> I don't understand what this part of the test is testing.  It compiles even
> without the patch.  Let's drop it.
>
> Marek


pr52869.patch
Description: Binary data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

2018-11-15 Thread Umesh Kalappa

Hi All,

The attached patch (pr85667.patch) fixes the subjected issue .
we tested on x86_64(linux and windows both) and no regress found .

ok to commit ?

Thank you
~Umesh


pr85667.patch
Description: Binary data

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85667

2018-11-15 Thread Umesh Kalappa

Edited the subjected for the proper PR no.
~Umesh

On Thu, Nov 15, 2018 at 2:32 PM Umesh Kalappa  wrote:
>
> Hi All,
>
> The attached patch (pr85667.patch) fixes the subjected issue .
> we tested on x86_64(linux and windows both) and no regress found .
>
> ok to commit ?
>
> Thank you
> ~Umesh

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

2018-11-15 Thread Umesh Kalappa

Thank you Marek,Appreciate your valuable feedback on the patch .

Attached the latest ,please do let us know your thoughts.

~Umesh

On Thu, Nov 15, 2018 at 9:26 PM Marek Polacek  wrote:
>
> On Thu, Nov 15, 2018 at 02:26:24PM +0530, Umesh Kalappa wrote:
> > Thank you Marek  for the inputs .
> > >>In the future, if using diff, please also use the -p option.
> > We are using svn diif  and other comments are addressed .
>
> Thanks, but it doesn't seem like the -p option was used.
>
> > please let us know  your take on the  revised attached patch .
>
>
> Index: cp/ChangeLog
> ===
> --- cp/ChangeLog(revision 266026)
> +++ cp/ChangeLog(working copy)
> @@ -1,3 +1,9 @@
> +2018-11-14  Kamlesh Kumar  
> +
> +   PR c++/52869
> +   *parser.c () :  restore the old current_class_{ptr,ref} by
> +   inject_this_parameter().
> +
>
> This is still the same; can you adjust it according to my last suggestion?
>
> Index: cp/parser.c
> ===
> --- cp/parser.c (revision 266026)
> +++ cp/parser.c (working copy)
> @@ -24620,6 +24620,12 @@
> {
>   matching_parens parens;
>   parens.consume_open (parser);
> +
> + tree save_ccp = current_class_ptr;
> + tree save_ccr = current_class_ref;
> +
>
> Watch out for trailing whitespace in the blank lines.
>
> + if (current_class_type)
> +  inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
>
> I think you can remove the if here.
>
>   if (require_constexpr)
> {
> @@ -24640,6 +24646,9 @@
> }
>
>   parens.require_close (parser);
> +
> + save_ccp = current_class_ptr = save_ccp;
> + save_ccr = current_class_ref = save_ccr;
>
> You don't need to set save_cc[pr] to itself here.
>
> Index: testsuite/ChangeLog
> ===
> --- testsuite/ChangeLog (revision 266026)
> +++ testsuite/ChangeLog (working copy)
> @@ -1,3 +1,8 @@
> +2018-11-14  Kamlesh Kumar  
> +
> +   PR c++/52869
> +   * g++.dg//DRs/dr52869.C: New.
> +
>
> So DR != PR.  Please name the test dr1207.C
>
> Index: testsuite/g++.dg/DRs/dr52869.C
> ===
> --- testsuite/g++.dg/DRs/dr52869.C  (nonexistent)
> +++ testsuite/g++.dg/DRs/dr52869.C  (working copy)
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -std=c++11" } */
>
> Instead of this, do:
>
> // { dg-do compile { target c++11 } }
>
> Also, I wrote a test that fails if current_class_{ptr,ref} aren't properly
> restored:
>
> // DR 1207
> // PR c++/52869
> // { dg-do compile { target c++11 } }
>
> void
> fn ()
> {
>   struct S {
> bool operator!() noexcept(false);
>   } s;
>   S t = s;
> }
>
> So you can add that one too, e.g. testsuite/g++.dg/DRs/dr1207-2.C.
>
> Thanks,
> Marek


pr52869.patch
Description: Binary data

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

2018-11-16 Thread Umesh Kalappa

Thank you Richard,

Made the required changes ,ok to commit ?

Thank you
~Umesh
On Thu, Nov 15, 2018 at 4:02 PM Richard Biener
 wrote:
>
> On Thu, Nov 15, 2018 at 10:02 AM Umesh Kalappa  
> wrote:
> >
> > Hi All,
> >
> > The attached patch (pr85667.patch) fixes the subjected issue .
> > we tested on x86_64(linux and windows both) and no regress found .
> >
> > ok to commit ?
>
> I wonder if you can turn the testcase into a dg-run one, making the
> functions noinline/noipa and check the correct values are returned.
>
> Richard.
>
> > Thank you
> > ~Umesh

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

2018-11-16 Thread Umesh Kalappa

My bad ,
attached the same now .

~Umesh
On Fri, Nov 16, 2018 at 2:38 PM Richard Biener
 wrote:
>
> On Fri, Nov 16, 2018 at 9:07 AM Umesh Kalappa  
> wrote:
> >
> > Thank you Richard,
> >
> > Made the required changes ,ok to commit ?
>
> Can you attach the adjusted patch?
>
> Thanks,
> Richard.
>
> > Thank you
> > ~Umesh
> > On Thu, Nov 15, 2018 at 4:02 PM Richard Biener
> >  wrote:
> > >
> > > On Thu, Nov 15, 2018 at 10:02 AM Umesh Kalappa  
> > > wrote:
> > > >
> > > > Hi All,
> > > >
> > > > The attached patch (pr85667.patch) fixes the subjected issue .
> > > > we tested on x86_64(linux and windows both) and no regress found .
> > > >
> > > > ok to commit ?
> > >
> > > I wonder if you can turn the testcase into a dg-run one, making the
> > > functions noinline/noipa and check the correct values are returned.
> > >
> > > Richard.
> > >
> > > > Thank you
> > > > ~Umesh


pr85667.patch
Description: Binary data

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

2018-11-19 Thread Umesh Kalappa

Hi Jakub ,

the attached patch is good to commit ?

Thank you
~Umesh
On Mon, Nov 19, 2018 at 4:00 PM Lokesh Janghel
 wrote:
>
> Thank you Jakub, I update the patch with your comments and tested it.
> Please let me know your thoughts/suggestions.
>
>
> Thanks
> Lokesh
>
> On Fri, Nov 16, 2018 at 4:57 PM Jakub Jelinek  wrote:
>>
>> On Fri, Nov 16, 2018 at 04:21:25PM +0530, Umesh Kalappa wrote:
>> > My bad ,
>> > attached the same now .
>>
>> +2018-11-15  Lokesh Janghel 
>>
>> Two spaces before < instead of just one.
>> +
>> +   PR  target/85667
>>
>> Only a single space between PR and target.
>>
>> +   * i386.c (function_value_ms_64): ms_abi insist to use the eax
>>
>> The filename is relative to the directory with ChangeLog file, so
>> * config/i386/i386.c
>> in this case.  The description should say what you've changed, so
>> something like:
>> * config/i386/i386.c (function_value_ms_64): Return AX_REG instead
>> of FIRST_SSE_REG for 4 or 8 byte modes.
>>
>> --- a/gcc/config/i386/i386.c
>> +++ b/gcc/config/i386/i386.c
>> @@ -9008,7 +9008,7 @@ function_value_ms_64 (machine_mode orig_mode, 
>> machine_mode mode,
>> case 8:
>> case 4:
>>   if (mode == SFmode || mode == DFmode)
>> -   regno = FIRST_SSE_REG;
>> +   regno = AX_REG;
>>   break;
>>
>> Is there something to back that up, say godbolt.org link with some testcases
>> showing how does MSVC, clang etc. handle those?
>> And, because the function starts with:
>>   unsigned int regno = AX_REG;
>> the change isn't right, you should remove all of:
>> case 8:
>> case 4:
>>   if (mode == SFmode || mode == DFmode)
>> regno = FIRST_SSE_REG;
>>   break;
>> because the default will do what you want.
>>
>> diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
>> index 50e53f0..ec54330 100644
>> --- a/gcc/testsuite/ChangeLog
>> +++ b/gcc/testsuite/ChangeLog
>> @@ -1,3 +1,8 @@
>> +2018-11-15 Lokesh Janghel  
>>
>> Two spaces between date and name.
>>
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/pr85667.c
>> @@ -0,0 +1,29 @@
>> +/* { dg-options "-O2 " } */
>> +/* { dg-final { scan-assembler-times "movl\[\t 
>> \]\.\[a-zA-Z\]\[a-zA-Z\]\[0-9\]\\(%rip\\), %eax" 1} } */
>>
>> First of all, the test is misplaced, it is clearly x86_64 specific
>> and probably lp64 only, so it shouldn't be in gcc.dg/ where it will
>> be run on all targets, but in gcc.target/i386/ and be guarded with
>> { target lp64 }.
>>
>> Second, seems like you'd like to run the testcase, so you'd better have it
>> /* { dg-do run { target lp64 } } */
>>
>> The assembler scanning will work only with -masm=att, not -masm=intel
>> and seems to be very fragile, so I'd suggest have one runtime test and one
>> compile time test in which you put just the fn1 function.  Why two arbitrary
>> letters after dot?  That makes on sense.  Either you are looking for 
>> .LC\[0-9]*
>> specifically, or for arbitrary symbol, then use something like
>> "movl\[^\n\r]*, %eax"
>> or so (and make sure to use -masm=intel).
>>
>> More interesting would be
>> make check ALT_CC_UNDER_TEST=msvc ALT_CXX_UNDER_TEST=msvc++ 
>> RUNTESTFLAGS='compat.exp struct-layout-1.exp'
>> (or whatever MSVC driver names are), i.e. try to run the compat testsuites
>> between MSVC and newly built gcc.
>>
>> Jakub
>
>
>
> --
> Thanks & Regards
> Lokesh Janghel
> +91-9752984749

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

2018-11-21 Thread Umesh Kalappa

Thank you for the inputs and please find the attachment for the update patch.

Do please let us know your comments on the same

~Umesh
On Tue, Nov 20, 2018 at 3:03 PM Jakub Jelinek  wrote:
>
> On Mon, Nov 19, 2018 at 04:08:29PM +0530, Lokesh Janghel wrote:
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 8ca2e73..b55dfa9 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,8 @@
> +2018-11-19 Lokesh Janghel 
>
> Two spaces between date and name and name and <, i.e.
> 2018-11-20  Lokesh Janghel  
> in both ChangeLog files.
>
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr85667-2.c
> @@ -0,0 +1,15 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O2 -masm=intel" } */
> +/* { dg-require-effective-target lp64 } */
> +/* { dg-require-effective-target masm_intel } */
> +/* { dg-final { scan-assembler-times "movl\[^\n\r]*, %eax" 1} } */
> +typedef struct
> +{
> +  float x;
> +} Float;
> +Float __attribute__((ms_abi)) fn1 ()
> +{
> +  Float v;
> +  v.x = 3.145;
> +  return v;
> +}
>
> This test wasn't properly tested:
>
> /usr/src/gcc/obj/gcc/xgcc -B/usr/src/gcc/obj/gcc/ -m64
-fno-diagnostics-show-caret -fno-diagnostics-show-line-numbers
-fdiagnostics-color=never -O2 -masm=intel -ffat-lto-objects -fno-ident
-c -o pr85667-2.o
/usr/src/gcc/gcc/testsuite/gcc.target/i386/pr85667-2.c
> PASS: gcc.target/i386/pr85667-2.c (test for excess errors)
> gcc.target/i386/pr85667-2.c: output file does not exist
> UNRESOLVED: gcc.target/i386/pr85667-2.c scan-assembler-times
movl[^\n\r]*, %eax 1
> testcase /usr/src/gcc/gcc/testsuite/gcc.target/i386/i386.exp
completed in 1 seconds
>
> 1) you do not want to use dg-do assemble, but dg-do compile, because only
>in that case (or when using -save-temps) assembly is produced
> 2) you do not want to use -masm=intel and then expect AT&T
syntax in the
>regexp
>
> Thus, I'd replace all the dg- directive lines with:
> /* { dg-do compile { target lp64 } } */
> /* { dg-options "-O2" } */
> /* { dg-final { scan-assembler-times "movl\[^\n\r]*, %eax|mov\[
\t]*eax," 1 } } */
>
> That way, it will work both with -masm=att (explicit or implicit) or
> -masm=intel.
>
> One can use
>
> make check-gcc
RUNTESTFLAGS='--target_board=unix\{-m32,-m64,-m64/-masm=intel\}
i386.exp=pr85667*'
>
> to verify and then look at the log file.
>
> Furthermore, I'd copy pr85667-1.c test to pr85667-3.c and the modified
> pr85667-2.c to pr85667-4.c, change Float to Double, float to double, remove
> f suffixes and adjust all the eax in the regexp to rax, so that you also
> test the struct with DFmode case.
>
> Jakub


85667.patch
Description: Binary data

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

2018-11-21 Thread Umesh Kalappa

Hi Jakub and All,

We don't have the commit access ,can  someone please commit for us ?

~Umesh

On Wed, Nov 21, 2018, 18:37 Jakub Jelinek  On Wed, Nov 21, 2018 at 06:06:41PM +0530, Umesh Kalappa wrote:
> > Thank you for the inputs and please find the attachment for the update
> patch.
>
> LGTM.
>
> Jakub
>

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54589

2018-11-29 Thread Umesh Kalappa

Hi All,

We are able to fix the subjected issue  with the  peephole patterns
(target specific) in the md file (attached the patch pr54589.patch).
While testing the fix ,we end up with some of the C constructs like

Testcase 1:
#include 
struct param {
int a, b, c, d;
__m128i array[256];
};
void func(struct param p, unsigned char *src, int *dst)
{
__m128i x = p.array[*src];
*dst = _mm_cvtsi128_si32(x);
}

compiles with -O2 for  x86-64 and asm looks like
func:
movzbl  (%rdi), %eax
addq$1, %rax
salq$4, %rax
movl8(%rsp,%rax), %eax
movl%eax, (%rsi)
ret

Testcase 2:
  #include 
  struct param {
int a, b, c, d;
__m128i array[256];
  };

struct param *p1;

void func(unsigned char *src, int *dst)
{
__m128i x = p1->array[*src];
*dst = _mm_cvtsi128_si32(x);
}

compiles with -O2 on x86-64 :
func:
movzbl  (%rdi), %eax
addq$1, %rax
salq$4, %rax
addqp1(%rip), %rax
movl(%rax), %eax
movl%eax, (%rsi)
ret

So, we are thinking to extend our fix with few more peephole patterns
in the md file.

OR it’s better to handle all C constructs in combiner/fwprop pass
,please let us know your suggestions or comments on this ,that guides
us in the right direction.

Thank you
~Umesh

On Fri, Nov 23, 2018 at 3:56 PM Umesh Kalappa  wrote:
>
> Hi Richard,
>
> for the subjected issue , we found few suggestions to handle the issue like
>
>  1. be more conservative(target specific) and defining the peephole in
> the md file to handle the patterns like add,shl and movl to "shlq and
> movl"
>  2. like you mentioned  in fwprop/combiner .
>
> we would like to know your inputs /suggestions before we go ahead with
> the patch.
>
> Thank you
> ~Umesh


pr54589.patch
Description: Binary data

Re: [Patch]Bug 89057 - [8/9/10 Regression] AArch64 ld3 st4 less optimized

2019-04-29 Thread Umesh Kalappa

>>Before getting started with reviewing the patch , the first question
is whether you have a copyright assignment on file or does your
employer have one on record with the FSF ?

Ramana, We asked for copyright assignment form ,with details asked by
copyright-cl...@fsf.org(craig)
@ ass...@gnu.org.

Waiting for the reply .
~Umesh

On Mon, Apr 29, 2019 at 2:55 PM Ramana Radhakrishnan
 wrote:
>
> On Mon, Apr 29, 2019 at 8:44 AM Jaydeep Chauhan
>  wrote:
> >
> > Hi All,
> >
> > The attached patch (89057.patch) fixes the subjected issue.
> > Please let me know your thoughts on the patch.
>
> Thanks for your patch.
>
> Before getting started with reviewing the patch , the first question
> is whether you have a copyright assignment on file or does your
> employer have one on record with the FSF ?
>
> Further could you elaborate more on what you have done to fix this by
> providing some description other than "fix the subjected issue" and
> why you have chosen the approach that you have. Finally one of the
> things required for any patch to be considered is a full test run. Can
> you tell us how you tested this patch ?
>
>
> Ramana
>
>
>
> >
> > Thanks,
> > Jaydeep.

RE: [EXTERNAL]Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.

2025-04-11 Thread Umesh Kalappa

Thank you @Kito Cheng for early suggestions ,we will break down the patch like 
suggested and address the below comments .

~U

-Original Message-
From: Kito Cheng  
Sent: 11 April 2025 12:37
To: Umesh Kalappa 
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Jesse Huang 
; pal...@dabbelt.com; and...@sifive.com; j...@sifive.com
Subject: [EXTERNAL]Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.

[You don't often get email from kito.ch...@gmail.com. Learn why this is 
important at https://aka.ms/LearnAboutSenderIdentification ]

Could you break this patch into two pieces:
1) Add new extensions.
2) Add new core (for -mcpu), pipeline model and cost model


> diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 
> 1326c67563a..d2642390b2a 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,24 @@
> +2025-04-09  Umesh Kalappa  
> +
> +P8700 is a high-performance processor from MIPS by extending RISCV
> +with the MIPS custom instructions.
> +The following changes enable P8700 processor for RISCV and
> +added MIPS specific insns.

GCC does not require editing the changelog directly, put that on the git commit 
log instead, and then there is a script that will update that automatically.

> index b34409adf39..c8467016c87 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -442,6 +442,11 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"xsfvqmaccdod",ISA_SPEC_CLASS_NONE, 1, 0},
>{"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"xmipscbop", ISA_SPEC_CLASS_NONE, 1, 0},  {"xmipscmov", 
> + ISA_SPEC_CLASS_NONE, 1, 0},  {"xmipsexectl", ISA_SPEC_CLASS_NONE, 1, 
> + 0},  {"xmipslsp", ISA_SPEC_CLASS_NONE, 1, 0},

one extension one line

> diff --git a/gcc/config/riscv/mips-insn.md 
> b/gcc/config/riscv/mips-insn.md new file mode 100644 index 
> 000..0c92a9d9e94
> --- /dev/null
> +++ b/gcc/config/riscv/mips-insn.md
> @@ -0,0 +1,37 @@
> +;; Machine description for MIPS custom instructioins.

s/instructioins/instructions/

> +;; Copyright (C) 2021-2025 Free Software Foundation, Inc.

2025 rather than 2021-2025

> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify ;; it 
> +under the terms of the GNU General Public License as published by ;; 
> +the Free Software Foundation; either version 3, or (at your option) 
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful, ;; but 
> +WITHOUT ANY WARRANTY; without even the implied warranty of ;; 
> +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;; GNU 
> +General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License 
> +;; along with GCC; see the file COPYING3.  If not see ;; 
> +<http://www.gnu.org/licenses/>.
> +
> +(define_insn "*movcc_bitmanip"

^^ the pattern name starting with * does not really matter to GCC itself, but 
it is useful when debugging, so maybe rename that to 
"*movcc_xmipscomv"?

> diff --git a/gcc/config/riscv/mips-p8700.md 
> b/gcc/config/riscv/mips-p8700.md new file mode 100644 index 
> 000..7cf50381cab
> --- /dev/null
> +++ b/gcc/config/riscv/mips-p8700.md
> @@ -0,0 +1,139 @@
> +;; DFA-based pipeline description for MIPS P8700.
> +;;
> +;; Copyright (C) 2018-2025 Free Software Foundation, Inc.

2025 rather than 2021-2025

> diff --git a/gcc/config/riscv/riscv-cores.def 
> b/gcc/config/riscv/riscv-cores.def
> index 2918496bcd0..73df04148fa 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -44,6 +44,7 @@ RISCV_TUNE("thead-c906", generic, 
> thead_c906_tune_info)  RISCV_TUNE("xiangshan-nanhu", xiangshan, 
> xiangshan_nanhu_tune_info)  RISCV_TUNE("generic-ooo", generic_ooo, 
> generic_ooo_tune_info)  RISCV_TUNE("size", generic, 
> optimize_size_tune_info)
> +RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)
>
>  #undef RISCV_TUNE
>
> diff --git a/gcc/config/riscv/riscv-opts.h 
> b/gcc/config/riscv/riscv-opts.h index 26fe228e0f8..3ae284b0d95 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -58,7 +58,8 @@ enum riscv_microarchitecture_type {
>sifive_p400,
>sifive_p600,
>xiangshan,
> -  generic_ooo
> +  generic_ooo,
> +  mips_p8700,
>  };
>  extern enum riscv_microarchitecture_type riscv_microarchitecture;
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc 
> index 38f3ae7cd84..a8325ece2e9 100644
> --- a/

[PATCH]RISCV :Added MIPS P8700 Subtarget

2025-04-11 Thread Umesh Kalappa

This is the first patch from the two-patch series, where configured gcc for 
P8700 micro architecture  in the first patch and 
Tested with dejagnu riscv.exp tests for --mtune=mips-p8700.
 
P8700 is a high-performance processor from MIPS by extending RISCV. The 
following changes enable P8700 processor for RISCV.

 * config/riscv/riscv-cores.def(RISCV_TUNE):Added mips-p8700 tune.
 * config/riscv/riscv-opts.h(riscv_microarchitecture_type):Likewise
 * config/riscv/riscv.cc(riscv_tune_param):Added insns costs p8700 tune.
 * config/riscv/riscv.md:Added p8700 tune for insn attribute.
 * config/riscv/mips-p8700.md:New File for mips-p8700 pipeline
   description
---
 gcc/config/riscv/mips-p8700.md   | 139 +++
 gcc/config/riscv/riscv-cores.def |   1 +
 gcc/config/riscv/riscv-opts.h|   3 +-
 gcc/config/riscv/riscv.cc|  22 +
 gcc/config/riscv/riscv.md|   3 +-
 5 files changed, 166 insertions(+), 2 deletions(-)  create mode 100644 
gcc/config/riscv/mips-p8700.md

diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md 
new file mode 100644 index 000..11d0b1ca793
--- /dev/null
+++ b/gcc/config/riscv/mips-p8700.md
@@ -0,0 +1,139 @@
+;; DFA-based pipeline description for MIPS P8700.
+;;
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it ;; 
+under the terms of the GNU General Public License as published ;; by 
+the Free Software Foundation; either version 3, or (at your ;; option) 
+any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public ;; 
+License for more details.
+
+;; You should have received a copy of the GNU General Public License ;; 
+along with GCC; see the file COPYING3.  If not see ;; 
+.
+
+(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe, 
+mips_p8700_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes 
+(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, 
mips_p8700_lsu"
+"mips_p8700_agen_alq_pipe")
+
+(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" 
+"mips_p8700_mdu_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe (define_cpu_unit 
+"mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes 
+(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long" 
+"mips_p8700_fpu_pipe")
+
+;; Long FPU pipeline.
+(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
+
+(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq, 
+mips_p8700_al2") (define_reservation "mips_p8700_agq_ctistd" 
+"mips_p8700_agq, mips_p8700_ctistd") (define_reservation 
+"mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu") 
+(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq, 
+mips_p8700_alu")
+
+;;
+;; FPU pipe
+;;
+
+(define_insn_reservation "mips_p8700_fpu_fadd" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fabs" 2
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcmp,fmove"))
+  "mips_p8700_fpu_short, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fload" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpload"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fstore" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpstore"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmadd" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmul" 5
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmul"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_div" 17
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fdiv,fsqrt"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu*17")
+
+(define_insn_reservation "mips_p8700_fpu_fcvt" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmtc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mtc"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmfc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mfc"))
+  "mips_p8700_agq_lsu")
+
+;;
+;; Integer pipe
+;;
+
+(define_insn_reservation "mips_p8700_int_load" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "load"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_

RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

2025-04-21 Thread Umesh Kalappa

Thank you @Jeff Law for the suggestions and 

>> Just quickly scanning the insn reservations, I suspect you're missing many 
>> cases and the compiler will trip assertion failures if you are missing cases.
Sure  will look at it .

>> You might want to look at these values more closely.  If you have questions 
>> about how the compiler uses them to make decisions, just ask
Sure ,and lets us tune the same and reach out here for future questions .

~U

-Original Message-
From: Jeff Law  
Sent: 18 April 2025 22:42
To: Umesh Kalappa ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; Jesse Huang ; 
pal...@dabbelt.com; and...@sifive.com
Subject: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget



On 4/11/25 6:02 AM, Umesh Kalappa wrote:
> This is the first patch from the two-patch series, where configured 
> gcc for P8700 micro architecture  in the first patch and Tested with dejagnu 
> riscv.exp tests for --mtune=mips-p8700.
>   
> P8700 is a high-performance processor from MIPS by extending RISCV. The 
> following changes enable P8700 processor for RISCV.
> 
>   * config/riscv/riscv-cores.def(RISCV_TUNE):Added mips-p8700 tune.
>   * config/riscv/riscv-opts.h(riscv_microarchitecture_type):Likewise
>   * config/riscv/riscv.cc(riscv_tune_param):Added insns costs p8700 tune.
>   * config/riscv/riscv.md:Added p8700 tune for insn attribute.
>   * config/riscv/mips-p8700.md:New File for mips-p8700 pipeline
> description
> ---
>   gcc/config/riscv/mips-p8700.md   | 139 +++
>   gcc/config/riscv/riscv-cores.def |   1 +
>   gcc/config/riscv/riscv-opts.h|   3 +-
>   gcc/config/riscv/riscv.cc|  22 +
>   gcc/config/riscv/riscv.md|   3 +-
>   5 files changed, 166 insertions(+), 2 deletions(-)  create mode 
> 100644 gcc/config/riscv/mips-p8700.md
> 
> diff --git a/gcc/config/riscv/mips-p8700.md 
> b/gcc/config/riscv/mips-p8700.md new file mode 100644 index 
> 000..11d0b1ca793
> --- /dev/null
> +++ b/gcc/config/riscv/mips-p8700.md
> @@ -0,0 +1,139 @@
> +;; DFA-based pipeline description for MIPS P8700.
> +;;
> +;; Copyright (C) 2025 Free Software Foundation, Inc.
> +;;
> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it ;; 
> +under the terms of the GNU General Public License as published ;; by 
> +the Free Software Foundation; either version 3, or (at your ;; 
> +option) any later version.
It looks like your patchfile is getting corrupted.  THe ';;' comment markers 
should have been at the beginning of each line.  This kind of problem seems 
pervasive in your patch and certainly makes it harder to read/evaluate as 
comments are mixed on the same line as the various parts of pipeline 
description.



> +
> +(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe,
> +mips_p8700_fpu_pipe")
We don't typically see things broken up like this.  Typically we only use 
distinct automaton for things like div/sqrt which can make the DFA unreasonably 
large and cause gen* to run for unreasonably long times.

Just quickly scanning the insn reservations, I suspect you're missing many 
cases and the compiler will trip assertion failures if you are missing cases.

Essentially every insn type must map to a reservation, even types that your 
design doesn't support.  I would suggest walking through each type in riscv.md 
and making sure each and every one maps to an insn reservation.  Feel free to 
make a dummy reservation for things you don't care about.



> +/* Costs to use when optimizing for MIPS P8700.  */ static const 
> +struct riscv_tune_param mips_p8700_tune_info = {
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},/* fp_add */
> +  {COSTS_N_INSNS (5), COSTS_N_INSNS (5)},/* fp_mul */
> +  {COSTS_N_INSNS (17), COSTS_N_INSNS (17)},  /* fp_div */
> +  {COSTS_N_INSNS (5), COSTS_N_INSNS (5)},/* int_mul */
> +  {COSTS_N_INSNS (8), COSTS_N_INSNS (8)},/* int_div */
> +  4, /* issue_rate */
> +  8, /* branch_cost */
> +  4, /* memory_cost */
> +  8, /* fmv_cost */
> +  true,/* slow_unaligned_access */
> +  false, /* 
> vector_unaligned_access */
> +  false, /* use_divmod_expansion */
> +  false, /* overlap_op_by_pieces */
> +  RISCV_FUSE_NOTHING,/* fusible_ops */
> +  NULL,  /* vector cost */
> +  NULL,

[PATCH] RISCV :Added MIPS P8700 Subtarget.

2025-04-10 Thread Umesh Kalappa

P8700 is a high-performance processor from MIPS by extending RISCV with the 
MIPS custom instructions.

Tested with dejagnu riscv.exp tests for --mtune=mips-p8700.

Please refer @ https://mips.com/products/hardware/p8700/
---
 gcc/ChangeLog|  21 +++
 gcc/common/config/riscv/riscv-common.cc  |  10 ++
 gcc/config/riscv/mips-insn.md|  37 +
 gcc/config/riscv/mips-p8700.md   | 139 +++
 gcc/config/riscv/riscv-cores.def |   1 +
 gcc/config/riscv/riscv-opts.h|   3 +-
 gcc/config/riscv/riscv.cc|  92 +++-
 gcc/config/riscv/riscv.md|  16 ++-
 gcc/config/riscv/riscv.opt   |  11 ++
 gcc/testsuite/gcc.target/riscv/mipscondmov.c |  30 
 10 files changed, 355 insertions(+), 5 deletions(-)  create mode 100644 
gcc/config/riscv/mips-insn.md  create mode 100644 
gcc/config/riscv/mips-p8700.md  create mode 100644 
gcc/testsuite/gcc.target/riscv/mipscondmov.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1326c67563a..d2642390b2a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2025-04-09  Umesh Kalappa  
+
+P8700 is a high-performance processor from MIPS by extending RISCV
+with the MIPS custom instructions.
+The following changes enable P8700 processor for RISCV and
+added MIPS specific insns.
+
+* common/config/riscv/riscv-common.cc (riscv_ext_version_table) :
+Added MIPS specific insns.
+* config/riscv/riscv-cores.def(RISCV_TUNE):Added mips-p8700 tune.
+* config/riscv/riscv-opts.h(riscv_microarchitecture_type): Likewise
+* config/riscv/riscv.c(riscv_expand_conditional_move):
+Added insns costs p8700 tune and handle the ccmov expand.
+* config/riscv/riscv.md(tune and movcc):
+Added p8700 tune for insn attribute and updated expand for MIPS CCMOV.
+* config/riscv/riscv.opt:Added riscv_mips_subext for MIPS ext insns.
+* config/riscv/mips-insn.md:New file for mips-p8700 ext insns.
+* config/riscv/mips-p8700.md:New File for mips-p8700 pipeline
+description.
+* testsuite/gcc.target/riscv/mipscondmov.c :New file to test ccmov 
insn.
+
 2025-04-10  Iain Sandoe  

* config/darwin.h (LINK_SPEC): Add support for diff --git 
a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index b34409adf39..c8467016c87 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -442,6 +442,11 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xsfvqmaccdod",ISA_SPEC_CLASS_NONE, 1, 0},
   {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0},

+  {"xmipscbop", ISA_SPEC_CLASS_NONE, 1, 0},  {"xmipscmov", 
+ ISA_SPEC_CLASS_NONE, 1, 0},  {"xmipsexectl", ISA_SPEC_CLASS_NONE, 1, 
+ 0},  {"xmipslsp", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1778,6 +1783,11 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod",x_riscv_sifive_subext, 
MASK_XSFVQMACCDOD),
   RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext, 
MASK_XSFVFNRCLIPXFQF),

+  RISCV_EXT_FLAG_ENTRY ("xmipscbop",   x_riscv_mips_subext, MASK_XMIPSCBOP),
+  RISCV_EXT_FLAG_ENTRY ("xmipscmov",   x_riscv_mips_subext, MASK_XMIPSCMOV),
+  RISCV_EXT_FLAG_ENTRY ("xmipsexectl",   x_riscv_mips_subext, 
MASK_XMIPSEXECTL),
+  RISCV_EXT_FLAG_ENTRY ("xmipslsp",   x_riscv_mips_subext, MASK_XMIPSLSP),
+
   {NULL, NULL, NULL, 0}
 };

diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md new 
file mode 100644 index 000..0c92a9d9e94
--- /dev/null
+++ b/gcc/config/riscv/mips-insn.md
@@ -0,0 +1,37 @@
+;; Machine description for MIPS custom instructioins.
+;; Copyright (C) 2021-2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify ;; it 
+under the terms of the GNU General Public License as published by ;; 
+the Free Software Foundation; either version 3, or (at your option) ;; 
+any later version.
+
+;; GCC is distributed in the hope that it will be useful, ;; but 
+WITHOUT ANY WARRANTY; without even the implied warranty of ;; 
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;; GNU 
+General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License ;; 
+along with GCC; see the file COPYING3.  If not see ;; 
+<http://www.gnu.org/licenses/>.
+
+(define_insn "*movcc_bitmanip"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+   (if_then_else:GPR
+(match_operator 5 "equality_operator"
+

RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

2025-04-29 Thread Umesh Kalappa

;mips_p8700_fpu_fmfc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mfc"))
+  "mips_p8700_agq_lsu")
+
+;;
+;; Integer pipe
+;;
+
+(define_insn_reservation "mips_p8700_int_load" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "load"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_store" 3
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "store"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_arith_1" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" 
+"unknown,const,arith,shift,slt,multi,auipc,logical,move,bitmanip,min,ma
+x,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond"))
+  "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_int_nop" 0
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "nop"))
+  "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_dsp_mult" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "imul,cpop,clmul"))
+  "mips_p8700_gpmul")
+
+(define_insn_reservation "mips_p8700_int_div" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "idiv"))
+  "mips_p8700_gpdiv*5")
+
+(define_insn_reservation "mips_p8700_int_branch" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "branch,jump,ret,sfb_alu,trap"))
+  "mips_p8700_agq_ctistd")
+
+(define_insn_reservation "mips_p8700_int_call" 2
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "call,jalr"))
+  "mips_p8700_agq_ctistd")
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index e31afc3fe70..118fef23cad 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -50,6 +50,7 @@ RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)  
RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)  
RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)  
RISCV_TUNE("size", generic, optimize_size_tune_info)
+RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)
 
 #undef RISCV_TUNE
 
@@ -152,4 +153,8 @@ RISCV_CORE("xiangshan-nanhu",  
"rv64imafdc_zba_zbb_zbc_zbs_"
  "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
  "svinval_zicbom_zicboz",
  "xiangshan-nanhu")
+
+RISCV_CORE("mips-p8700",   "rv64imafd_zicsr_zmmul_"
+ "zaamo_zalrsc_zba_zbb",
+ "mips-p8700")
 #undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h 
index 26fe228e0f8..3ae284b0d95 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -58,7 +58,8 @@ enum riscv_microarchitecture_type {
   sifive_p400,
   sifive_p600,
   xiangshan,
-  generic_ooo
+  generic_ooo,
+  mips_p8700,
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 
bad59e248d0..1e116061d3c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -642,6 +642,28 @@ static const struct riscv_tune_param 
optimize_size_tune_info = {
   NULL,/* loop_align */
 };
 
+/* Costs to use when optimizing for MIPS P8700 */ static const struct 
+riscv_tune_param mips_p8700_tune_info = {
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_add */
+  {COSTS_N_INSNS (5), COSTS_N_INSNS (5)},  /* fp_mul */
+  {COSTS_N_INSNS (17), COSTS_N_INSNS (17)},/* fp_div */
+  {COSTS_N_INSNS (5), COSTS_N_INSNS (5)},  /* int_mul */
+  {COSTS_N_INSNS (8), COSTS_N_INSNS (8)},  /* int_div */
+  4,/* issue_rate */
+  8,/* branch_cost */
+  4,    /* memory_cost */
+  8,/* fmv_cost */
+  true, /* slow_unaligned_access */
+  false,/* vector_unaligned_access */
+  true, /* use_divmod_expansion */
+  false,/* overlap_op_by_pieces */
+  RISCV_FUSE_NOTHING,  /* fusible_ops */
+  NULL, /* vector cost */
+  NULL, /* function_align */
+  NULL, /* jump_align */
+  NULL, /* loop_align */
+};
+
 static bool riscv_avoid_shrink_wrapping_separate ();  static tree 
riscv_handle_fndecl_attrib

Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

2025-05-02 Thread Umesh Kalappa

Hi @Jeff Law and @pal...@dabbelt.com ,

Please do needful by reviewing the below changes and helps us to upstream the 
same .

Thank you 
~U

-Original Message-
From: Umesh Kalappa 
Sent: 29 April 2025 16:16
To: Umesh Kalappa ; Jeff Law ; 
gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; Jesse Huang ; 
pal...@dabbelt.com; and...@sifive.com
Subject: RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

Hi all,

Here is the updated patch that address some of the   @Jeff Law comments .

P8700  don't  have a vector engine and we support the insns type till 
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.md#L358 
and schedule module enabled the same .

---
 gcc/config/riscv/mips-p8700.md   | 139 +++
 gcc/config/riscv/riscv-cores.def |   5 ++
 gcc/config/riscv/riscv-opts.h|   3 +-
 gcc/config/riscv/riscv.cc|  22 +
 gcc/config/riscv/riscv.md|   3 +-
 5 files changed, 170 insertions(+), 2 deletions(-)  create mode 100644 
gcc/config/riscv/mips-p8700.md

diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md 
new file mode 100644 index 000..11d0b1ca793
--- /dev/null
+++ b/gcc/config/riscv/mips-p8700.md
@@ -0,0 +1,139 @@
+;; DFA-based pipeline description for MIPS P8700.
+;;
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it ;; 
+under the terms of the GNU General Public License as published ;; by 
+the Free Software Foundation; either version 3, or (at your ;; option) 
+any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public ;; 
+License for more details.
+
+;; You should have received a copy of the GNU General Public License ;; 
+along with GCC; see the file COPYING3.  If not see ;; 
+<http://www.gnu.org/licenses/>.
+
+(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe,
+mips_p8700_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes 
+(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, 
mips_p8700_lsu"
+"mips_p8700_agen_alq_pipe")
+
+(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" 
+"mips_p8700_mdu_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe (define_cpu_unit 
+"mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes 
+(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long"
+"mips_p8700_fpu_pipe")
+
+;; Long FPU pipeline.
+(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
+
+(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq,
+mips_p8700_al2") (define_reservation "mips_p8700_agq_ctistd" 
+"mips_p8700_agq, mips_p8700_ctistd") (define_reservation 
+"mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu") 
+(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq,
+mips_p8700_alu")
+
+;;
+;; FPU pipe
+;;
+
+(define_insn_reservation "mips_p8700_fpu_fadd" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fabs" 2
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcmp,fmove"))
+  "mips_p8700_fpu_short, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fload" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpload"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fstore" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpstore"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmadd" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmul" 5
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmul"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_div" 17
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fdiv,fsqrt"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu*17")
+
+(define_insn_reservation "mips_p8700_fpu_fcvt" 4

RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget

2025-05-08 Thread Umesh Kalappa

Hi All ,

We have couple of patch series that enables the P8700 tune for RISCV core to 
upstream for GCC mainline.

It will be good to hear from you guys on the patch feedback 

Thank you in advance
~U



-Original Message-
From: Umesh Kalappa 
Sent: 03 May 2025 11:27
To: Jeff Law ; gcc-patches@gcc.gnu.org; 
pal...@dabbelt.com
Cc: kito.ch...@sifive.com; Jesse Huang ; 
and...@sifive.com
Subject: Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

Hi @Jeff Law and @pal...@dabbelt.com ,

Please do needful by reviewing the below changes and helps us to upstream the 
same .

Thank you
~U

-Original Message-
From: Umesh Kalappa
Sent: 29 April 2025 16:16
To: Umesh Kalappa ; Jeff Law ; 
gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; Jesse Huang ; 
pal...@dabbelt.com; and...@sifive.com
Subject: RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

Hi all,

Here is the updated patch that address some of the   @Jeff Law comments .

P8700  don't  have a vector engine and we support the insns type till 
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.md#L358 
and schedule module enabled the same .

---
 gcc/config/riscv/mips-p8700.md   | 139 +++
 gcc/config/riscv/riscv-cores.def |   5 ++
 gcc/config/riscv/riscv-opts.h|   3 +-
 gcc/config/riscv/riscv.cc|  22 +
 gcc/config/riscv/riscv.md|   3 +-
 5 files changed, 170 insertions(+), 2 deletions(-)  create mode 100644 
gcc/config/riscv/mips-p8700.md

diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md 
new file mode 100644 index 000..11d0b1ca793
--- /dev/null
+++ b/gcc/config/riscv/mips-p8700.md
@@ -0,0 +1,139 @@
+;; DFA-based pipeline description for MIPS P8700.
+;;
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it ;; 
+under the terms of the GNU General Public License as published ;; by 
+the Free Software Foundation; either version 3, or (at your ;; option) 
+any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public ;; 
+License for more details.
+
+;; You should have received a copy of the GNU General Public License ;; 
+along with GCC; see the file COPYING3.  If not see ;; 
+<http://www.gnu.org/licenses/>.
+
+(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe,
+mips_p8700_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes 
+(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, 
mips_p8700_lsu"
+"mips_p8700_agen_alq_pipe")
+
+(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" 
+"mips_p8700_mdu_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe (define_cpu_unit 
+"mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes 
+(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long"
+"mips_p8700_fpu_pipe")
+
+;; Long FPU pipeline.
+(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
+
+(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq,
+mips_p8700_al2") (define_reservation "mips_p8700_agq_ctistd" 
+"mips_p8700_agq, mips_p8700_ctistd") (define_reservation 
+"mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu") 
+(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq,
+mips_p8700_alu")
+
+;;
+;; FPU pipe
+;;
+
+(define_insn_reservation "mips_p8700_fpu_fadd" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fabs" 2
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcmp,fmove"))
+  "mips_p8700_fpu_short, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fload" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpload"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fstore" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpstore"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmadd" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmul" 5
+  (and (eq_attr "

Ignore me ..

2025-05-07 Thread Umesh Kalappa

[PATCH v1 0/1]RISC-V :The following changes enable P8700 MIPS processor for RISC-V.

2025-05-12 Thread Umesh Kalappa

---
 gcc/config/riscv/mips-p8700.md   | 139 +++
 gcc/config/riscv/riscv-cores.def |   5 ++
 gcc/config/riscv/riscv-opts.h|   3 +-
 gcc/config/riscv/riscv.cc|  22 +
 gcc/config/riscv/riscv.md|   3 +-
 5 files changed, 170 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/riscv/mips-p8700.md

diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md
new file mode 100644
index 000..11d0b1ca793
--- /dev/null
+++ b/gcc/config/riscv/mips-p8700.md
@@ -0,0 +1,139 @@
+;; DFA-based pipeline description for MIPS P8700.
+;;
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe, 
mips_p8700_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes
+(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, 
mips_p8700_lsu"
+"mips_p8700_agen_alq_pipe")
+
+(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" "mips_p8700_mdu_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe
+(define_cpu_unit "mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes
+(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long" 
"mips_p8700_fpu_pipe")
+
+;; Long FPU pipeline.
+(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
+
+(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq, mips_p8700_al2")
+(define_reservation "mips_p8700_agq_ctistd" "mips_p8700_agq, 
mips_p8700_ctistd")
+(define_reservation "mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu")
+(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq, mips_p8700_alu")
+
+;;
+;; FPU pipe
+;;
+
+(define_insn_reservation "mips_p8700_fpu_fadd" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fabs" 2
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcmp,fmove"))
+  "mips_p8700_fpu_short, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fload" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpload"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fstore" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpstore"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmadd" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmul" 5
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmul"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_div" 17
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fdiv,fsqrt"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu*17")
+
+(define_insn_reservation "mips_p8700_fpu_fcvt" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmtc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mtc"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmfc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mfc"))
+  "mips_p8700_agq_lsu")
+
+;;
+;; Integer pipe
+;;
+
+(define_insn_reservation "mips_p8700_int_load" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "load"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_store" 3
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "store"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_arith_1" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond"))
+  "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_int_nop" 0
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "nop"))
+  "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_dsp_mult" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "imul,cpop,clmul

RE: [EXTERNAL]RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget

2025-05-12 Thread Umesh Kalappa

Sure @Palmer Dabbelt ,sent in a different thread email with updated patch.

Thank you 
~U

 

-Original Message-
From: Palmer Dabbelt  
Sent: 08 May 2025 23:38
To: Umesh Kalappa 
Cc: jeffreya...@gmail.com; gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; 
jesse.hu...@sifive.com; Andrew Waterman 
Subject: [EXTERNAL]RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget

On Thu, 08 May 2025 08:53:18 PDT (-0700), ukala...@mips.com wrote:
> Hi All ,
> 
> We have couple of patch series that enables the P8700 tune for RISCV core to 
> upstream for GCC mainline.
> 
> It will be good to hear from you guys on the patch feedback

It's kind of hard to read because your patch is getting mangled by some 
email-related thing.

Can you try using git-send-email to send a clean v2 of the patch?

> 
> Thank you in advance
> ~U
> 
> 
> 
> -Original Message-
> From: Umesh Kalappa
> Sent: 03 May 2025 11:27
> To: Jeff Law ; gcc-patches@gcc.gnu.org; 
> pal...@dabbelt.com
> Cc: kito.ch...@sifive.com; Jesse Huang ; 
> and...@sifive.com
> Subject: Re: [PATCH]RISCV :Added MIPS P8700 Subtarget
> 
> Hi @Jeff Law and @pal...@dabbelt.com ,
> 
> Please do needful by reviewing the below changes and helps us to upstream the 
> same .
> 
> Thank you
> ~U
> 
> -Original Message-
> From: Umesh Kalappa
> Sent: 29 April 2025 16:16
> To: Umesh Kalappa ; Jeff Law 
> ; gcc-patches@gcc.gnu.org
> Cc: kito.ch...@sifive.com; Jesse Huang ; 
> pal...@dabbelt.com; and...@sifive.com
> Subject: RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget
> 
> Hi all,
> 
> Here is the updated patch that address some of the   @Jeff Law comments .
> 
> P8700  don't  have a vector engine and we support the insns type till 
> https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.md#L358 
> and schedule module enabled the same .
> 
> ---
>  gcc/config/riscv/mips-p8700.md   | 139 +++
>  gcc/config/riscv/riscv-cores.def |   5 ++
>  gcc/config/riscv/riscv-opts.h|   3 +-
>  gcc/config/riscv/riscv.cc|  22 +
>  gcc/config/riscv/riscv.md|   3 +-
>  5 files changed, 170 insertions(+), 2 deletions(-)  create mode 
> 100644 gcc/config/riscv/mips-p8700.md
> 
> diff --git a/gcc/config/riscv/mips-p8700.md 
> b/gcc/config/riscv/mips-p8700.md new file mode 100644 index 
> 000..11d0b1ca793
> --- /dev/null
> +++ b/gcc/config/riscv/mips-p8700.md
> @@ -0,0 +1,139 @@
> +;; DFA-based pipeline description for MIPS P8700.
> +;;
> +;; Copyright (C) 2025 Free Software Foundation, Inc.
> +;;
> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it ;; 
> +under the terms of the GNU General Public License as published ;; by 
> +the Free Software Foundation; either version 3, or (at your ;; 
> +option) any later version.
> +
> +;; GCC is distributed in the hope that it will be useful, but WITHOUT 
> +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
> +;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public 
> +;; License for more details.
> +
> +;; You should have received a copy of the GNU General Public License 
> +;; along with GCC; see the file COPYING3.  If not see ;; 
> +<http://www.gnu.org/licenses/>.
> +
> +(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe,
> +mips_p8700_fpu_pipe")
> +
> +;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes 
> +(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, 
> mips_p8700_lsu"
> +  "mips_p8700_agen_alq_pipe")
> +
> +(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" 
> +"mips_p8700_mdu_pipe")
> +
> +;; The arithmetic-logic-unit queue (ALQ) has ALU pipe 
> +(define_cpu_unit "mips_p8700_alq, mips_p8700_alu" 
> +"mips_p8700_agen_alq_pipe")
> +
> +;; The floating-point-unit queue (FPQ) has short and long pipes 
> +(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long"
> +"mips_p8700_fpu_pipe")
> +
> +;; Long FPU pipeline.
> +(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
> +
> +(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq,
> +mips_p8700_al2") (define_reservation "mips_p8700_agq_ctistd" 
> +"mips_p8700_agq, mips_p8700_ctistd") (define_reservation 
> +"mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu") 
> +(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq,
> +mips_p8700_alu")
> +
> +;;
> +;; FPU pipe
> +;;
> +
> +(define_insn_reservation

Re: [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same.

2025-05-20 Thread Umesh Kalappa

>> I've pushed this to the trunk as well.
Thank you Jeff ,

~U

On Tue, May 20, 2025 at 11:29 PM Jeff Law  wrote:

>
>
> On 5/19/25 1:03 AM, Umesh Kalappa wrote:
> > ---
> >   gcc/config/riscv/mips-p8700.md | 28 
> >   1 file changed, 28 insertions(+)
> I've pushed this to the trunk as well.
>
> Thanks,
> jeff
>
>

Re: [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions.

2025-05-20 Thread Umesh Kalappa

>>Thanks.  I added the new cpu/tune options to the documentation in
doc/invoke.texi.
Thank you for the same

>>Going forward make sure to create a git commit message as well as a
ChangeLog entry.
Sure and we make sure that ChangeLog details in the commit log .

Thank you again
~U

On Tue, May 20, 2025 at 11:26 PM Jeff Law  wrote:

>
>
> On 5/19/25 1:02 AM, Umesh Kalappa wrote:
> > ---
> >   gcc/config/riscv/mips-p8700.md   | 139 +++
> >   gcc/config/riscv/riscv-cores.def |   5 ++
> >   gcc/config/riscv/riscv-opts.h|   3 +-
> >   gcc/config/riscv/riscv.cc|  22 +
> >   gcc/config/riscv/riscv.md|   3 +-
> >   5 files changed, 170 insertions(+), 2 deletions(-)
> >   create mode 100644 gcc/config/riscv/mips-p8700.md
> Thanks.  I added the new cpu/tune options to the documentation in
> doc/invoke.texi.
>
> Going forward make sure to create a git commit message as well as a
> ChangeLog entry.  You can look in the git log to see examples of commit
> messages.  The ChangeLog entry should be part of the commit message as
> we use scripting to create the ChangeLog file from the git commit messages.
>
> Jeff
>
>

[PATCH v2 0/1]RISC-V :The following changes enable P8700 MIPS processor for RISC-V.

2025-05-19 Thread Umesh Kalappa

>>Every type listed in that attribute must have a mapping to a function unit in 
>>your scheduler model
Thank you Jeff and added the dummies reservation for the leftout attributes and 
tested with dejagnu riscv.exp.

Thank you again for reference
~U

[PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same.

2025-05-19 Thread Umesh Kalappa

---
 gcc/config/riscv/mips-p8700.md | 28 
 1 file changed, 28 insertions(+)

diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md
index 11d0b1ca793..ae0ea8dc896 100644
--- a/gcc/config/riscv/mips-p8700.md
+++ b/gcc/config/riscv/mips-p8700.md
@@ -35,6 +35,11 @@
 ;; Long FPU pipeline.
 (define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
 
+;; P8700 unsupported insns are mapped to dummies reservations
+(define_reservation "mips_p8700_dummies"
+ "mips_p8700_agq |  mips_p8700_al2 |  mips_p8700_ctistd |  mips_p8700_lsu |
+ mips_p8700_fpu_short |  mips_p8700_fpu_long")
+
 (define_reservation "mips_p8700_agq_al2" "mips_p8700_agq, mips_p8700_al2")
 (define_reservation "mips_p8700_agq_ctistd" "mips_p8700_agq, 
mips_p8700_ctistd")
 (define_reservation "mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu")
@@ -137,3 +142,26 @@
   (and (eq_attr "tune" "mips_p8700")
(eq_attr "type" "call,jalr"))
   "mips_p8700_agq_ctistd")
+
+;; mips-p8700 dummies insn and placeholder that had no mapping to p8700 
hardware.
+(define_insn_reservation "mips_p8700_unknown" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "rdvlenb,rdvl,wrvxrm,wrfrm,
+   rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
+   vldux,vldox,vstux,vstox,vldff,vldr,vstr,
+   
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
+   vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
+   vimul,vidiv,viwmul,vimuladd,sf_vqmacc,viwmuladd,vimerge,vimov,
+   vsalu,vaalu,vsmul,vsshift,vnclip,sf_vfnrclip,
+   vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,
+   vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,
+   vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
+   vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,
+   vired,viwred,vfredu,vfredo,vfwredu,vfwredo,
+   vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,
+   vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,
+   
vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,
+   
vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,
+   
vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,
+   sf_vc,sf_vc_se"))
+  "mips_p8700_dummies")
-- 
2.43.0

[PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions.

2025-05-19 Thread Umesh Kalappa

---
 gcc/config/riscv/mips-p8700.md   | 139 +++
 gcc/config/riscv/riscv-cores.def |   5 ++
 gcc/config/riscv/riscv-opts.h|   3 +-
 gcc/config/riscv/riscv.cc|  22 +
 gcc/config/riscv/riscv.md|   3 +-
 5 files changed, 170 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/riscv/mips-p8700.md

diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md
new file mode 100644
index 000..11d0b1ca793
--- /dev/null
+++ b/gcc/config/riscv/mips-p8700.md
@@ -0,0 +1,139 @@
+;; DFA-based pipeline description for MIPS P8700.
+;;
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe, 
mips_p8700_fpu_pipe")
+
+;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes
+(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, 
mips_p8700_lsu"
+"mips_p8700_agen_alq_pipe")
+
+(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" "mips_p8700_mdu_pipe")
+
+;; The arithmetic-logic-unit queue (ALQ) has ALU pipe
+(define_cpu_unit "mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe")
+
+;; The floating-point-unit queue (FPQ) has short and long pipes
+(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long" 
"mips_p8700_fpu_pipe")
+
+;; Long FPU pipeline.
+(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe")
+
+(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq, mips_p8700_al2")
+(define_reservation "mips_p8700_agq_ctistd" "mips_p8700_agq, 
mips_p8700_ctistd")
+(define_reservation "mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu")
+(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq, mips_p8700_alu")
+
+;;
+;; FPU pipe
+;;
+
+(define_insn_reservation "mips_p8700_fpu_fadd" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fabs" 2
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcmp,fmove"))
+  "mips_p8700_fpu_short, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fload" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpload"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fstore" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fpstore"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmadd" 8
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmadd"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmul" 5
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fmul"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_div" 17
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fdiv,fsqrt"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu*17")
+
+(define_insn_reservation "mips_p8700_fpu_fcvt" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
+  "mips_p8700_fpu_long, mips_p8700_fpu_apu")
+
+(define_insn_reservation "mips_p8700_fpu_fmtc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mtc"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_fpu_fmfc" 7
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "mfc"))
+  "mips_p8700_agq_lsu")
+
+;;
+;; Integer pipe
+;;
+
+(define_insn_reservation "mips_p8700_int_load" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "load"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_store" 3
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "store"))
+  "mips_p8700_agq_lsu")
+
+(define_insn_reservation "mips_p8700_int_arith_1" 1
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" 
"unknown,const,arith,shift,slt,multi,auipc,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond"))
+  "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_int_nop" 0
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "nop"))
+  "mips_p8700_alq_alu | mips_p8700_agq_al2")
+
+(define_insn_reservation "mips_p8700_dsp_mult" 4
+  (and (eq_attr "tune" "mips_p8700")
+   (eq_attr "type" "imul,cpop,clmul

[PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

2025-05-27 Thread Umesh Kalappa

The P8700 is a high-performance processor from MIPS by extending RISCV with
the MIPS custom instruction and the following changes are added to enable the 
conditional move support from mips.

No regression found for "runtest --tool gcc 
--target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=mips-p8700/-O2 ' 
riscv.exp"

gcc/ChangeLog:

*common/config/riscv/riscv-common.cc (riscv_ext_version_table) :
 Added MIPS specific insns for P8700.
*config/riscv/riscv-cores.def(RISCV_CORE):Updated the march for 
mips-p8700 tune.
*config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT):
 New file added the mips conditional mov extension.
*config/riscv/riscv-ext.def: Likewise.
*config/riscv/t-riscv:Generates riscv-ext.opt
*config/riscv/riscv-ext.opt: Generated file.
*config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for mips 
cmov.
*config/riscv/riscv.md(movcc):updated expand for MIPS CCMOV.
*config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn.
*testsuite/gcc.target/riscv/mipscondmov.c:New file to test the ccmov 
insn.
*gcc/doc/riscv-ext.texi:Updated for mips cmov.
---
 gcc/config/riscv/mips-insn.md| 37 
 gcc/config/riscv/riscv-ext-mips.def  | 35 ++
 gcc/testsuite/gcc.target/riscv/mipscondmov.c | 30 
 3 files changed, 102 insertions(+)
 create mode 100644 gcc/config/riscv/mips-insn.md
 create mode 100644 gcc/config/riscv/riscv-ext-mips.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c

diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md
new file mode 100644
index 000..ee106c4221e
--- /dev/null
+++ b/gcc/config/riscv/mips-insn.md
@@ -0,0 +1,37 @@
+;; Machine description for MIPS custom instructioins.
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_insn "*movcc_bitmanip"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+   (if_then_else:GPR
+(match_operator 5 "equality_operator"
+   [(match_operand:X 1 "register_operand" "r")
+(match_operand:X 2 "const_0_operand" "J")])
+(match_operand:GPR 3 "reg_or_0_operand" "rJ")
+(match_operand:GPR 4 "reg_or_0_operand" "rJ")))]
+  "TARGET_XMIPSCMOV"
+{
+  enum rtx_code code = GET_CODE (operands[5]);
+  if (code == NE)
+return "mips.ccmov\t%0,%1,%z3,%z4";
+  else
+return "mips.ccmov\t%0,%1,%z4,%z3";
+}
+  [(set_attr "type" "condmove")
+   (set_attr "mode" "")])
diff --git a/gcc/config/riscv/riscv-ext-mips.def 
b/gcc/config/riscv/riscv-ext-mips.def
new file mode 100644
index 000..86492223cb3
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-mips.def
@@ -0,0 +1,35 @@
+/* MIPS extension definition file for RISC-V.
+   Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.
+
+Please run `make riscv-regen` in build folder to make sure updated anything.
+
+Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def.  */
+
+DEFINE_RISCV_EXT(
+  /* NAME */ xmipscmov,
+  /* UPPERCAE_NAME */ XMIPSCMOV,
+  /* FULL_NAME */ "Mips conditional move extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ xmips,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
diff --git a/gcc/testsuite/gcc.target/riscv/mipscondmov.c 
b/gcc/testsuite/gcc.target/riscv/mipscondmov.c
new file mode 100644
index 000..144a6b718ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mipscondmov.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { d

[PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

2025-05-27 Thread Umesh Kalappa

The P8700 is a high-performance processor from MIPS by extending RISCV with
the MIPS custom instruction and the following changes are added to enable the 
conditional move support from mips

No regressions are found for "runtest --tool gcc 
--target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=mips-p8700/-O2 ' 
riscv.exp"

*config/riscv/riscv-cores.def(RISCV_CORE):Updated the march for 
mips-p8700 tune.
*config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT):
 New file added for mips conditional mov extension.
*config/riscv/riscv-ext.def: Likewise.
*config/riscv/t-riscv:Generates riscv-ext.opt
*config/riscv/riscv-ext.opt: Generated file.
*config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for mips 
cmov.
*config/riscv/riscv.md(movcc):updated expand for MIPS CCMOV.
*config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn.
*testsuite/gcc.target/riscv/mipscondmov.c:Test file for mips.ccmov insn.
*gcc/doc/riscv-ext.texi:Updated for mips cmov.
---
 gcc/config/riscv/mips-insn.md| 37 
 gcc/config/riscv/riscv-cores.def |  2 +-
 gcc/config/riscv/riscv-ext-mips.def  | 35 ++
 gcc/config/riscv/riscv-ext.def   |  1 +
 gcc/config/riscv/riscv-ext.opt   |  5 +++
 gcc/config/riscv/riscv.cc| 27 --
 gcc/config/riscv/riscv.md| 13 ++-
 gcc/config/riscv/t-riscv |  3 +-
 gcc/doc/riscv-ext.texi   |  4 +++
 gcc/testsuite/gcc.target/riscv/mipscondmov.c | 30 
 10 files changed, 152 insertions(+), 5 deletions(-)
 create mode 100644 gcc/config/riscv/mips-insn.md
 create mode 100644 gcc/config/riscv/riscv-ext-mips.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c

diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md
new file mode 100644
index 000..ee106c4221e
--- /dev/null
+++ b/gcc/config/riscv/mips-insn.md
@@ -0,0 +1,37 @@
+;; Machine description for MIPS custom instructioins.
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_insn "*movcc_bitmanip"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+   (if_then_else:GPR
+(match_operator 5 "equality_operator"
+   [(match_operand:X 1 "register_operand" "r")
+(match_operand:X 2 "const_0_operand" "J")])
+(match_operand:GPR 3 "reg_or_0_operand" "rJ")
+(match_operand:GPR 4 "reg_or_0_operand" "rJ")))]
+  "TARGET_XMIPSCMOV"
+{
+  enum rtx_code code = GET_CODE (operands[5]);
+  if (code == NE)
+return "mips.ccmov\t%0,%1,%z3,%z4";
+  else
+return "mips.ccmov\t%0,%1,%z4,%z3";
+}
+  [(set_attr "type" "condmove")
+   (set_attr "mode" "")])
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 118fef23cad..b8bf81e7883 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -154,7 +154,7 @@ RISCV_CORE("xiangshan-nanhu",  
"rv64imafdc_zba_zbb_zbc_zbs_"
  "svinval_zicbom_zicboz",
  "xiangshan-nanhu")
 
-RISCV_CORE("mips-p8700",   "rv64imafd_zicsr_zmmul_"
+RISCV_CORE("mips-p8700",  "rv64imafd_"
  "zaamo_zalrsc_zba_zbb",
  "mips-p8700")
 #undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-ext-mips.def 
b/gcc/config/riscv/riscv-ext-mips.def
new file mode 100644
index 000..86492223cb3
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-mips.def
@@ -0,0 +1,35 @@
+/* MIPS extension definition file for RISC-V.
+   Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; s

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

2025-05-27 Thread Umesh Kalappa

Hi all,

Sorry for the noise ,looks like patch was truncated and will be sending a
new email with proper patch for the same.

Thank you and again my apologies for the noise.
~U

On Tue, May 27, 2025 at 3:41 PM Umesh Kalappa 
wrote:

> The P8700 is a high-performance processor from MIPS by extending RISCV with
> the MIPS custom instruction and the following changes are added to enable
> the conditional move support from mips.
>
> No regression found for "runtest --tool gcc
> --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=mips-p8700/-O2
> ' riscv.exp"
>
> gcc/ChangeLog:
>
> *common/config/riscv/riscv-common.cc (riscv_ext_version_table) :
>  Added MIPS specific insns for P8700.
> *config/riscv/riscv-cores.def(RISCV_CORE):Updated the march for
> mips-p8700 tune.
> *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT):
>  New file added the mips conditional mov extension.
> *config/riscv/riscv-ext.def: Likewise.
> *config/riscv/t-riscv:Generates riscv-ext.opt
> *config/riscv/riscv-ext.opt: Generated file.
> *config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for
> mips cmov.
> *config/riscv/riscv.md(movcc):updated expand for MIPS CCMOV.
> *config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn.
> *testsuite/gcc.target/riscv/mipscondmov.c:New file to test the
> ccmov insn.
> *gcc/doc/riscv-ext.texi:Updated for mips cmov.
> ---
>  gcc/config/riscv/mips-insn.md| 37 
>  gcc/config/riscv/riscv-ext-mips.def  | 35 ++
>  gcc/testsuite/gcc.target/riscv/mipscondmov.c | 30 
>  3 files changed, 102 insertions(+)
>  create mode 100644 gcc/config/riscv/mips-insn.md
>  create mode 100644 gcc/config/riscv/riscv-ext-mips.def
>  create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c
>
> diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md
> new file mode 100644
> index 000..ee106c4221e
> --- /dev/null
> +++ b/gcc/config/riscv/mips-insn.md
> @@ -0,0 +1,37 @@
> +;; Machine description for MIPS custom instructioins.
> +;; Copyright (C) 2025 Free Software Foundation, Inc.
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +(define_insn "*movcc_bitmanip"
> +  [(set (match_operand:GPR 0 "register_operand" "=r")
> +   (if_then_else:GPR
> +(match_operator 5 "equality_operator"
> +   [(match_operand:X 1 "register_operand" "r")
> +(match_operand:X 2 "const_0_operand" "J")])
> +(match_operand:GPR 3 "reg_or_0_operand" "rJ")
> +(match_operand:GPR 4 "reg_or_0_operand" "rJ")))]
> +  "TARGET_XMIPSCMOV"
> +{
> +  enum rtx_code code = GET_CODE (operands[5]);
> +  if (code == NE)
> +return "mips.ccmov\t%0,%1,%z3,%z4";
> +  else
> +return "mips.ccmov\t%0,%1,%z4,%z3";
> +}
> +  [(set_attr "type" "condmove")
> +   (set_attr "mode" "")])
> diff --git a/gcc/config/riscv/riscv-ext-mips.def
> b/gcc/config/riscv/riscv-ext-mips.def
> new file mode 100644
> index 000..86492223cb3
> --- /dev/null
> +++ b/gcc/config/riscv/riscv-ext-mips.def
> @@ -0,0 +1,35 @@
> +/* MIPS extension definition file for RISC-V.
> +   Copyright (C) 2025 Free Software Foundation, Inc.
> +
> +This file is part of GCC.
> +
> +GCC is free software; you can redistribute it and/or modify
> +it under the terms of the GNU General Public License as published by
> +the Free Software Foundation; either version 3, or (at your option)
> +any later version.
> +
> +GCC is distributed in the hope that it will be useful,
> +but WITHOUT ANY WARRANTY; without even the implied warranty of
> +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +GNU General Public License for more details.
> +
> +You should have received

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

2025-06-03 Thread Umesh Kalappa

Hi @Jeff Law   , @pal...@dabbelt.com
  and all ,

Please can you pass your comments on the below changes ,thank you
~U

On Tue, May 27, 2025 at 4:36 PM Umesh Kalappa 
wrote:

> The P8700 is a high-performance processor from MIPS by extending RISCV with
> the MIPS custom instruction and the following changes are added to enable
> the conditional move support from mips
>
> No regressions are found for "runtest --tool gcc
> --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=mips-p8700/-O2
> ' riscv.exp"
>
> *config/riscv/riscv-cores.def(RISCV_CORE):Updated the march for
> mips-p8700 tune.
> *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT):
>  New file added for mips conditional mov extension.
> *config/riscv/riscv-ext.def: Likewise.
> *config/riscv/t-riscv:Generates riscv-ext.opt
> *config/riscv/riscv-ext.opt: Generated file.
> *config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for
> mips cmov.
> *config/riscv/riscv.md(movcc):updated expand for MIPS CCMOV.
> *config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn.
> *testsuite/gcc.target/riscv/mipscondmov.c:Test file for mips.ccmov
> insn.
> *gcc/doc/riscv-ext.texi:Updated for mips cmov.
> ---
>  gcc/config/riscv/mips-insn.md| 37 
>  gcc/config/riscv/riscv-cores.def |  2 +-
>  gcc/config/riscv/riscv-ext-mips.def  | 35 ++
>  gcc/config/riscv/riscv-ext.def   |  1 +
>  gcc/config/riscv/riscv-ext.opt   |  5 +++
>  gcc/config/riscv/riscv.cc| 27 --
>  gcc/config/riscv/riscv.md| 13 ++-
>  gcc/config/riscv/t-riscv |  3 +-
>  gcc/doc/riscv-ext.texi   |  4 +++
>  gcc/testsuite/gcc.target/riscv/mipscondmov.c | 30 
>  10 files changed, 152 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/config/riscv/mips-insn.md
>  create mode 100644 gcc/config/riscv/riscv-ext-mips.def
>  create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c
>
> diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md
> new file mode 100644
> index 000..ee106c4221e
> --- /dev/null
> +++ b/gcc/config/riscv/mips-insn.md
> @@ -0,0 +1,37 @@
> +;; Machine description for MIPS custom instructioins.
> +;; Copyright (C) 2025 Free Software Foundation, Inc.
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +(define_insn "*movcc_bitmanip"
> +  [(set (match_operand:GPR 0 "register_operand" "=r")
> +   (if_then_else:GPR
> +(match_operator 5 "equality_operator"
> +   [(match_operand:X 1 "register_operand" "r")
> +(match_operand:X 2 "const_0_operand" "J")])
> +(match_operand:GPR 3 "reg_or_0_operand" "rJ")
> +(match_operand:GPR 4 "reg_or_0_operand" "rJ")))]
> +  "TARGET_XMIPSCMOV"
> +{
> +  enum rtx_code code = GET_CODE (operands[5]);
> +  if (code == NE)
> +return "mips.ccmov\t%0,%1,%z3,%z4";
> +  else
> +return "mips.ccmov\t%0,%1,%z4,%z3";
> +}
> +  [(set_attr "type" "condmove")
> +   (set_attr "mode" "")])
> diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> index 118fef23cad..b8bf81e7883 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -154,7 +154,7 @@ RISCV_CORE("xiangshan-nanhu",
> "rv64imafdc_zba_zbb_zbc_zbs_"
>   "svinval_zicbom_zicboz",
>   "xiangshan-nanhu")
>
> -RISCV_CORE("mips-p8700",   "rv64imafd_zicsr_zmmul_"
> +RISCV_CORE("mips-p8700",  "rv64imafd_"
>   "zaamo_zalrsc_zba_zbb",
&g

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

2025-06-05 Thread Umesh Kalappa

Thank you @Jeff Law   for the initial comments ,yes
will update the ChangeLog accordingly and typo fix and

>>My biggest concern is overall structure of
riscv_expand_conditional_move.  I kind of get the sense
>>that we need to refactor operand canonicalization into its own routine,
>>then have two subroutines,
Well ,it makes sense to refactor to have two subroutines .

Thank you again  for your  time ,we will make changes and will send the
updated patch soon .
~U

On Wed, Jun 4, 2025 at 8:22 PM Jeff Law  wrote:

>
>
> On 5/27/25 5:06 AM, Umesh Kalappa wrote:
> > The P8700 is a high-performance processor from MIPS by extending RISCV
> with
> > the MIPS custom instruction and the following changes are added to
> enable the conditional move support from mips
> >
> > No regressions are found for "runtest --tool gcc
> --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=mips-p8700/-O2
> ' riscv.exp"
> >
> >   *config/riscv/riscv-cores.def(RISCV_CORE):Updated the march for
> mips-p8700 tune.
> >   *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT):
> >New file added for mips conditional mov extension.
> >   *config/riscv/riscv-ext.def: Likewise.
> >   *config/riscv/t-riscv:Generates riscv-ext.opt
> >   *config/riscv/riscv-ext.opt: Generated file.
> >   *config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for
> mips cmov.
> >   *config/riscv/riscv.md(movcc):updated expand for MIPS CCMOV.
> >   *config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn.
> >   *testsuite/gcc.target/riscv/mipscondmov.c:Test file for mips.ccmov
> insn.
> >   *gcc/doc/riscv-ext.texi:Updated for mips cmov.
> > ---
> >
> >
> > diff --git a/gcc/config/riscv/mips-insn.md
> b/gcc/config/riscv/mips-insn.md
> > new file mode 100644
> > index 000..ee106c4221e
> > --- /dev/null
> > +++ b/gcc/config/riscv/mips-insn.md
> > @@ -0,0 +1,37 @@
> > +;; Machine description for MIPS custom instructioins.
> Typo.  Should be "instructions".
>
>
>
>
> > diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> > index 118fef23cad..b8bf81e7883 100644
> > --- a/gcc/config/riscv/riscv-cores.def
> > +++ b/gcc/config/riscv/riscv-cores.def
> > @@ -154,7 +154,7 @@ RISCV_CORE("xiangshan-nanhu",
> "rv64imafdc_zba_zbb_zbc_zbs_"
> > "svinval_zicbom_zicboz",
> > "xiangshan-nanhu")
> >
> > -RISCV_CORE("mips-p8700", "rv64imafd_zicsr_zmmul_"
> > +RISCV_CORE("mips-p8700",  "rv64imafd_"
> > "zaamo_zalrsc_zba_zbb",
> > "mips-p8700")
> You know your core better than I, so I'm going to assume your
> architecture string is reasonably correct.  But the change does not
> match your ChangeLog entry.  You're not adjusting tuning at all.  This
> adjusts the supported architecture.
>
>
>
> > +  /* UPPERCAE_NAME */ XMIPSCMOV,
> Should be "UPPERCASE".  I think Kito got it wrong in his original patch
> and the typo keeps getting copied into new files ;(
>
>
>
> > @@ -5352,8 +5352,31 @@ riscv_expand_conditional_move (rtx dest, rtx op,
> rtx cons, rtx alt)
> > rtx_code code = GET_CODE (op);
> > rtx op0 = XEXP (op, 0);
> > rtx op1 = XEXP (op, 1);
> > +  rtx target;
> >
> > -  if (((TARGET_ZICOND_LIKE
> > +  if (TARGET_XMIPSCMOV && mode == word_mode && GET_MODE (op0) ==
> word_mode)
> > +{
> > +  if (code == EQ || code == NE)
> > +   {
> > +op0 = riscv_zero_if_equal (op0, op1);
> > +op1 = const0_rtx;
> > +   }
> Your formatting looks goofy here.  The open-curley appears to be
> indented one space inside the IF.  Occasionally this is due to tabs, so
> double check it may be a false positive.
>
>
> > +  else
> > +   {
> > +target = gen_reg_rtx (GET_MODE (op0));
> > +riscv_emit_int_order_test(code, 0, target, op0, op1);
> Always a space between the function name and the open paren for the
> argument list.
>
> Given your semantics are full conditional move rather than zicond I
> wonder if we should restructure this code a little.  Other than things
> like canonicalization of the condition I doubt we're going to be able to
> share much between the zicond forms and full conditional move forms.
>
>
>
> > diff --git a/gcc/config

[PATCH] RISC-V: Use scratch reg for Rd , so that src/rs2 is not clobbered for Store-Conditional.

2025-06-11 Thread Umesh Kalappa

gcc/ChangeLog:

* config/riscv/sync.md (lrsc_atomic_exchange):
Use the scratch reg for rd.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zalrsc.c: New test.
---
 gcc/config/riscv/sync.md| 11 +--
 gcc/testsuite/gcc.target/riscv/zalrsc.c | 13 +
 2 files changed, 18 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zalrsc.c

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 726800a9662..a75ea6834e4 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -405,18 +405,17 @@
   (match_operand:SI 3 "const_int_operand")] ;; model
  UNSPEC_SYNC_EXCHANGE))
(set (match_dup 1)
-   (match_operand:GPR 2 "register_operand" "0"))
+   (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:GPR 4 "=&r"))];; tmp_1
   "!TARGET_ZAAMO && TARGET_ZALRSC"
   {
 return "1:\;"
-  "lr.%I3\t%4, %1\;"
-  "sc.%J3\t%0, %0, %1\;"
-  "bnez\t%0, 1b\;"
-  "mv\t%0, %4";
+  "lr.%I3\t%0, %1\;"
+  "sc.%J3\t%4, %z2, %1\;"
+  "bnez\t%4, 1b\";
   }
   [(set_attr "type" "atomic")
-   (set (attr "length") (const_int 16))])
+   (set (attr "length") (const_int 12))])
 
 (define_expand "atomic_exchange"
   [(match_operand:SHORT 0 "register_operand") ;; old value at mem
diff --git a/gcc/testsuite/gcc.target/riscv/zalrsc.c 
b/gcc/testsuite/gcc.target/riscv/zalrsc.c
new file mode 100644
index 000..b8991f13da8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zalrsc.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imfd_zalrsc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+
+/* lr.w/sc.w */
+int *i;
+int lr_sc(int v)
+{
+  return __atomic_exchange_4(i, v, __ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times {\mlr.w} 1 } } */
+/* { dg-final { scan-assembler-times {\msc.w} 1 } } */

base-commit: e477e7cd104af96c55379f69125db3f1c350c9ed
-- 
2.43.0

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