RE: [EXT] Re: [dpdk-stable] [PATCH v2] test: avoid hang if queues are full and Tx fails

[Rakesh Kudurumalla]

> -Original Message-
> From: Thomas Monjalon 
> Sent: Monday, November 22, 2021 2:28 PM
> To: Rakesh Kudurumalla 
> Cc: sta...@dpdk.org; dev@dpdk.org; david.march...@redhat.com;
> ferruh.yi...@intel.com; andrew.rybche...@oktetlabs.ru;
> ajit.khapa...@broadcom.com; Jerin Jacob Kollanukkaran
> 
> Subject: Re: [EXT] Re: [dpdk-stable] [PATCH v2] test: avoid hang if queues are
> full and Tx fails
> 
> 22/11/2021 08:59, Rakesh Kudurumalla:
> > From: Thomas Monjalon 
> > > 20/07/2021 18:50, Rakesh Kudurumalla:
> > > > Current pmd_perf_autotest() in continuous mode tries to enqueue
> > > > MAX_TRAFFIC_BURST completely before starting the test. Some
> > > > drivers cannot accept complete MAX_TRAFFIC_BURST even though
> rx+tx
> > > > desc
> > > count
> > > > can fit it.
> > >
> > > Which driver is failing to do so?
> > > Why it cannot enqueue 32 packets?
> >
> > Octeontx2 driver is failing to enqueue because hardware buffers are full
> before test.
> 
> Why hardware buffers are full?
Hardware buffers are full because number of number of descriptors in continuous 
mode 
Is less than MAX_TRAFFIC_BURST, so if enque fails , there is no way hardware 
can drop the
Packets . pmd_per_autotest application evaluates performance after enqueueing 
packets
Initially.
> 
> > pmd_perf_autotest() in continuous mode tries to enqueue
> > MAX_TRAFFIC_BURST (2048) before starting the test.
> >
> > > > This patch changes behaviour to stop enqueuing after few retries.
> > >
> > > If there is a real limitation, there will be issues in more places
> > > than this test program.
> > > I feel it should be addressed either in the driver or at ethdev level.
> > >
> > > [...]
> > > > @@ -480,10 +483,19 @@ main_loop(__rte_unused void *args)
> > > > nb_tx = RTE_MIN(MAX_PKT_BURST, num);
> > > > nb_tx = rte_eth_tx_burst(portid, 0,
> > > > &tx_burst[idx], nb_tx);
> > > > +   if (nb_tx == 0)
> > > > +   retry_cnt++;
> > > > num -= nb_tx;
> > > > idx += nb_tx;
> > > > +   if (retry_cnt == MAX_RETRY_COUNT) {
> > > > +   retry_cnt = 0;
> > > > +   break;
> > > > +   }
> 
> 

Re: [EXT] Re: [dpdk-stable] [PATCH v2] test: avoid hang if queues are full and Tx fails

[Thomas Monjalon]

29/11/2021 09:52, Rakesh Kudurumalla:
> From: Thomas Monjalon 
> > 22/11/2021 08:59, Rakesh Kudurumalla:
> > > From: Thomas Monjalon 
> > > > 20/07/2021 18:50, Rakesh Kudurumalla:
> > > > > Current pmd_perf_autotest() in continuous mode tries to enqueue
> > > > > MAX_TRAFFIC_BURST completely before starting the test. Some
> > > > > drivers cannot accept complete MAX_TRAFFIC_BURST even though
> > rx+tx
> > > > > desc
> > > > count
> > > > > can fit it.
> > > >
> > > > Which driver is failing to do so?
> > > > Why it cannot enqueue 32 packets?
> > >
> > > Octeontx2 driver is failing to enqueue because hardware buffers are full
> > before test.

Aren't you stopping the support of octeontx2?
Why do you care now?

> > 
> > Why hardware buffers are full?
> Hardware buffers are full because number of number of descriptors in 
> continuous mode 
> Is less than MAX_TRAFFIC_BURST, so if enque fails , there is no way hardware 
> can drop the
> Packets . pmd_per_autotest application evaluates performance after enqueueing 
> packets
> Initially.
> > 
> > > pmd_perf_autotest() in continuous mode tries to enqueue
> > > MAX_TRAFFIC_BURST (2048) before starting the test.
> > >
> > > > > This patch changes behaviour to stop enqueuing after few retries.
> > > >
> > > > If there is a real limitation, there will be issues in more places
> > > > than this test program.
> > > > I feel it should be addressed either in the driver or at ethdev level.
> > > >
> > > > [...]
> > > > > @@ -480,10 +483,19 @@ main_loop(__rte_unused void *args)
> > > > >   nb_tx = RTE_MIN(MAX_PKT_BURST, num);
> > > > >   nb_tx = rte_eth_tx_burst(portid, 0,
> > > > >   &tx_burst[idx], nb_tx);
> > > > > + if (nb_tx == 0)
> > > > > + retry_cnt++;
> > > > >   num -= nb_tx;
> > > > >   idx += nb_tx;
> > > > > + if (retry_cnt == MAX_RETRY_COUNT) {
> > > > > + retry_cnt = 0;
> > > > > + break;
> > > > > + }

RE: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure

[Liron Himi]

Hi Thomas,


-Original Message-
From: Thomas Monjalon  
Sent: Sunday, 28 November 2021 22:37
To: Liron Himi 
Cc: David Marchand ; Yigit, Ferruh 
; Jerin Jacob Kollanukkaran ; 
dev@dpdk.org
Subject: Re: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk 
infrastructure

28/11/2021 21:17, Liron Himi:
> Hi,
> 
> I have fixed the error below but got additional errors which I need your 
> advice if to ignore or update it is some way.
> This patch also replace the name of the 'regexdevs/octeontx2' folder to 
> 'regexdevs/cn9k'
> Note that Jerin is going to remove the current 'octeontx2' references as the 
> new cnxk is replacing it.
> 
> What should I do with those errors:
> dpdk-next-net-mrvl/doc/guides/platform/octeontx2.rst:158:unknown document: 
> ../regexdevs/octeontx2

This one, you must fix to the next regex doc.
[L.H.] okay.

> dpdk-next-net-mrvl/doc/guides/rel_notes/release_20_11.rst:293:unknown 
> document: ../regexdevs/octeontx2

This one, you must replace the link with a normal text.
For instance, this is what was done for another octeontx2 driver:

-  See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.
+  See ``rawdevs/octeontx2_ep`` for more details on this new PMD.
[L.H.] but this file represent the release notes of dpdk-20.11, right? so, in 
this release the driver is still 'regexdevs/octeontx2'.
only in the upcoming release the driver name will be changed to 
"regexdevs/cn9k".
I also think this is relevant for the example you provided. In dpdk-20.11 the 
driver was "rawdevs/octeontx2_ep"

Re: [EXT] |FAILURE| pw104631 [PATCH v2 5/5] regex/cn9k: use cnxk infrastructure

[Thomas Monjalon]

29/11/2021 10:55, Liron Himi:
> From: Thomas Monjalon  
> 28/11/2021 21:17, Liron Himi:
> > Hi,
> > 
> > I have fixed the error below but got additional errors which I need your 
> > advice if to ignore or update it is some way.
> > This patch also replace the name of the 'regexdevs/octeontx2' folder to 
> > 'regexdevs/cn9k'
> > Note that Jerin is going to remove the current 'octeontx2' references as 
> > the new cnxk is replacing it.
> > 
> > What should I do with those errors:
> > dpdk-next-net-mrvl/doc/guides/platform/octeontx2.rst:158:unknown document: 
> > ../regexdevs/octeontx2
> 
> This one, you must fix to the next regex doc.
> [L.H.] okay.
> 
> > dpdk-next-net-mrvl/doc/guides/rel_notes/release_20_11.rst:293:unknown 
> > document: ../regexdevs/octeontx2
> 
> This one, you must replace the link with a normal text.
> For instance, this is what was done for another octeontx2 driver:
> 
> -  See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.
> +  See ``rawdevs/octeontx2_ep`` for more details on this new PMD.
> [L.H.] but this file represent the release notes of dpdk-20.11, right? so, in 
> this release the driver is still 'regexdevs/octeontx2'.
> only in the upcoming release the driver name will be changed to 
> "regexdevs/cn9k".
> I also think this is relevant for the example you provided. In dpdk-20.11 the 
> driver was "rawdevs/octeontx2_ep"

In new releases, the driver doesn't exist, right?
So the documentation, including old release notes cannot compile
with a reference to a removed page.
That's why we need to transform this link to a removed page.

If you want to see the old documentation, you can go to
https://doc.dpdk.org/guides-20.11/

[PATCH 0/5] cryptodev: fix inconsistency in RSA op usage

[Ramkumar Balu]

From: Ramkumar 

The RSA verify operation is performed in two stages: 1. decrypt using
public key (output: plaintext message) 2. Compare resultant plaintext
message with the expected plaintext message to verify. (return
succ/fail in status field) Some applications need the decrypted
plaintext (stage 1 result) also to be retunred. For reference, OpenSSL
also provides similar API (RSA_public_decrypt).

lib cryptodev API failed to specify a field in 'struct
rte_crypto_rsa_op_param' to return the plaintext result after public
key decryption. It created inconsistency among crypto PMDs in returning
plaintext during RSA verify.

Inconsistency in RSA verify,
crypto/octeontx - uses 'sign' field to return plaintext
crypto/cnxk - uses 'sign' field to return plaintext
crypto/openssl - does not return plaintext
crypto/qat - uses 'cipher' field to return plaintext
test/cryptodev_asym - expects PMDs to use 'cipher' field

Thus, this patch series fixes all usages to only use 'cipher' field for
above described scenario.  The 'sign' and 'message' fields are not
chosen as they are used for different purpose under same operation.

rte_crypto_rsa_op_param struct fields to use for
RTE_CRYPTO_ASYM_OP_VERIFY:
1. input: rsa.sign - signature to be decrypted or verified
2. input: rsa.message - expected plaintext, used to compare
3. output: rsa.cipher - resultant plaintext from decryption


Ramkumar (5):
  cryptodev: fix RSA op cipher field description
  crypto/openssl: fix output of RSA verify op
  crypto/octeontx: fix output field for RSA verify
  crypto/octeontx2: fix output field for RSA verify
  crypto/cnxk: fix output field for RSA verify

 drivers/crypto/cnxk/cnxk_ae.h | 15 +--
 drivers/crypto/octeontx/otx_cryptodev_ops.c   | 10 ++
 drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 16 +---
 drivers/crypto/openssl/rte_openssl_pmd.c  | 16 +++-
 lib/cryptodev/rte_crypto_asym.h   |  7 ---
 5 files changed, 39 insertions(+), 25 deletions(-)

-- 
2.17.1

[PATCH 1/5] cryptodev: fix RSA op cipher field description

[Ramkumar Balu]

From: Ramkumar 

The description for 'struct rte_crypto_rsa_op_param' failed to specify
a field for returning the plaintext from RSA public key decryption.

This patch fixes the rte_crypto_rsa_op_param description to specify
'cipher' field to be used for returning plaintext during RSA op_type
== RTE_CRYPTO_ASYM_OP_VERIFY.

Fixes: 501ed9c6611f ("cryptodev: add cipher field to RSA op")
Cc: sta...@dpdk.org

Signed-off-by: Ramkumar 
---
 lib/cryptodev/rte_crypto_asym.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/lib/cryptodev/rte_crypto_asym.h b/lib/cryptodev/rte_crypto_asym.h
index 9c866f553f..b99cf6843c 100644
--- a/lib/cryptodev/rte_crypto_asym.h
+++ b/lib/cryptodev/rte_crypto_asym.h
@@ -461,11 +461,12 @@ struct rte_crypto_rsa_op_param {
 * - to be decrypted for RSA private decrypt.
 *
 * Pointer to output data
-* - for RSA public encrypt.
+* - for RSA public encrypt/decrypt.
 * In this case the underlying array should have been allocated
-* with enough memory to hold ciphertext output (i.e. must be
+* with enough memory to hold ciphertext/plaintext output (i.e. must be
 * at least RSA key size). The cipher.length field should
-* be 0 and will be overwritten by the PMD with the encrypted length.
+* be 0 and will be overwritten by the PMD with the encrypted/decrypted
+* length.
 *
 * All data is in Octet-string network byte order format.
 */
-- 
2.17.1

[PATCH 2/5] crypto/openssl: fix output of RSA verify op

[Ramkumar Balu]

From: Ramkumar 

During RSA verify, the OpenSSL PMD fails to return the plaintext after
public key decryption.
This patch fixes the OpenSSL PMD to return the decrypted plaintext in
cipher.data / cipher.length fields

Fixes: 3e9d6bd447fb ("crypto/openssl: add RSA and mod asym operations")
Fixes: fe1606e0138c ("crypto/openssl: fix RSA verify operation")
Cc: sta...@dpdk.org

Signed-off-by: Ramkumar 
---
 drivers/crypto/openssl/rte_openssl_pmd.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/openssl/rte_openssl_pmd.c 
b/drivers/crypto/openssl/rte_openssl_pmd.c
index 5794ed8159..3ab2c3b5c1 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd.c
@@ -1953,12 +1953,16 @@ process_openssl_rsa_op(struct rte_crypto_op *cop,
break;
 
case RTE_CRYPTO_ASYM_OP_VERIFY:
-   tmp = rte_malloc(NULL, op->rsa.sign.length, 0);
+   tmp = op->rsa.cipher.data;
if (tmp == NULL) {
-   OPENSSL_LOG(ERR, "Memory allocation failed");
-   cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
-   break;
+   tmp = rte_malloc(NULL, op->rsa.sign.length, 0);
+   if (tmp == NULL) {
+   OPENSSL_LOG(ERR, "Memory allocation failed");
+   cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
+   break;
+   }
}
+
ret = RSA_public_decrypt(op->rsa.sign.length,
op->rsa.sign.data,
tmp,
@@ -1974,7 +1978,9 @@ process_openssl_rsa_op(struct rte_crypto_op *cop,
OPENSSL_LOG(ERR, "RSA sign Verification failed");
cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
}
-   rte_free(tmp);
+   op->rsa.cipher.length = ret;
+   if (tmp != op->rsa.cipher.data)
+   rte_free(tmp);
break;
 
default:
-- 
2.17.1

[PATCH 3/5] crypto/octeontx: fix output field for RSA verify

[Ramkumar Balu]

From: Ramkumar 

During RSA sign verification, the OCTEONTX PMD returns the decrypted
plaintext in 'sign' field of rte_crypto_rsa_op_param. The 'sign' field
is actually used to pass input to the operation. This PMD overwrites
the 'sign' field buffer. This is non-compliance to lib cryptodev.

This patch fixes the PMD to use 'cipher' field to return the decrypted
plaintext during RSA verify operation.

Fixes: e9a356e2fc71 ("crypto/octeontx: add asymmetric enqueue/dequeue ops")
Cc: sta...@dpdk.org

Signed-off-by: Ramkumar 
---
 drivers/crypto/octeontx/otx_cryptodev_ops.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c 
b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 9e8fd495cf..07ce079d87 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -788,18 +788,20 @@ otx_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct 
cpt_request_info *req,
break;
case RTE_CRYPTO_ASYM_OP_VERIFY:
if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE)
-   rsa->sign.length = rsa_ctx->n.length;
+   rsa->cipher.length = rsa_ctx->n.length;
else {
/* Get length of decrypted output */
-   rsa->sign.length = rte_cpu_to_be_16
+   rsa->cipher.length = rte_cpu_to_be_16
(*((uint16_t *)req->rptr));
 
/* Offset data pointer by length fields */
req->rptr += 2;
}
-   memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
 
-   if (memcmp(rsa->sign.data, rsa->message.data,
+   if (rsa->cipher.data != NULL)
+   memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
+
+   if (memcmp(req->rptr, rsa->message.data,
   rsa->message.length)) {
CPT_LOG_DP_ERR("RSA verification failed");
cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
-- 
2.17.1

[PATCH 4/5] crypto/octeontx2: fix output field for RSA verify

[Ramkumar Balu]

From: Ramkumar 

During RSA sign verification, the OCTEONTX2 PMD returns the decrypted
plaintext in 'sign' field of rte_crypto_rsa_op_param. The 'sign'
field is actually used to pass input to the operation. This PMD
overwrites the 'sign' field buffer. This is non-compliance to lib
cryptodev.

This patch fixes the PMD to use 'cipher' field to return the decrypted
plaintext during RSA verify operation.

Fixes: 04227377c81b ("crypto/octeontx2: support asymmetric in enqueue/dequeue")
Cc: sta...@dpdk.org

Signed-off-by: Ramkumar 
---
 drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c 
b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 339b82f33e..fb38e309aa 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -876,20 +876,22 @@ otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct 
cpt_request_info *req,
break;
case RTE_CRYPTO_ASYM_OP_VERIFY:
if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
-   rsa->sign.length = rsa_ctx->n.length;
-   memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
+   rsa->cipher.length = rsa_ctx->n.length;
} else {
/* Get length of signed output */
-   rsa->sign.length = rte_cpu_to_be_16
+   rsa->cipher.length = rte_cpu_to_be_16
  (*((uint16_t *)req->rptr));
/*
 * Offset output data pointer by length field
-* (2 bytes) and copy signed data.
+* (2 bytes).
 */
-   memcpy(rsa->sign.data, req->rptr + 2,
-  rsa->sign.length);
+   req->rptr += 2;
}
-   if (memcmp(rsa->sign.data, rsa->message.data,
+
+   if (rsa->cipher.data != NULL)
+   memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
+
+   if (memcmp(req->rptr, rsa->message.data,
   rsa->message.length)) {
CPT_LOG_DP_ERR("RSA verification failed");
cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
-- 
2.17.1

[PATCH 5/5] crypto/cnxk: fix output field for RSA verify

[Ramkumar Balu]

From: Ramkumar 

During RSA sign verification, this PMD returns the decrypted plaintext
in 'sign' field of rte_crypto_rsa_op_param. The 'sign' field is
actually used to pass input to the operation. This PMD overwrites the
'sign' field buffer. This is non-compliance to lib cryptodev.

This patch fixes the PMD to use 'cipher' field to return the decrypted
plaintext during RSA verify operation.

Fixes: 6661bedf1605 ("crypto/cnxk: add asymmetric datapath")
Cc: sta...@dpdk.org

Signed-off-by: Ramkumar 
---
 drivers/crypto/cnxk/cnxk_ae.h | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h
index 6222171fe6..f4c6c92880 100644
--- a/drivers/crypto/cnxk/cnxk_ae.h
+++ b/drivers/crypto/cnxk/cnxk_ae.h
@@ -696,19 +696,22 @@ cnxk_ae_dequeue_rsa_op(struct rte_crypto_op *cop, uint8_t 
*rptr,
break;
case RTE_CRYPTO_ASYM_OP_VERIFY:
if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
-   rsa->sign.length = rsa_ctx->n.length;
-   memcpy(rsa->sign.data, rptr, rsa->sign.length);
+   rsa->cipher.length = rsa_ctx->n.length;
} else {
/* Get length of signed output */
-   rsa->sign.length =
+   rsa->cipher.length =
rte_cpu_to_be_16(*((uint16_t *)rptr));
/*
 * Offset output data pointer by length field
-* (2 bytes) and copy signed data.
+* (2 bytes).
 */
-   memcpy(rsa->sign.data, rptr + 2, rsa->sign.length);
+   rptr += 2;
}
-   if (memcmp(rsa->sign.data, rsa->message.data,
+
+   if (rsa->cipher.data != NULL)
+   memcpy(rsa->cipher.data, rptr, rsa->cipher.length);
+
+   if (memcmp(rptr, rsa->message.data,
   rsa->message.length)) {
cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
}
-- 
2.17.1

FOSDEM 2022 Network Devroom CFP

[Kinsella, Ray]

We are excited to announce that the call for proposals is now open for the
Network devroom at [FOSDEM 2022]. FOSDEM is a free event for engineers to meet,
share ideas and collaborate. FOSDEM is one of the largest events of its kind,
hosting, thousands of developers of free and open source software from all over
the world.

Please note that, due to Covid-19, FOSDEM will be held virtually again next year
on the 5th and 6th of February, 2022. All presentations will be pre-recorded
with live chat during each presentation and live Q&A after each presentation.


[FOSDEM 2022] https://fosdem.org/2022/


Important Dates
===

   Sunday 12th December  Submission deadline
   Friday 24th December  Announcement of selected talks
   Friday 28th January   Recorded Presentation and slide upload deadline
   5 & 6th February  Conference dates (online)


About the devroom
=

  The FOSDEM Network devroom hosts a diversity of talks covering open source
  networking projects and technologies. The scope of the Network devroom is
  broad and targets those software developers engaged in network design,
  monitoring, management and software development with open source tools.

  We typically host a variety of talks on Networking topics including:
  - Network monitoring (inventory, discovery & telemetry),
  - Network management (enterprise, carrier-grade, cloud, IoT)
  - Networking protocols (the full alphabet soup)
  - Security (IPS, IDS, protocols)
  - Authentication
  - Development tools (libraries, SDKs, plugins)
  - Network stacks


Suggested Topics:
=

  If it moves network packets, monitors, or interacts with, or supervises
  entities that moves network packets, it is likely a topic the devroom is
  interested in. A very /non-exhaustive/ list of the projects and topics we
  would love to see on the schedule are:

   Monitoring   Nagios, Icinga2, Naemon, NTop, SNAS, Graphana, Prometheus, 
collectd
   Frameworks   DPDK, eBPF, XDP, FD.io, PANDA
   SwitchingSnabb, OpenvSwitch, Tungsten Fabric, Lagopus, FastClick
   Stacks   Linux, *BSD, F-Stack
   Controllers  Istio, Envoy, Network Service Mesh, OpenDayLight, Calico, Contiv
   Edge Akraino, Openness
   Routing  FRRouting, BIRD, Go-BGP
   Management   ONAP, Ganglia, NetSNMP, PNDA.io
   Security Suricata, Snort
   Tooling  VSPerf, TRex, Moongen, Scapy, Warp17


  Talks should be aimed at a technical audience, but should not assume that
  attendees are already familiar with your project or how it solves a given
  problem. Talk proposals may cover very specific solutions to a problem, or may
  be a higher level project overview for lesser known projects.


Code of Conduct
===

  [FOSDEM Code of Conduct]:

  We'd like to remind all speakers and attendees that all of the presentations
  and discussions in our devroom are held under the guidelines set in the CoC
  and we expect attendees, speakers, and volunteers to follow the CoC at all
  times.

  If you submit a proposal and it is accepted, you will be required to confirm
  that you accept the FOSDEM CoC. If you have any questions about the CoC or
  wish to have one of the devroom organizers review your presentation slides or
  any other content for CoC compliance, please email us and we will do our best
  to assist you.


[FOSDEM Code of Conduct] https://fosdem.org/2022/practical/conduct/


Proposals:
==

  Proposals should be made through the [FOSDEM Pentabarf submission tool]. You
  do not need to create a new Pentabarf account if you already have one from a
  past year.

  Please select the "Network" as the *track* and ensure you include the
  following information when submitting a proposal:

   Section  FieldNotes
  
-
   Person   Name(s)  Your first, last and public names.
   Person   Abstract A short bio.
   Person   PhotoPlease provide a photo.
   EventEvent Title  *This is the title of your talk* - please be 
descriptive to encourage attendance.
   EventAbstract Short abstract of one or two paragraphs.
   EventDuration Please indicate the length of your talk; 15 min, 30 
min or 45 min


  If your talk is accepted, the deadline to upload your slides and a
  pre-recorded version of your talk is Friday 28th January. FOSDEM will be held
  on the weekend of February 5th & 6th, 2022.

  Please also join the devroom’s mailing list, which is the official
  communication channel for the devroom:

  [network-devr...@lists.fosdem.org] (subscription page)


[FOSDEM Pentabarf submission tool]
https://penta.fosdem.org/submission/FOSDEM22

[network-devr...@lists.fosdem.org]
https://lists.fosdem.org/listinfo/network-devroom


Team:
=

  Ray Kinsella
  Stephan Schmidt
  Thomas Monjalon
  Emma Foley
  Alexander Biehl
  Charles Eckel

[PATCH] net/mlx5: fix metadata endianness in modify field action

[Viacheslav Ovsiienko]

As modify field action immediate source parameter the metadata
should follow the CPU endianness (according to SET_META action
structure format), and mlx5 PMD wrongly handled the immediate
parameter metadata buffer as big-endian, resulting in wrong
metadata set action with incorrect endianness.

Fixes: 40c8fb1fd3b3 ("net/mlx5: update modify field action")
Cc: sta...@dpdk.org

Signed-off-by: Viacheslav Ovsiienko 
---
 drivers/net/mlx5/mlx5_flow_dv.c | 23 +++
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 4834c752d9..1c6cae8779 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1465,7 +1465,7 @@ static void
 mlx5_flow_field_id_to_modify_info
(const struct rte_flow_action_modify_data *data,
 struct field_modify_info *info, uint32_t *mask,
-uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
+uint32_t width, struct rte_eth_dev *dev,
 const struct rte_flow_attr *attr, struct rte_flow_error *error)
 {
struct mlx5_priv *priv = dev->data->dev_private;
@@ -1820,16 +1820,11 @@ mlx5_flow_field_id_to_modify_info
{
uint32_t meta_mask = priv->sh->dv_meta_mask;
uint32_t meta_count = __builtin_popcount(meta_mask);
-   uint32_t msk_c0 =
-   rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
-   uint32_t shl_c0 = rte_bsf32(msk_c0);
int reg = flow_dv_get_metadata_reg(dev, attr, error);
if (reg < 0)
return;
MLX5_ASSERT(reg != REG_NON);
MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
-   if (reg == REG_C_0)
-   *shift = shl_c0;
info[idx] = (struct field_modify_info){4, 0,
reg_to_field[reg]};
if (mask)
@@ -1881,29 +1876,33 @@ flow_dv_convert_action_modify_field
struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
{0, 0, 0} };
uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
-   uint32_t type;
-   uint32_t shift = 0;
+   uint32_t type, meta = 0;
 
if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
conf->src.field == RTE_FLOW_FIELD_VALUE) {
type = MLX5_MODIFICATION_TYPE_SET;
/** For SET fill the destination field (field) first. */
mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
- conf->width, &shift, dev,
+ conf->width, dev,
  attr, error);
item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
(void *)(uintptr_t)conf->src.pvalue :
(void *)(uintptr_t)&conf->src.value;
+   if (conf->dst.field == RTE_FLOW_FIELD_META) {
+   meta = *(const unaligned_uint32_t *)item.spec;
+   meta = rte_cpu_to_be_32(meta);
+   item.spec = &meta;
+   }
} else {
type = MLX5_MODIFICATION_TYPE_COPY;
/** For COPY fill the destination field (dcopy) without mask. */
mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
- conf->width, &shift, dev,
+ conf->width, dev,
  attr, error);
/** Then construct the source field (field) with mask. */
mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
- conf->width, &shift,
- dev, attr, error);
+ conf->width, dev,
+ attr, error);
}
item.mask = &mask;
return flow_dv_convert_modify_action(&item,
-- 
2.18.1

Re: [PATCH] Spelling

[Ferruh Yigit]

On 11/26/2021 7:58 PM, Josh Soref wrote:

diff --git a/app/test-eventdev/test_order_common.c 
b/app/test-eventdev/test_order_common.c
index ff7813f9..603e7c91 100644
--- a/app/test-eventdev/test_order_common.c
+++ b/app/test-eventdev/test_order_common.c
@@ -253,7 +253,7 @@ void
  order_opt_dump(struct evt_options *opt)
  {
evt_dump_producer_lcores(opt);
-   evt_dump("nb_wrker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
+   evt_dump("nb_worker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));


Hi Josh, Thanks for the patch.

The typo fixes for comments and logs are more straightforward, but I have
mixed feeling about the variable / macro typo fixes, let's see what others
think.

And I think we should get this patch either one of the first patch or last
patch to prevent conflict with other patches.

[PATCH] version: 22.03-rc0

[David Marchand]

Start a new release cycle with empty release notes.
Bump version and ABI minor.
Enable ABI checks using latest libabigail.

Signed-off-by: David Marchand 
---
 .github/workflows/build.yml|   6 +-
 .travis.yml|  23 -
 ABI_VERSION|   2 +-
 VERSION|   2 +-
 doc/guides/rel_notes/index.rst |   1 +
 doc/guides/rel_notes/release_22_03.rst | 138 +
 6 files changed, 165 insertions(+), 7 deletions(-)
 create mode 100644 doc/guides/rel_notes/release_22_03.rst

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 2e9c4be6d0..1a29e107be 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -20,10 +20,10 @@ jobs:
   BUILD_DOCS: ${{ contains(matrix.config.checks, 'doc') }}
   CC: ccache ${{ matrix.config.compiler }}
   DEF_LIB: ${{ matrix.config.library }}
-  LIBABIGAIL_VERSION: libabigail-1.8
+  LIBABIGAIL_VERSION: libabigail-2.0
   MINI: ${{ matrix.config.mini != '' }}
   PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
-  REF_GIT_TAG: none
+  REF_GIT_TAG: v21.11
   RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
 
 strategy:
@@ -40,7 +40,7 @@ jobs:
   - os: ubuntu-18.04
 compiler: gcc
 library: shared
-checks: doc+tests
+checks: abi+doc+tests
   - os: ubuntu-18.04
 compiler: clang
 library: static
diff --git a/.travis.yml b/.travis.yml
index 4bb5bf629e..da5273048f 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -41,8 +41,8 @@ script: ./.ci/${TRAVIS_OS_NAME}-build.sh
 
 env:
   global:
-- LIBABIGAIL_VERSION=libabigail-1.8
-- REF_GIT_TAG=none
+- LIBABIGAIL_VERSION=libabigail-2.0
+- REF_GIT_TAG=v21.11
 
 jobs:
   include:
@@ -61,6 +61,14 @@ jobs:
 packages:
   - *required_packages
   - *doc_packages
+  - env: DEF_LIB="shared" ABI_CHECKS=true
+arch: amd64
+compiler: gcc
+addons:
+  apt:
+packages:
+  - *required_packages
+  - *libabigail_build_packages
   # x86_64 clang jobs
   - env: DEF_LIB="static"
 arch: amd64
@@ -137,6 +145,17 @@ jobs:
 packages:
   - *required_packages
   - *doc_packages
+  - env: DEF_LIB="shared" ABI_CHECKS=true
+dist: focal
+arch: arm64-graviton2
+virt: vm
+group: edge
+compiler: gcc
+addons:
+  apt:
+packages:
+  - *required_packages
+  - *libabigail_build_packages
   # aarch64 clang jobs
   - env: DEF_LIB="static"
 dist: focal
diff --git a/ABI_VERSION b/ABI_VERSION
index b090fe57f6..70a91e23ec 100644
--- a/ABI_VERSION
+++ b/ABI_VERSION
@@ -1 +1 @@
-22.0
+22.1
diff --git a/VERSION b/VERSION
index b570734337..25bb269237 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-21.11.0
+22.03.0-rc0
diff --git a/doc/guides/rel_notes/index.rst b/doc/guides/rel_notes/index.rst
index 78861ee57b..876ffd28f6 100644
--- a/doc/guides/rel_notes/index.rst
+++ b/doc/guides/rel_notes/index.rst
@@ -8,6 +8,7 @@ Release Notes
 :maxdepth: 1
 :numbered:
 
+release_22_03
 release_21_11
 release_21_08
 release_21_05
diff --git a/doc/guides/rel_notes/release_22_03.rst 
b/doc/guides/rel_notes/release_22_03.rst
new file mode 100644
index 00..6d99d1eaa9
--- /dev/null
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -0,0 +1,138 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright 2021 The DPDK contributors
+
+.. include:: 
+
+DPDK Release 22.03
+==
+
+.. **Read this first.**
+
+   The text in the sections below explains how to update the release notes.
+
+   Use proper spelling, capitalization and punctuation in all sections.
+
+   Variable and config names should be quoted as fixed width text:
+   ``LIKE_THIS``.
+
+   Build the docs and view the output file to ensure the changes are correct::
+
+  ninja -C build doc
+  xdg-open build/doc/guides/html/rel_notes/release_22_03.html
+
+
+New Features
+
+
+.. This section should contain new features added in this release.
+   Sample format:
+
+   * **Add a title in the past tense with a full stop.**
+
+ Add a short 1-2 sentence description in the past tense.
+ The description should be enough to allow someone scanning
+ the release notes to understand the new feature.
+
+ If the feature adds a lot of sub-features you can use a bullet list
+ like this:
+
+ * Added feature foo to do something.
+ * Enhanced feature bar to do something else.
+
+ Refer to the previous release notes for examples.
+
+ Suggested order in release notes items:
+ * Core libs (EAL, mempool, ring, mbuf, buses)
+ * Device abstraction libs and PMDs (ordered alphabetically by vendor name)
+   - ethdev (lib, PMDs)
+   - cryptodev (lib, PMDs)
+   - eventdev (lib, PMDs)
+   - etc
+ * Other libs
+ * Apps, 

Re: [PATCH] Spelling

[Bruce Richardson]

On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:
> On 11/26/2021 7:58 PM, Josh Soref wrote:
> > diff --git a/app/test-eventdev/test_order_common.c 
> > b/app/test-eventdev/test_order_common.c
> > index ff7813f9..603e7c91 100644
> > --- a/app/test-eventdev/test_order_common.c
> > +++ b/app/test-eventdev/test_order_common.c
> > @@ -253,7 +253,7 @@ void
> >   order_opt_dump(struct evt_options *opt)
> >   {
> > evt_dump_producer_lcores(opt);
> > -   evt_dump("nb_wrker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
> > +   evt_dump("nb_worker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
> 
> Hi Josh, Thanks for the patch.
> 
> The typo fixes for comments and logs are more straightforward, but I have
> mixed feeling about the variable / macro typo fixes, let's see what others
> think.
> 
> And I think we should get this patch either one of the first patch or last
> patch to prevent conflict with other patches.

+1 to being a first patch to start things off clean.

For the macros, since there is quick a bit of content in the patch, could
we have the patch split into a separate patch for macro changes to review
separately, allowing the simple doc/printf spelling changes to go in
immediately?

Re: [PATCH] Spelling

[Thomas Monjalon]

29/11/2021 14:59, Bruce Richardson:
> On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:
> > On 11/26/2021 7:58 PM, Josh Soref wrote:
> > > diff --git a/app/test-eventdev/test_order_common.c 
> > > b/app/test-eventdev/test_order_common.c
> > > index ff7813f9..603e7c91 100644
> > > --- a/app/test-eventdev/test_order_common.c
> > > +++ b/app/test-eventdev/test_order_common.c
> > > @@ -253,7 +253,7 @@ void
> > >   order_opt_dump(struct evt_options *opt)
> > >   {
> > >   evt_dump_producer_lcores(opt);
> > > - evt_dump("nb_wrker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
> > > + evt_dump("nb_worker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
> > 
> > Hi Josh, Thanks for the patch.
> > 
> > The typo fixes for comments and logs are more straightforward, but I have
> > mixed feeling about the variable / macro typo fixes, let's see what others
> > think.
> > 
> > And I think we should get this patch either one of the first patch or last
> > patch to prevent conflict with other patches.
> 
> +1 to being a first patch to start things off clean.
> 
> For the macros, since there is quick a bit of content in the patch, could
> we have the patch split into a separate patch for macro changes to review
> separately, allowing the simple doc/printf spelling changes to go in
> immediately?

+1 to start with a patch on doc, comments and log messages

Re: [PATCH] Spelling

[Ferruh Yigit]

On 11/29/2021 1:59 PM, Bruce Richardson wrote:

On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:

On 11/26/2021 7:58 PM, Josh Soref wrote:

diff --git a/app/test-eventdev/test_order_common.c 
b/app/test-eventdev/test_order_common.c
index ff7813f9..603e7c91 100644
--- a/app/test-eventdev/test_order_common.c
+++ b/app/test-eventdev/test_order_common.c
@@ -253,7 +253,7 @@ void
   order_opt_dump(struct evt_options *opt)
   {
evt_dump_producer_lcores(opt);
-   evt_dump("nb_wrker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
+   evt_dump("nb_worker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));


Hi Josh, Thanks for the patch.

The typo fixes for comments and logs are more straightforward, but I have
mixed feeling about the variable / macro typo fixes, let's see what others
think.

And I think we should get this patch either one of the first patch or last
patch to prevent conflict with other patches.


+1 to being a first patch to start things off clean.

For the macros, since there is quick a bit of content in the patch, could
we have the patch split into a separate patch for macro changes to review
separately, allowing the simple doc/printf spelling changes to go in
immediately?



Also as far as I can see there are multiple build errors related to the
variable / macro renames, which was the concern.

Re: [PATCH] Spelling

[Bruce Richardson]

On Mon, Nov 29, 2021 at 09:12:53AM -0500, Josh Soref wrote:
>On Mon, Nov 29, 2021, 9:05 AM Ferruh Yigit <[1]ferruh.yi...@intel.com>
>wrote:
> 
>  On 11/29/2021 1:59 PM, Bruce Richardson wrote:
>  > On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:
>  >> Hi Josh, Thanks for the patch.
>  >>
>  >> The typo fixes for comments and logs are more straightforward,
>  but I have
>  >> mixed feeling about the variable / macro typo fixes, let's see
>  what others
>  >> think.
>  >>
>  >> And I think we should get this patch either one of the first
>  patch or last
>  >> patch to prevent conflict with other patches.
>  >
>  > +1 to being a first patch to start things off clean.
>  >
>  > For the macros, since there is quick a bit of content in the
>  patch, could
>  > we have the patch split into a separate patch for macro changes to
>  review
>  > separately, allowing the simple doc/printf spelling changes to go
>  in
>  > immediately?
> 
>Yeah, this is doable. I'll see if I can do it now. It's a lot of files,
>plus I'll need to figure out the command sequence to reply to this
>thread. If someone is available on Slack for some handholding, that
>might help me get it done faster.

Thanks.
To reply to this thread with any new patches add 
"--in-reply-to 20211126195851.50167-1-jso...@users.noreply.github.com"
to your git send-email command. (The long string above is the message id
from the email headers of your original patch. you can get it from
patchwork if you look at the headers or also the address to your patch in
patchwork [1]).

[1] 
http://patches.dpdk.org/project/dpdk/patch/20211126195851.50167-1-jso...@users.noreply.github.com/

Re: [PATCH] Spelling

[Ferruh Yigit]

On 11/29/2021 2:12 PM, Josh Soref wrote:



On Mon, Nov 29, 2021, 9:05 AM Ferruh Yigit mailto:ferruh.yi...@intel.com>> wrote:

On 11/29/2021 1:59 PM, Bruce Richardson wrote:
 > On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:
 >> Hi Josh, Thanks for the patch.
 >>
 >> The typo fixes for comments and logs are more straightforward, but I 
have
 >> mixed feeling about the variable / macro typo fixes, let's see what 
others
 >> think.
 >>
 >> And I think we should get this patch either one of the first patch or 
last
 >> patch to prevent conflict with other patches.
 >
 > +1 to being a first patch to start things off clean.
 >
 > For the macros, since there is quick a bit of content in the patch, could
 > we have the patch split into a separate patch for macro changes to review
 > separately, allowing the simple doc/printf spelling changes to go in
 > immediately?


Yeah, this is doable. I'll see if I can do it now. It's a lot of files, plus 
I'll need to figure out the command sequence to reply to this thread. If 
someone is available on Slack for some handholding, that might help me get it 
done faster.

Also as far as I can see there are multiple build errors related to the
variable / macro renames, which was the concern.


I'm used to having access to GitHub based CI that let me test before making a 
PR. I've locally dropped the peer change, but didn't resubmit since I figured 
I'd wait for replies.

(Last night I installed meson and ninja, so I might be able to do a local 
build.)



Following changes fixes the build errors, I am not saying they are the
best fix, that is just to give you an idea what is failing:

 diff --git a/drivers/baseband/acc100/acc100_pf_enum.h 
b/drivers/baseband/acc100/acc100_pf_enum.h
 index a1ee416d26c1..cdb58dfbb92e 100644
 --- a/drivers/baseband/acc100/acc100_pf_enum.h
 +++ b/drivers/baseband/acc100/acc100_pf_enum.h
 @@ -42,11 +42,11 @@ enum {
 HWPfQmgrDebugProcessWdTimeoutMsiFifo  =  0x00A001C4,
 HWPfQmgrDepthLog2Grp  =  0x00A00200,
 HWPfQmgrTholdGrp  =  0x00A00300,
 -   HWPfQmgrGrpTmplateReg0Indx=  0x00A00600,
 -   HWPfQmgrGrpTmplateReg1Indx=  0x00A00680,
 -   HWPfQmgrGrpTmplateReg2indx=  0x00A00700,
 -   HWPfQmgrGrpTmplateReg3Indx=  0x00A00780,
 -   HWPfQmgrGrpTmplateReg4Indx=  0x00A00800,
 +   HWPfQmgrGrpTemplateReg0Indx=  0x00A00600,
 +   HWPfQmgrGrpTemplateReg1Indx=  0x00A00680,
 +   HWPfQmgrGrpTemplateReg2indx=  0x00A00700,
 +   HWPfQmgrGrpTemplateReg3Indx=  0x00A00780,
 +   HWPfQmgrGrpTemplateReg4Indx=  0x00A00800,
 HWPfQmgrVfBaseAddr=  0x00A01000,
 HWPfQmgrUl4GWeightRrVf=  0x00A02000,
 HWPfQmgrDl4GWeightRrVf=  0x00A02100,
 @@ -113,7 +113,7 @@ enum {
 HWPfDmaStatusDataErrLoVf  =  0x00B8085C,
 HWPfDmaStatusDataErrHiVf  =  0x00B80860,
 HWPfDmaCfgMsiEnSoftwareErr=  0x00B80864,
 -   HWPfDmaDescriptorSignatuture  =  0x00B80868,
 +   HWPfDmaDescriptorSignature  =  0x00B80868,
 HWPfDmaFcwSignature   =  0x00B8086C,
 HWPfDmaErrorDetectionEn   =  0x00B80870,
 HWPfDmaErrCntrlFifoDebug  =  0x00B8087C,
 diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
 index dd2ebecc6a9c..ee8cb91d92a8 100644
 --- a/drivers/common/cnxk/hw/nix.h
 +++ b/drivers/common/cnxk/hw/nix.h
 @@ -921,7 +921,7 @@ struct nix_band_prof_s {
 uint64_t icolor : 2;
 uint64_t tnl_ena : 1;
 uint64_t rsvd_7_5 : 3;
 -   uint64_t peir_exponent : 5;
 +   uint64_t peer_exponent : 5;
 uint64_t rsvd_15_13 : 3;
 uint64_t pebs_exponent : 5;
 uint64_t rsvd_23_21 : 3;
 @@ -929,7 +929,7 @@ struct nix_band_prof_s {
 uint64_t rsvd_31_29 : 3;
 uint64_t cbs_exponent : 5;
 uint64_t rsvd_39_37 : 3;
 -   uint64_t peir_mantissa : 8;
 +   uint64_t peer_mantissa : 8;
 uint64_t pebs_mantissa : 8;
 uint64_t cir_mantissa : 8;
 uint64_t cbs_mantissa : 8;
 diff --git a/drivers/crypto/qat/qat_sym_session.h 
b/drivers/crypto/qat/qat_sym_session.h
 index 21afb90cad3a..6965b31efc53 100644
 --- a/drivers/crypto/qat/qat_sym_session.h
 +++ b/drivers/crypto/qat/qat_sym_session.h
 @@ -141,10 +141,6 @@ qat_sym_session_clear(struct rte_cryptodev *dev,
  unsigned int
  qat_sym_session_get_private_size(struct rte_cryptodev *dev);
  
 -void

 -qat_sym_session_init_common_hdr(struct qat_sym_session *session,
 -   struct icp_qat_fw_comn_req_hdr *header,
 -   enum qat_sym_proto_flag proto_flags);
  int
  qat_sym_validate_aes_key(int ke

Re: [dpdk-dev] [RFC PATCH] ethdev: support priority based flow control

[Jerin Jacob]

On Sun, Nov 28, 2021 at 5:07 PM Jerin Jacob  wrote:
>
> On Sun, Nov 28, 2021 at 5:01 PM Ori Kam  wrote:
> >
> > Good for me
> >
> > Please send the meeting invite.


Thanks, Ori, Thomas, and Ferruh for attending the meeting.

General consensus to expose the feature as ethdev API instead of rte_flow i.e
rte_flow will be used for steering the traffic to Queue for given VLAN
TCI field or so and the
ethdev Rx queue will have the configuration for traffic class value.

I will reject this
http://patches.dpdk.org/project/dpdk/patch/20211005125923.2651449-1-jer...@marvell.com/
patch and send a new one
based on the above theme.

>
>
> Meeting invite at 2 PM UTC on 29th Nov(Monday)
>
> Hi there,
>
> Jerin Jacob Kollanukkaran is inviting you to a scheduled Zoom meeting.
>
> Topic: Jerin Jacob Kollanukkaran's Personal Meeting Room
>
>
> Join Zoom Meeting:
> https://marvell.zoom.us/j/9901077677?pwd=T2lTTGMwYlc1YTQzMnR4eGRWQXR6QT09
> Password: 339888
>
>
> Or Telephone：
> Dial(for higher quality, dial a number based on your current location)：
> US: +1 301 715 8592  or +1 312 626 6799  or +1 346 248 7799
> or +1 646 558 8656  or +1 669 900 6833  or +1 253 215 8782  or 888 788
> 0099 (Toll Free) or 833 548 0276 (Toll Free) or 833 548 0282 (Toll
> Free) or 877 853 5247 (Toll Free)
> Meeting ID: 990 107 7677
> Password: 358309
> International numbers available: https://marvell.zoom.us/u/adpcCpMHYt
>
> Or a Video Conference Room:
> From Touchpad: Tap Join Zoom button. When prompted, enter 990 107 7677
> Password: 358309
>
> For China locations, from Touchpad: Dial* then 990 107 7677
> Password: 358309
>
> >
> > Ori
> >
> > > -Original Message-
> > > From: Jerin Jacob 
> > > Sent: Friday, November 26, 2021 8:46 AM
> > > To: Ori Kam 
> > > Subject: Re: [dpdk-dev] [RFC PATCH] ethdev: support priority based flow 
> > > control
> > >
> > > On Thu, Nov 25, 2021 at 7:32 PM Ori Kam  wrote:
> > > >
> > > > Hi Jerin,
> > > >
> > > > I think that we are not on the same page and I'm missing some critical 
> > > > info to decide
> > > > on the best approch.
> > > >
> > > > Can we please have a short meeting so you can explain to me about this 
> > > > feature?
> > > >
> > > > I think it will be good if Thomas, Ferruh and Andrew could join.
> > >
> > > Sure, Ori. Is 2 PM UTC on 29th Nov(Monday) on
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmeet.jit.si%2Fdpdk&dat
> > > a=04%7C01%7Corika%40nvidia.com%7C515af20d94c0419f1e2208d9b0a88983%7C43083d15727340c1b7
> > > db39efd9ccc17a%7C0%7C0%7C637735060187259293%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wL
> > > jAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=V3n8P%2F%2BM
> > > udw4IMntVry8PO71PgxBAJyS9QYfTJN5i7A%3D&reserved=0
> > > is fine for you/Thomas/Ferruh/Andrew?
> > > If not, Please suggest some time.
> > >
> > >
> > > >
> > > > Best,
> > > > Ori
> > > >
> > > > > -Original Message-
> > > > > From: Jerin Jacob 
> > > > > Sent: Thursday, November 25, 2021 1:12 PM
> > > > > To: Ori Kam 
> > > > > Subject: Re: [dpdk-dev] [RFC PATCH] ethdev: support priority based 
> > > > > flow control
> > > > >
> > > > > On Wed, Nov 24, 2021 at 9:30 PM Ori Kam  wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Jerin Jacob 
> > > > > > > Sent: Wednesday, November 24, 2021 12:48 PM
> > > > > > >
> > > > > > > On Wed, Nov 24, 2021 at 3:01 PM Ori Kam  wrote:
> > > > > > > >
> > > > > > > > Hi Jerin,
> > > > > > > >
> > > > > > > > > -Original Message-
> > > > > > > > > From: Jerin Jacob 
> > > > > > > > > Sent: Tuesday, November 23, 2021 12:58 PM
> > > > > > > > > To: Ori Kam 
> > > > > > > > >
> > > > > > > > > On Sun, Nov 21, 2021 at 3:20 PM Ori Kam  
> > > > > > > > > wrote:
> > > > > > > > > >
> > > > > > > > > > Hi Jerin,
> > > > > > > > >
> > > > > > > > > Hi Ori,
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Sorry for my late response,
> > > > > > > > >
> > > > > > > > > Thanks for the review.
> > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > > -Original Message-
> > > > > > > > > > > From: Jerin Jacob 
> > > > > > > > > > > Sent: Wednesday, November 17, 2021 11:49 AM
> > > > > > > > > > > To: Jerin Jacob 
> > > > > > > > > > > Subject: Re: [dpdk-dev] [RFC PATCH] ethdev: support 
> > > > > > > > > > > priority based flow control
> > > > > > > > > > >
> > > > > > > > > > > On Tue, Oct 5, 2021 at 6:32 PM  wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > From: Jerin Jacob 
> > > > > > > > > > > >
> > > > > > > > > > > > rte_eth_dev_priority_flow_ctrl_set() based API is not 
> > > > > > > > > > > > generic as it
> > > > > > > > > > > > can not support other than VLAN priority mapping to PFC 
> > > > > > > > > > > > traffic class.
> > > > > > > > > > > >
> > > > > > > > > > > > Introducing RTE_FLOW_ACTION_TYPE_PFC_SET_TC rte_flow 
> > > > > > > > > > > > action to
> > > > > > > > > > > > set the traffic class as per 802.1Qbb spe

Re: [dpdk-dev] [Bug 826] red_autotest random failures

[Brandon Lo]

On Wed, Nov 24, 2021 at 2:48 AM Liguzinski, WojciechX <
wojciechx.liguzin...@intel.com> wrote:

> Hi,
>
>
>
> Thanks Lincoln, I will also have a try with such script.
>
>
>
> Cheers,
>
> Wojciech
>
>
Hello Wojciech,

I also recommend trying to run the test with around 4GB of RAM and 2GB of
hugepages to see if it fails. That is roughly the number of resources we
have per machine that is completely dedicated to unit tests. The amount of
RAM available can sometimes increase depending on how many jobs are running
per machine, but 4GB is the lowest it can go for the unit test job.

Thanks,
Brandon



-- 
Brandon Lo
UNH InterOperability Laboratory
21 Madbury Rd, Suite 100, Durham, NH 03824
b...@iol.unh.edu
www.iol.unh.edu

Re: [PATCH] Spelling

[Ajit Khaparde]

On Mon, Nov 29, 2021 at 6:02 AM Thomas Monjalon  wrote:
>
> 29/11/2021 14:59, Bruce Richardson:
> > On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:
> > > On 11/26/2021 7:58 PM, Josh Soref wrote:
> > > > diff --git a/app/test-eventdev/test_order_common.c 
> > > > b/app/test-eventdev/test_order_common.c
> > > > index ff7813f9..603e7c91 100644
> > > > --- a/app/test-eventdev/test_order_common.c
> > > > +++ b/app/test-eventdev/test_order_common.c
> > > > @@ -253,7 +253,7 @@ void
> > > >   order_opt_dump(struct evt_options *opt)
> > > >   {
> > > >   evt_dump_producer_lcores(opt);
> > > > - evt_dump("nb_wrker_lcores", "%d", evt_nr_active_lcores(opt->wlcores));
> > > > + evt_dump("nb_worker_lcores", "%d", 
> > > > evt_nr_active_lcores(opt->wlcores));
> > >
> > > Hi Josh, Thanks for the patch.
> > >
> > > The typo fixes for comments and logs are more straightforward, but I have
> > > mixed feeling about the variable / macro typo fixes, let's see what others
> > > think.
> > >
> > > And I think we should get this patch either one of the first patch or last
> > > patch to prevent conflict with other patches.
> >
> > +1 to being a first patch to start things off clean.
> >
> > For the macros, since there is quick a bit of content in the patch, could
> > we have the patch split into a separate patch for macro changes to review
> > separately, allowing the simple doc/printf spelling changes to go in
> > immediately?
>
> +1 to start with a patch on doc, comments and log messages
+1

>
>

Re: [PATCH] Spelling

[Josh Soref]

On Mon, Nov 29, 2021, 9:05 AM Ferruh Yigit  wrote:

> On 11/29/2021 1:59 PM, Bruce Richardson wrote:
> > On Mon, Nov 29, 2021 at 12:49:56PM +, Ferruh Yigit wrote:
> >> Hi Josh, Thanks for the patch.
> >>
> >> The typo fixes for comments and logs are more straightforward, but I
> have
> >> mixed feeling about the variable / macro typo fixes, let's see what
> others
> >> think.
> >>
> >> And I think we should get this patch either one of the first patch or
> last
> >> patch to prevent conflict with other patches.
> >
> > +1 to being a first patch to start things off clean.
> >
> > For the macros, since there is quick a bit of content in the patch, could
> > we have the patch split into a separate patch for macro changes to review
> > separately, allowing the simple doc/printf spelling changes to go in
> > immediately?
>

Yeah, this is doable. I'll see if I can do it now. It's a lot of files,
plus I'll need to figure out the command sequence to reply to this thread.
If someone is available on Slack for some handholding, that might help me
get it done faster.

Also as far as I can see there are multiple build errors related to the
> variable / macro renames, which was the concern.
>

I'm used to having access to GitHub based CI that let me test before making
a PR. I've locally dropped the peer change, but didn't resubmit since I
figured I'd wait for replies.

(Last night I installed meson and ninja, so I might be able to do a local
build.)

>

RE: TSC for dmaengine API batch support for DSA (linux-idxd-ka2 @ 211126)

[Ananyev, Konstantin]

 1.7 GHz SPR, 'D' stepping
 1 DSA device, 1 WQ (size=128, 1 engine, mode="dedicated", type="kernel", 
name="dmaengine")
 io_uring-bench with some mods:
 1 thread, 1 io_uring context (sq_ring=64,cq_ring=128), random reads over one 
1GB file on tmpfs

 Without touching data in user-space:
  SW copy (KIOPS)   DMA copy (irq) (KIOPS)DMA copy 
(poll) (KIOPS)
1KB 1488.8  583.9   1189.0
2KB 1300.7  582.0   1170.8
4KB 1045.5  580.1   1214.8
8KB   709.7 532.2 952.3
16KB  393.3 441.1 690.7
32KB  203.2 313.6 434.2
64KB91.5229.3 266.8
128KB   46.1128.9 155.2
 
With touching data in user-space:
  SW copy (KIOPS)   DMA copy (irq) (KIOPS)DMA copy 
(poll) (KIOPS)
1KB 1281.4  586.8   1157.0
2KB 1129.0  603.9   1058.1
4K888.9 615.7 935.6
8KB   506.2 511.8 757.8
16KB  309.4 363.1 472.6
32KB  131.1 221.4 275.2
64KB65.7147.2 152.8
128KB   31.4  79.5  76.2

FS layer1KB 4KB 8KB 16KB
32KB128KB
---
read_iter (get_page + sw copy)  986 1367219439948237
35441   
read_iter (get_page)442 459 652 10891852
  5599
sw copy (deduced)   542 908 154229056385
29842

io_uring layer
---
alloc dma_copy_vec  222 214 244 248 284 
381
dma_map_sg  130 132 146 210 296 
1034
cleanup dma_copy_vec208 303 375 451 700 
2108
(dma_unmap_sg, put_page, kfree)

dma driver layer
--
dma_memcpy_sg_prep  345 344 329 479 713 
2611
dma_txd_submit  108 109 108 109 109   111
dma_tx_status   327 349 431 534 797 
2346
idxd_dma_tx_status (deduced)119   41  56  83  97
  238   ???

SW copy
===

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 1024 -d 64 -- /tmp/xz1
[  152.636953] _io_ring_call_stat_print(read_iter): 
nb_call=37514528,nb_cycle=37008954492,cycle/call=986;

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 4096 -d 64 -- /tmp/xz1
[   70.028931] _io_ring_call_stat_print(read_iter): 
nb_call=28191936,nb_cycle=38541193956,cycle/call=1367;

taskset -c 1 /bin/bash -x /mnt/share0/buildroot-prev1/build/images/io_uring -b 
8192 -d 64 -- /tmp/xz1
[  218.785124] _io_ring_call_stat_print(read_iter): 
nb_call=19109312,nb_cycle=41928352830,cycle/call=2194;

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 16384 -d 64 -- /tmp/xz1
[  337.191163] _io_ring_call_stat_print(read_iter): 
nb_call=11452608,nb_cycle=45751699798,cycle/call=3994;

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 32768 -d 64 -- /tmp/xz1
[  294.087806] _io_ring_call_stat_print(read_iter): 
nb_call=5717280,nb_cycle=47097616396,cycle/call=8237;

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 131072 -d 64 -- /tmp/xz1
[  152.502022] _io_ring_call_stat_print(read_iter): 
nb_call=1404480,nb_cycle=49777091724,cycle/call=35441;

DMA copy (ipoll)
==

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 1024 -d 64 -p 1 -- /tmp/xz1
[  838.747911] _io_ring_call_stat_print(read_iter): 
nb_call=24296523,nb_cycle=10747261984,cycle/call=442;
[  838.749273] _io_ring_call_stat_print(dma_copy): 
nb_call=24296523,nb_cycle=10502724540,cycle/call=432;
[  838.750632] _io_ring_call_stat_print(dma_tx_status): 
nb_call=24296523,nb_cycle=7600041778,cycle/call=312;

taskset -c 1 /bin/bash -x /mnt/share0/run_bg_task.sh 30 
/mnt/share0/buildroot-prev1/build/images/io_uring -b 4096 -d 64 -p 1 -- /tmp/xz1
[ 1007.960910] _io_ring_call_stat_print(read_iter): 
nb_call=23038754,nb_cycle=10597803630,cycle/call=459;
[ 1007.962291] _io_ring_call_stat_print(

[PATCH v3 0/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v3:
- fix documentation issues

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 doc/guides/platform/octeontx2.rst |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 doc/guides/rel_notes/release_20_11.rst|   2 +-
 drivers/common/cnxk/hw/ree.h  | 126 
 drivers/common/cnxk/hw/rvu.h  |   5 +
 drivers/common/cnxk/meson.build   |   1 +
 drivers/common/cnxk/roc_api.h |   4 +
 drivers/common/cnxk/roc_constants.h   |   2 +
 drivers/common/cnxk/roc_mbox.h| 100 +++
 drivers/common/cnxk/roc_platform.c|   1 +
 drivers/common/cnxk/roc_platform.h|   2 +
 drivers/common/cnxk/roc_priv.h|   3 +
 drivers/common/cnxk/roc_ree.c | 647 ++
 drivers/common/cnxk/roc_ree.h | 137 
 drivers/common/cnxk/roc_ree_priv.h|  18 +
 drivers/common/cnxk/version.map   |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +--
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 --
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 ---
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 33 files changed, 1332 insertions(+), 1206 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0

[PATCH v2 0/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 drivers/common/cnxk/hw/ree.h  | 126 
 drivers/common/cnxk/hw/rvu.h  |   5 +
 drivers/common/cnxk/meson.build   |   1 +
 drivers/common/cnxk/roc_api.h |   4 +
 drivers/common/cnxk/roc_constants.h   |   2 +
 drivers/common/cnxk/roc_mbox.h| 100 +++
 drivers/common/cnxk/roc_platform.c|   1 +
 drivers/common/cnxk/roc_platform.h|   2 +
 drivers/common/cnxk/roc_priv.h|   3 +
 drivers/common/cnxk/roc_ree.c | 647 ++
 drivers/common/cnxk/roc_ree.h | 137 
 drivers/common/cnxk/roc_ree_priv.h|  18 +
 drivers/common/cnxk/version.map   |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +--
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 --
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 ---
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 31 files changed, 1331 insertions(+), 1202 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (68%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0

[PATCH v3 1/5] common/cnxk: add REE HW definitions

[lironh]

From: Liron Himi 

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/hw/ree.h | 126 +++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 00..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BITBIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BITBIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT0x120ull
+#define REE_LF_DONE_INT_W1S0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT0x300ull
+#define REE_LF_MISC_INT_W1S0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA 0x10ull
+#define REE_LF_SBUF_ADDR   0x20ull
+#define REE_LF_DONE0x100ull
+#define REE_LF_DONE_ACK0x110ull
+#define REE_LF_DONE_WAIT   0x148ull
+#define REE_LF_DOORBELL0x400ull
+#define REE_LF_OUTSTAND_JOB0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a) (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS (0x0ull)
+#define REE_AF_INT_VEC_RVU (0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ  (0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)  
\
+   ((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+   REE_TYPE_JOB_DESC = 0x0,
+   REE_TYPE_RESULT_DESC = 0x1,
+   REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+   uint64_t u;
+   struct {
+   uint64_t job_type : 3;
+   uint64_t mpt_cnt_det : 1;
+   uint64_t mst_cnt_det : 1;
+   uint64_t ml_cnt_det : 1;
+   uint64_t mm_cnt_det : 1;
+   uint64_t mp_cnt_det : 1;
+   uint64_t mode : 2;
+   uint64_t reserved_10_11 : 2;
+   uint64_t reserved_12_12 : 1;
+   uint64_t pmi_soj : 1;
+   uint64_t pmi_eoj : 1;
+   uint64_t reserved_15_15 : 1;
+   uint64_t reserved_16_63 : 48;
+   } s;
+};
+
+union ree_res {
+   uint64_t u[8];
+   struct ree_res_s_98 {
+   uint64_t done : 1;
+   uint64_t hwjid : 7;
+   uint64_t ree_res_job_id : 24;
+   uint64_t ree_res_status : 16;
+   uint64_t ree_res_dmcnt : 8;
+   uint64_t ree_res_mcnt : 8;
+   uint64_t ree_meta_ptcnt : 16;
+   uint64_t ree_meta_icnt : 16;
+   uint64_t ree_meta_lcnt : 16;
+   uint64_t ree_pmi_min_byte_ptr : 16;
+   uint64_t ree_err : 1;
+   uint64_t reserved_129_190 : 62;
+   uint64_t doneint : 1;
+   uint64_t reserved_192_255 : 64;
+   uint64_t reserved_256_319 : 64;
+   uint64_t reserved_320_383 : 64;
+   uint64_t reserved_384_447 : 64;
+   uint64_t reserved_448_511 : 64;
+   } s;
+};
+
+union ree_match {
+   uint64_t u;
+   struct {
+   uint64_t ree_rule_id : 32;
+   uint64_t start_ptr : 14;
+   uint64_t reserved_46_47 : 2;
+   uint64_t match_length : 15;
+   uint64_t reserved_63_6 : 1;
+   } s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM(0x0ull)
 #define RVU_BLOCK_

[PATCH v3 2/5] common/cnxk: add REE mbox definitions

[lironh]

From: Liron Himi 

add REE mbox definitions

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/roc_mbox.h | 100 +
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\
M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,\
  cpt_eng_grp_rsp) \
+   /* REE mbox IDs (range 0xE00 - 0xFFF) */   \
+   M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)\
+   M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,\
+ ree_rd_wr_reg_msg)   \
+   M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+ msg_rsp) \
+   M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,\
+ ree_rule_db_len_rsp_msg) \
+   M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,\
+ ree_rule_db_get_rsp_msg) \
/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
  msg_rsp) \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+   REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+   REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+   REE_AF_ERR_LF_INVALID = -1003,
+   REE_AF_ERR_ACCESS_DENIED = -1004,
+   REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+   REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+   REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+   REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+   REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+   REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+   REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+   REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+   REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+   REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+   REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+   REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+   REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+   REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+   REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+   REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+   REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+   REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+   REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io size;
+   uint8_t __io lf;
+   uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+   struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+   uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+   uint32_t __io blkaddr;   /* REE0 or REE1 */
+   uint32_t __io total_len; /* total len of rule db */
+   uint32_t __io offset;/* offset of current rule db block */
+   uint16_t __io len;   /* length of rule db block */
+   uint8_t __io is_last;/* is this the last block */
+   uint8_t __io is_incremental; /* is incremental flow */
+   uint8_t __io is_dbi; /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io offset; /* retrieve db from this offset */
+   uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+   struct mbox_msghdr hdr;
+   uint64_t __io reg_offset;
+   uint64_t __io *ret_val;
+   uint64_t __io val;
+   uint32_t __io blkaddr;
+   uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io len;
+   uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+   struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+   uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+   uint32_t __io total_len; /* total len of rule db */
+   uint32_t __io offset;/* offset of current rule db block */
+   uint16_t __io len;   /* length of rule db block */
+   uint8_t __io is_last;/* is this the last block */
+};
+

[PATCH v3 3/5] common/cnxk: add REE support

[lironh]

From: Liron Himi 

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/roc_ree.c  | 647 +
 drivers/common/cnxk/roc_ree.h  | 137 ++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 00..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+   struct free_rsrcs_rsp *rsp;
+   struct dev *dev = vf->dev;
+   int ret;
+
+   mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+   ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+   if (ret)
+   return -EIO;
+
+   if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+   *nb_queues = rsp->ree0;
+   else
+   *nb_queues = rsp->ree1;
+   return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+   uint64_t val;
+   int ret;
+
+   ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+   if (ret)
+   return ret;
+
+   *max_matches = val;
+   return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+   struct rsrc_attach_req *req;
+   struct mbox *mbox;
+
+   mbox = vf->dev->mbox;
+   /* Ask AF to attach required LFs */
+   req = mbox_alloc_msg_attach_resources(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+
+   /* 1 LF = 1 queue */
+   req->reelfs = nb_queues;
+   req->ree_blkaddr = vf->block_address;
+
+   if (mbox_process(mbox) < 0)
+   return -EIO;
+
+   /* Update number of attached queues */
+   vf->nb_queues = nb_queues;
+
+   return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+   struct rsrc_detach_req *req;
+   struct mbox *mbox;
+
+   mbox = vf->dev->mbox;
+   req = mbox_alloc_msg_detach_resources(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+   req->reelfs = true;
+   req->partial = true;
+   if (mbox_process(mbox) < 0)
+   return -EIO;
+
+   /* Queues have been detached */
+   vf->nb_queues = 0;
+
+   return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+   struct msix_offset_rsp *rsp;
+   struct mbox *mbox;
+   uint32_t i, ret;
+
+   /* Get REE MSI-X vector offsets */
+   mbox = vf->dev->mbox;
+   mbox_alloc_msg_msix_offset(mbox);
+
+   ret = mbox_process_msg(mbox, (void *)&rsp);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < vf->nb_queues; i++) {
+   if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+   vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+   else
+   vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+   plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+   }
+
+   return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+   struct mbox *mbox = vf->dev->mbox;
+   int ret;
+
+   mbox_msg_send(mbox, 0);
+
+   ret = mbox_wait_for_rsp(mbox, 0);
+   if (ret < 0) {
+   plt_err("Could not get mailbox response");
+   return ret;
+   }
+
+   return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t 
size)
+{
+   struct ree_lf_req_msg *req;
+   struct mbox *mbox;
+   int ret;
+
+   mbox = vf->dev->mbox;
+   req = mbox_alloc_msg_ree_config_lf(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+
+   req->lf = lf;
+   req->pri = pri ? 1 : 0;
+   req->size = size;
+   req->blkaddr = vf->block_address;
+
+   ret = mbox_process(mbox);
+   if (ret < 0) {
+   plt_err("Could not get mailbox response");
+   return ret;
+   }
+   return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+   struct ree_rd_wr_reg_msg *msg;
+   struct mbox_dev *mdev;
+   struct mbox *mbox;
+   int ret, off;
+
+   mbox = vf->dev->mbox;
+   mdev = &mbox->dev[0];
+   msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+   mbox, 0, sizeof(*msg), sizeof(*msg));
+  

[PATCH v3 4/5] common/cnxk: link REE support to ROC files

[lironh]

From: Liron Himi 

add references to REE files from ROC files

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/meson.build |  1 +
 drivers/common/cnxk/roc_api.h   |  4 
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h  |  3 +++
 drivers/common/cnxk/version.map | 18 +-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
 'roc_tim.c',
 'roc_tim_irq.c',
 'roc_utils.c',
+'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h 
b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY  0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF 0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF 0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c 
b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h 
b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)  
\
RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)  plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)  plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)   plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)  plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)   
\
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
cnxk_logtype_nix;
cnxk_logtype_npa;
cnxk_logtype_npc;
+   cnxk_logtype_ree;
cnxk_logtype_sso;
cnxk_logtype_tim;
cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
roc_tim_lf_enable;
roc_tim_lf_free;
roc_se_ctx_swap;
-
+   roc_ree_af_reg_read;
+   roc_ree_af_reg_write;
+   roc_ree_config_lf;
+   roc_ree_dev_fini;
+   roc_ree_dev_init;
+   roc_ree_err_intr_register;
+   roc_ree_err_intr_unregister;
+   roc_ree_iq_disable;
+   roc_ree_iq_enable;
+   roc_ree_msix_offsets_get;
+   roc_ree_qp_get_base;
+   roc_ree_queues_attach;
+   roc_ree_queues_detach;
+   roc_ree_rule_db_get;
+   roc_ree_rule_db_len_get;
+   roc_ree_rule_db_prog;
local: *;
 };
-- 
2.28.0

[PATCH v3 5/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

update driver to use the REE cnxk code
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi 
---
 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 doc/guides/platform/octeontx2.rst |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 doc/guides/rel_notes/release_20_11.rst|   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 --
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 -
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 -
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 20 files changed, 269 insertions(+), 1205 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi 
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam 
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk 
SoC.
 #. **Dmadev Driver**
See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---
 
diff --git a/doc/guides/platform/octeontx2.rst 
b/doc/guides/platform/octeontx2.rst
index 3a3d28571c..5ab43abbdd 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in 
OCTEON TX2 SoC.
 #. **Crypto Device Driver**
See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
-#. **Regex Device Driver**
-   See :doc:`../regexdevs/octeontx2` for REE regex device driver information.
-
 Procedure to Setup Platform
 ---
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 69%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..c23c295b93 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
 Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell 
OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell 
CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 `_.
 
 Features
 
 
-Features of 

[PATCH v3 0/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v3:
- fix documentation issues

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 doc/guides/platform/octeontx2.rst |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 doc/guides/rel_notes/release_20_11.rst|   2 +-
 drivers/common/cnxk/hw/ree.h  | 126 
 drivers/common/cnxk/hw/rvu.h  |   5 +
 drivers/common/cnxk/meson.build   |   1 +
 drivers/common/cnxk/roc_api.h |   4 +
 drivers/common/cnxk/roc_constants.h   |   2 +
 drivers/common/cnxk/roc_mbox.h| 100 +++
 drivers/common/cnxk/roc_platform.c|   1 +
 drivers/common/cnxk/roc_platform.h|   2 +
 drivers/common/cnxk/roc_priv.h|   3 +
 drivers/common/cnxk/roc_ree.c | 647 ++
 drivers/common/cnxk/roc_ree.h | 137 
 drivers/common/cnxk/roc_ree_priv.h|  18 +
 drivers/common/cnxk/version.map   |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +--
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 --
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 ---
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 33 files changed, 1332 insertions(+), 1206 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0

[PATCH v3 1/5] common/cnxk: add REE HW definitions

[lironh]

From: Liron Himi 

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/hw/ree.h | 126 +++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 00..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BITBIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BITBIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT0x120ull
+#define REE_LF_DONE_INT_W1S0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT0x300ull
+#define REE_LF_MISC_INT_W1S0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA 0x10ull
+#define REE_LF_SBUF_ADDR   0x20ull
+#define REE_LF_DONE0x100ull
+#define REE_LF_DONE_ACK0x110ull
+#define REE_LF_DONE_WAIT   0x148ull
+#define REE_LF_DOORBELL0x400ull
+#define REE_LF_OUTSTAND_JOB0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a) (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS (0x0ull)
+#define REE_AF_INT_VEC_RVU (0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ  (0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)  
\
+   ((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+   REE_TYPE_JOB_DESC = 0x0,
+   REE_TYPE_RESULT_DESC = 0x1,
+   REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+   uint64_t u;
+   struct {
+   uint64_t job_type : 3;
+   uint64_t mpt_cnt_det : 1;
+   uint64_t mst_cnt_det : 1;
+   uint64_t ml_cnt_det : 1;
+   uint64_t mm_cnt_det : 1;
+   uint64_t mp_cnt_det : 1;
+   uint64_t mode : 2;
+   uint64_t reserved_10_11 : 2;
+   uint64_t reserved_12_12 : 1;
+   uint64_t pmi_soj : 1;
+   uint64_t pmi_eoj : 1;
+   uint64_t reserved_15_15 : 1;
+   uint64_t reserved_16_63 : 48;
+   } s;
+};
+
+union ree_res {
+   uint64_t u[8];
+   struct ree_res_s_98 {
+   uint64_t done : 1;
+   uint64_t hwjid : 7;
+   uint64_t ree_res_job_id : 24;
+   uint64_t ree_res_status : 16;
+   uint64_t ree_res_dmcnt : 8;
+   uint64_t ree_res_mcnt : 8;
+   uint64_t ree_meta_ptcnt : 16;
+   uint64_t ree_meta_icnt : 16;
+   uint64_t ree_meta_lcnt : 16;
+   uint64_t ree_pmi_min_byte_ptr : 16;
+   uint64_t ree_err : 1;
+   uint64_t reserved_129_190 : 62;
+   uint64_t doneint : 1;
+   uint64_t reserved_192_255 : 64;
+   uint64_t reserved_256_319 : 64;
+   uint64_t reserved_320_383 : 64;
+   uint64_t reserved_384_447 : 64;
+   uint64_t reserved_448_511 : 64;
+   } s;
+};
+
+union ree_match {
+   uint64_t u;
+   struct {
+   uint64_t ree_rule_id : 32;
+   uint64_t start_ptr : 14;
+   uint64_t reserved_46_47 : 2;
+   uint64_t match_length : 15;
+   uint64_t reserved_63_6 : 1;
+   } s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM(0x0ull)
 #define RVU_BLOCK_

[PATCH v3 2/5] common/cnxk: add REE mbox definitions

[lironh]

From: Liron Himi 

add REE mbox definitions

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/roc_mbox.h | 100 +
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\
M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,\
  cpt_eng_grp_rsp) \
+   /* REE mbox IDs (range 0xE00 - 0xFFF) */   \
+   M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)\
+   M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,\
+ ree_rd_wr_reg_msg)   \
+   M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+ msg_rsp) \
+   M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,\
+ ree_rule_db_len_rsp_msg) \
+   M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,\
+ ree_rule_db_get_rsp_msg) \
/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
  msg_rsp) \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+   REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+   REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+   REE_AF_ERR_LF_INVALID = -1003,
+   REE_AF_ERR_ACCESS_DENIED = -1004,
+   REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+   REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+   REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+   REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+   REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+   REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+   REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+   REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+   REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+   REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+   REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+   REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+   REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+   REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+   REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+   REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+   REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+   REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+   REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io size;
+   uint8_t __io lf;
+   uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+   struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+   uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+   uint32_t __io blkaddr;   /* REE0 or REE1 */
+   uint32_t __io total_len; /* total len of rule db */
+   uint32_t __io offset;/* offset of current rule db block */
+   uint16_t __io len;   /* length of rule db block */
+   uint8_t __io is_last;/* is this the last block */
+   uint8_t __io is_incremental; /* is incremental flow */
+   uint8_t __io is_dbi; /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io offset; /* retrieve db from this offset */
+   uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+   struct mbox_msghdr hdr;
+   uint64_t __io reg_offset;
+   uint64_t __io *ret_val;
+   uint64_t __io val;
+   uint32_t __io blkaddr;
+   uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io len;
+   uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+   struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+   uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+   uint32_t __io total_len; /* total len of rule db */
+   uint32_t __io offset;/* offset of current rule db block */
+   uint16_t __io len;   /* length of rule db block */
+   uint8_t __io is_last;/* is this the last block */
+};
+

[PATCH v3 3/5] common/cnxk: add REE support

[lironh]

From: Liron Himi 

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/roc_ree.c  | 647 +
 drivers/common/cnxk/roc_ree.h  | 137 ++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 00..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+   struct free_rsrcs_rsp *rsp;
+   struct dev *dev = vf->dev;
+   int ret;
+
+   mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+   ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+   if (ret)
+   return -EIO;
+
+   if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+   *nb_queues = rsp->ree0;
+   else
+   *nb_queues = rsp->ree1;
+   return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+   uint64_t val;
+   int ret;
+
+   ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+   if (ret)
+   return ret;
+
+   *max_matches = val;
+   return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+   struct rsrc_attach_req *req;
+   struct mbox *mbox;
+
+   mbox = vf->dev->mbox;
+   /* Ask AF to attach required LFs */
+   req = mbox_alloc_msg_attach_resources(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+
+   /* 1 LF = 1 queue */
+   req->reelfs = nb_queues;
+   req->ree_blkaddr = vf->block_address;
+
+   if (mbox_process(mbox) < 0)
+   return -EIO;
+
+   /* Update number of attached queues */
+   vf->nb_queues = nb_queues;
+
+   return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+   struct rsrc_detach_req *req;
+   struct mbox *mbox;
+
+   mbox = vf->dev->mbox;
+   req = mbox_alloc_msg_detach_resources(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+   req->reelfs = true;
+   req->partial = true;
+   if (mbox_process(mbox) < 0)
+   return -EIO;
+
+   /* Queues have been detached */
+   vf->nb_queues = 0;
+
+   return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+   struct msix_offset_rsp *rsp;
+   struct mbox *mbox;
+   uint32_t i, ret;
+
+   /* Get REE MSI-X vector offsets */
+   mbox = vf->dev->mbox;
+   mbox_alloc_msg_msix_offset(mbox);
+
+   ret = mbox_process_msg(mbox, (void *)&rsp);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < vf->nb_queues; i++) {
+   if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+   vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+   else
+   vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+   plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+   }
+
+   return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+   struct mbox *mbox = vf->dev->mbox;
+   int ret;
+
+   mbox_msg_send(mbox, 0);
+
+   ret = mbox_wait_for_rsp(mbox, 0);
+   if (ret < 0) {
+   plt_err("Could not get mailbox response");
+   return ret;
+   }
+
+   return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t 
size)
+{
+   struct ree_lf_req_msg *req;
+   struct mbox *mbox;
+   int ret;
+
+   mbox = vf->dev->mbox;
+   req = mbox_alloc_msg_ree_config_lf(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+
+   req->lf = lf;
+   req->pri = pri ? 1 : 0;
+   req->size = size;
+   req->blkaddr = vf->block_address;
+
+   ret = mbox_process(mbox);
+   if (ret < 0) {
+   plt_err("Could not get mailbox response");
+   return ret;
+   }
+   return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+   struct ree_rd_wr_reg_msg *msg;
+   struct mbox_dev *mdev;
+   struct mbox *mbox;
+   int ret, off;
+
+   mbox = vf->dev->mbox;
+   mdev = &mbox->dev[0];
+   msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+   mbox, 0, sizeof(*msg), sizeof(*msg));
+  

[PATCH v3 4/5] common/cnxk: link REE support to ROC files

[lironh]

From: Liron Himi 

add references to REE files from ROC files

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/meson.build |  1 +
 drivers/common/cnxk/roc_api.h   |  4 
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h  |  3 +++
 drivers/common/cnxk/version.map | 18 +-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
 'roc_tim.c',
 'roc_tim_irq.c',
 'roc_utils.c',
+'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h 
b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY  0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF 0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF 0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c 
b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h 
b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)  
\
RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)  plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)  plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)   plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)  plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)   
\
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
cnxk_logtype_nix;
cnxk_logtype_npa;
cnxk_logtype_npc;
+   cnxk_logtype_ree;
cnxk_logtype_sso;
cnxk_logtype_tim;
cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
roc_tim_lf_enable;
roc_tim_lf_free;
roc_se_ctx_swap;
-
+   roc_ree_af_reg_read;
+   roc_ree_af_reg_write;
+   roc_ree_config_lf;
+   roc_ree_dev_fini;
+   roc_ree_dev_init;
+   roc_ree_err_intr_register;
+   roc_ree_err_intr_unregister;
+   roc_ree_iq_disable;
+   roc_ree_iq_enable;
+   roc_ree_msix_offsets_get;
+   roc_ree_qp_get_base;
+   roc_ree_queues_attach;
+   roc_ree_queues_detach;
+   roc_ree_rule_db_get;
+   roc_ree_rule_db_len_get;
+   roc_ree_rule_db_prog;
local: *;
 };
-- 
2.28.0

[PATCH v3 5/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

update driver to use the REE cnxk code
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi 
---
 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 doc/guides/platform/octeontx2.rst |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 doc/guides/rel_notes/release_20_11.rst|   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 --
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 -
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 -
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 20 files changed, 269 insertions(+), 1205 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi 
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam 
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk 
SoC.
 #. **Dmadev Driver**
See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---
 
diff --git a/doc/guides/platform/octeontx2.rst 
b/doc/guides/platform/octeontx2.rst
index 3a3d28571c..5ab43abbdd 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in 
OCTEON TX2 SoC.
 #. **Crypto Device Driver**
See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
-#. **Regex Device Driver**
-   See :doc:`../regexdevs/octeontx2` for REE regex device driver information.
-
 Procedure to Setup Platform
 ---
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 69%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..c23c295b93 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
 Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell 
OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell 
CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 `_.
 
 Features
 
 
-Features of 

[PATCH v3 0/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

4 patches add support for REE into cnkx infrastructure.
the last patch change the octeontx2 driver to use
the new cnxk code. in addition all references to
octeontx2/otx2 were replaced with cn9k.

v3:
- fix documentation issues

v2:
- fix review comments.
- split original patch.
- add the driver patch.

Liron Himi (5):
  common/cnxk: add REE HW definitions
  common/cnxk: add REE mbox definitions
  common/cnxk: add REE support
  common/cnxk: link REE support to ROC files
  regex/cn9k: use cnxk infrastructure

 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 doc/guides/platform/octeontx2.rst |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 doc/guides/rel_notes/release_20_11.rst|   2 +-
 drivers/common/cnxk/hw/ree.h  | 126 
 drivers/common/cnxk/hw/rvu.h  |   5 +
 drivers/common/cnxk/meson.build   |   1 +
 drivers/common/cnxk/roc_api.h |   4 +
 drivers/common/cnxk/roc_constants.h   |   2 +
 drivers/common/cnxk/roc_mbox.h| 100 +++
 drivers/common/cnxk/roc_platform.c|   1 +
 drivers/common/cnxk/roc_platform.h|   2 +
 drivers/common/cnxk/roc_priv.h|   3 +
 drivers/common/cnxk/roc_ree.c | 647 ++
 drivers/common/cnxk/roc_ree.h | 137 
 drivers/common/cnxk/roc_ree_priv.h|  18 +
 drivers/common/cnxk/version.map   |  18 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 +--
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 ---
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 -
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 --
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 ---
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 -
 33 files changed, 1332 insertions(+), 1206 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 create mode 100644 drivers/common/cnxk/hw/ree.h
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

-- 
2.28.0

[PATCH v3 1/5] common/cnxk: add REE HW definitions

[lironh]

From: Liron Himi 

adding REE (Regular Expression Engine) HW definitions

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/hw/ree.h | 126 +++
 drivers/common/cnxk/hw/rvu.h |   5 ++
 2 files changed, 131 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/ree.h

diff --git a/drivers/common/cnxk/hw/ree.h b/drivers/common/cnxk/hw/ree.h
new file mode 100644
index 00..30af61d704
--- /dev/null
+++ b/drivers/common/cnxk/hw/ree.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __REE_HW_H__
+#define __REE_HW_H__
+
+/* REE instruction queue length */
+#define REE_IQ_LEN (1 << 13)
+
+#define REE_DEFAULT_CMD_QLEN REE_IQ_LEN
+
+/* Status register bits */
+#define REE_STATUS_PMI_EOJ_BITBIT_ULL(14)
+#define REE_STATUS_PMI_SOJ_BITBIT_ULL(13)
+#define REE_STATUS_MP_CNT_DET_BIT  BIT_ULL(7)
+#define REE_STATUS_MM_CNT_DET_BIT  BIT_ULL(6)
+#define REE_STATUS_ML_CNT_DET_BIT  BIT_ULL(5)
+#define REE_STATUS_MST_CNT_DET_BIT BIT_ULL(4)
+#define REE_STATUS_MPT_CNT_DET_BIT BIT_ULL(3)
+
+/* Register offsets */
+/* REE LF registers */
+#define REE_LF_DONE_INT0x120ull
+#define REE_LF_DONE_INT_W1S0x130ull
+#define REE_LF_DONE_INT_ENA_W1S 0x138ull
+#define REE_LF_DONE_INT_ENA_W1C 0x140ull
+#define REE_LF_MISC_INT0x300ull
+#define REE_LF_MISC_INT_W1S0x310ull
+#define REE_LF_MISC_INT_ENA_W1S 0x320ull
+#define REE_LF_MISC_INT_ENA_W1C 0x330ull
+#define REE_LF_ENA 0x10ull
+#define REE_LF_SBUF_ADDR   0x20ull
+#define REE_LF_DONE0x100ull
+#define REE_LF_DONE_ACK0x110ull
+#define REE_LF_DONE_WAIT   0x148ull
+#define REE_LF_DOORBELL0x400ull
+#define REE_LF_OUTSTAND_JOB0x410ull
+
+/* BAR 0 */
+#define REE_AF_REEXM_MAX_MATCH (0x80c8ull)
+#define REE_AF_QUE_SBUF_CTL(a) (0x1200ull | (uint64_t)(a) << 3)
+#define REE_PRIV_LF_CFG(a) (0x41000ull | (uint64_t)(a) << 3)
+
+#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS (0x0ull)
+#define REE_AF_INT_VEC_RVU (0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE (0x2ull)
+#define REE_AF_INT_VEC_AQ  (0x3ull)
+
+
+#define REE_LF_INT_VEC_QUE_DONE (0x0ull)
+#define REE_LF_INT_VEC_MISC(0x1ull)
+
+#define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
+#define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
+
+#define REE_LF_ENA_ENA_MASK BIT_ULL(0)
+
+#define REE_LF_BAR2(vf, q_id)  
\
+   ((vf)->dev->bar2 + (((vf)->block_address << 20) | ((q_id) << 12)))
+
+#define REE_QUEUE_HI_PRIO 0x1
+
+enum ree_desc_type_e {
+   REE_TYPE_JOB_DESC = 0x0,
+   REE_TYPE_RESULT_DESC = 0x1,
+   REE_TYPE_ENUM_LAST = 0x2
+};
+
+union ree_res_status {
+   uint64_t u;
+   struct {
+   uint64_t job_type : 3;
+   uint64_t mpt_cnt_det : 1;
+   uint64_t mst_cnt_det : 1;
+   uint64_t ml_cnt_det : 1;
+   uint64_t mm_cnt_det : 1;
+   uint64_t mp_cnt_det : 1;
+   uint64_t mode : 2;
+   uint64_t reserved_10_11 : 2;
+   uint64_t reserved_12_12 : 1;
+   uint64_t pmi_soj : 1;
+   uint64_t pmi_eoj : 1;
+   uint64_t reserved_15_15 : 1;
+   uint64_t reserved_16_63 : 48;
+   } s;
+};
+
+union ree_res {
+   uint64_t u[8];
+   struct ree_res_s_98 {
+   uint64_t done : 1;
+   uint64_t hwjid : 7;
+   uint64_t ree_res_job_id : 24;
+   uint64_t ree_res_status : 16;
+   uint64_t ree_res_dmcnt : 8;
+   uint64_t ree_res_mcnt : 8;
+   uint64_t ree_meta_ptcnt : 16;
+   uint64_t ree_meta_icnt : 16;
+   uint64_t ree_meta_lcnt : 16;
+   uint64_t ree_pmi_min_byte_ptr : 16;
+   uint64_t ree_err : 1;
+   uint64_t reserved_129_190 : 62;
+   uint64_t doneint : 1;
+   uint64_t reserved_192_255 : 64;
+   uint64_t reserved_256_319 : 64;
+   uint64_t reserved_320_383 : 64;
+   uint64_t reserved_384_447 : 64;
+   uint64_t reserved_448_511 : 64;
+   } s;
+};
+
+union ree_match {
+   uint64_t u;
+   struct {
+   uint64_t ree_rule_id : 32;
+   uint64_t start_ptr : 14;
+   uint64_t reserved_46_47 : 2;
+   uint64_t match_length : 15;
+   uint64_t reserved_63_6 : 1;
+   } s;
+};
+
+#endif /* __REE_HW_H__ */
diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index 632d9499ea..daf758f0b5 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD  (0xdull)
 #define RVU_BLOCK_TYPE_DFA  (0xeull)
 #define RVU_BLOCK_TYPE_HNA  (0xfull)
+#define RVU_BLOCK_TYPE_REE  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM(0x0ull)
 #define RVU_BLOCK_

[PATCH v3 2/5] common/cnxk: add REE mbox definitions

[lironh]

From: Liron Himi 

add REE mbox definitions

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/roc_mbox.h | 100 +
 1 file changed, 100 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b63fe108c9..e97d93e261 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -151,6 +151,16 @@ struct mbox_msghdr {
M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\
M(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req,\
  cpt_eng_grp_rsp) \
+   /* REE mbox IDs (range 0xE00 - 0xFFF) */   \
+   M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, msg_rsp)\
+   M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,\
+ ree_rd_wr_reg_msg)   \
+   M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, ree_rule_db_prog_req_msg, \
+ msg_rsp) \
+   M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg,\
+ ree_rule_db_len_rsp_msg) \
+   M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, ree_rule_db_get_req_msg,\
+ ree_rule_db_get_rsp_msg) \
/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, \
  msg_rsp) \
@@ -1452,6 +1462,96 @@ struct cpt_eng_grp_rsp {
uint8_t __io eng_grp_num;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+   REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
+   REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
+   REE_AF_ERR_LF_INVALID = -1003,
+   REE_AF_ERR_ACCESS_DENIED = -1004,
+   REE_AF_ERR_RULE_DB_PARTIAL = -1005,
+   REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
+   REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
+   REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
+   REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
+   REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
+   REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
+   REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
+   REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
+   REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
+   REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
+   REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
+   REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
+   REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
+   REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
+   REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
+   REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
+   REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
+   REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+};
+
+struct ree_lf_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io size;
+   uint8_t __io lf;
+   uint8_t __io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+   struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE ((64ULL * 1024ULL) >> 1)
+   uint8_t __io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+   uint32_t __io blkaddr;   /* REE0 or REE1 */
+   uint32_t __io total_len; /* total len of rule db */
+   uint32_t __io offset;/* offset of current rule db block */
+   uint16_t __io len;   /* length of rule db block */
+   uint8_t __io is_last;/* is this the last block */
+   uint8_t __io is_incremental; /* is incremental flow */
+   uint8_t __io is_dbi; /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io offset; /* retrieve db from this offset */
+   uint8_t __io is_dbi;  /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+   struct mbox_msghdr hdr;
+   uint64_t __io reg_offset;
+   uint64_t __io *ret_val;
+   uint64_t __io val;
+   uint32_t __io blkaddr;
+   uint8_t __io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+   struct mbox_msghdr hdr;
+   uint32_t __io blkaddr;
+   uint32_t __io len;
+   uint32_t __io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+   struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (15ULL * 1024ULL)
+   uint8_t __io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+   uint32_t __io total_len; /* total len of rule db */
+   uint32_t __io offset;/* offset of current rule db block */
+   uint16_t __io len;   /* length of rule db block */
+   uint8_t __io is_last;/* is this the last block */
+};
+

[PATCH v3 3/5] common/cnxk: add REE support

[lironh]

From: Liron Himi 

extend cnxk infrastructure to support REE

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/roc_ree.c  | 647 +
 drivers/common/cnxk/roc_ree.h  | 137 ++
 drivers/common/cnxk/roc_ree_priv.h |  18 +
 3 files changed, 802 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ree.c
 create mode 100644 drivers/common/cnxk/roc_ree.h
 create mode 100644 drivers/common/cnxk/roc_ree_priv.h

diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
new file mode 100644
index 00..1eb2ae7272
--- /dev/null
+++ b/drivers/common/cnxk/roc_ree.c
@@ -0,0 +1,647 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define REE0_PF 19
+#define REE1_PF 20
+
+static int
+roc_ree_available_queues_get(struct roc_ree_vf *vf, uint16_t *nb_queues)
+{
+   struct free_rsrcs_rsp *rsp;
+   struct dev *dev = vf->dev;
+   int ret;
+
+   mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
+
+   ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+   if (ret)
+   return -EIO;
+
+   if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+   *nb_queues = rsp->ree0;
+   else
+   *nb_queues = rsp->ree1;
+   return 0;
+}
+
+static int
+roc_ree_max_matches_get(struct roc_ree_vf *vf, uint8_t *max_matches)
+{
+   uint64_t val;
+   int ret;
+
+   ret = roc_ree_af_reg_read(vf, REE_AF_REEXM_MAX_MATCH, &val);
+   if (ret)
+   return ret;
+
+   *max_matches = val;
+   return 0;
+}
+
+int
+roc_ree_queues_attach(struct roc_ree_vf *vf, uint8_t nb_queues)
+{
+   struct rsrc_attach_req *req;
+   struct mbox *mbox;
+
+   mbox = vf->dev->mbox;
+   /* Ask AF to attach required LFs */
+   req = mbox_alloc_msg_attach_resources(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+
+   /* 1 LF = 1 queue */
+   req->reelfs = nb_queues;
+   req->ree_blkaddr = vf->block_address;
+
+   if (mbox_process(mbox) < 0)
+   return -EIO;
+
+   /* Update number of attached queues */
+   vf->nb_queues = nb_queues;
+
+   return 0;
+}
+
+int
+roc_ree_queues_detach(struct roc_ree_vf *vf)
+{
+   struct rsrc_detach_req *req;
+   struct mbox *mbox;
+
+   mbox = vf->dev->mbox;
+   req = mbox_alloc_msg_detach_resources(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+   req->reelfs = true;
+   req->partial = true;
+   if (mbox_process(mbox) < 0)
+   return -EIO;
+
+   /* Queues have been detached */
+   vf->nb_queues = 0;
+
+   return 0;
+}
+
+int
+roc_ree_msix_offsets_get(struct roc_ree_vf *vf)
+{
+   struct msix_offset_rsp *rsp;
+   struct mbox *mbox;
+   uint32_t i, ret;
+
+   /* Get REE MSI-X vector offsets */
+   mbox = vf->dev->mbox;
+   mbox_alloc_msg_msix_offset(mbox);
+
+   ret = mbox_process_msg(mbox, (void *)&rsp);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < vf->nb_queues; i++) {
+   if (vf->block_address == RVU_BLOCK_ADDR_REE0)
+   vf->lf_msixoff[i] = rsp->ree0_lf_msixoff[i];
+   else
+   vf->lf_msixoff[i] = rsp->ree1_lf_msixoff[i];
+   plt_ree_dbg("lf_msixoff[%d]  0x%x", i, vf->lf_msixoff[i]);
+   }
+
+   return 0;
+}
+
+static int
+ree_send_mbox_msg(struct roc_ree_vf *vf)
+{
+   struct mbox *mbox = vf->dev->mbox;
+   int ret;
+
+   mbox_msg_send(mbox, 0);
+
+   ret = mbox_wait_for_rsp(mbox, 0);
+   if (ret < 0) {
+   plt_err("Could not get mailbox response");
+   return ret;
+   }
+
+   return 0;
+}
+
+int
+roc_ree_config_lf(struct roc_ree_vf *vf, uint8_t lf, uint8_t pri, uint32_t 
size)
+{
+   struct ree_lf_req_msg *req;
+   struct mbox *mbox;
+   int ret;
+
+   mbox = vf->dev->mbox;
+   req = mbox_alloc_msg_ree_config_lf(mbox);
+   if (req == NULL) {
+   plt_err("Could not allocate mailbox message");
+   return -EFAULT;
+   }
+
+   req->lf = lf;
+   req->pri = pri ? 1 : 0;
+   req->size = size;
+   req->blkaddr = vf->block_address;
+
+   ret = mbox_process(mbox);
+   if (ret < 0) {
+   plt_err("Could not get mailbox response");
+   return ret;
+   }
+   return 0;
+}
+
+int
+roc_ree_af_reg_read(struct roc_ree_vf *vf, uint64_t reg, uint64_t *val)
+{
+   struct ree_rd_wr_reg_msg *msg;
+   struct mbox_dev *mdev;
+   struct mbox *mbox;
+   int ret, off;
+
+   mbox = vf->dev->mbox;
+   mdev = &mbox->dev[0];
+   msg = (struct ree_rd_wr_reg_msg *)mbox_alloc_msg_rsp(
+   mbox, 0, sizeof(*msg), sizeof(*msg));
+  

[PATCH v3 4/5] common/cnxk: link REE support to ROC files

[lironh]

From: Liron Himi 

add references to REE files from ROC files

Signed-off-by: Liron Himi 
---
 drivers/common/cnxk/meson.build |  1 +
 drivers/common/cnxk/roc_api.h   |  4 
 drivers/common/cnxk/roc_constants.h |  2 ++
 drivers/common/cnxk/roc_platform.c  |  1 +
 drivers/common/cnxk/roc_platform.h  |  2 ++
 drivers/common/cnxk/roc_priv.h  |  3 +++
 drivers/common/cnxk/version.map | 18 +-
 7 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4928f7e549..7e27b3cc0a 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -61,6 +61,7 @@ sources = files(
 'roc_tim.c',
 'roc_tim_irq.c',
 'roc_utils.c',
+'roc_ree.c',
 )
 
 # Security common code
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index e7aaa07563..1b46c21f7f 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -37,6 +37,7 @@
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
+#include "hw/ree.h"
 #include "hw/rvu.h"
 #include "hw/sdp.h"
 #include "hw/sso.h"
@@ -90,6 +91,9 @@
 /* DPI */
 #include "roc_dpi.h"
 
+/* REE */
+#include "roc_ree.h"
+
 /* HASH computation */
 #include "roc_hash.h"
 
diff --git a/drivers/common/cnxk/roc_constants.h 
b/drivers/common/cnxk/roc_constants.h
index ac7335061c..5f78823642 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -37,6 +37,8 @@
 #define PCI_DEVID_CNXK_BPHY  0xA089
 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0
 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1
+#define PCI_DEVID_CNXK_RVU_REE_PF 0xA0f4
+#define PCI_DEVID_CNXK_RVU_REE_VF 0xA0f5
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
diff --git a/drivers/common/cnxk/roc_platform.c 
b/drivers/common/cnxk/roc_platform.c
index 74dbdeceb9..ebb6225f4d 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -65,3 +65,4 @@ RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
+RTE_LOG_REGISTER_DEFAULT(cnxk_logtype_ree, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h 
b/drivers/common/cnxk/roc_platform.h
index 61d4781209..85aa6dcebc 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -197,6 +197,7 @@ extern int cnxk_logtype_npc;
 extern int cnxk_logtype_sso;
 extern int cnxk_logtype_tim;
 extern int cnxk_logtype_tm;
+extern int cnxk_logtype_ree;
 
 #define plt_err(fmt, args...)  
\
RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
@@ -222,6 +223,7 @@ extern int cnxk_logtype_tm;
 #define plt_sso_dbg(fmt, ...)  plt_dbg(sso, fmt, ##__VA_ARGS__)
 #define plt_tim_dbg(fmt, ...)  plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)   plt_dbg(tm, fmt, ##__VA_ARGS__)
+#define plt_ree_dbg(fmt, ...)  plt_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* Datapath logs */
 #define plt_dp_err(fmt, args...)   
\
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 782b90cf8d..122d411fe7 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -44,4 +44,7 @@
 /* DPI */
 #include "roc_dpi_priv.h"
 
+/* REE */
+#include "roc_ree_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..5a03b91784 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
cnxk_logtype_nix;
cnxk_logtype_npa;
cnxk_logtype_npc;
+   cnxk_logtype_ree;
cnxk_logtype_sso;
cnxk_logtype_tim;
cnxk_logtype_tm;
@@ -347,6 +348,21 @@ INTERNAL {
roc_tim_lf_enable;
roc_tim_lf_free;
roc_se_ctx_swap;
-
+   roc_ree_af_reg_read;
+   roc_ree_af_reg_write;
+   roc_ree_config_lf;
+   roc_ree_dev_fini;
+   roc_ree_dev_init;
+   roc_ree_err_intr_register;
+   roc_ree_err_intr_unregister;
+   roc_ree_iq_disable;
+   roc_ree_iq_enable;
+   roc_ree_msix_offsets_get;
+   roc_ree_qp_get_base;
+   roc_ree_queues_attach;
+   roc_ree_queues_detach;
+   roc_ree_rule_db_get;
+   roc_ree_rule_db_len_get;
+   roc_ree_rule_db_prog;
local: *;
 };
-- 
2.28.0

[PATCH v3 5/5] regex/cn9k: use cnxk infrastructure

[lironh]

From: Liron Himi 

update driver to use the REE cnxk code
replace octeontx2/otx2 with cn9k

Signed-off-by: Liron Himi 
---
 MAINTAINERS   |   8 +-
 doc/guides/platform/cnxk.rst  |   3 +
 doc/guides/platform/octeontx2.rst |   3 -
 .../regexdevs/{octeontx2.rst => cn9k.rst} |  20 +-
 .../features/{octeontx2.ini => cn9k.ini}  |   2 +-
 doc/guides/regexdevs/index.rst|   2 +-
 doc/guides/rel_notes/release_20_11.rst|   2 +-
 .../otx2_regexdev.c => cn9k/cn9k_regexdev.c}  | 405 --
 drivers/regex/cn9k/cn9k_regexdev.h|  44 ++
 .../cn9k_regexdev_compiler.c} |  34 +-
 drivers/regex/cn9k/cn9k_regexdev_compiler.h   |  11 +
 drivers/regex/{octeontx2 => cn9k}/meson.build |  10 +-
 drivers/regex/{octeontx2 => cn9k}/version.map |   0
 drivers/regex/meson.build |   2 +-
 drivers/regex/octeontx2/otx2_regexdev.h   | 109 -
 .../regex/octeontx2/otx2_regexdev_compiler.h  |  11 -
 .../regex/octeontx2/otx2_regexdev_hw_access.c | 167 
 .../regex/octeontx2/otx2_regexdev_hw_access.h | 202 -
 drivers/regex/octeontx2/otx2_regexdev_mbox.c  | 401 -
 drivers/regex/octeontx2/otx2_regexdev_mbox.h  |  38 --
 20 files changed, 269 insertions(+), 1205 deletions(-)
 rename doc/guides/regexdevs/{octeontx2.rst => cn9k.rst} (69%)
 rename doc/guides/regexdevs/features/{octeontx2.ini => cn9k.ini} (80%)
 rename drivers/regex/{octeontx2/otx2_regexdev.c => cn9k/cn9k_regexdev.c} (61%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev.h
 rename drivers/regex/{octeontx2/otx2_regexdev_compiler.c => 
cn9k/cn9k_regexdev_compiler.c} (86%)
 create mode 100644 drivers/regex/cn9k/cn9k_regexdev_compiler.h
 rename drivers/regex/{octeontx2 => cn9k}/meson.build (65%)
 rename drivers/regex/{octeontx2 => cn9k}/version.map (100%)
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_compiler.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_hw_access.h
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.c
 delete mode 100644 drivers/regex/octeontx2/otx2_regexdev_mbox.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e157e12f88..5f45b35c51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,11 +1228,11 @@ F: doc/guides/dmadevs/cnxk.rst
 RegEx Drivers
 -
 
-Marvell OCTEON TX2 regex
+Marvell OCTEON CN9K regex
 M: Liron Himi 
-F: drivers/regex/octeontx2/
-F: doc/guides/regexdevs/octeontx2.rst
-F: doc/guides/regexdevs/features/octeontx2.ini
+F: drivers/regex/cn9k/
+F: doc/guides/regexdevs/cn9k.rst
+F: doc/guides/regexdevs/features/cn9k.ini
 
 Mellanox mlx5
 M: Ori Kam 
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 88995cc70c..5213df3ccd 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -156,6 +156,9 @@ This section lists dataplane H/W block(s) available in cnxk 
SoC.
 #. **Dmadev Driver**
See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
 
+#. **Regex Device Driver**
+   See :doc:`../regexdevs/cn9k` for REE Regex device driver information.
+
 Procedure to Setup Platform
 ---
 
diff --git a/doc/guides/platform/octeontx2.rst 
b/doc/guides/platform/octeontx2.rst
index 3a3d28571c..5ab43abbdd 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -155,9 +155,6 @@ This section lists dataplane H/W block(s) available in 
OCTEON TX2 SoC.
 #. **Crypto Device Driver**
See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
-#. **Regex Device Driver**
-   See :doc:`../regexdevs/octeontx2` for REE regex device driver information.
-
 Procedure to Setup Platform
 ---
 
diff --git a/doc/guides/regexdevs/octeontx2.rst b/doc/guides/regexdevs/cn9k.rst
similarity index 69%
rename from doc/guides/regexdevs/octeontx2.rst
rename to doc/guides/regexdevs/cn9k.rst
index b39d457d60..c23c295b93 100644
--- a/doc/guides/regexdevs/octeontx2.rst
+++ b/doc/guides/regexdevs/cn9k.rst
@@ -1,20 +1,20 @@
 ..  SPDX-License-Identifier: BSD-3-Clause
 Copyright(c) 2020 Marvell International Ltd.
 
-OCTEON TX2 REE Regexdev Driver
+CN9K REE Regexdev Driver
 ==
 
-The OCTEON TX2 REE PMD (**librte_regex_octeontx2**) provides poll mode
-regexdev driver support for the inbuilt regex device found in the **Marvell 
OCTEON TX2**
+The CN9K REE PMD (**librte_regex_cn9k**) provides poll mode
+regexdev driver support for the inbuilt regex device found in the **Marvell 
CN9K**
 SoC family.
 
-More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+More information about CN9K SoC can be found at `Marvell Official Website
 `_.
 
 Features
 
 
-Features of 

vmxnet3 no longer functional on DPDK 21.11

[Lewis Donzis]

Hello. 

We just upgraded from 21.08 to 21.11 and it's rather astounding the number of 
incompatible changes in three months. Not a big deal, just kind of a surprise, 
that's all. 

Anyway, the problem is that the vmxnet3 driver is no longer functional on 
FreeBSD. 

In drivers/net/vmxnet3/vmxnet3_ethdev.c, vmxnet3_dev_start() gets an error 
calling rte_intr_enable(). So it logs "interrupt enable failed" and returns an 
error. 

In lib/eal/freebsd/eal_interrupts.c, rte_intr_enable() is returning an error 
because rte_intr_dev_fd_get(intr_handle) is returning -1. 

I don't see how that could ever return anything other than -1 since it appears 
that there is no code that ever calls rte_intr_dev_fd_set() with a value other 
than -1 on FreeBSD. Also weird to me is that even if it didn't get an error, 
the switch statement that follows looks like it will return an error in every 
case. 

Nonetheless, it worked in 21.08, and I can't quite see why the difference, so I 
must be missing something. 

For the moment, I just commented the "return -EIO" in vmxnet3_ethdev.c, and 
it's now working again, but that's obviously not the correct solution. 

Can someone who's knowledgable about this mechanism perhaps explain a little 
bit about what's going on? I'll be happy to help troubleshoot. It seems like it 
must be something simple, but I just don't see it yet. 

Thanks, 
lew 

[PATCH] common/cnxk: ensure ROC cache alignment of NPA stack size

[Ashwin Sekhar T K]

When PLT_CACHE_LINE_SIZE is set to 64B, the memzone size reserved for
NPA stack could be a multiple of 64B. In such a case, when NDC SYNC
is initiated for the NPA LF, it could go and corrupt an additional
64B bytes as NDC flushes in multiples of ROC cache line size (128B).

So ensure that NPA stack size requested is a multiple of 128B.

Signed-off-by: Ashwin Sekhar T K 
---
 drivers/common/cnxk/roc_npa.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index efcb7582eb..75fc22442f 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -205,6 +205,7 @@ static inline const struct plt_memzone *
 npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
 {
const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
+   size = PLT_ALIGN_CEIL(size, ROC_ALIGN);
 
return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
 }
-- 
2.32.0

[PATCH] common/cnxk: use cas with release semantics for batch alloc

[Ashwin Sekhar T K]

Before issuing the batch alloc, we clear the first word of
cache lines so that NPA can update the status. Make sure that
this line clear is flushed before the batch alloc is issued.

Signed-off-by: Ashwin Sekhar T K 
---
 drivers/common/cnxk/roc_io.h | 12 
 drivers/common/cnxk/roc_io_generic.h |  9 +
 drivers/common/cnxk/roc_npa.h|  2 +-
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h
index fe5f7f46d0..4f15503c29 100644
--- a/drivers/common/cnxk/roc_io.h
+++ b/drivers/common/cnxk/roc_io.h
@@ -78,6 +78,18 @@ roc_atomic64_cas(uint64_t compare, uint64_t swap, int64_t 
*ptr)
return compare;
 }
 
+static __plt_always_inline uint64_t
+roc_atomic64_casl(uint64_t compare, uint64_t swap, int64_t *ptr)
+{
+   asm volatile(PLT_CPU_FEATURE_PREAMBLE
+"casl %[compare], %[swap], [%[ptr]]\n"
+: [compare] "+r"(compare)
+: [swap] "r"(swap), [ptr] "r"(ptr)
+: "memory");
+
+   return compare;
+}
+
 static __plt_always_inline uint64_t
 roc_atomic64_add_nosync(int64_t incr, int64_t *ptr)
 {
diff --git a/drivers/common/cnxk/roc_io_generic.h 
b/drivers/common/cnxk/roc_io_generic.h
index ceaa3a38d8..5f90835c09 100644
--- a/drivers/common/cnxk/roc_io_generic.h
+++ b/drivers/common/cnxk/roc_io_generic.h
@@ -41,6 +41,15 @@ roc_atomic64_cas(uint64_t compare, uint64_t swap, int64_t 
*ptr)
return compare;
 }
 
+static __plt_always_inline uint64_t
+roc_atomic64_casl(uint64_t compare, uint64_t swap, int64_t *ptr)
+{
+   PLT_SET_USED(swap);
+   PLT_SET_USED(ptr);
+
+   return compare;
+}
+
 static inline uint64_t
 roc_atomic64_add_nosync(int64_t incr, int64_t *ptr)
 {
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 46350fdb48..19b9a9352c 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -218,7 +218,7 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, 
uint64_t *buf,
cmp.compare_s.dis_wait = dis_wait;
cmp.compare_s.count = num;
 
-   res = roc_atomic64_cas(cmp.u, (uint64_t)buf, addr);
+   res = roc_atomic64_casl(cmp.u, (uint64_t)buf, addr);
if (res != ALLOC_RESULT_ACCEPTED && res != ALLOC_RESULT_NOCORE)
return -1;
 
-- 
2.32.0

[PATCH] common/cnxk: update cpu directive in NPA assembly code

[Ashwin Sekhar T K]

Update the CPU directive in ROC NPA assembly code snippets.

Signed-off-by: Ashwin Sekhar T K 
---
 drivers/common/cnxk/roc_npa.h | 30 +-
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 46350fdb48..aeadc3d5e2 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -433,7 +433,7 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t 
*buf, unsigned int num,
switch (num) {
case 30:
asm volatile(
-   ".cpu  generic+lse\n"
+   ".arch_extension lse\n"
"mov v18.d[0], %[dst]\n"
"mov v18.d[1], %[loc]\n"
"mov v19.d[0], %[wdata]\n"
@@ -497,7 +497,7 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t 
*buf, unsigned int num,
break;
case 16:
asm volatile(
-   ".cpu  generic+lse\n"
+   ".arch_extension lse\n"
"mov x16, %[wdata]\n"
"mov x17, %[wdata]\n"
"casp x0, x1, x16, x17, [%[loc]]\n"
@@ -517,15 +517,14 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t 
*buf, unsigned int num,
"stp x12, x13, [%[dst], #96]\n"
"stp x14, x15, [%[dst], #112]\n"
:
-   : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
+   : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr)
: "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6",
  "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14",
- "x15", "x16", "x17"
-   );
+ "x15", "x16", "x17");
break;
case 8:
asm volatile(
-   ".cpu  generic+lse\n"
+   ".arch_extension lse\n"
"mov x16, %[wdata]\n"
"mov x17, %[wdata]\n"
"casp x0, x1, x16, x17, [%[loc]]\n"
@@ -537,14 +536,13 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t 
*buf, unsigned int num,
"stp x4, x5, [%[dst], #32]\n"
"stp x6, x7, [%[dst], #48]\n"
:
-   : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
+   : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr)
: "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6",
- "x7", "x16", "x17"
-   );
+ "x7", "x16", "x17");
break;
case 4:
asm volatile(
-   ".cpu  generic+lse\n"
+   ".arch_extension lse\n"
"mov x16, %[wdata]\n"
"mov x17, %[wdata]\n"
"casp x0, x1, x16, x17, [%[loc]]\n"
@@ -552,21 +550,19 @@ roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t 
*buf, unsigned int num,
"stp x0, x1, [%[dst]]\n"
"stp x2, x3, [%[dst], #16]\n"
:
-   : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
-   : "memory", "x0", "x1", "x2", "x3", "x16", "x17"
-   );
+   : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr)
+   : "memory", "x0", "x1", "x2", "x3", "x16", "x17");
break;
case 2:
asm volatile(
-   ".cpu  generic+lse\n"
+   ".arch_extension lse\n"
"mov x16, %[wdata]\n"
"mov x17, %[wdata]\n"
"casp x0, x1, x16, x17, [%[loc]]\n"
"stp x0, x1, [%[dst]]\n"
:
-   : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
-   : "memory", "x0", "x1", "x16", "x17"
-   );
+   : [wdata] "r"(wdata), [dst] "r"(buf), [loc] "r"(addr)
+   : "memory", "x0", "x1", "x16", "x17");
break;
case 1:
buf[0] = roc_npa_aura_op_alloc(aura_handle, drop);
-- 
2.32.0

[PATCH 0/3] Wait for NPA pools to get filled

[Ashwin Sekhar T K]

NPA could take some time to reflect the pointers which
has been freed into pools. So, after populating a pool
with pointers, wait until the populated pointers are
reflected in the pool.

Ashwin Sekhar T K (3):
  common/cnxk: add support to wait for pool filling
  common/cnxk: wait for sqb pool to fill
  common/cnxk: wait for xaq pool to fill

 drivers/common/cnxk/roc_nix_queue.c | 10 ++
 drivers/common/cnxk/roc_npa.h   | 26 ++
 drivers/common/cnxk/roc_sso.c   |  9 +
 3 files changed, 45 insertions(+)

-- 
2.32.0

[PATCH 1/3] common/cnxk: add support to wait for pool filling

[Ashwin Sekhar T K]

Add roc_npa_aura_op_available_wait() API which can be used to wait
until an NPA pool gets filled up to a certain count of pointers.

Signed-off-by: Ashwin Sekhar T K 
---
 drivers/common/cnxk/roc_npa.h | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 46350fdb48..d05c5c4af4 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -155,6 +155,32 @@ roc_npa_aura_op_available(uint64_t aura_handle)
return reg & 0xF;
 }
 
+/* Wait for a given timeout, repeatedly checking whether the available
+ * pointers has reached the given count. Returns the available pointer
+ * count if it has reached the given count or if timeout has expired
+ */
+static inline uint32_t
+roc_npa_aura_op_available_wait(uint64_t aura_handle, uint32_t count,
+  uint32_t tmo_ms)
+{
+#define OP_AVAIL_WAIT_MS_DEFAULT   (100)
+#define OP_AVAIL_CHECK_INTERVAL_MS (1)
+   uint32_t op_avail;
+   int retry;
+
+   tmo_ms = tmo_ms ? tmo_ms : OP_AVAIL_WAIT_MS_DEFAULT;
+
+   retry = tmo_ms / OP_AVAIL_CHECK_INTERVAL_MS;
+   op_avail = roc_npa_aura_op_available(aura_handle);
+   while (retry && (op_avail < count)) {
+   plt_delay_ms(OP_AVAIL_CHECK_INTERVAL_MS);
+   op_avail = roc_npa_aura_op_available(aura_handle);
+   retry--;
+   }
+
+   return op_avail;
+}
+
 static inline uint64_t
 roc_npa_pool_op_performance_counter(uint64_t aura_handle, const int drop)
 {
-- 
2.32.0

[PATCH 2/3] common/cnxk: wait for sqb pool to fill

[Ashwin Sekhar T K]

Wait for SQB pool to get filled with the freed pointers
before proceeding.

Signed-off-by: Ashwin Sekhar T K 
---
 drivers/common/cnxk/roc_nix_queue.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix_queue.c 
b/drivers/common/cnxk/roc_nix_queue.c
index c8c8401d81..c638cd43e4 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -638,11 +638,21 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct 
roc_nix_sq *sq)
roc_npa_aura_op_free(sq->aura_handle, 0, iova);
iova += blk_sz;
}
+
+   if (roc_npa_aura_op_available_wait(sq->aura_handle, NIX_MAX_SQB, 0) !=
+   NIX_MAX_SQB) {
+   plt_err("Failed to free all pointers to the pool");
+   rc = NIX_ERR_NO_MEM;
+   goto npa_fail;
+   }
+
roc_npa_aura_op_range_set(sq->aura_handle, (uint64_t)sq->sqe_mem, iova);
roc_npa_aura_limit_modify(sq->aura_handle, sq->nb_sqb_bufs);
sq->aura_sqb_bufs = NIX_MAX_SQB;
 
return rc;
+npa_fail:
+   plt_free(sq->sqe_mem);
 nomem:
roc_npa_pool_destroy(sq->aura_handle);
 fail:
-- 
2.32.0

[PATCH 3/3] common/cnxk: wait for xaq pool to fill

[Ashwin Sekhar T K]

Wait for XAQ pool to get filled with the freed pointers
before proceeding.

Signed-off-by: Ashwin Sekhar T K 
---
 drivers/common/cnxk/roc_sso.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c
index 45ff16ca0e..c1aa3324be 100644
--- a/drivers/common/cnxk/roc_sso.c
+++ b/drivers/common/cnxk/roc_sso.c
@@ -453,6 +453,13 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct 
roc_sso_xaq_data *xaq,
}
roc_npa_aura_op_range_set(xaq->aura_handle, (uint64_t)xaq->mem, iova);
 
+   if (roc_npa_aura_op_available_wait(xaq->aura_handle, xaq->nb_xaq, 0) !=
+   xaq->nb_xaq) {
+   plt_err("Failed to free all pointers to the pool");
+   rc = -ENOMEM;
+   goto npa_fill_fail;
+   }
+
/* When SW does addwork (enqueue) check if there is space in XAQ by
 * comparing fc_addr above against the xaq_lmt calculated below.
 * There should be a minimum headroom of 7 XAQs per HWGRP for SSO
@@ -461,6 +468,8 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct 
roc_sso_xaq_data *xaq,
xaq->xaq_lmt = xaq->nb_xaq - (nb_hwgrp * SSO_XAQ_CACHE_CNT);
 
return 0;
+npa_fill_fail:
+   roc_npa_pool_destroy(xaq->aura_handle);
 npa_fail:
plt_free(xaq->mem);
 free_fc:
-- 
2.32.0

[PATCH 1/2] net/cnxk: update meter bpf ID in rq

[Rakesh Kudurumalla]

Patch updates configured meter bpf is in rq context
during meter creation

Signed-off-by: Rakesh Kudurumalla 
---
 drivers/net/cnxk/cn10k_rte_flow.c  |  9 -
 drivers/net/cnxk/cnxk_ethdev_mtr.c | 25 ++---
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rte_flow.c 
b/drivers/net/cnxk/cn10k_rte_flow.c
index b830abe63e..402bb1c72f 100644
--- a/drivers/net/cnxk/cn10k_rte_flow.c
+++ b/drivers/net/cnxk/cn10k_rte_flow.c
@@ -36,20 +36,20 @@ cn10k_mtr_configure(struct rte_eth_dev *eth_dev,
for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) {
mtr_conf = (const struct rte_flow_action_meter
-   *)(actions->conf);
+   *)(actions[i].conf);
mtr_id = mtr_conf->mtr_id;
is_mtr_act = true;
}
if (actions[i].type == RTE_FLOW_ACTION_TYPE_QUEUE) {
q_conf = (const struct rte_flow_action_queue
- *)(actions->conf);
+ *)(actions[i].conf);
if (is_mtr_act)
nix_mtr_rq_update(eth_dev, mtr_id, 1,
  &q_conf->index);
}
if (actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
rss_conf = (const struct rte_flow_action_rss
-   *)(actions->conf);
+   *)(actions[i].conf);
if (is_mtr_act)
nix_mtr_rq_update(eth_dev, mtr_id,
  rss_conf->queue_num,
@@ -98,7 +98,7 @@ cn10k_rss_action_validate(struct rte_eth_dev *eth_dev,
return -EINVAL;
}
 
-   if (eth_dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_RSS) {
+   if (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
plt_err("multi-queue mode is disabled");
return -ENOTSUP;
}
@@ -171,7 +171,6 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct 
rte_flow_attr *attr,
return NULL;
}
}
-
for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) {
mtr = (const struct rte_flow_action_meter *)actions[i]
diff --git a/drivers/net/cnxk/cnxk_ethdev_mtr.c 
b/drivers/net/cnxk/cnxk_ethdev_mtr.c
index 39d8563826..a36fcb8aaf 100644
--- a/drivers/net/cnxk/cnxk_ethdev_mtr.c
+++ b/drivers/net/cnxk/cnxk_ethdev_mtr.c
@@ -35,7 +35,6 @@ static struct rte_mtr_capabilities mtr_capa = {
.chaining_n_mtrs_per_flow_max = NIX_MTR_COUNT_PER_FLOW,
.chaining_use_prev_mtr_color_supported = true,
.chaining_use_prev_mtr_color_enforced = true,
-   .meter_rate_max = NIX_BPF_RATE_MAX / 8, /* Bytes per second */
.color_aware_srtcm_rfc2697_supported = true,
.color_aware_trtcm_rfc2698_supported = true,
.color_aware_trtcm_rfc4115_supported = true,
@@ -180,20 +179,20 @@ cnxk_nix_mtr_capabilities_get(struct rte_eth_dev *dev,
  struct rte_mtr_capabilities *capa,
  struct rte_mtr_error *error)
 {
-   struct cnxk_eth_dev *eth_dev = cnxk_eth_pmd_priv(dev);
-   uint16_t count[ROC_NIX_BPF_LEVEL_MAX] = {0};
uint8_t lvl_mask = ROC_NIX_BPF_LEVEL_F_LEAF | ROC_NIX_BPF_LEVEL_F_MID |
   ROC_NIX_BPF_LEVEL_F_TOP;
+   struct cnxk_eth_dev *eth_dev = cnxk_eth_pmd_priv(dev);
+   uint16_t count[ROC_NIX_BPF_LEVEL_MAX] = {0};
struct roc_nix *nix = ð_dev->nix;
-   int rc;
-   int i;
+   uint32_t time_unit;
+   int rc, i;
 
RTE_SET_USED(dev);
 
if (!capa)
return -rte_mtr_error_set(error, EINVAL,
-   RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,
-   "NULL input parameter");
+ RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,
+ "NULL input parameter");
 
rc = roc_nix_bpf_count_get(nix, lvl_mask, count);
if (rc)
@@ -207,6 +206,15 @@ cnxk_nix_mtr_capabilities_get(struct rte_eth_dev *dev,
mtr_capa.meter_trtcm_rfc4115_n_max = mtr_capa.n_max;
mtr_capa.meter_policy_n_max = mtr_capa.n_max;
 
+   rc = roc_nix_bpf_timeunit_get(nix, &time_unit);
+   if (rc)
+   return rc;
+
+   mtr_capa.meter_rate_max =
+   NIX_BPF_RATE(time_unit, NIX_BPF_MAX_RATE_EXPONENT,
+NIX_BPF_MAX_RATE_MANTISSA, 0) /
+   8;
+
*capa = mtr_capa;
return 0;
 }
@@

[PATCH 2/2] common/cnxk: update meter algorithm in band profile

[Rakesh Kudurumalla]

Patch updates meter algorithm in nix band profile
structure

Signed-off-by: Rakesh Kudurumalla 
---
 drivers/common/cnxk/hw/nix.h  |  5 ---
 drivers/common/cnxk/roc_nix_bpf.c | 61 +--
 2 files changed, 17 insertions(+), 49 deletions(-)

diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index dd2ebecc6a..6931f1d1d2 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -2133,11 +2133,6 @@ struct nix_lso_format {
((NIX_BPF_RATE_CONST * ((256 + (mantissa)) << (exponent))) /   \
 (((1ull << (div_exp)) * 256 * policer_timeunit)))
 
-/* Meter rate limits in Bits/Sec */
-#define NIX_BPF_RATE_MIN NIX_BPF_RATE(10, 0, 0, 0)
-#define NIX_BPF_RATE_MAX   
\
-   NIX_BPF_RATE(1, NIX_BPF_MAX_RATE_EXPONENT, NIX_BPF_MAX_RATE_MANTISSA, 0)
-
 #define NIX_BPF_DEFAULT_ADJUST_MANTISSA 511
 #define NIX_BPF_DEFAULT_ADJUST_EXPONENT 0
 
diff --git a/drivers/common/cnxk/roc_nix_bpf.c 
b/drivers/common/cnxk/roc_nix_bpf.c
index 6996a54be0..46ed91e87b 100644
--- a/drivers/common/cnxk/roc_nix_bpf.c
+++ b/drivers/common/cnxk/roc_nix_bpf.c
@@ -38,48 +38,23 @@ meter_rate_to_nix(uint64_t value, uint64_t *exponent_p, 
uint64_t *mantissa_p,
  uint64_t *div_exp_p, uint32_t timeunit_p)
 {
uint64_t div_exp, exponent, mantissa;
-   uint32_t time_us = timeunit_p;
+   uint32_t time_ns = timeunit_p;
 
/* Boundary checks */
-   if (value < NIX_BPF_RATE_MIN || value > NIX_BPF_RATE_MAX)
+   if (value < NIX_BPF_RATE(time_ns, 0, 0, 0) ||
+   value > NIX_BPF_RATE(time_ns, NIX_BPF_MAX_RATE_EXPONENT,
+NIX_BPF_MAX_RATE_MANTISSA, 0))
return 0;
 
-   if (value <= NIX_BPF_RATE(time_us, 0, 0, 0)) {
-   /* Calculate rate div_exp and mantissa using
-* the following formula:
-*
-* value = (2E6 * (256 + mantissa)
-*  / ((1 << div_exp) * 256))
-*/
-   div_exp = 0;
-   exponent = 0;
-   mantissa = NIX_BPF_MAX_RATE_MANTISSA;
-
-   while (value < (NIX_BPF_RATE_CONST / (1 << div_exp)))
-   div_exp += 1;
-
-   while (value < ((NIX_BPF_RATE_CONST * (256 + mantissa)) /
-   ((1 << div_exp) * 256)))
-   mantissa -= 1;
-   } else {
-   /* Calculate rate exponent and mantissa using
-* the following formula:
-*
-* value = (2E6 * ((256 + mantissa) << exponent)) / 256
-*
-*/
-   div_exp = 0;
-   exponent = NIX_BPF_MAX_RATE_EXPONENT;
-   mantissa = NIX_BPF_MAX_RATE_MANTISSA;
-
-   while (value < (NIX_BPF_RATE_CONST * (1 << exponent)))
-   exponent -= 1;
-
-   while (value <
-  ((NIX_BPF_RATE_CONST * ((256 + mantissa) << exponent)) /
-   256))
-   mantissa -= 1;
-   }
+   div_exp = 0;
+   exponent = NIX_BPF_MAX_RATE_EXPONENT;
+   mantissa = NIX_BPF_MAX_RATE_MANTISSA;
+
+   while (value < (NIX_BPF_RATE(time_ns, exponent, 0, 0)))
+   exponent -= 1;
+
+   while (value < (NIX_BPF_RATE(time_ns, exponent, mantissa, 0)))
+   mantissa -= 1;
 
if (div_exp > NIX_BPF_MAX_RATE_DIV_EXP ||
exponent > NIX_BPF_MAX_RATE_EXPONENT ||
@@ -94,7 +69,7 @@ meter_rate_to_nix(uint64_t value, uint64_t *exponent_p, 
uint64_t *mantissa_p,
*mantissa_p = mantissa;
 
/* Calculate real rate value */
-   return NIX_BPF_RATE(time_us, exponent, mantissa, div_exp);
+   return NIX_BPF_RATE(time_ns, exponent, mantissa, div_exp);
 }
 
 static inline uint64_t
@@ -195,11 +170,7 @@ nix_precolor_conv_table_write(struct roc_nix *roc_nix, 
uint64_t val,
int64_t *addr;
 
addr = PLT_PTR_ADD(nix->base, off);
-   /* FIXME: Currently writing to this register throwing kernel dump.
-* plt_write64(val, addr);
-*/
-   PLT_SET_USED(val);
-   PLT_SET_USED(addr);
+   plt_write64(val, addr);
 }
 
 static uint8_t
@@ -665,6 +636,7 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,
 
aq->prof.lmode = cfg->lmode;
aq->prof.icolor = cfg->icolor;
+   aq->prof.meter_algo = cfg->alg;
aq->prof.pc_mode = cfg->pc_mode;
aq->prof.tnl_ena = cfg->tnl_ena;
aq->prof.gc_action = cfg->action[ROC_NIX_BPF_COLOR_GREEN];
@@ -673,6 +645,7 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t id,
 
aq->prof_mask.lmode = ~(aq->prof_mask.lmode);
aq->prof_mask.icolor = ~(aq->prof_mask.icolor);
+   aq->prof_mask.meter_algo = ~(aq->prof_mask.meter_algo);
aq->prof_mask.pc_mode = ~(aq->prof_mask.pc_mode);
aq->

RE: [PATCH 2/2] common/cnxk: update meter algorithm in band profile

[Sunil Kumar Kori]

>-Original Message-
>From: Rakesh Kudurumalla 
>Sent: Tuesday, November 30, 2021 12:12 PM
>To: Nithin Kumar Dabilpuram ; Kiran Kumar
>Kokkilagadda ; Sunil Kumar Kori
>; Satha Koteswara Rao Kottidi
>
>Cc: dev@dpdk.org; Rakesh Kudurumalla 
>Subject: [PATCH 2/2] common/cnxk: update meter algorithm in band profile
>
>Patch updates meter algorithm in nix band profile structure
>
>Signed-off-by: Rakesh Kudurumalla 
>---
> drivers/common/cnxk/hw/nix.h  |  5 ---
> drivers/common/cnxk/roc_nix_bpf.c | 61 +--
> 2 files changed, 17 insertions(+), 49 deletions(-)
>
>diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
>index dd2ebecc6a..6931f1d1d2 100644
>--- a/drivers/common/cnxk/hw/nix.h
>+++ b/drivers/common/cnxk/hw/nix.h
>@@ -2133,11 +2133,6 @@ struct nix_lso_format {
>   ((NIX_BPF_RATE_CONST * ((256 + (mantissa)) << (exponent))) /   \
>(((1ull << (div_exp)) * 256 * policer_timeunit)))
>
>-/* Meter rate limits in Bits/Sec */
>-#define NIX_BPF_RATE_MIN NIX_BPF_RATE(10, 0, 0, 0)
>-#define NIX_BPF_RATE_MAX  
> \
>-  NIX_BPF_RATE(1, NIX_BPF_MAX_RATE_EXPONENT,
>NIX_BPF_MAX_RATE_MANTISSA, 0)
>-
> #define NIX_BPF_DEFAULT_ADJUST_MANTISSA 511  #define
>NIX_BPF_DEFAULT_ADJUST_EXPONENT 0
>
>diff --git a/drivers/common/cnxk/roc_nix_bpf.c
>b/drivers/common/cnxk/roc_nix_bpf.c
>index 6996a54be0..46ed91e87b 100644
>--- a/drivers/common/cnxk/roc_nix_bpf.c
>+++ b/drivers/common/cnxk/roc_nix_bpf.c
>@@ -38,48 +38,23 @@ meter_rate_to_nix(uint64_t value, uint64_t
>*exponent_p, uint64_t *mantissa_p,
> uint64_t *div_exp_p, uint32_t timeunit_p)  {
>   uint64_t div_exp, exponent, mantissa;
>-  uint32_t time_us = timeunit_p;
>+  uint32_t time_ns = timeunit_p;
>
>   /* Boundary checks */
>-  if (value < NIX_BPF_RATE_MIN || value > NIX_BPF_RATE_MAX)
>+  if (value < NIX_BPF_RATE(time_ns, 0, 0, 0) ||
>+  value > NIX_BPF_RATE(time_ns, NIX_BPF_MAX_RATE_EXPONENT,
>+   NIX_BPF_MAX_RATE_MANTISSA, 0))
>   return 0;
>
>-  if (value <= NIX_BPF_RATE(time_us, 0, 0, 0)) {
>-  /* Calculate rate div_exp and mantissa using
>-   * the following formula:
>-   *
>-   * value = (2E6 * (256 + mantissa)
>-   *  / ((1 << div_exp) * 256))
>-   */
>-  div_exp = 0;
>-  exponent = 0;
>-  mantissa = NIX_BPF_MAX_RATE_MANTISSA;
>-
>-  while (value < (NIX_BPF_RATE_CONST / (1 << div_exp)))
>-  div_exp += 1;
>-
>-  while (value < ((NIX_BPF_RATE_CONST * (256 + mantissa)) /
>-  ((1 << div_exp) * 256)))
>-  mantissa -= 1;
>-  } else {
>-  /* Calculate rate exponent and mantissa using
>-   * the following formula:
>-   *
>-   * value = (2E6 * ((256 + mantissa) << exponent)) / 256
>-   *
>-   */
>-  div_exp = 0;
>-  exponent = NIX_BPF_MAX_RATE_EXPONENT;
>-  mantissa = NIX_BPF_MAX_RATE_MANTISSA;
>-
>-  while (value < (NIX_BPF_RATE_CONST * (1 << exponent)))
>-  exponent -= 1;
>-
>-  while (value <
>- ((NIX_BPF_RATE_CONST * ((256 + mantissa) << exponent))
>/
>-  256))
>-  mantissa -= 1;
>-  }
>+  div_exp = 0;
>+  exponent = NIX_BPF_MAX_RATE_EXPONENT;
>+  mantissa = NIX_BPF_MAX_RATE_MANTISSA;
>+
>+  while (value < (NIX_BPF_RATE(time_ns, exponent, 0, 0)))
>+  exponent -= 1;
>+
>+  while (value < (NIX_BPF_RATE(time_ns, exponent, mantissa, 0)))
>+  mantissa -= 1;
>
>   if (div_exp > NIX_BPF_MAX_RATE_DIV_EXP ||
>   exponent > NIX_BPF_MAX_RATE_EXPONENT || @@ -94,7 +69,7
>@@ meter_rate_to_nix(uint64_t value, uint64_t *exponent_p, uint64_t
>*mantissa_p,
>   *mantissa_p = mantissa;
>
>   /* Calculate real rate value */
>-  return NIX_BPF_RATE(time_us, exponent, mantissa, div_exp);
>+  return NIX_BPF_RATE(time_ns, exponent, mantissa, div_exp);
> }
>
> static inline uint64_t
>@@ -195,11 +170,7 @@ nix_precolor_conv_table_write(struct roc_nix
>*roc_nix, uint64_t val,
>   int64_t *addr;
>
>   addr = PLT_PTR_ADD(nix->base, off);
>-  /* FIXME: Currently writing to this register throwing kernel dump.
>-   * plt_write64(val, addr);
>-   */
>-  PLT_SET_USED(val);
>-  PLT_SET_USED(addr);
>+  plt_write64(val, addr);
> }
>
> static uint8_t
>@@ -665,6 +636,7 @@ roc_nix_bpf_config(struct roc_nix *roc_nix, uint16_t
>id,
>
>   aq->prof.lmode = cfg->lmode;
>   aq->prof.icolor = cfg->icolor;
>+  aq->prof.meter_algo = cfg->alg;
>   aq->prof.pc_mode = cfg->pc_mode;
>   aq->prof.tnl_ena = cfg->tnl_ena;
>   aq->prof.gc_action 

RE: [PATCH 1/2] net/cnxk: update meter bpf ID in rq

[Sunil Kumar Kori]

>-Original Message-
>From: Rakesh Kudurumalla 
>Sent: Tuesday, November 30, 2021 12:12 PM
>To: Nithin Kumar Dabilpuram ; Kiran Kumar
>Kokkilagadda ; Sunil Kumar Kori
>; Satha Koteswara Rao Kottidi
>
>Cc: dev@dpdk.org; Rakesh Kudurumalla 
>Subject: [PATCH 1/2] net/cnxk: update meter bpf ID in rq
>
>Patch updates configured meter bpf is in rq context during meter creation
>
>Signed-off-by: Rakesh Kudurumalla 
>---
> drivers/net/cnxk/cn10k_rte_flow.c  |  9 -
>drivers/net/cnxk/cnxk_ethdev_mtr.c | 25 ++---
> 2 files changed, 22 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/net/cnxk/cn10k_rte_flow.c
>b/drivers/net/cnxk/cn10k_rte_flow.c
>index b830abe63e..402bb1c72f 100644
>--- a/drivers/net/cnxk/cn10k_rte_flow.c
>+++ b/drivers/net/cnxk/cn10k_rte_flow.c
>@@ -36,20 +36,20 @@ cn10k_mtr_configure(struct rte_eth_dev *eth_dev,
>   for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
>   if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) {
>   mtr_conf = (const struct rte_flow_action_meter
>-  *)(actions->conf);
>+  *)(actions[i].conf);
>   mtr_id = mtr_conf->mtr_id;
>   is_mtr_act = true;
>   }
>   if (actions[i].type == RTE_FLOW_ACTION_TYPE_QUEUE) {
>   q_conf = (const struct rte_flow_action_queue
>-*)(actions->conf);
>+*)(actions[i].conf);
>   if (is_mtr_act)
>   nix_mtr_rq_update(eth_dev, mtr_id, 1,
> &q_conf->index);
>   }
>   if (actions[i].type == RTE_FLOW_ACTION_TYPE_RSS) {
>   rss_conf = (const struct rte_flow_action_rss
>-  *)(actions->conf);
>+  *)(actions[i].conf);
>   if (is_mtr_act)
>   nix_mtr_rq_update(eth_dev, mtr_id,
> rss_conf->queue_num,
>@@ -98,7 +98,7 @@ cn10k_rss_action_validate(struct rte_eth_dev *eth_dev,
>   return -EINVAL;
>   }
>
>-  if (eth_dev->data->dev_conf.rxmode.mq_mode !=
>RTE_ETH_MQ_RX_RSS) {
>+  if (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
>   plt_err("multi-queue mode is disabled");
>   return -ENOTSUP;
>   }
>@@ -171,7 +171,6 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const
>struct rte_flow_attr *attr,
>   return NULL;
>   }
>   }
>-
>   for (i = 0; actions[i].type != RTE_FLOW_ACTION_TYPE_END; i++) {
>   if (actions[i].type == RTE_FLOW_ACTION_TYPE_METER) {
>   mtr = (const struct rte_flow_action_meter *)actions[i]
>diff --git a/drivers/net/cnxk/cnxk_ethdev_mtr.c
>b/drivers/net/cnxk/cnxk_ethdev_mtr.c
>index 39d8563826..a36fcb8aaf 100644
>--- a/drivers/net/cnxk/cnxk_ethdev_mtr.c
>+++ b/drivers/net/cnxk/cnxk_ethdev_mtr.c
>@@ -35,7 +35,6 @@ static struct rte_mtr_capabilities mtr_capa = {
>   .chaining_n_mtrs_per_flow_max = NIX_MTR_COUNT_PER_FLOW,
>   .chaining_use_prev_mtr_color_supported = true,
>   .chaining_use_prev_mtr_color_enforced = true,
>-  .meter_rate_max = NIX_BPF_RATE_MAX / 8, /* Bytes per second */
>   .color_aware_srtcm_rfc2697_supported = true,
>   .color_aware_trtcm_rfc2698_supported = true,
>   .color_aware_trtcm_rfc4115_supported = true, @@ -180,20 +179,20
>@@ cnxk_nix_mtr_capabilities_get(struct rte_eth_dev *dev,
> struct rte_mtr_capabilities *capa,
> struct rte_mtr_error *error)
> {
>-  struct cnxk_eth_dev *eth_dev = cnxk_eth_pmd_priv(dev);
>-  uint16_t count[ROC_NIX_BPF_LEVEL_MAX] = {0};
>   uint8_t lvl_mask = ROC_NIX_BPF_LEVEL_F_LEAF |
>ROC_NIX_BPF_LEVEL_F_MID |
>  ROC_NIX_BPF_LEVEL_F_TOP;
>+  struct cnxk_eth_dev *eth_dev = cnxk_eth_pmd_priv(dev);
>+  uint16_t count[ROC_NIX_BPF_LEVEL_MAX] = {0};
>   struct roc_nix *nix = ð_dev->nix;
>-  int rc;
>-  int i;
>+  uint32_t time_unit;
>+  int rc, i;
>
>   RTE_SET_USED(dev);
>
>   if (!capa)
>   return -rte_mtr_error_set(error, EINVAL,
>-  RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,
>-  "NULL input parameter");
>+
>RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL,
>+"NULL input parameter");
>
>   rc = roc_nix_bpf_count_get(nix, lvl_mask, count);
>   if (rc)
>@@ -207,6 +206,15 @@ cnxk_nix_mtr_capabilities_get(struct rte_eth_dev
>*dev,
>   mtr_capa.meter_trtcm_rfc4115_n_max = mtr_capa.n_max;
>   mtr_capa.meter_policy_n_max = mtr_capa.n_max;
>
>+  rc = roc_nix_bpf_timeunit_get(n

Re: [PATCH] net/vmxnet3: add spinlocks to register command access

[Yong Wang]

-Original Message-
From: "sahithi.sin...@oracle.com" 
Date: Monday, November 8, 2021 at 12:23 AM
To: Yong Wang 
Cc: "dev@dpdk.org" , Sahithi Singam 
Subject: [PATCH] net/vmxnet3: add spinlocks to register command access

From: Sahithi Singam 

At present, there are no spinlocks around register command access.
This resulted in a race condition when two threads running on
two different cores invoked link_update function at the same time
to get link status. Due to this race condition, one of the threads
reported false link status value.

Signed-off-by: Sahithi Singam 
---

Thanks Sahithi for the patch.  As we discussed offline, in DPDK, the 
expectation is that control level synchronization should be handled by the 
application.  In my knowledge, currently no PMD guarantee such synchronization 
at driver callback level.  It makes more sense to have the application manages 
the synchronization as most likely it needs to work with multiple PMDs and it's 
better to keep this behavior consistent across all PMDs (i.e, it does not make 
a lot of sense to support this behavior only in one particular PMD).

 drivers/net/vmxnet3/vmxnet3_ethdev.c | 37 
 drivers/net/vmxnet3/vmxnet3_ethdev.h |  1 +
 drivers/net/vmxnet3/vmxnet3_rxtx.c   |  2 ++
 3 files changed, 40 insertions(+)

diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c 
b/drivers/net/vmxnet3/vmxnet3_ethdev.c
index d1ef1cad08..d4a433e0db 100644
--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c
+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c
@@ -252,9 +252,11 @@ eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
 {
uint16 txdata_desc_size;

+   rte_spinlock_lock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
   VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
+   rte_spinlock_unlock(&hw->cmd_lock);

return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
@@ -285,6 +287,7 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+   rte_spinlock_init(&hw->cmd_lock);

/* extra mbuf field is required to guess MSS */
vmxnet3_segs_dynfield_offset =
@@ -375,7 +378,9 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);

/* Put device in Quiesce Mode */
+   rte_spinlock_lock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
+   rte_spinlock_unlock(&hw->cmd_lock);

/* allow untagged pkts */
VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
@@ -451,9 +456,11 @@ vmxnet3_alloc_intr_resources(struct rte_eth_dev *dev)
int nvec = 1; /* for link event */

/* intr settings */
+   rte_spinlock_lock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
   VMXNET3_CMD_GET_CONF_INTR);
cfg = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
+   rte_spinlock_unlock(&hw->cmd_lock);
hw->intr.type = cfg & 0x3;
hw->intr.mask_mode = (cfg >> 2) & 0x3;

@@ -910,8 +917,10 @@ vmxnet3_dev_start(struct rte_eth_dev *dev)
   VMXNET3_GET_ADDR_HI(hw->sharedPA));

/* Activate device by register write */
+   rte_spinlock_lock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
+   rte_spinlock_unlock(&hw->cmd_lock);

if (ret != 0) {
PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
@@ -921,9 +930,11 @@ vmxnet3_dev_start(struct rte_eth_dev *dev)
/* Setup memory region for rx buffers */
ret = vmxnet3_dev_setup_memreg(dev);
if (ret == 0) {
+   rte_spinlock_lock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
   VMXNET3_CMD_REGISTER_MEMREGS);
ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
+   rte_spinlock_unlock(&hw->cmd_lock);
if (ret != 0)
PMD_INIT_LOG(DEBUG,
 "Failed in setup memory region cmd\n");
@@ -1027,12 +1038,16 @@ vmxnet3_dev_stop(struct rte_eth_dev *dev)
rte_intr_vec_list_free(intr_handle);

/* quiesce the device first */
+   rte_spinlock_lock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
+   rte_spinlock_unlock(&hw->cmd_lock);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);

/*

RE: [dpdk-dev] [Bug 826] red_autotest random failures

[Liguzinski, WojciechX]

Ok, thanks Brandon for the tip :)
Let’s see if I can setup the machine with such configuration.

Cheers,
Wojciech

From: Brandon Lo 
Sent: Monday, November 29, 2021 6:58 PM
To: Liguzinski, WojciechX 
Cc: Lincoln Lavoie ; Dumitrescu, Cristian 
; Thomas Monjalon ; David 
Marchand ; Ajmera, Megha ; 
Singh, Jasvinder ; dev ; Aaron Conole 
; Yigit, Ferruh ; c...@dpdk.org; 
Zegota, AnnaX 
Subject: Re: [dpdk-dev] [Bug 826] red_autotest random failures

On Wed, Nov 24, 2021 at 2:48 AM Liguzinski, WojciechX 
mailto:wojciechx.liguzin...@intel.com>> wrote:
Hi,

Thanks Lincoln, I will also have a try with such script.

Cheers,
Wojciech

Hello Wojciech,

I also recommend trying to run the test with around 4GB of RAM and 2GB of 
hugepages to see if it fails. That is roughly the number of resources we have 
per machine that is completely dedicated to unit tests. The amount of RAM 
available can sometimes increase depending on how many jobs are running per 
machine, but 4GB is the lowest it can go for the unit test job.

Thanks,
Brandon



--
Brandon Lo
UNH InterOperability Laboratory
21 Madbury Rd, Suite 100, Durham, NH 03824
b...@iol.unh.edu
www.iol.unh.edu