[PATCH] D51093: [ARM] Set __ARM_FEATURE_SIMD32 for +dsp cores
samparker created this revision.
samparker added reviewers: erichkeane, t.p.northover, SjoerdMeijer.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.
__ARM_FEATURE_DSP is already set for targets with the +dsp feature. In the
backend, this target feature is also used to represent the availability of the
of the instructions that the ACLE guard through the __ARM_FEATURE_SIMD32 macro.
So set this macro for cores later than V6 and that the target parser, or user,
reports that the 'dsp' instructions are supported.
https://reviews.llvm.org/D51093
Files:
lib/Basic/Targets/ARM.cpp
test/Preprocessor/arm-acle-6.4.c
Index: test/Preprocessor/arm-acle-6.4.c
===
--- test/Preprocessor/arm-acle-6.4.c
+++ test/Preprocessor/arm-acle-6.4.c
@@ -174,10 +174,13 @@
// CHECK-V7M: __ARM_FEATURE_SAT 1
// CHECK-V7M: __ARM_FEATURE_UNALIGNED 1
-// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-V7EM
+// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m4 -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m7 -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m33 -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
-// CHECK-V7EM: __ARM_FEATURE_DSP 1
-// CHECK-V7EM: __ARM_FEATURE_SIMD32 1
+// CHECK-M-DSP: __ARM_FEATURE_DSP 1
+// CHECK-M-DSP: __ARM_FEATURE_SIMD32 1
// RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-V8A
Index: lib/Basic/Targets/ARM.cpp
===
--- lib/Basic/Targets/ARM.cpp
+++ lib/Basic/Targets/ARM.cpp
@@ -661,7 +661,7 @@
}
// ACLE 6.4.9 32-bit SIMD instructions
- if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
+ if ((ArchVersion >= 6 && DSP))
Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
// ACLE 6.4.10 Hardware Integer Divide
Index: test/Preprocessor/arm-acle-6.4.c
===
--- test/Preprocessor/arm-acle-6.4.c
+++ test/Preprocessor/arm-acle-6.4.c
@@ -174,10 +174,13 @@
// CHECK-V7M: __ARM_FEATURE_SAT 1
// CHECK-V7M: __ARM_FEATURE_UNALIGNED 1
-// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7EM
+// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m33 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
-// CHECK-V7EM: __ARM_FEATURE_DSP 1
-// CHECK-V7EM: __ARM_FEATURE_SIMD32 1
+// CHECK-M-DSP: __ARM_FEATURE_DSP 1
+// CHECK-M-DSP: __ARM_FEATURE_SIMD32 1
// RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V8A
Index: lib/Basic/Targets/ARM.cpp
===
--- lib/Basic/Targets/ARM.cpp
+++ lib/Basic/Targets/ARM.cpp
@@ -661,7 +661,7 @@
}
// ACLE 6.4.9 32-bit SIMD instructions
- if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
+ if ((ArchVersion >= 6 && DSP))
Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
// ACLE 6.4.10 Hardware Integer Divide
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[PATCH] D51093: [ARM] Set __ARM_FEATURE_SIMD32 for +dsp cores
samparker updated this revision to Diff 161925.
samparker added a comment.
Added test for armv8m.main+dsp.
https://reviews.llvm.org/D51093
Files:
lib/Basic/Targets/ARM.cpp
test/Preprocessor/arm-acle-6.4.c
Index: test/Preprocessor/arm-acle-6.4.c
===
--- test/Preprocessor/arm-acle-6.4.c
+++ test/Preprocessor/arm-acle-6.4.c
@@ -174,10 +174,14 @@
// CHECK-V7M: __ARM_FEATURE_SAT 1
// CHECK-V7M: __ARM_FEATURE_UNALIGNED 1
-// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-V7EM
-
-// CHECK-V7EM: __ARM_FEATURE_DSP 1
-// CHECK-V7EM: __ARM_FEATURE_SIMD32 1
+// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m4 -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m7 -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m33 -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -march=armv8m.main+dsp -x c -E -dM
%s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+
+// CHECK-M-DSP: __ARM_FEATURE_DSP 1
+// CHECK-M-DSP: __ARM_FEATURE_SIMD32 1
// RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o -
| FileCheck %s -check-prefix CHECK-V8A
Index: lib/Basic/Targets/ARM.cpp
===
--- lib/Basic/Targets/ARM.cpp
+++ lib/Basic/Targets/ARM.cpp
@@ -661,7 +661,7 @@
}
// ACLE 6.4.9 32-bit SIMD instructions
- if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
+ if ((ArchVersion >= 6 && DSP))
Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
// ACLE 6.4.10 Hardware Integer Divide
Index: test/Preprocessor/arm-acle-6.4.c
===
--- test/Preprocessor/arm-acle-6.4.c
+++ test/Preprocessor/arm-acle-6.4.c
@@ -174,10 +174,14 @@
// CHECK-V7M: __ARM_FEATURE_SAT 1
// CHECK-V7M: __ARM_FEATURE_UNALIGNED 1
-// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V7EM
-
-// CHECK-V7EM: __ARM_FEATURE_DSP 1
-// CHECK-V7EM: __ARM_FEATURE_SIMD32 1
+// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m33 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -march=armv8m.main+dsp -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-M-DSP
+
+// CHECK-M-DSP: __ARM_FEATURE_DSP 1
+// CHECK-M-DSP: __ARM_FEATURE_SIMD32 1
// RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-V8A
Index: lib/Basic/Targets/ARM.cpp
===
--- lib/Basic/Targets/ARM.cpp
+++ lib/Basic/Targets/ARM.cpp
@@ -661,7 +661,7 @@
}
// ACLE 6.4.9 32-bit SIMD instructions
- if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
+ if ((ArchVersion >= 6 && DSP))
Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
// ACLE 6.4.10 Hardware Integer Divide
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[PATCH] D42978: Make march/target-cpu print a note with the list of valid values
samparker added a comment. No tests? Repository: rC Clang https://reviews.llvm.org/D42978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D56852: [AArch64] Use LLU for 64-bit crc32 arguments
samparker created this revision.
samparker added a reviewer: t.p.northover.
Herald added subscribers: kristof.beyls, javed.absar.
The ACLE states that 64-bit crc32 operands are uint64_t so we should have the
clang builtin match this description - which is what we already do for AArch32.
https://reviews.llvm.org/D56852
Files:
include/clang/Basic/BuiltinsAArch64.def
test/CodeGen/arm64-crc32.c
Index: test/CodeGen/arm64-crc32.c
===
--- test/CodeGen/arm64-crc32.c
+++ test/CodeGen/arm64-crc32.c
@@ -1,54 +1,57 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple arm64-none-linux-gnu \
// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg |
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg |
FileCheck %s
+#include
-int crc32b(int a, char b)
+uint32_t crc32b(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32b(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
}
-int crc32cb(int a, char b)
+uint32_t crc32cb(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32cb(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
}
-int crc32h(int a, short b)
+uint32_t crc32h(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32h(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
}
-int crc32ch(int a, short b)
+uint32_t crc32ch(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32ch(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
}
-int crc32w(int a, int b)
+uint32_t crc32w(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32w(a,b);
// CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
}
-int crc32cw(int a, int b)
+uint32_t crc32cw(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32cw(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
}
-int crc32d(int a, long b)
+uint32_t crc32d(uint32_t a, uint64_t b)
{
return __builtin_arm_crc32d(a,b);
// CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b)
}
-int crc32cd(int a, long b)
+uint32_t crc32cd(uint32_t a, uint64_t b)
{
return __builtin_arm_crc32cd(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b)
Index: include/clang/Basic/BuiltinsAArch64.def
===
--- include/clang/Basic/BuiltinsAArch64.def
+++ include/clang/Basic/BuiltinsAArch64.def
@@ -50,8 +50,8 @@
BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
-BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc")
-BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc")
+BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
+BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
// Memory barrier
BUILTIN(__builtin_arm_dmb, "vUi", "nc")
Index: test/CodeGen/arm64-crc32.c
===
--- test/CodeGen/arm64-crc32.c
+++ test/CodeGen/arm64-crc32.c
@@ -1,54 +1,57 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple arm64-none-linux-gnu \
// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+#include
-int crc32b(int a, char b)
+uint32_t crc32b(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32b(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
}
-int crc32cb(int a, char b)
+uint32_t crc32cb(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32cb(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
}
-int crc32h(int a, short b)
+uint32_t crc32h(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32h(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
}
-int crc32ch(int a, short b)
+uint32_t crc32ch(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32ch(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
}
-int crc32w(int a, int b)
+uint32_t crc32w(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32w(a,b);
// CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
}
-int crc32cw(int a, int b)
+uint32_t crc32cw(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32cw(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
}
-int crc32d(int a, long b)
+uint32_t crc32d(uint32_t a, uint64_t b)
{
[PATCH] D56852: [AArch64] Use LLU for 64-bit crc32 arguments
samparker updated this revision to Diff 182481.
samparker added a comment.
Updated wsr, rsr and rbit
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D56852/new/
https://reviews.llvm.org/D56852
Files:
include/clang/Basic/BuiltinsAArch64.def
test/CodeGen/arm64-crc32.c
test/CodeGen/builtins-arm64.c
Index: test/CodeGen/builtins-arm64.c
===
--- test/CodeGen/builtins-arm64.c
+++ test/CodeGen/builtins-arm64.c
@@ -1,4 +1,6 @@
// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+#include
void f0(void *a, void *b) {
__clear_cache(a,b);
@@ -55,7 +57,7 @@
return __builtin_arm_rsr("1:2:3:4:5");
}
-unsigned long rsr64() {
+uint64_t rsr64() {
// CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
return __builtin_arm_rsr64("1:2:3:4:5");
}
@@ -72,7 +74,7 @@
__builtin_arm_wsr("1:2:3:4:5", v);
}
-void wsr64(unsigned long v) {
+void wsr64(uint64_t v) {
// CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v)
__builtin_arm_wsr64("1:2:3:4:5", v);
}
Index: test/CodeGen/arm64-crc32.c
===
--- test/CodeGen/arm64-crc32.c
+++ test/CodeGen/arm64-crc32.c
@@ -1,54 +1,57 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple arm64-none-linux-gnu \
// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+#include
-int crc32b(int a, char b)
+uint32_t crc32b(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32b(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
}
-int crc32cb(int a, char b)
+uint32_t crc32cb(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32cb(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
}
-int crc32h(int a, short b)
+uint32_t crc32h(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32h(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
}
-int crc32ch(int a, short b)
+uint32_t crc32ch(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32ch(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
}
-int crc32w(int a, int b)
+uint32_t crc32w(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32w(a,b);
// CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
}
-int crc32cw(int a, int b)
+uint32_t crc32cw(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32cw(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
}
-int crc32d(int a, long b)
+uint32_t crc32d(uint32_t a, uint64_t b)
{
return __builtin_arm_crc32d(a,b);
// CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b)
}
-int crc32cd(int a, long b)
+uint32_t crc32cd(uint32_t a, uint64_t b)
{
return __builtin_arm_crc32cd(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b)
Index: include/clang/Basic/BuiltinsAArch64.def
===
--- include/clang/Basic/BuiltinsAArch64.def
+++ include/clang/Basic/BuiltinsAArch64.def
@@ -33,7 +33,7 @@
// Bit manipulation
BUILTIN(__builtin_arm_rbit, "UiUi", "nc")
-BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc")
+BUILTIN(__builtin_arm_rbit64, "LLUiLLUi", "nc")
// HINT
BUILTIN(__builtin_arm_nop, "v", "")
@@ -50,8 +50,8 @@
BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
-BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc")
-BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc")
+BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
+BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
// Memory barrier
BUILTIN(__builtin_arm_dmb, "vUi", "nc")
@@ -63,10 +63,10 @@
// System Registers
BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
-BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc")
+BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc")
BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
-BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
+BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc")
BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
// MSVC
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[PATCH] D56852: [AArch64] Use LL for 64-bit arguments
samparker updated this revision to Diff 183820.
samparker added reviewers: phosek, rnk.
samparker added a comment.
Changed the builtins to use W instead of LL. I've also updated the tests,
adding a test for rbitl.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D56852/new/
https://reviews.llvm.org/D56852
Files:
include/clang/Basic/BuiltinsAArch64.def
test/CodeGen/arm64-crc32.c
test/CodeGen/builtins-arm64.c
Index: test/CodeGen/builtins-arm64.c
===
--- test/CodeGen/builtins-arm64.c
+++ test/CodeGen/builtins-arm64.c
@@ -1,4 +1,5 @@
-// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LINUX
+// RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-WIN
#include
void f0(void *a, void *b) {
@@ -16,8 +17,15 @@
return __builtin_arm_rbit(a);
}
+// CHECK-WIN: [[A64:%[^ ]+]] = zext i32 %a to i64
+// CHECK-WIN: call i64 @llvm.bitreverse.i64(i64 [[A64]])
+// CHECK-LINUX: call i64 @llvm.bitreverse.i64(i64 %a)
+unsigned long rbitl(unsigned long a) {
+ return __builtin_arm_rbit64(a);
+}
+
// CHECK: call {{.*}} @llvm.bitreverse.i64(i64 %a)
-unsigned long long rbit64(unsigned long long a) {
+uint64_t rbit64(uint64_t a) {
return __builtin_arm_rbit64(a);
}
@@ -60,7 +68,7 @@
__typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);
-uint64_t rsr64() {
+uint64_t rsr64(void) {
// CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
return __builtin_arm_rsr64("1:2:3:4:5");
}
@@ -71,13 +79,17 @@
return __builtin_arm_rsrp("1:2:3:4:5");
}
+__typeof__(__builtin_arm_wsr("1:2:3:4:5", 0)) wsr(unsigned);
+
void wsr(unsigned v) {
// CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64
// CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
__builtin_arm_wsr("1:2:3:4:5", v);
}
-void wsr64(unsigned long v) {
+__typeof__(__builtin_arm_wsr64("1:2:3:4:5", 0)) wsr64(uint64_t);
+
+void wsr64(uint64_t v) {
// CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v)
__builtin_arm_wsr64("1:2:3:4:5", v);
}
Index: test/CodeGen/arm64-crc32.c
===
--- test/CodeGen/arm64-crc32.c
+++ test/CodeGen/arm64-crc32.c
@@ -1,54 +1,57 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple arm64-none-linux-gnu \
// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows \
+// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+#include
-int crc32b(int a, char b)
+uint32_t crc32b(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32b(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
}
-int crc32cb(int a, char b)
+uint32_t crc32cb(uint32_t a, uint8_t b)
{
return __builtin_arm_crc32cb(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
}
-int crc32h(int a, short b)
+uint32_t crc32h(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32h(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
}
-int crc32ch(int a, short b)
+uint32_t crc32ch(uint32_t a, uint16_t b)
{
return __builtin_arm_crc32ch(a,b);
// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
// CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
}
-int crc32w(int a, int b)
+uint32_t crc32w(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32w(a,b);
// CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
}
-int crc32cw(int a, int b)
+uint32_t crc32cw(uint32_t a, uint32_t b)
{
return __builtin_arm_crc32cw(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
}
-int crc32d(int a, long b)
+uint32_t crc32d(uint32_t a, uint64_t b)
{
return __builtin_arm_crc32d(a,b);
// CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b)
}
-int crc32cd(int a, long b)
+uint32_t crc32cd(uint32_t a, uint64_t b)
{
return __builtin_arm_crc32cd(a,b);
// CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b)
Index: include/clang/Basic/BuiltinsAArch64.def
===
--- include/clang/Basic/BuiltinsAArch64.def
+++ include/clang/Basic/BuiltinsAArch64.def
@@ -32,7 +32,7 @@
// Bit manipulation
BUILTIN(__builtin_arm_rbit, "UiUi", "nc")
-BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc")
+BUILTIN(__builtin_arm_rbit64, "WUiWUi", "nc")
// HINT
BUILTIN(__builtin_arm_nop, "v", "")
@@ -49,8 +49,8 @@
BUILTIN(_
[PATCH] D54961: [AArch64] Add command-line option for SSBS
samparker accepted this revision. samparker added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54961/new/ https://reviews.llvm.org/D54961 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D64471: Loop pragma parsing. NFC.
samparker accepted this revision. samparker added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64471/new/ https://reviews.llvm.org/D64471 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D79869: [clang][BFloat] Add reinterpret cast intrinsics
samparker accepted this revision. samparker added a comment. This revision is now accepted and ready to land. > csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs. I cry inside every time I see those wonderful strings, but oh well... probably best to appease the lint gods before committing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79869/new/ https://reviews.llvm.org/D79869 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker added a comment.
Hi Yvan,
Thanks for adding the tests, I've added a few concerns and questions.
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5606
+ // candidates.
+ auto CantGuaranteeValueAcrossCall = [&TRI](outliner::Candidate &C) {
+// If the unsafe registers in this block are all dead, then we don't need
Does this code work with the DSP instructions that read/write the Q and GE
flags? I have a nasty feeling that we don't model their register usage.
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5765
+if (Opc == ARM::BX_RET || Opc == ARM::tBX_RET || Opc == ARM::MOVPCLR) {
+ if (MI.getOperand(0).getImm() != ARMCC::AL)
+return outliner::InstrType::Illegal;
There's the getPredicate helper is ARMBaseInstrInfo which looks like it would
be useful here.
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5801
+
+ // Don't touch the link register
+ if (MI.readsRegister(ARM::LR, TRI) || MI.modifiesRegister(ARM::LR, TRI))
Probably worth doing these simple checks earlier. Should we also be concerned
about the PC too?
Comment at: llvm/lib/Target/ARM/ARMTargetMachine.cpp:553
addPass(createARMConstantIslandPass());
- addPass(createARMLowOverheadLoopsPass());
+ if (!MachineOutlinerEnabled)
+addPass(createARMLowOverheadLoopsPass());
We'll need the LowOverheadLoops pass to run for correctness, so we should
instead only add the MachineOutliner if the subtarget doesn't support LOB.
Repository:
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[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker added inline comments. Comment at: llvm/lib/Target/ARM/ARMTargetMachine.cpp:553 addPass(createARMConstantIslandPass()); - addPass(createARMLowOverheadLoopsPass()); + if (!MachineOutlinerEnabled) +addPass(createARMLowOverheadLoopsPass()); yroux wrote: > samparker wrote: > > We'll need the LowOverheadLoops pass to run for correctness, so we should > > instead only add the MachineOutliner if the subtarget doesn't support LOB. > What do you mean by "for correctness" ? > > I think that it makes more sense that until MachineOutliner and > LowOverheadLoops can work together, we have loloops enabled on targets which > have LOB support unless it is explicitly disabled by -disable-arm-loloops > flag or if the user wants machine outlining with the flag -moutline. If we > do that in the opposite way it means that passing the flag -moutline will > have no impact on such targets unless the -disable-arm-loloops flag is used > Ok. Well, the HardwareLoops pass inserts intrinsics, which are lowered to pseudos and then finalised by ARMLowOverheadLoops so the compiler could crash with this logic. TTI controls whether we generate a low-overhead loop and it also controls whether the vectorizer tries to optimise for those loops too... So, I think TTI will need to understand when we're trying to use the outliner too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76066/new/ https://reviews.llvm.org/D76066 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker added inline comments.
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5606
+ // candidates.
+ auto CantGuaranteeValueAcrossCall = [&TRI](outliner::Candidate &C) {
+// If the unsafe registers in this block are all dead, then we don't need
yroux wrote:
> yroux wrote:
> > samparker wrote:
> > > Does this code work with the DSP instructions that read/write the Q and
> > > GE flags? I have a nasty feeling that we don't model their register usage.
> > Good question, I'll test that
> From what I saw in my testing of DSP instructions, these flags are handled by
> CPSR usage, so this code seems good to me, do you have something else in mind
> ?
Ah, good, then could you please add a couple of tests for those instructions? I
think my last concern is back with low-overhead loops and tail-predication. I
think we should explicitly avoid outlining any MVE instructions and, if this
pass can, then also don't move pseudo instructions too.
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[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker added inline comments.
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5606
+ // candidates.
+ auto CantGuaranteeValueAcrossCall = [&TRI](outliner::Candidate &C) {
+// If the unsafe registers in this block are all dead, then we don't need
yroux wrote:
> samparker wrote:
> > yroux wrote:
> > > yroux wrote:
> > > > samparker wrote:
> > > > > Does this code work with the DSP instructions that read/write the Q
> > > > > and GE flags? I have a nasty feeling that we don't model their
> > > > > register usage.
> > > > Good question, I'll test that
> > > From what I saw in my testing of DSP instructions, these flags are
> > > handled by CPSR usage, so this code seems good to me, do you have
> > > something else in mind ?
> > Ah, good, then could you please add a couple of tests for those
> > instructions? I think my last concern is back with low-overhead loops and
> > tail-predication. I think we should explicitly avoid outlining any MVE
> > instructions and, if this pass can, then also don't move pseudo
> > instructions too.
> OK, do you know a pretty way to check if an instruction is a MVE one or a
> pseudo ? If not I'll add a new helper isMVEOpcode...
Sure, for pseudos there's the MachineInstr isPseudo(). For MVE, it's encoded in
the target flags:
```
const MCInstrDesc &MCID = MI.getDesc();
uint64_t Flags = MCID.TSFlags;
if ((Flags & ARMII::DomainMask) == ARMII::DomainMVE)
```
Repository:
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[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker added a comment. Thanks for adding the MVE changes, but I also still don't see any DSP tests, i.e QADD, SADD16. Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5753 + // ahead and skip over them. + if (MI.isKill()) +return outliner::InstrType::Invisible; Should IMPLICIT_DEF instructions be considered invisible too? Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5817 + // Be conservative with program counter. + if (MI.readsRegister(ARM::PC, TRI) || MI.modifiesRegister(ARM::PC, TRI)) +return outliner::InstrType::Illegal; Cheers. AArch64 is nice and doesn't allow arbitrary writes to the PC, but we won't have that luxury here. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76066/new/ https://reviews.llvm.org/D76066 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker accepted this revision. samparker added a comment. This revision is now accepted and ready to land. > Eli said in his comments we don't really need to worry about APCS but only to > linker veneers and I don't think a linker would clear the sticky Q bit or > touch the GE ones. Ah, yes, good point. Then I have nothing else, but definitely worth waiting to see if Eli has further comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76066/new/ https://reviews.llvm.org/D76066 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D40888: [ARM] ACLE parallel arithmetic and DSP style multiplications
samparker added a comment. Thanks for looking into this! Comment at: include/clang/Basic/BuiltinsARM.def:39 BUILTIN(__builtin_arm_qsub, "iii", "nc") +BUILTIN(__builtin_arm_qdbl, "ii", "nc") BUILTIN(__builtin_arm_ssat, "iiUi", "nc") Do we now need a codegen tests for this one? Comment at: test/Sema/builtins-arm.c:161 + r = __builtin_arm_smulwt(-1, -2); + r = __builtin_arm_smulwt(-1.0f, -2); +} Interesting that this doesn't give an error? Comment at: test/Sema/builtins-arm.c:236 + y = __builtin_arm_uxtab16(c, d); + y = __builtin_arm_uxtab16(-1, -2); + y = __builtin_arm_uxtb16(d); Can / should we warn the user when using signed arguments? Looks like I missed the unsigned qualifiers in the original patch. https://reviews.llvm.org/D40888 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D40888: [ARM] ACLE parallel arithmetic and DSP style multiplications
samparker accepted this revision. samparker added a comment. This revision is now accepted and ready to land. Great, LGTM, many thanks for doing this! https://reviews.llvm.org/D40888 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D36731: [ARM][AArch64] Cortex-A75 and Cortex-A55 support
samparker created this revision.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.
This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest
big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including
the cryptography and RAS extensions, plus the optional dot product extension.
They also implement the RCpc AArch64 extension from ARMv8.3-A.
Cortex-A75:
https://developer.arm.com/products/processors/cortex-a/cortex-a75
Cortex-A55:
https://developer.arm.com/products/processors/cortex-a/cortex-a55
https://reviews.llvm.org/D36731
Files:
lib/Driver/ToolChains/Arch/ARM.cpp
test/Driver/aarch64-cpus.c
test/Driver/aarch64-dotprod.c
test/Driver/aarch64-ras.c
test/Driver/aarch64-rcpc.s
test/Driver/arm-cortex-cpus.c
test/Driver/arm-dotprod.c
test/Driver/arm-ras.c
Index: test/Driver/arm-ras.c
===
--- test/Driver/arm-ras.c
+++ test/Driver/arm-ras.c
@@ -1,5 +1,7 @@
// RUN: %clang -target arm-none-none-eabi -march=armv8a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
// CHECK-RAS: "-target-feature" "+ras"
// RUN: %clang -target arm-none-none-eabi -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s
Index: test/Driver/arm-dotprod.c
===
--- /dev/null
+++ test/Driver/arm-dotprod.c
@@ -0,0 +1,11 @@
+// RUN: %clang -### -target arm %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -### -target arm -march=armv8.1a %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -### -target arm -march=armv8.2a %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -### -target arm -march=armv8.3a %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// CHECK-NONE-NOT: "-target-feature" "+dotprod"
+
+// RUN: %clang -### -target arm -march=armv8.2a+dotprod %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm -march=armv8.3a+dotprod %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm -mcpu=cortex-a75 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm -mcpu=cortex-a55 %s 2>&1 | FileCheck %s
+// CHECK: "+dotprod"
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -258,34 +258,34 @@
// RUN: %clang -target armv8.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
// RUN: %clang -target arm -mlittle-endian -march=armv8.2-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
-// CHECK-V82A: "-cc1"{{.*}} "-triple" "armv8.2{{.*}}" "-target-cpu" "generic"
+// CHECK-V82A: "-cc1"{{.*}} "-triple" "armv8.2{{.*}}" "-target-cpu" "cortex-a55"
// RUN: %clang -target armebv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V82A %s
// RUN: %clang -target armv8.2a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V82A %s
// RUN: %clang -target armeb -march=armebv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V82A %s
// RUN: %clang -target armeb -march=armebv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V82A %s
// RUN: %clang -target arm -march=armebv8.2a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V82A %s
// RUN: %clang -target arm -march=armebv8.2-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V82A %s
-// CHECK-BE-V82A: "-cc1"{{.*}} "-triple" "armebv8.2{{.*}}" "-target-cpu" "generic"
+// CHECK-BE-V82A: "-cc1"{{.*}} "-triple" "armebv8.2{{.*}}" "-target-cpu" "cortex-a55"
// RUN: %clang -target armv8.2a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
// RUN: %clang -target arm -march=armv8.2a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
// RUN: %clang -target arm -march=armv8.2-a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
// RUN: %clang -target armv8.2a -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
// RUN: %clang -target arm -march=armv8.2-a -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
-// CHECK-V82A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.2a-{{.*}}" "-target-cpu" "generic"
+// CHECK-V82A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.2a-{{.*}}" "-target-cpu" "cortex-a55
[PATCH] D36731: [ARM][AArch64] Cortex-A75 and Cortex-A55 tests
samparker added a comment.
Thanks guys, I will sort my logic out.
Renato, the new Decode function is really just there to allow me to double
check the target features. This is already possible with AArch64 and it just
felt right to also be able to test ARM in the same way. I've renamed the title
so others aren't mislead.
cheers,
sam
Comment at: test/Driver/arm-cortex-cpus.c:261
// RUN: %clang -target arm -mlittle-endian -march=armv8.2-a -mlittle-endian
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
-// CHECK-V82A: "-cc1"{{.*}} "-triple" "armv8.2{{.*}}" "-target-cpu" "generic"
+// CHECK-V82A: "-cc1"{{.*}} "-triple" "armv8.2{{.*}}" "-target-cpu"
"cortex-a55"
SjoerdMeijer wrote:
> Just checking: why has the default cpu changed from generic to cortex-a55,
> and secondly, is that what we want?
I was thinking about this on the way to work, and no I don't think it is what
we want! I will change this.
https://reviews.llvm.org/D36731
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[PATCH] D36731: [ARM][AArch64] Cortex-A75 and Cortex-A55 tests
samparker updated this revision to Diff 111664.
samparker added a comment.
Reverted the default cpu v8.2-a to generic, I will update
https://reviews.llvm.org/D36667 accordingly. Also fixed up the boolean issues.
https://reviews.llvm.org/D36731
Files:
lib/Driver/ToolChains/Arch/ARM.cpp
test/Driver/aarch64-cpus.c
test/Driver/aarch64-dotprod.c
test/Driver/aarch64-ras.c
test/Driver/aarch64-rcpc.s
test/Driver/arm-cortex-cpus.c
test/Driver/arm-dotprod.c
test/Driver/arm-ras.c
Index: test/Driver/arm-ras.c
===
--- test/Driver/arm-ras.c
+++ test/Driver/arm-ras.c
@@ -1,5 +1,7 @@
// RUN: %clang -target arm-none-none-eabi -march=armv8a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s
// CHECK-RAS: "-target-feature" "+ras"
// RUN: %clang -target arm-none-none-eabi -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s
Index: test/Driver/arm-dotprod.c
===
--- /dev/null
+++ test/Driver/arm-dotprod.c
@@ -0,0 +1,11 @@
+// RUN: %clang -### -target arm %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -### -target arm -march=armv8.1a %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -### -target arm -march=armv8.2a %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -### -target arm -march=armv8.3a %s 2>&1 | FileCheck %s --check-prefix=CHECK-NONE
+// CHECK-NONE-NOT: "-target-feature" "+dotprod"
+
+// RUN: %clang -### -target arm -march=armv8.2a+dotprod %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm -march=armv8.3a+dotprod %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm -mcpu=cortex-a75 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm -mcpu=cortex-a55 %s 2>&1 | FileCheck %s
+// CHECK: "+dotprod"
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -507,6 +507,12 @@
// RUN: %clang -target arm -mcpu=exynos-m3 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
// CHECK-CPUV8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}
+// RUN: %clang -target arm -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a55 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a75 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// CHECK-CPUV82A: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}}
+
// RUN: %clang -target armeb -mcpu=cortex-a32 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target armeb -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// RUN: %clang -target armeb -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
@@ -527,6 +533,12 @@
// RUN: %clang -target arm -mcpu=exynos-m3 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// CHECK-BE-CPUV8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}
+// RUN: %clang -target armeb -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target armeb -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a55 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a75 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// CHECK-BE-CPUV82A: "-cc1"{{.*}} "-triple" "armebv8.2a-{{.*}}
+
// RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-r52 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8R %s
// CHECK-CPUV8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}}
@@ -550,6 +562,12 @@
// RUN: %clang -target arm -mcpu=exynos-m3 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// CHECK-CPUV8A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8-{{.*}}
+// RUN: %clang -target arm -mcpu=cortex-a55 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECKCPUV82A-THUMB %s
+// RUN: %clang -target arm -mcpu=cortex-a75 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECKCPUV82A-THUMB %s
+// RUN: %clang -target arm -mcpu=cortex-a55 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECKCPUV82A-THUMB %s
+// RUN: %clang -target arm -mcpu=cortex-a75 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-p
[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM
samparker added a comment. > It might be possible to rearrange Low Overhead Loops to run before > ConstantIslands, but you'd probably need to do more to make it work properly. > I don't think ConstantIslands knows how to handle the branches generated by > LowOverheadLoop. This, and the fact that LowOverheadLoops is dependent upon block sizes and placement (I need to add a comment in the header on that pass). So, ConstantIslands would have to guarantee not to change branch targets or change the distance between blocks around the low-overhead loop constructs. I think updating liveness information would be the easier option. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57054/new/ https://reviews.llvm.org/D57054 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM
samparker added a comment. > I can add liveness info into the outlined function, but we will need to do > the same on AArch64 even if is not necessary. Hmm, would it be possible to pass a bool to the pass which will control whether liveness is updated? The other, suboptimal, option would be to not do outlining when we have the LOB extension. > On the other hand isn't it the same for the ConstantIslands pass, I mean > isn't the size of blocks modified by the LowOverheadLoops pass which can > potentially break the accesses to some constant ? Yes, but LowOverheadLoops does not increase block size or change the CFG. We mainly remove instructions but in the cases where we add instructions, they're replacing pseudos with a size that represents the maximum number of instructions that could be inserted. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57054/new/ https://reviews.llvm.org/D57054 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM
samparker added a comment. > Even if you only decrease the size you can have a distance increase due to > aligment constraints Ah... thanks for raising this. I'll look into it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57054/new/ https://reviews.llvm.org/D57054 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D76066: [ARM][MachineOutliner] Add Machine Outliner support for ARM
samparker added a comment. Hi, I like reading your code! But I'm concerned around the lack of tests here, specifically: - CPSR liveness. - LR liveness. - All things PIC related. - Linkage legality. - A negative test for Thumb-1. - Inline asm generally concerns me too. Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5653 + + // Check if each of the unsafe registers are available... + bool R12AvailableInBlock = LRU.available(ARM::R12); When you say 'available', do you mean 'dead'? I'm struggling to follow the logic here... Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5663 + // Now, add the live outs to the set. + LRU.addLiveOuts(MBB); + Do you need to clear LRU first? Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5705 + unsigned Opc = MI.getOpcode(); + if (Opc == ARM::t2IT || Opc == ARM::tPICADD || Opc == ARM::PICADD || + Opc == ARM::PICSTR || Opc == ARM::PICSTRB || Opc == ARM::PICSTRH || I'm surprised to see IT here? Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5761 + + // Don't touch the link register + if (MI.readsRegister(ARM::LR, &getRegisterInfo()) || Isn't this already handled in the loop above? I prefer this notation though. Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5781 +if (Subtarget.isThumb()) + if (Call->getOperand(2).isReg()) +BuildMI(MBB, MBB.end(), DebugLoc(), get(ARM::tTAILJMPr)) Looks like this MI building could be refactored. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76066/new/ https://reviews.llvm.org/D76066 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM
samparker added a comment. How about removing Thumb-1 support until it's properly handled? I also suggest that this gets broken down a bit too, by handling the different types of function call in different patches, like getting tail-call support in first or something. Also, is this currently set to run all the time and not just when optimising for size? Comment at: llvm/lib/CodeGen/MachineOutliner.cpp:1159 + MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); + MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs); + MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); Looks like these should these be set in getRequiredProperties. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57054/new/ https://reviews.llvm.org/D57054 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D42318: [ARM] Pass _Float16 as int or float
samparker added a comment. Hi Sjoerd, Seems sensible to me to treat these two types the same way, though I must admit having different half types confuses me... So a few questions for my understanding: - What issue are you trying to workaround? -What would the ideal solution be? - Why do we need a workaround instead of implementing the ideal solution? cheers! Comment at: test/CodeGen/arm-float16-arguments.c:4 +// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fnative-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=NATIVE + +_Float16 g; Probably worth keeping these in arm-fp16-arguments.c since they're basically the same. https://reviews.llvm.org/D42318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D42318: [ARM] Pass _Float16 as int or float
samparker accepted this revision. samparker added a comment. This revision is now accepted and ready to land. Thanks for the explanation, LGTM, thanks! https://reviews.llvm.org/D42318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
