r364399 - [CC1Option] Add the option to enable the debug entry values

[Djordje Todorovic via cfe-commits]

Author: djtodoro
Date: Wed Jun 26 02:38:09 2019
New Revision: 364399

URL: http://llvm.org/viewvc/llvm-project?rev=364399&view=rev
Log:
[CC1Option] Add the option to enable the debug entry values

The option enables debug info about parameter's entry values.

The example of using the option:

clang -g -O2 -Xclang -femit-debug-entry-values test.c

In addition, when the option is set add the flag all_call_sites
in a subprogram in order to support GNU extension as well.

([3/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda 
Co-authored-by: Nikola Prica 
Co-authored-by: Ivan Baev 

Differential Revision: https://reviews.llvm.org/D58033

Modified:
cfe/trunk/include/clang/Basic/CodeGenOptions.def
cfe/trunk/include/clang/Driver/CC1Options.td
cfe/trunk/lib/CodeGen/BackendUtil.cpp
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp
cfe/trunk/test/CodeGenCXX/dbg-info-all-calls-described.cpp

Modified: cfe/trunk/include/clang/Basic/CodeGenOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/CodeGenOptions.def?rev=364399&r1=364398&r2=364399&view=diff
==
--- cfe/trunk/include/clang/Basic/CodeGenOptions.def (original)
+++ cfe/trunk/include/clang/Basic/CodeGenOptions.def Wed Jun 26 02:38:09 2019
@@ -61,6 +61,7 @@ CODEGENOPT(ExperimentalNewPassManager, 1
 CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new
///< pass manager.
 CODEGENOPT(DisableRedZone, 1, 0) ///< Set when -mno-red-zone is enabled.
+CODEGENOPT(EnableDebugEntryValues, 1, 0) ///< Emit call site parameter dbg info
 CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs
  ///< is specified.
 CODEGENOPT(DisableTailCalls  , 1, 0) ///< Do not emit tail calls.

Modified: cfe/trunk/include/clang/Driver/CC1Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/CC1Options.td?rev=364399&r1=364398&r2=364399&view=diff
==
--- cfe/trunk/include/clang/Driver/CC1Options.td (original)
+++ cfe/trunk/include/clang/Driver/CC1Options.td Wed Jun 26 02:38:09 2019
@@ -386,6 +386,8 @@ def flto_unit: Flag<["-"], "flto-unit">,
 def fno_lto_unit: Flag<["-"], "fno-lto-unit">;
 def fthin_link_bitcode_EQ : Joined<["-"], "fthin-link-bitcode=">,
 HelpText<"Write minimized bitcode to  for the ThinLTO thin link 
only">;
+def femit_debug_entry_values : Flag<["-"], "femit-debug-entry-values">,
+HelpText<"Enables debug info about call site parameter's entry values">;
 def fdebug_pass_manager : Flag<["-"], "fdebug-pass-manager">,
 HelpText<"Prints debug information for the new pass manager">;
 def fno_debug_pass_manager : Flag<["-"], "fno-debug-pass-manager">,

Modified: cfe/trunk/lib/CodeGen/BackendUtil.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/BackendUtil.cpp?rev=364399&r1=364398&r2=364399&view=diff
==
--- cfe/trunk/lib/CodeGen/BackendUtil.cpp (original)
+++ cfe/trunk/lib/CodeGen/BackendUtil.cpp Wed Jun 26 02:38:09 2019
@@ -471,6 +471,7 @@ static void initTargetOptions(llvm::Targ
   Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning();
   Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection;
   Options.EmitAddrsig = CodeGenOpts.Addrsig;
+  Options.EnableDebugEntryValues = CodeGenOpts.EnableDebugEntryValues;
 
   if (CodeGenOpts.getSplitDwarfMode() != CodeGenOptions::NoFission)
 Options.MCOptions.SplitDwarfFile = CodeGenOpts.SplitDwarfFile;

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=364399&r1=364398&r2=364399&view=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Wed Jun 26 02:38:09 2019
@@ -4659,7 +4659,10 @@ llvm::DINode::DIFlags CGDebugInfo::getCa
   // were part of DWARF v4.
   bool SupportsDWARFv4Ext =
   CGM.getCodeGenOpts().DwarfVersion == 4 &&
-  CGM.getCodeGenOpts().getDebuggerTuning() == llvm::DebuggerKind::LLDB;
+  (CGM.getCodeGenOpts().getDebuggerTuning() == llvm::DebuggerKind::LLDB ||
+   (CGM.getCodeGenOpts().EnableDebugEntryValues &&
+   CGM.getCodeGenOpts().getDebuggerTuning() == llvm::DebuggerKind::GDB));
+
   if (!SupportsDWARFv4Ext && CGM.getCodeGenOpts().DwarfVersion < 5)
 return llvm::DINode::FlagZero;
 

Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/CompilerInvocation.cpp?rev=364399&r1=364398&r2=364399&view=diff
==
--- cfe/trunk/lib/Frontend/CompilerInvocatio

r364402 - [clang] Fix test failures after the rL364399

[Djordje Todorovic via cfe-commits]

Author: djtodoro
Date: Wed Jun 26 03:23:25 2019
New Revision: 364402

URL: http://llvm.org/viewvc/llvm-project?rev=364402&view=rev
Log:
[clang] Fix test failures after the rL364399

Modified:
cfe/trunk/test/CodeGenCXX/dbg-info-all-calls-described.cpp

Modified: cfe/trunk/test/CodeGenCXX/dbg-info-all-calls-described.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/dbg-info-all-calls-described.cpp?rev=364402&r1=364401&r2=364402&view=diff
==
--- cfe/trunk/test/CodeGenCXX/dbg-info-all-calls-described.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/dbg-info-all-calls-described.cpp Wed Jun 26 
03:23:25 2019
@@ -16,15 +16,15 @@
 // RUN: -implicit-check-not=DISubprogram 
-implicit-check-not=DIFlagAllCallsDescribed
 
 // Supported: DWARF4 + GDB tuning by using '-femit-debug-entry-values'
-// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm %s -o - \
-// RUN:   -O1 -disable-llvm-passes -debugger-tuning=gdb \
+// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm -triple 
x86_64-linux-gnu \
+// RUN:   %s -o - -O1 -disable-llvm-passes -debugger-tuning=gdb \
 // RUN:   -debug-info-kind=standalone -dwarf-version=4 \
 // RUN: | FileCheck %s -check-prefix=HAS-ATTR \
 // RUN: -implicit-check-not=DIFlagAllCallsDescribed
 
 // Unsupported: -O0 + '-femit-debug-entry-values'
-// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm %s -o - \
-// RUN:   -O0 -disable-llvm-passes -debugger-tuning=gdb \
+// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm -triple 
x86_64-linux-gnu \
+// RUN:   %s -o - -O0 -disable-llvm-passes -debugger-tuning=gdb \
 // RUN:   -debug-info-kind=standalone -dwarf-version=4 \
 // RUN: | FileCheck %s -check-prefix=NO-ATTR
 


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r364424 - [clang/DIVar] Emit the flag for params that have unmodified value

[Djordje Todorovic via cfe-commits]

Author: djtodoro
Date: Wed Jun 26 06:32:02 2019
New Revision: 364424

URL: http://llvm.org/viewvc/llvm-project?rev=364424&view=rev
Log:
[clang/DIVar] Emit the flag for params that have unmodified value

Emit the debug info flag that indicates that a parameter has unchanged
value throughout a function.

([5/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda 
Co-authored-by: Nikola Prica 
Co-authored-by: Ivan Baev 

Differential Revision: https://reviews.llvm.org/D58035

Added:
cfe/trunk/test/CodeGen/debug-info-param-modification.c
Modified:
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/CodeGen/CGDebugInfo.h

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=364424&r1=364423&r2=364424&view=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Wed Jun 26 06:32:02 2019
@@ -18,6 +18,7 @@
 #include "CodeGenFunction.h"
 #include "CodeGenModule.h"
 #include "ConstantEmitter.h"
+#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclFriend.h"
 #include "clang/AST/DeclObjC.h"
@@ -3588,6 +3589,12 @@ void CGDebugInfo::EmitFunctionStart(Glob
   if (HasDecl && isa(D))
 DeclCache[D->getCanonicalDecl()].reset(SP);
 
+  // We use the SPDefCache only in the case when the debug entry values option
+  // is set, in order to speed up parameters modification analysis.
+  if (CGM.getCodeGenOpts().EnableDebugEntryValues && HasDecl &&
+  isa(D))
+SPDefCache[cast(D)].reset(SP);
+
   if (CGM.getCodeGenOpts().DwarfVersion >= 5) {
 // Starting with DWARF V5 method declarations are emitted as children of
 // the interface type.
@@ -3964,6 +3971,11 @@ llvm::DILocalVariable *CGDebugInfo::Emit
  llvm::DebugLoc::get(Line, Column, Scope, 
CurInlinedAt),
  Builder.GetInsertBlock());
 
+  if (CGM.getCodeGenOpts().EnableDebugEntryValues && ArgNo) {
+if (auto *PD = dyn_cast(VD))
+  ParamCache[PD].reset(D);
+  }
+
   return D;
 }
 
@@ -4555,6 +4567,29 @@ void CGDebugInfo::setDwoId(uint64_t Sign
   TheCU->setDWOId(Signature);
 }
 
+/// Analyzes each function parameter to determine whether it is constant
+/// throughout the function body.
+static void analyzeParametersModification(
+ASTContext &Ctx,
+llvm::DenseMap &SPDefCache,
+llvm::DenseMap &ParamCache) {
+  for (auto &SP : SPDefCache) {
+auto *FD = SP.first;
+assert(FD->hasBody() && "Functions must have body here");
+const Stmt *FuncBody = (*FD).getBody();
+for (auto Parm : FD->parameters()) {
+  ExprMutationAnalyzer FuncAnalyzer(*FuncBody, Ctx);
+  if (FuncAnalyzer.isMutated(Parm))
+continue;
+
+  auto I = ParamCache.find(Parm);
+  assert(I != ParamCache.end() && "Parameters should be already cached");
+  auto *DIParm = cast(I->second);
+  DIParm->setIsNotModified();
+}
+  }
+}
+
 void CGDebugInfo::finalize() {
   // Creating types might create further types - invalidating the current
   // element and the size(), so don't cache/reference them.
@@ -4627,6 +4662,10 @@ void CGDebugInfo::finalize() {
 if (auto MD = TypeCache[RT])
   DBuilder.retainType(cast(MD));
 
+  if (CGM.getCodeGenOpts().EnableDebugEntryValues)
+// This will be used to emit debug entry values.
+analyzeParametersModification(CGM.getContext(), SPDefCache, ParamCache);
+
   DBuilder.finalize();
 }
 

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.h?rev=364424&r1=364423&r2=364424&view=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.h (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.h Wed Jun 26 06:32:02 2019
@@ -134,6 +134,10 @@ class CGDebugInfo {
 
   llvm::DenseMap DIFileCache;
   llvm::DenseMap SPCache;
+  /// Cache function definitions relevant to use for parameters mutation
+  /// analysis.
+  llvm::DenseMap SPDefCache;
+  llvm::DenseMap ParamCache;
   /// Cache declarations relevant to DW_TAG_imported_declarations (C++
   /// using declarations) that aren't covered by other more specific caches.
   llvm::DenseMap DeclCache;

Added: cfe/trunk/test/CodeGen/debug-info-param-modification.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/debug-info-param-modification.c?rev=364424&view=auto
==
--- cfe/trunk/test/CodeGen/debug-info-param-modification.c (added)
+++ cfe/trunk/test/CodeGen/debug-info-param-modification.c Wed Jun 26 06:32:02 
2019
@@ -0,0 +1,12 @@
+// RUN: %clang -Xclang -femit-debug-entry-values -g -O2 -S -target 
x86_64-none-linux-gnu -emit-llvm %s -o - | FileCheck %s 
-check-prefix=CHECK-ENTRY-VAL-OPT
+// CHECK-ENTRY-VAL-

r364502 - [clang] Add DISuprogram and DIE for a func decl

[Djordje Todorovic via cfe-commits]

Author: djtodoro
Date: Wed Jun 26 23:44:44 2019
New Revision: 364502

URL: http://llvm.org/viewvc/llvm-project?rev=364502&view=rev
Log:
[clang] Add DISuprogram and DIE for a func decl

Attach a unique DISubprogram to a function declaration that will be
used for call site debug info.

([7/13] Introduce the debug entry values.)

Co-authored-by: Ananth Sowda 
Co-authored-by: Nikola Prica 
Co-authored-by: Ivan Baev 

Differential Revision: https://reviews.llvm.org/D60714

Added:
cfe/trunk/test/CodeGen/debug-info-extern-call.c
Modified:
cfe/trunk/include/clang/AST/Decl.h
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/CodeGen/CGDebugInfo.h
cfe/trunk/lib/CodeGen/CGExpr.cpp

Modified: cfe/trunk/include/clang/AST/Decl.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/AST/Decl.h?rev=364502&r1=364501&r2=364502&view=diff
==
--- cfe/trunk/include/clang/AST/Decl.h (original)
+++ cfe/trunk/include/clang/AST/Decl.h Wed Jun 26 23:44:44 2019
@@ -2396,6 +2396,8 @@ public:
 
   bool doesDeclarationForceExternallyVisibleDefinition() const;
 
+  bool isStatic() const { return getStorageClass() == SC_Static; }
+
   /// Whether this function declaration represents an C++ overloaded
   /// operator, e.g., "operator+".
   bool isOverloadedOperator() const {

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=364502&r1=364501&r2=364502&view=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Wed Jun 26 23:44:44 2019
@@ -3619,7 +3619,7 @@ void CGDebugInfo::EmitFunctionStart(Glob
 }
 
 void CGDebugInfo::EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc,
-   QualType FnType) {
+   QualType FnType, llvm::Function *Fn) {
   StringRef Name;
   StringRef LinkageName;
 
@@ -3629,7 +3629,9 @@ void CGDebugInfo::EmitFunctionDecl(Globa
 
   llvm::DINode::DIFlags Flags = llvm::DINode::FlagZero;
   llvm::DIFile *Unit = getOrCreateFile(Loc);
-  llvm::DIScope *FDContext = getDeclContextDescriptor(D);
+  bool IsDeclForCallSite = Fn ? true : false;
+  llvm::DIScope *FDContext =
+  IsDeclForCallSite ? Unit : getDeclContextDescriptor(D);
   llvm::DINodeArray TParamsArray;
   if (isa(D)) {
 // If there is a DISubprogram for this function available then use it.
@@ -3656,10 +3658,38 @@ void CGDebugInfo::EmitFunctionDecl(Globa
   if (CGM.getLangOpts().Optimize)
 SPFlags |= llvm::DISubprogram::SPFlagOptimized;
 
-  DBuilder.retainType(DBuilder.createFunction(
+  llvm::DISubprogram *SP = DBuilder.createFunction(
   FDContext, Name, LinkageName, Unit, LineNo,
   getOrCreateFunctionType(D, FnType, Unit), ScopeLine, Flags, SPFlags,
-  TParamsArray.get(), getFunctionDeclaration(D)));
+  TParamsArray.get(), getFunctionDeclaration(D));
+
+  if (IsDeclForCallSite)
+Fn->setSubprogram(SP);
+
+  DBuilder.retainType(SP);
+}
+
+void CGDebugInfo::EmitFuncDeclForCallSite(llvm::CallBase *CallOrInvoke,
+  QualType CalleeType,
+  const FunctionDecl *CalleeDecl) {
+  auto &CGOpts = CGM.getCodeGenOpts();
+  if (!CGOpts.EnableDebugEntryValues || !CGM.getLangOpts().Optimize ||
+  !CallOrInvoke ||
+  CGM.getCodeGenOpts().getDebugInfo() < codegenoptions::LimitedDebugInfo)
+return;
+
+  auto *Func = CallOrInvoke->getCalledFunction();
+  if (!Func)
+return;
+
+  // If there is no DISubprogram attached to the function being called,
+  // create the one describing the function in order to have complete
+  // call site debug info.
+  if (Func->getSubprogram())
+return;
+
+  if (!CalleeDecl->isStatic() && !CalleeDecl->isInlined())
+EmitFunctionDecl(CalleeDecl, CalleeDecl->getLocation(), CalleeType, Func);
 }
 
 void CGDebugInfo::EmitInlineFunctionStart(CGBuilderTy &Builder, GlobalDecl GD) 
{

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.h?rev=364502&r1=364501&r2=364502&view=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.h (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.h Wed Jun 26 23:44:44 2019
@@ -409,7 +409,15 @@ public:
   void EmitInlineFunctionEnd(CGBuilderTy &Builder);
 
   /// Emit debug info for a function declaration.
-  void EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc, QualType FnType);
+  /// \p Fn is set only when a declaration for a debug call site gets created.
+  void EmitFunctionDecl(GlobalDecl GD, SourceLocation Loc,
+QualType FnType, llvm::Function *Fn = nullptr);
+
+  /// Emit debug info for an extern function being called.
+  /// This is needed for call site debug inf

Re: r364424 - [clang/DIVar] Emit the flag for params that have unmodified value

[Djordje Todorovic via cfe-commits]

Hi Vedant,

This looks good! Thanks!

Regards,
Djordje

On 11.7.19. 02:11, Vedant Kumar wrote:
> Hi Djordje,
> 
> Just a heads-up that I’ve landed r365716 to fix a crash in a stage2 build of 
> AppleClang with -femit-debug-entry-values enabled.
> 
> I went ahead and landed the fix as it seemed simple enough. Let me know if 
> you have any concerns.
> 
> Thanks,
> Vedant
> 
>> On Jun 26, 2019, at 6:32 AM, Djordje Todorovic via cfe-commits 
>>  wrote:
>>
>> Author: djtodoro
>> Date: Wed Jun 26 06:32:02 2019
>> New Revision: 364424
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=364424&view=rev
>> Log:
>> [clang/DIVar] Emit the flag for params that have unmodified value
>>
>> Emit the debug info flag that indicates that a parameter has unchanged
>> value throughout a function.
>>
>> ([5/13] Introduce the debug entry values.)
>>
>> Co-authored-by: Ananth Sowda 
>> Co-authored-by: Nikola Prica 
>> Co-authored-by: Ivan Baev 
>>
>> Differential Revision: https://reviews.llvm.org/D58035
>>
>> Added:
>>cfe/trunk/test/CodeGen/debug-info-param-modification.c
>> Modified:
>>cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
>>cfe/trunk/lib/CodeGen/CGDebugInfo.h
>>
>> Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=364424&r1=364423&r2=364424&view=diff
>> ==
>> --- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
>> +++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Wed Jun 26 06:32:02 2019
>> @@ -18,6 +18,7 @@
>> #include "CodeGenFunction.h"
>> #include "CodeGenModule.h"
>> #include "ConstantEmitter.h"
>> +#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
>> #include "clang/AST/ASTContext.h"
>> #include "clang/AST/DeclFriend.h"
>> #include "clang/AST/DeclObjC.h"
>> @@ -3588,6 +3589,12 @@ void CGDebugInfo::EmitFunctionStart(Glob
>>   if (HasDecl && isa(D))
>> DeclCache[D->getCanonicalDecl()].reset(SP);
>>
>> +  // We use the SPDefCache only in the case when the debug entry values 
>> option
>> +  // is set, in order to speed up parameters modification analysis.
>> +  if (CGM.getCodeGenOpts().EnableDebugEntryValues && HasDecl &&
>> +  isa(D))
>> +SPDefCache[cast(D)].reset(SP);
>> +
>>   if (CGM.getCodeGenOpts().DwarfVersion >= 5) {
>> // Starting with DWARF V5 method declarations are emitted as children of
>> // the interface type.
>> @@ -3964,6 +3971,11 @@ llvm::DILocalVariable *CGDebugInfo::Emit
>>  llvm::DebugLoc::get(Line, Column, Scope, 
>> CurInlinedAt),
>>  Builder.GetInsertBlock());
>>
>> +  if (CGM.getCodeGenOpts().EnableDebugEntryValues && ArgNo) {
>> +if (auto *PD = dyn_cast(VD))
>> +  ParamCache[PD].reset(D);
>> +  }
>> +
>>   return D;
>> }
>>
>> @@ -4555,6 +4567,29 @@ void CGDebugInfo::setDwoId(uint64_t Sign
>>   TheCU->setDWOId(Signature);
>> }
>>
>> +/// Analyzes each function parameter to determine whether it is constant
>> +/// throughout the function body.
>> +static void analyzeParametersModification(
>> +ASTContext &Ctx,
>> +llvm::DenseMap &SPDefCache,
>> +llvm::DenseMap &ParamCache) {
>> +  for (auto &SP : SPDefCache) {
>> +auto *FD = SP.first;
>> +assert(FD->hasBody() && "Functions must have body here");
>> +const Stmt *FuncBody = (*FD).getBody();
>> +for (auto Parm : FD->parameters()) {
>> +  ExprMutationAnalyzer FuncAnalyzer(*FuncBody, Ctx);
>> +  if (FuncAnalyzer.isMutated(Parm))
>> +continue;
>> +
>> +  auto I = ParamCache.find(Parm);
>> +  assert(I != ParamCache.end() && "Parameters should be already 
>> cached");
>> +  auto *DIParm = cast(I->second);
>> +  DIParm->setIsNotModified();
>> +}
>> +  }
>> +}
>> +
>> void CGDebugInfo::finalize() {
>>   // Creating types might create further types - invalidating the current
>>   // element and the size(), so don't cache/reference them.
>> @@ -4627,6 +4662,10 @@ void CGDebugInfo::finalize() {
>> if (auto MD = TypeCache[RT])
>>   DBuilder.retainType(cast(MD));
>>
>> +  if (CGM.getCodeGen

[clang] 40a3fcb - [DebugInfo][CallSites] Remove decl subprograms from 'retainedTypes:'

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-06-01T09:10:05+02:00
New Revision: 40a3fcb05c83c41862038277aa667c956e7cac82

URL: 
https://github.com/llvm/llvm-project/commit/40a3fcb05c83c41862038277aa667c956e7cac82
DIFF: 
https://github.com/llvm/llvm-project/commit/40a3fcb05c83c41862038277aa667c956e7cac82.diff

LOG: [DebugInfo][CallSites] Remove decl subprograms from 'retainedTypes:'

After the D70350, the retainedTypes: isn't being used for the purpose
of call site debug info for extern calls, so it is safe to delete it
from IR representation.
We are also adding a test to ensure the subprogram isn't stored within
the retainedTypes: from corresponding DICompileUnit.

Differential Revision: https://reviews.llvm.org/D80369

Added: 


Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/Modules/DebugInfoTransitiveImport.m
clang/test/Modules/ModuleDebugInfo.cpp
clang/test/Modules/ModuleDebugInfo.m

Removed: 




diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 31f8df243017..5be8e77c0b49 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3900,7 +3900,7 @@ void CGDebugInfo::EmitFunctionDecl(GlobalDecl GD, 
SourceLocation Loc,
   if (IsDeclForCallSite)
 Fn->setSubprogram(SP);
 
-  DBuilder.retainType(SP);
+  DBuilder.finalizeSubprogram(SP);
 }
 
 void CGDebugInfo::EmitFuncDeclForCallSite(llvm::CallBase *CallOrInvoke,

diff  --git a/clang/test/CodeGen/debug-info-extern-call.c 
b/clang/test/CodeGen/debug-info-extern-call.c
index 072e578b5898..7ba115ad2ec9 100644
--- a/clang/test/CodeGen/debug-info-extern-call.c
+++ b/clang/test/CodeGen/debug-info-extern-call.c
@@ -1,6 +1,10 @@
 // When entry values are emitted, expect a subprogram for extern decls so that
 // the dwarf generator can describe call site parameters at extern call sites.
 //
+// Initial implementation relied on the 'retainedTypes:' from the corresponding
+// DICompileUnit, so we also ensure that we do not store the extern declaration
+// subprogram into the 'retainedTypes:'.
+//
 // RUN: %clang -g -O2 -target x86_64-none-linux-gnu -S -emit-llvm %s -o - \
 // RUN:   | FileCheck %s -check-prefix=DECLS-FOR-EXTERN
 
@@ -17,6 +21,8 @@
 // RUN: %clang -g -O2 -target x86_64-none-linux-gnu -gsce -S -emit-llvm %s -o 
- \
 // RUN:   | FileCheck %s -check-prefix=NO-DECLS-FOR-EXTERN
 
+// DECLS-FOR-EXTERN-NOT: !DICompileUnit({{.*}}retainedTypes: 
![[RETTYPES:[0-9]+]]
+// DECLS-FOR-EXTERN-NOT: ![[RETTYPES]] = !{
 // DECLS-FOR-EXTERN: !DISubprogram(name: "fn1"
 // DECLS-FOR-EXTERN-NOT: !DISubprogram(name: "memcmp"
 // DECLS-FOR-EXTERN-NOT: !DISubprogram(name: "__some_reserved_name"

diff  --git a/clang/test/Modules/DebugInfoTransitiveImport.m 
b/clang/test/Modules/DebugInfoTransitiveImport.m
index 08dfecfb7899..bd763e81cf85 100644
--- a/clang/test/Modules/DebugInfoTransitiveImport.m
+++ b/clang/test/Modules/DebugInfoTransitiveImport.m
@@ -12,10 +12,10 @@
 
 // Definition of left:
 // CHECK: !DICompileUnit({{.*}}dwoId:
-// CHECK: ![[LEFT:[0-9]+]] = !DIFile({{.*}}diamond_left.h
 // CHECK: !DIImportedEntity(tag: DW_TAG_imported_declaration,
-// CHECK-SAME:  entity: ![[MODULE:.*]], file: ![[LEFT]], line: 3)
+// CHECK-SAME:  entity: ![[MODULE:.*]], file: ![[LEFT:.*]], line: 
3)
 // CHECK: ![[MODULE]] = !DIModule(scope: null, name: "diamond_top"
+// CHECK: ![[LEFT]] = !DIFile({{.*}}diamond_left.h
 
 // Skeleton for top:
 // CHECK: !DICompileUnit({{.*}}splitDebugFilename: 
{{.*}}diamond_top{{.*}}dwoId:

diff  --git a/clang/test/Modules/ModuleDebugInfo.cpp 
b/clang/test/Modules/ModuleDebugInfo.cpp
index e6e99ed4e537..3121719e55a6 100644
--- a/clang/test/Modules/ModuleDebugInfo.cpp
+++ b/clang/test/Modules/ModuleDebugInfo.cpp
@@ -51,15 +51,6 @@
 // CHECK-SAME: )
 // CHECK: !DIEnumerator(name: "e5", value: 5, isUnsigned: true)
 
-// CHECK: !DIDerivedType(tag: DW_TAG_typedef, name: "B",
-// no mangled name here yet.
-
-// This type is anchored by a function parameter.
-// CHECK: !DICompositeType(tag: DW_TAG_class_type, name: "A"
-// CHECK-SAME: elements:
-// CHECK-SAME: templateParams:
-// CHECK-SAME: identifier: "_ZTSN8DebugCXX1AIJvEEE")
-
 // CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "Struct"
 // CHECK-SAME: identifier: "_ZTSN8DebugCXX6StructE")
 
@@ -85,6 +76,12 @@
 // CHECK-SAME: templateParams:
 // CHECK-SAME: identifier: 
"_ZTSN8DebugCXX8TemplateIlNS_6traitsIl")
 
+// This type is anchored by a function parameter.
+// CHECK: !DICompositeType(tag: DW_TAG_class_type, name: "A"
+// CHECK-SAME: elements:
+// CHECK-SAME: templateParams:
+// CHECK-SAME: identifier: "_ZTSN8DebugCXX1AIJvEEE")
+
 // CHECK: !DIDerivedType(tag: DW_TAG_typedef, name: "FloatInstantiation"
 // no mangled name her

[clang] 170ac4b - [CSInfo][ISEL] Call site info generation support for Mips

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-05-15T10:13:15+02:00
New Revision: 170ac4be3392201d5f5e124e8a1b7d78de3f82c8

URL: 
https://github.com/llvm/llvm-project/commit/170ac4be3392201d5f5e124e8a1b7d78de3f82c8
DIFF: 
https://github.com/llvm/llvm-project/commit/170ac4be3392201d5f5e124e8a1b7d78de3f82c8.diff

LOG: [CSInfo][ISEL] Call site info generation support for Mips

Debug entry values functionality provides debug information about
call sites and function parameters values at the call entry spot.
Condition for generating this type of information is
compiling with -g option and optimization level higher
than zero(-O0).

In ISEL phase, while lowering call instructions, collect info
about registers that forward arguments into following
function frame. We store such info into MachineFunction of
the caller function. This is used very late, when dumping DWARF
info about call site parameters.

The call site info is visible at MIR level, as callSites attribute
of MachineFunction. Also, when using unmodified parameter value
inside callee it could be described as DW_OP_entry_value expression.
To deal with callSites attribute, we should pass
-emit-call-site-info option to llc.

This patch enables functionality in clang frontend and adds
call site info generation support for MIPS targets
(mips, mipsel, mips64, mips64el).

Patch by Nikola Tesic

Differential Revision: https://reviews.llvm.org/D78105

Added: 
llvm/test/CodeGen/Mips/call-site-info-output.ll
llvm/test/CodeGen/Mips/dbg-call-site-info-reg-d-split.ll
llvm/test/DebugInfo/Mips/dw_op_entry_value_32bit.ll
llvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll

Modified: 
clang/lib/Frontend/CompilerInvocation.cpp
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/Mips/MipsTargetMachine.cpp

Removed: 




diff  --git a/clang/lib/Frontend/CompilerInvocation.cpp 
b/clang/lib/Frontend/CompilerInvocation.cpp
index 7e4bb6ea97e3..2ce71a96c35f 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -783,7 +783,8 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList 
&Args, InputKind IK,
 
   const llvm::Triple::ArchType DebugEntryValueArchs[] = {
   llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::aarch64,
-  llvm::Triple::arm, llvm::Triple::armeb};
+  llvm::Triple::arm, llvm::Triple::armeb, llvm::Triple::mips,
+  llvm::Triple::mipsel, llvm::Triple::mips64, llvm::Triple::mips64el};
 
   llvm::Triple T(TargetOpts.Triple);
   if (Opts.OptimizationLevel > 0 && Opts.hasReducedDebugInfo() &&

diff  --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp 
b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index f0b88cd63f4b..3018d8d77c19 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3217,6 +3217,9 @@ 
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NextStackOffset = CCInfo.getNextStackOffset();
 
+  // Call site info for function parameters tracking.
+  MachineFunction::CallSiteInfo CSInfo;
+
   // Check if it's really possible to do a tail call. Restrict it to functions
   // that are part of this compilation unit.
   bool InternalLinkage = false;
@@ -3343,6 +3346,17 @@ 
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
 // RegsToPass vector
 if (VA.isRegLoc()) {
   RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
+
+  // If the parameter is passed through reg $D, which splits into
+  // two physical registers, avoid creating call site info.
+  if (Mips::AFGR64RegClass.contains(VA.getLocReg()))
+continue;
+
+  // Collect CSInfo about which register passes which parameter.
+  const TargetOptions &Options = DAG.getTarget().Options;
+  if (Options.SupportsDebugEntryValues)
+CSInfo.emplace_back(VA.getLocReg(), i);
+
   continue;
 }
 
@@ -3447,12 +3461,16 @@ 
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
 
   if (IsTailCall) {
 MF.getFrameInfo().setHasTailCall();
-return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
+SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
+DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
+return Ret;
   }
 
   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
   SDValue InFlag = Chain.getValue(1);
 
+  DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
+
   // Create the CALLSEQ_END node in the case of where it is not a call to
   // memcpy.
   if (!(MemcpyInByVal)) {

diff  --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp 
b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 8fec6db00cb9..80cb6ce7ac0c 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -131,6 +131,9 @@ MipsTargetMachine::Mi

[clang] b5b6d3a - [Debugify] Port verify-debuginfo-preserve to NewPM

[Djordje Todorovic via cfe-commits]

Author: Nikola Tesic
Date: 2022-07-06T17:07:20+02:00
New Revision: b5b6d3a41b4eba23b604f37942b892a382caae57

URL: 
https://github.com/llvm/llvm-project/commit/b5b6d3a41b4eba23b604f37942b892a382caae57
DIFF: 
https://github.com/llvm/llvm-project/commit/b5b6d3a41b4eba23b604f37942b892a382caae57.diff

LOG: [Debugify] Port verify-debuginfo-preserve to NewPM

Debugify in OriginalDebugInfo mode, introduced with D82545,
runs only with legacy PassManager.

This patch enables this utility for the NewPM.

Differential Revision: https://reviews.llvm.org/D115351

Added: 
llvm/test/DebugInfo/verify-di-preserve.ll

Modified: 
clang/lib/CodeGen/BackendUtil.cpp
llvm/include/llvm/Transforms/Utils/Debugify.h
llvm/lib/Transforms/Utils/Debugify.cpp
llvm/test/DebugInfo/debugify-original-no-dbg-info.ll
llvm/test/Transforms/Util/Debugify/loc-only-original-mode.ll
llvm/tools/opt/NewPMDriver.cpp
llvm/tools/opt/NewPMDriver.h
llvm/tools/opt/opt.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/BackendUtil.cpp 
b/clang/lib/CodeGen/BackendUtil.cpp
index eb40e446057f9..7c4e35634e5dc 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -788,6 +788,18 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
   SI.registerCallbacks(PIC, &FAM);
   PassBuilder PB(TM.get(), PTO, PGOOpt, &PIC);
 
+  // Enable verify-debuginfo-preserve-each for new PM.
+  DebugifyEachInstrumentation Debugify;
+  DebugInfoPerPass DebugInfoBeforePass;
+  if (CodeGenOpts.EnableDIPreservationVerify) {
+Debugify.setDebugifyMode(DebugifyMode::OriginalDebugInfo);
+Debugify.setDebugInfoBeforePass(DebugInfoBeforePass);
+
+if (!CodeGenOpts.DIBugsReportFilePath.empty())
+  Debugify.setOrigDIVerifyBugsReportFilePath(
+  CodeGenOpts.DIBugsReportFilePath);
+Debugify.registerCallbacks(PIC);
+  }
   // Attempt to load pass plugins and register their callbacks with PB.
   for (auto &PluginFN : CodeGenOpts.PassPlugins) {
 auto PassPlugin = PassPlugin::Load(PluginFN);

diff  --git a/llvm/include/llvm/Transforms/Utils/Debugify.h 
b/llvm/include/llvm/Transforms/Utils/Debugify.h
index 405bbb8e0be8a..24b9eeab6ee45 100644
--- a/llvm/include/llvm/Transforms/Utils/Debugify.h
+++ b/llvm/include/llvm/Transforms/Utils/Debugify.h
@@ -101,7 +101,18 @@ llvm::FunctionPass *createDebugifyFunctionPass(
 llvm::StringRef NameOfWrappedPass = "",
 DebugInfoPerPass *DebugInfoBeforePass = nullptr);
 
-struct NewPMDebugifyPass : public llvm::PassInfoMixin {
+class NewPMDebugifyPass : public llvm::PassInfoMixin {
+  llvm::StringRef NameOfWrappedPass;
+  DebugInfoPerPass *DebugInfoBeforePass = nullptr;
+  enum DebugifyMode Mode = DebugifyMode::NoDebugify;
+public:
+  NewPMDebugifyPass(
+  enum DebugifyMode Mode = DebugifyMode::SyntheticDebugInfo,
+  llvm::StringRef NameOfWrappedPass = "",
+  DebugInfoPerPass *DebugInfoBeforePass = nullptr)
+  : NameOfWrappedPass(NameOfWrappedPass),
+DebugInfoBeforePass(DebugInfoBeforePass), Mode(Mode) {}
+
   llvm::PreservedAnalyses run(llvm::Module &M, llvm::ModuleAnalysisManager 
&AM);
 };
 
@@ -148,18 +159,65 @@ llvm::FunctionPass *createCheckDebugifyFunctionPass(
 DebugInfoPerPass *DebugInfoBeforePass = nullptr,
 llvm::StringRef OrigDIVerifyBugsReportFilePath = "");
 
-struct NewPMCheckDebugifyPass
+class NewPMCheckDebugifyPass
 : public llvm::PassInfoMixin {
+  llvm::StringRef NameOfWrappedPass;
+  llvm::StringRef OrigDIVerifyBugsReportFilePath;
+  DebugifyStatsMap *StatsMap;
+  DebugInfoPerPass *DebugInfoBeforePass;
+  enum DebugifyMode Mode;
+  bool Strip;
+public:
+  NewPMCheckDebugifyPass(
+  bool Strip = false, llvm::StringRef NameOfWrappedPass = "",
+  DebugifyStatsMap *StatsMap = nullptr,
+  enum DebugifyMode Mode = DebugifyMode::SyntheticDebugInfo,
+  DebugInfoPerPass *DebugInfoBeforePass = nullptr,
+  llvm::StringRef OrigDIVerifyBugsReportFilePath = "")
+  : NameOfWrappedPass(NameOfWrappedPass),
+OrigDIVerifyBugsReportFilePath(OrigDIVerifyBugsReportFilePath),
+StatsMap(StatsMap), DebugInfoBeforePass(DebugInfoBeforePass), 
Mode(Mode),
+Strip(Strip) {}
+
   llvm::PreservedAnalyses run(llvm::Module &M, llvm::ModuleAnalysisManager 
&AM);
 };
 
 namespace llvm {
 void exportDebugifyStats(StringRef Path, const DebugifyStatsMap &Map);
 
-struct DebugifyEachInstrumentation {
-  DebugifyStatsMap StatsMap;
+class DebugifyEachInstrumentation {
+  llvm::StringRef OrigDIVerifyBugsReportFilePath = "";
+  DebugInfoPerPass *DebugInfoBeforePass = nullptr;
+  enum DebugifyMode Mode = DebugifyMode::NoDebugify;
+  DebugifyStatsMap *DIStatsMap = nullptr;
+
+public:
 
   void registerCallbacks(PassInstrumentationCallbacks &PIC);
+  // Used within DebugifyMode::SyntheticDebugInfo mode.
+  void setDIStatsMap(DebugifyStatsMap &StatMap) { DIStatsMap = &StatMap; }
+  const DebugifyStatsMap &getDebugifyStatsMap(

[clang] 73777b4 - [Debugify] Optimize debugify original mode

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2022-03-22T12:14:00+01:00
New Revision: 73777b4c35a390617cce0f6b4516e98fe5a88df1

URL: 
https://github.com/llvm/llvm-project/commit/73777b4c35a390617cce0f6b4516e98fe5a88df1
DIFF: 
https://github.com/llvm/llvm-project/commit/73777b4c35a390617cce0f6b4516e98fe5a88df1.diff

LOG: [Debugify] Optimize debugify original mode

Before we start addressing the issue with having
a lot of false positives when using debugify in
the original mode, we have made a few patches that
should speed up the execution of the testing
utility Passes.

For example, when testing a large project
(let's say LLVM project itself), we can face
a lot of potential DI issues. Usually, we use
-verify-each-debuginfo-preserve (that is very
similar to -debugify-each) -- it collects
DI metadata before each Pass, and after the Pass
it checks if the Pass preserved the DI metadata.
However, we can speed up this process, since we
don't need to collect DI metadata before each
Pass -- we could use the DI metadata that are
collected after the previous Pass from
the pipeline as an input for the next Pass.

This patch speeds up the utility for ~2x.

Differential Revision: https://reviews.llvm.org/D115622

Added: 


Modified: 
clang/lib/CodeGen/BackendUtil.cpp
llvm/include/llvm/Transforms/Utils/Debugify.h
llvm/lib/Transforms/Utils/Debugify.cpp
llvm/tools/opt/opt.cpp
llvm/unittests/Transforms/Utils/DebugifyTest.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/BackendUtil.cpp 
b/clang/lib/CodeGen/BackendUtil.cpp
index 716a565ee7871..eaf34eedcb2bb 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -1003,10 +1003,10 @@ void 
EmitAssemblyHelper::EmitAssemblyWithLegacyPassManager(
 TheModule->setDataLayout(TM->createDataLayout());
 
   DebugifyCustomPassManager PerModulePasses;
-  DebugInfoPerPassMap DIPreservationMap;
+  DebugInfoPerPass DebugInfoBeforePass;
   if (CodeGenOpts.EnableDIPreservationVerify) {
 PerModulePasses.setDebugifyMode(DebugifyMode::OriginalDebugInfo);
-PerModulePasses.setDIPreservationMap(DIPreservationMap);
+PerModulePasses.setDebugInfoBeforePass(DebugInfoBeforePass);
 
 if (!CodeGenOpts.DIBugsReportFilePath.empty())
   PerModulePasses.setOrigDIVerifyBugsReportFilePath(

diff  --git a/llvm/include/llvm/Transforms/Utils/Debugify.h 
b/llvm/include/llvm/Transforms/Utils/Debugify.h
index 892e354cd9edb..405bbb8e0be8a 100644
--- a/llvm/include/llvm/Transforms/Utils/Debugify.h
+++ b/llvm/include/llvm/Transforms/Utils/Debugify.h
@@ -23,7 +23,8 @@
 #include "llvm/IR/ValueHandle.h"
 #include "llvm/Pass.h"
 
-using DebugFnMap = llvm::MapVector;
+using DebugFnMap =
+llvm::MapVector;
 using DebugInstMap = llvm::MapVector;
 using DebugVarMap = llvm::MapVector;
 using WeakInstValueMap =
@@ -42,9 +43,6 @@ struct DebugInfoPerPass {
   DebugVarMap DIVariables;
 };
 
-/// Map pass names to a per-pass DebugInfoPerPass instance.
-using DebugInfoPerPassMap = llvm::MapVector;
-
 namespace llvm {
 class DIBuilder;
 
@@ -69,24 +67,24 @@ bool stripDebugifyMetadata(Module &M);
 ///
 /// \param M The module to collect debug information from.
 /// \param Functions A range of functions to collect debug information from.
-/// \param DIPreservationMap A map to collect the DI metadata.
+/// \param DebugInfoBeforePass DI metadata before a pass.
 /// \param Banner A prefix string to add to debug/error messages.
 /// \param NameOfWrappedPass A name of a pass to add to debug/error messages.
 bool collectDebugInfoMetadata(Module &M,
   iterator_range Functions,
-  DebugInfoPerPassMap &DIPreservationMap,
+  DebugInfoPerPass &DebugInfoBeforePass,
   StringRef Banner, StringRef NameOfWrappedPass);
 
 /// Check original debug information after a pass.
 ///
 /// \param M The module to collect debug information from.
 /// \param Functions A range of functions to collect debug information from.
-/// \param DIPreservationMap A map used to check collected the DI metadata.
+/// \param DebugInfoBeforePass DI metadata before a pass.
 /// \param Banner A prefix string to add to debug/error messages.
 /// \param NameOfWrappedPass A name of a pass to add to debug/error messages.
 bool checkDebugInfoMetadata(Module &M,
 iterator_range Functions,
-DebugInfoPerPassMap &DIPreservationMap,
+DebugInfoPerPass &DebugInfoBeforePass,
 StringRef Banner, StringRef NameOfWrappedPass,
 StringRef OrigDIVerifyBugsReportFilePath);
 } // namespace llvm
@@ -97,11 +95,11 @@ enum class DebugifyMode { NoDebugify, SyntheticDebugInfo, 
OriginalDebugInfo };
 llvm::ModulePass *createDebugifyModulePass(
 enum DebugifyMode Mode = DebugifyMode::SyntheticDebugInfo,

Re: [clang] ce1f95a - Reland "[clang] Remove the DIFlagArgumentNotModified debug info flag"

[Djordje Todorovic via cfe-commits]

Thanks!

Best regards,
Djordje

On 27.12.19. 20:30, David Blaikie wrote:
> 
> 
> On Thu, Dec 26, 2019 at 11:58 PM Djordje Todorovic 
> mailto:djordje.todoro...@rt-rk.com>> wrote:
> 
> Hi David,
> 
> It's a good question.
> 
> Current approach of the debug entry values will consider an entry value 
> as a valid value until the variable gets modified.
> 
> Please consider this.
> 
> void fn(int a) {
>   ...
>   a++;
> }
> 
> If there is an instruction that does not affect the code generated, e.g. 
> an ADD instruction that gets optimized out from the case above, it won't 
> force us to invalidate all the entry values before, since the instruction is 
> not there in the final code generated. The GCC does the same thing in that 
> situation. But if the instruction were at the beginning of the function (or 
> somewhere else), we believe that there is an DBG_VALUE representing that 
> variable's change (e.g. generated from the Salvage Debug Info), so the entry 
> value would not be used any more.
> 
> If we come up with a case where a dead store causing an invalid use of 
> the entry values, that will be good point for improvements.
> 
> 
> Ah, OK, so you actually want to know whether the entry value gets really 
> modified, makes sense to do that in the backend then - thanks for explaining!
>  
> 
> 
> Best regards,
>     Djordje
> 
> On 26.12.19. 22:33, David Blaikie wrote:
> >
> >
> > On Wed, Nov 20, 2019 at 1:08 AM Djordje Todorovic via cfe-commits 
> mailto:cfe-commits@lists.llvm.org> 
> <mailto:cfe-commits@lists.llvm.org <mailto:cfe-commits@lists.llvm.org>>> 
> wrote:
> >
> >
> >     Author: Djordje Todorovic
> >     Date: 2019-11-20T10:08:07+01:00
> >     New Revision: ce1f95a6e077693f93d8869245f911aff3eb7e4c
> >
> >     URL: 
> https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c
> >     DIFF: 
> https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c.diff
> >
> >     LOG: Reland "[clang] Remove the DIFlagArgumentNotModified debug 
> info flag"
> >
> >     It turns out that the ExprMutationAnalyzer can be very slow when AST
> >     gets huge in some cases. The idea is to move this analysis to the 
> LLVM
> >     back-end level (more precisely, in the LiveDebugValues pass). The 
> new
> >     approach will remove the performance regression, simplify the
> >     implementation and give us front-end independent implementation.
> >
> >
> > What if the LLVM backend optimized out a dead store? (then we might 
> concnlude that the argument is not modified, when it actually is modified?)
> >  
> >
> >
> >     Differential Revision: https://reviews.llvm.org/D68206
> >
> >     Added:
> >
> >
> >     Modified:
> >         clang/lib/CodeGen/CGDebugInfo.cpp
> >         clang/lib/CodeGen/CGDebugInfo.h
> >         
> lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/TestBasicEntryValuesX86_64.py
> >
> >     Removed:
> >         clang/test/CodeGen/debug-info-param-modification.c
> >
> >
> >     
> 
> >     diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
> b/clang/lib/CodeGen/CGDebugInfo.cpp
> >     index 116517a9cb99..a9b3831aa0b5 100644
> >     --- a/clang/lib/CodeGen/CGDebugInfo.cpp
> >     +++ b/clang/lib/CodeGen/CGDebugInfo.cpp
> >     @@ -18,7 +18,6 @@
> >      #include "CodeGenFunction.h"
> >      #include "CodeGenModule.h"
> >      #include "ConstantEmitter.h"
> >     -#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
> >      #include "clang/AST/ASTContext.h"
> >      #include "clang/AST/DeclFriend.h"
> >      #include "clang/AST/DeclObjC.h"
> >     @@ -3686,15 +3685,6 @@ void 
> CGDebugInfo::EmitFunctionStart(GlobalDecl GD, SourceLocation Loc,
> >        if (HasDecl && isa(D))
> >          DeclCache[D->getCanonicalDecl()].reset(SP);
> >
> >     -  // We use the SPDefCache only in the case when the debug entry 
> values option
> >     -  // is set, in order to speed up parameters modification analysis.

[clang] faff707 - Reland "[DebugInfo] Enable the debug entry values feature by default"

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-02-19T11:12:26+01:00
New Revision: faff707db82d7db12fcd9f7826b8741261230e63

URL: 
https://github.com/llvm/llvm-project/commit/faff707db82d7db12fcd9f7826b8741261230e63
DIFF: 
https://github.com/llvm/llvm-project/commit/faff707db82d7db12fcd9f7826b8741261230e63.diff

LOG: Reland "[DebugInfo] Enable the debug entry values feature by default"

Differential Revision: https://reviews.llvm.org/D73534

Added: 
llvm/test/DebugInfo/MIR/ARM/dbgcallsite-noreg-is-imm-check.mir
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll

Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/AArch64/arm64-anyregcc.ll
llvm/test/CodeGen/AArch64/arm64-patchpoint.ll
llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
llvm/test/CodeGen/ARM/smml.ll
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/CodeGen/X86/hoist-invariant-load.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/statepoint-allocas.ll
llvm/test/CodeGen/X86/tail-dup-repeat.ll
llvm/test/CodeGen/X86/xray-custom-log.ll
llvm/test/CodeGen/X86/xray-typed-event-log.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86

[clang] 2f215cf - Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-02-20T14:41:39+01:00
New Revision: 2f215cf36adced6bf1abda4bdbbc6422c1369353

URL: 
https://github.com/llvm/llvm-project/commit/2f215cf36adced6bf1abda4bdbbc6422c1369353
DIFF: 
https://github.com/llvm/llvm-project/commit/2f215cf36adced6bf1abda4bdbbc6422c1369353.diff

LOG: Revert "Reland "[DebugInfo] Enable the debug entry values feature by 
default""

This reverts commit rGfaff707db82d.
A failure found on an ARM 2-stage buildbot.
The investigation is needed.

Added: 


Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/AArch64/arm64-anyregcc.ll
llvm/test/CodeGen/AArch64/arm64-patchpoint.ll
llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
llvm/test/CodeGen/ARM/smml.ll
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/CodeGen/X86/hoist-invariant-load.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/statepoint-allocas.ll
llvm/test/CodeGen/X86/tail-dup-repeat.ll
llvm/test/CodeGen/X86/xray-custom-log.ll
llvm/test/CodeGen/X86/xray-typed-event-log.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86/loclists-dwp.ll
llvm/test/tools/llvm-dwarfdump/X

[clang] 1643734 - [clang] Remove the DIFlagArgumentNotModified debug info flag

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2019-11-15T11:10:19+01:00
New Revision: 1643734741d2f2957206774a50960ba335a36a0c

URL: 
https://github.com/llvm/llvm-project/commit/1643734741d2f2957206774a50960ba335a36a0c
DIFF: 
https://github.com/llvm/llvm-project/commit/1643734741d2f2957206774a50960ba335a36a0c.diff

LOG: [clang] Remove the DIFlagArgumentNotModified debug info flag

It turns out that the ExprMutationAnalyzer can be very slow when AST
gets huge in some cases. The idea is to move this analysis to the LLVM
back-end level (more precisely, in the LiveDebugValues pass). The new
approach will remove the performance regression, simplify the
implementation and give us front-end independent implementation.

Differential Revision: https://reviews.llvm.org/D68206

Added: 


Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CGDebugInfo.h

Removed: 
clang/test/CodeGen/debug-info-param-modification.c



diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 75c4b2ae2339..399fa95c3e0b 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -18,7 +18,6 @@
 #include "CodeGenFunction.h"
 #include "CodeGenModule.h"
 #include "ConstantEmitter.h"
-#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclFriend.h"
 #include "clang/AST/DeclObjC.h"
@@ -3686,15 +3685,6 @@ void CGDebugInfo::EmitFunctionStart(GlobalDecl GD, 
SourceLocation Loc,
   if (HasDecl && isa(D))
 DeclCache[D->getCanonicalDecl()].reset(SP);
 
-  // We use the SPDefCache only in the case when the debug entry values option
-  // is set, in order to speed up parameters modification analysis.
-  //
-  // FIXME: Use AbstractCallee here to support ObjCMethodDecl.
-  if (CGM.getCodeGenOpts().EnableDebugEntryValues && HasDecl)
-if (auto *FD = dyn_cast(D))
-  if (FD->hasBody() && !FD->param_empty())
-SPDefCache[FD].reset(SP);
-
   // Push the function onto the lexical block stack.
   LexicalBlockStack.emplace_back(SP);
 
@@ -4089,11 +4079,6 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const 
VarDecl *VD,
  llvm::DebugLoc::get(Line, Column, Scope, 
CurInlinedAt),
  Builder.GetInsertBlock());
 
-  if (CGM.getCodeGenOpts().EnableDebugEntryValues && ArgNo) {
-if (auto *PD = dyn_cast(VD))
-  ParamCache[PD].reset(D);
-  }
-
   return D;
 }
 
@@ -4709,29 +4694,6 @@ void CGDebugInfo::setDwoId(uint64_t Signature) {
   TheCU->setDWOId(Signature);
 }
 
-/// Analyzes each function parameter to determine whether it is constant
-/// throughout the function body.
-static void analyzeParametersModification(
-ASTContext &Ctx,
-llvm::DenseMap &SPDefCache,
-llvm::DenseMap &ParamCache) {
-  for (auto &SP : SPDefCache) {
-auto *FD = SP.first;
-assert(FD->hasBody() && "Functions must have body here");
-const Stmt *FuncBody = (*FD).getBody();
-for (auto Parm : FD->parameters()) {
-  ExprMutationAnalyzer FuncAnalyzer(*FuncBody, Ctx);
-  if (FuncAnalyzer.isMutated(Parm))
-continue;
-
-  auto I = ParamCache.find(Parm);
-  assert(I != ParamCache.end() && "Parameters should be already cached");
-  auto *DIParm = cast(I->second);
-  DIParm->setIsNotModified();
-}
-  }
-}
-
 void CGDebugInfo::finalize() {
   // Creating types might create further types - invalidating the current
   // element and the size(), so don't cache/reference them.
@@ -4804,10 +4766,6 @@ void CGDebugInfo::finalize() {
 if (auto MD = TypeCache[RT])
   DBuilder.retainType(cast(MD));
 
-  if (CGM.getCodeGenOpts().EnableDebugEntryValues)
-// This will be used to emit debug entry values.
-analyzeParametersModification(CGM.getContext(), SPDefCache, ParamCache);
-
   DBuilder.finalize();
 }
 

diff  --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 9a097615b4b4..5341bfa7f350 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -146,10 +146,6 @@ class CGDebugInfo {
 
   llvm::DenseMap DIFileCache;
   llvm::DenseMap SPCache;
-  /// Cache function definitions relevant to use for parameters mutation
-  /// analysis.
-  llvm::DenseMap SPDefCache;
-  llvm::DenseMap ParamCache;
   /// Cache declarations relevant to DW_TAG_imported_declarations (C++
   /// using declarations) that aren't covered by other more specific caches.
   llvm::DenseMap DeclCache;

diff  --git a/clang/test/CodeGen/debug-info-param-modification.c 
b/clang/test/CodeGen/debug-info-param-modification.c
deleted file mode 100644
index f0a13a3777db..
--- a/clang/test/CodeGen/debug-info-param-modification.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// RUN: %clang -Xclang -femit-debug-entry-values -g -O2 -Xclang 
-disable-llvm-passes -S -target x86_64-none-linux-gnu -emit-llvm %s -o - | 
FileCheck %s -check-prefix=

[clang] 41d6ad6 - Revert "[clang] Remove the DIFlagArgumentNotModified debug info flag"

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2019-11-15T12:16:44+01:00
New Revision: 41d6ad6efddadbb905bd14c53c2731b75f30cca7

URL: 
https://github.com/llvm/llvm-project/commit/41d6ad6efddadbb905bd14c53c2731b75f30cca7
DIFF: 
https://github.com/llvm/llvm-project/commit/41d6ad6efddadbb905bd14c53c2731b75f30cca7.diff

LOG: Revert "[clang] Remove the DIFlagArgumentNotModified debug info flag"

This reverts commit rG1643734741d2 due to LLDB test failure.

Added: 
clang/test/CodeGen/debug-info-param-modification.c

Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CGDebugInfo.h

Removed: 




diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 399fa95c3e0b..75c4b2ae2339 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -18,6 +18,7 @@
 #include "CodeGenFunction.h"
 #include "CodeGenModule.h"
 #include "ConstantEmitter.h"
+#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclFriend.h"
 #include "clang/AST/DeclObjC.h"
@@ -3685,6 +3686,15 @@ void CGDebugInfo::EmitFunctionStart(GlobalDecl GD, 
SourceLocation Loc,
   if (HasDecl && isa(D))
 DeclCache[D->getCanonicalDecl()].reset(SP);
 
+  // We use the SPDefCache only in the case when the debug entry values option
+  // is set, in order to speed up parameters modification analysis.
+  //
+  // FIXME: Use AbstractCallee here to support ObjCMethodDecl.
+  if (CGM.getCodeGenOpts().EnableDebugEntryValues && HasDecl)
+if (auto *FD = dyn_cast(D))
+  if (FD->hasBody() && !FD->param_empty())
+SPDefCache[FD].reset(SP);
+
   // Push the function onto the lexical block stack.
   LexicalBlockStack.emplace_back(SP);
 
@@ -4079,6 +4089,11 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const 
VarDecl *VD,
  llvm::DebugLoc::get(Line, Column, Scope, 
CurInlinedAt),
  Builder.GetInsertBlock());
 
+  if (CGM.getCodeGenOpts().EnableDebugEntryValues && ArgNo) {
+if (auto *PD = dyn_cast(VD))
+  ParamCache[PD].reset(D);
+  }
+
   return D;
 }
 
@@ -4694,6 +4709,29 @@ void CGDebugInfo::setDwoId(uint64_t Signature) {
   TheCU->setDWOId(Signature);
 }
 
+/// Analyzes each function parameter to determine whether it is constant
+/// throughout the function body.
+static void analyzeParametersModification(
+ASTContext &Ctx,
+llvm::DenseMap &SPDefCache,
+llvm::DenseMap &ParamCache) {
+  for (auto &SP : SPDefCache) {
+auto *FD = SP.first;
+assert(FD->hasBody() && "Functions must have body here");
+const Stmt *FuncBody = (*FD).getBody();
+for (auto Parm : FD->parameters()) {
+  ExprMutationAnalyzer FuncAnalyzer(*FuncBody, Ctx);
+  if (FuncAnalyzer.isMutated(Parm))
+continue;
+
+  auto I = ParamCache.find(Parm);
+  assert(I != ParamCache.end() && "Parameters should be already cached");
+  auto *DIParm = cast(I->second);
+  DIParm->setIsNotModified();
+}
+  }
+}
+
 void CGDebugInfo::finalize() {
   // Creating types might create further types - invalidating the current
   // element and the size(), so don't cache/reference them.
@@ -4766,6 +4804,10 @@ void CGDebugInfo::finalize() {
 if (auto MD = TypeCache[RT])
   DBuilder.retainType(cast(MD));
 
+  if (CGM.getCodeGenOpts().EnableDebugEntryValues)
+// This will be used to emit debug entry values.
+analyzeParametersModification(CGM.getContext(), SPDefCache, ParamCache);
+
   DBuilder.finalize();
 }
 

diff  --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 5341bfa7f350..9a097615b4b4 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -146,6 +146,10 @@ class CGDebugInfo {
 
   llvm::DenseMap DIFileCache;
   llvm::DenseMap SPCache;
+  /// Cache function definitions relevant to use for parameters mutation
+  /// analysis.
+  llvm::DenseMap SPDefCache;
+  llvm::DenseMap ParamCache;
   /// Cache declarations relevant to DW_TAG_imported_declarations (C++
   /// using declarations) that aren't covered by other more specific caches.
   llvm::DenseMap DeclCache;

diff  --git a/clang/test/CodeGen/debug-info-param-modification.c 
b/clang/test/CodeGen/debug-info-param-modification.c
new file mode 100644
index ..f0a13a3777db
--- /dev/null
+++ b/clang/test/CodeGen/debug-info-param-modification.c
@@ -0,0 +1,25 @@
+// RUN: %clang -Xclang -femit-debug-entry-values -g -O2 -Xclang 
-disable-llvm-passes -S -target x86_64-none-linux-gnu -emit-llvm %s -o - | 
FileCheck %s -check-prefix=CHECK-ENTRY-VAL-OPT
+// RUN: %clang -Xclang -femit-debug-entry-values -g -O2 -Xclang 
-disable-llvm-passes -S -target arm-none-linux-gnu -emit-llvm %s -o - | 
FileCheck %s -check-prefix=CHECK-ENTRY-VAL-OPT
+// RUN: %clang -Xclang -femit-debug-entry-values -g -O2 -Xclang 
-disable-llvm-passes -S -target aarch64-none-linux-gnu 

[clang] ce1f95a - Reland "[clang] Remove the DIFlagArgumentNotModified debug info flag"

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2019-11-20T10:08:07+01:00
New Revision: ce1f95a6e077693f93d8869245f911aff3eb7e4c

URL: 
https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c
DIFF: 
https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c.diff

LOG: Reland "[clang] Remove the DIFlagArgumentNotModified debug info flag"

It turns out that the ExprMutationAnalyzer can be very slow when AST
gets huge in some cases. The idea is to move this analysis to the LLVM
back-end level (more precisely, in the LiveDebugValues pass). The new
approach will remove the performance regression, simplify the
implementation and give us front-end independent implementation.

Differential Revision: https://reviews.llvm.org/D68206

Added: 


Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CGDebugInfo.h

lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/TestBasicEntryValuesX86_64.py

Removed: 
clang/test/CodeGen/debug-info-param-modification.c



diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 116517a9cb99..a9b3831aa0b5 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -18,7 +18,6 @@
 #include "CodeGenFunction.h"
 #include "CodeGenModule.h"
 #include "ConstantEmitter.h"
-#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclFriend.h"
 #include "clang/AST/DeclObjC.h"
@@ -3686,15 +3685,6 @@ void CGDebugInfo::EmitFunctionStart(GlobalDecl GD, 
SourceLocation Loc,
   if (HasDecl && isa(D))
 DeclCache[D->getCanonicalDecl()].reset(SP);
 
-  // We use the SPDefCache only in the case when the debug entry values option
-  // is set, in order to speed up parameters modification analysis.
-  //
-  // FIXME: Use AbstractCallee here to support ObjCMethodDecl.
-  if (CGM.getCodeGenOpts().EnableDebugEntryValues && HasDecl)
-if (auto *FD = dyn_cast(D))
-  if (FD->hasBody() && !FD->param_empty())
-SPDefCache[FD].reset(SP);
-
   // Push the function onto the lexical block stack.
   LexicalBlockStack.emplace_back(SP);
 
@@ -4097,11 +4087,6 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const 
VarDecl *VD,
  llvm::DebugLoc::get(Line, Column, Scope, 
CurInlinedAt),
  Builder.GetInsertBlock());
 
-  if (CGM.getCodeGenOpts().EnableDebugEntryValues && ArgNo) {
-if (auto *PD = dyn_cast(VD))
-  ParamCache[PD].reset(D);
-  }
-
   return D;
 }
 
@@ -4717,29 +4702,6 @@ void CGDebugInfo::setDwoId(uint64_t Signature) {
   TheCU->setDWOId(Signature);
 }
 
-/// Analyzes each function parameter to determine whether it is constant
-/// throughout the function body.
-static void analyzeParametersModification(
-ASTContext &Ctx,
-llvm::DenseMap &SPDefCache,
-llvm::DenseMap &ParamCache) {
-  for (auto &SP : SPDefCache) {
-auto *FD = SP.first;
-assert(FD->hasBody() && "Functions must have body here");
-const Stmt *FuncBody = (*FD).getBody();
-for (auto Parm : FD->parameters()) {
-  ExprMutationAnalyzer FuncAnalyzer(*FuncBody, Ctx);
-  if (FuncAnalyzer.isMutated(Parm))
-continue;
-
-  auto I = ParamCache.find(Parm);
-  assert(I != ParamCache.end() && "Parameters should be already cached");
-  auto *DIParm = cast(I->second);
-  DIParm->setIsNotModified();
-}
-  }
-}
-
 void CGDebugInfo::finalize() {
   // Creating types might create further types - invalidating the current
   // element and the size(), so don't cache/reference them.
@@ -4812,10 +4774,6 @@ void CGDebugInfo::finalize() {
 if (auto MD = TypeCache[RT])
   DBuilder.retainType(cast(MD));
 
-  if (CGM.getCodeGenOpts().EnableDebugEntryValues)
-// This will be used to emit debug entry values.
-analyzeParametersModification(CGM.getContext(), SPDefCache, ParamCache);
-
   DBuilder.finalize();
 }
 

diff  --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 9a097615b4b4..5341bfa7f350 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -146,10 +146,6 @@ class CGDebugInfo {
 
   llvm::DenseMap DIFileCache;
   llvm::DenseMap SPCache;
-  /// Cache function definitions relevant to use for parameters mutation
-  /// analysis.
-  llvm::DenseMap SPDefCache;
-  llvm::DenseMap ParamCache;
   /// Cache declarations relevant to DW_TAG_imported_declarations (C++
   /// using declarations) that aren't covered by other more specific caches.
   llvm::DenseMap DeclCache;

diff  --git a/clang/test/CodeGen/debug-info-param-modification.c 
b/clang/test/CodeGen/debug-info-param-modification.c
deleted file mode 100644
index f0a13a3777db..
--- a/clang/test/CodeGen/debug-info-param-modification.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// RUN: %clang -Xclang -femit

Re: [clang] ce1f95a - Reland "[clang] Remove the DIFlagArgumentNotModified debug info flag"

[Djordje Todorovic via cfe-commits]

Hi David,

It's a good question.

Current approach of the debug entry values will consider an entry value as a 
valid value until the variable gets modified.

Please consider this.

void fn(int a) {
  ...
  a++;
}

If there is an instruction that does not affect the code generated, e.g. an ADD 
instruction that gets optimized out from the case above, it won't force us to 
invalidate all the entry values before, since the instruction is not there in 
the final code generated. The GCC does the same thing in that situation. But if 
the instruction were at the beginning of the function (or somewhere else), we 
believe that there is an DBG_VALUE representing that variable's change (e.g. 
generated from the Salvage Debug Info), so the entry value would not be used 
any more.

If we come up with a case where a dead store causing an invalid use of the 
entry values, that will be good point for improvements.

Best regards,
Djordje

On 26.12.19. 22:33, David Blaikie wrote:
> 
> 
> On Wed, Nov 20, 2019 at 1:08 AM Djordje Todorovic via cfe-commits 
> mailto:cfe-commits@lists.llvm.org>> wrote:
> 
> 
> Author: Djordje Todorovic
> Date: 2019-11-20T10:08:07+01:00
> New Revision: ce1f95a6e077693f93d8869245f911aff3eb7e4c
> 
> URL: 
> https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c
> DIFF: 
> https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c.diff
> 
> LOG: Reland "[clang] Remove the DIFlagArgumentNotModified debug info flag"
> 
> It turns out that the ExprMutationAnalyzer can be very slow when AST
> gets huge in some cases. The idea is to move this analysis to the LLVM
> back-end level (more precisely, in the LiveDebugValues pass). The new
> approach will remove the performance regression, simplify the
> implementation and give us front-end independent implementation.
> 
> 
> What if the LLVM backend optimized out a dead store? (then we might concnlude 
> that the argument is not modified, when it actually is modified?)
>  
> 
> 
> Differential Revision: https://reviews.llvm.org/D68206
> 
> Added:
> 
> 
> Modified:
>     clang/lib/CodeGen/CGDebugInfo.cpp
>     clang/lib/CodeGen/CGDebugInfo.h
>     
> lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/TestBasicEntryValuesX86_64.py
> 
> Removed:
>     clang/test/CodeGen/debug-info-param-modification.c
> 
> 
> 
> 
> diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
> b/clang/lib/CodeGen/CGDebugInfo.cpp
> index 116517a9cb99..a9b3831aa0b5 100644
> --- a/clang/lib/CodeGen/CGDebugInfo.cpp
> +++ b/clang/lib/CodeGen/CGDebugInfo.cpp
> @@ -18,7 +18,6 @@
>  #include "CodeGenFunction.h"
>  #include "CodeGenModule.h"
>  #include "ConstantEmitter.h"
> -#include "clang/Analysis/Analyses/ExprMutationAnalyzer.h"
>  #include "clang/AST/ASTContext.h"
>  #include "clang/AST/DeclFriend.h"
>  #include "clang/AST/DeclObjC.h"
> @@ -3686,15 +3685,6 @@ void CGDebugInfo::EmitFunctionStart(GlobalDecl GD, 
> SourceLocation Loc,
>    if (HasDecl && isa(D))
>      DeclCache[D->getCanonicalDecl()].reset(SP);
> 
> -  // We use the SPDefCache only in the case when the debug entry values 
> option
> -  // is set, in order to speed up parameters modification analysis.
> -  //
> -  // FIXME: Use AbstractCallee here to support ObjCMethodDecl.
> -  if (CGM.getCodeGenOpts().EnableDebugEntryValues && HasDecl)
> -    if (auto *FD = dyn_cast(D))
> -      if (FD->hasBody() && !FD->param_empty())
> -        SPDefCache[FD].reset(SP);
> -
>    // Push the function onto the lexical block stack.
>    LexicalBlockStack.emplace_back(SP);
> 
> @@ -4097,11 +4087,6 @@ llvm::DILocalVariable 
> *CGDebugInfo::EmitDeclare(const VarDecl *VD,
>                           llvm::DebugLoc::get(Line, Column, Scope, 
> CurInlinedAt),
>                           Builder.GetInsertBlock());
> 
> -  if (CGM.getCodeGenOpts().EnableDebugEntryValues && ArgNo) {
> -    if (auto *PD = dyn_cast(VD))
> -      ParamCache[PD].reset(D);
> -  }
> -
>    return D;
>  }
> 
> @@ -4717,29 +4702,6 @@ void CGDebugInfo::setDwoId(uint64_t Signature) {
>    TheCU->setDWOId(Signature);
>  }
> 
> -/// Analyzes each function parameter to determine whether it is constant
> -/// throughout the function body.

[clang] c15c68a - [CallSiteInfo] Enable the call site info only for -g + optimizations

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-03-09T12:12:44+01:00
New Revision: c15c68abdc6f1afece637bdedba808676191a8e6

URL: 
https://github.com/llvm/llvm-project/commit/c15c68abdc6f1afece637bdedba808676191a8e6
DIFF: 
https://github.com/llvm/llvm-project/commit/c15c68abdc6f1afece637bdedba808676191a8e6.diff

LOG: [CallSiteInfo] Enable the call site info only for -g + optimizations

Emit call site info only in the case of '-g' + 'O>0' level.

Differential Revision: https://reviews.llvm.org/D75175

Added: 


Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/Frontend/CompilerInvocation.cpp
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-chain.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-entry-value.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir
llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir
llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/dbgcallsite-noreg-is-imm-check.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll

Removed: 




diff  --git a/clang/include/clang/Basic/CodeGenOptions.def 
b/clang/include/clang/Basic/CodeGenOptions.def
index 48c0df49e32d..3c8b0eeb47a5 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -64,6 +64,8 @@ CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug 
information for the new
///< pass manager.
 CODEGENOPT(DisableRedZone, 1, 0) ///< Set when -mno-red-zone is enabled.
 CODEGENOPT(EnableDebugEntryValues, 1, 0) ///< Emit call site parameter dbg info
+CODEGENOPT(EmitCallSiteInfo, 1, 0) ///< Emit call site info only in the case of
+   ///< '-g' + 'O>0' level.
 CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs
  ///< is specified.
 CODEGENOPT(DisableTailCalls  , 1, 0) ///< Do not emit tail calls.

diff  --git a/clang/lib/CodeGen/BackendUtil.cpp 
b/clang/lib/CodeGen/BackendUtil.cpp
index b244fd499fb0..b6ca46e7e835 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -487,6 +487,7 @@ static void initTargetOptions(llvm::TargetOptions &Options,
   Options.EmitAddrsig = CodeGenOpts.Addrsig;
   Options.EnableDebugEntryValues = CodeGenOpts.EnableDebugEntryValues;
   Options.ForceDwarfFrameSection = CodeGenOpts.ForceDwarfFrameSection;
+  Options.EmitCallSiteIn

[clang] 5aa5c94 - Reland "[DebugInfo] Enable the debug entry values feature by default"

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-03-10T09:15:06+01:00
New Revision: 5aa5c943f7da155b95564058cd5d50a93eabfc89

URL: 
https://github.com/llvm/llvm-project/commit/5aa5c943f7da155b95564058cd5d50a93eabfc89
DIFF: 
https://github.com/llvm/llvm-project/commit/5aa5c943f7da155b95564058cd5d50a93eabfc89.diff

LOG: Reland "[DebugInfo] Enable the debug entry values feature by default"

Differential Revision: https://reviews.llvm.org/D73534

Added: 
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll

Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir
llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86/loclists-dwp.ll
llvm/test/tools/llvm-locstats/locstats.ll

Removed: 




diff  --git a/clang/include/clang/Basic/CodeGenOptions.def 
b/clang/include/clang/Basic/CodeGenOptions.def
index 3c8b0eeb47a5..e047054447f3 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -63,7 +63,6 @@ CODEGENOPT(ExperimentalNewPassManager, 1, 0) ///< Enables the 
new, experimental
 CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new
///< pass manager.
 CODEGENOPT(DisableRedZone, 1, 0) ///< Set when -mno-red-zone is enabled.
-CODEGENOPT(EnableDebugEntryValues, 1, 0) ///< Emit call site parameter dbg info
 CODEGENOPT(EmitCallSiteInfo, 1, 0) ///< Emit call site info only in the case of
///< '-g' + 'O>0' level.
 CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs

diff  --git a/clang/include/clang/Driver/CC1Options.td 
b/clang/include/clang/Driver/CC1Options.td
index b7a2826d8fcb..cc30893703df 100644
--- a/clang/include/clang/Driver/CC1Options.td
+++ b/clang/include/clang/Driver/CC1Options.td
@@ -388,8 +388,6 @@ def flto_visibility_public_std:
 def flto_unit: Flag<["-"], "flto-unit">,
 HelpText<"Emit IR to support LTO unit features (CFI, whole program vtable 
opt)">;
 def fno_lto_unit: Flag<["-"], "fno-lto-unit">;
-def femit_debug_entry_values : Flag<["-"], "femit-debug-entry-values">,
-HelpText<"Enables debug info about call site parameter's entry values">;
 def fdebug_pass_manager : Flag<["-"], "fdebug-pass-manager">,
 HelpText<"Prints debug information for the new pass m

[clang] d9b9621 - Reland D73534: [DebugInfo] Enable the debug entry values feature by default

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-03-19T13:57:30+01:00
New Revision: d9b962100942c71a4c26debaa716f7ab0c4ea8a1

URL: 
https://github.com/llvm/llvm-project/commit/d9b962100942c71a4c26debaa716f7ab0c4ea8a1
DIFF: 
https://github.com/llvm/llvm-project/commit/d9b962100942c71a4c26debaa716f7ab0c4ea8a1.diff

LOG: Reland D73534: [DebugInfo] Enable the debug entry values feature by default

The issue that was causing the build failures was fixed with the D76164.

Added: 
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll

Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/CommandFlags.cpp
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/DebugInfo/AArch64/dbgcall-site-float-entry-value.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir
llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/callsite-stack-value.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86/loclists-dwp.ll
llvm/test/tools/llvm-locstats/locstats.ll

Removed: 




diff  --git a/clang/include/clang/Basic/CodeGenOptions.def 
b/clang/include/clang/Basic/CodeGenOptions.def
index 3c8b0eeb47a5..e047054447f3 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -63,7 +63,6 @@ CODEGENOPT(ExperimentalNewPassManager, 1, 0) ///< Enables the 
new, experimental
 CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new
///< pass manager.
 CODEGENOPT(DisableRedZone, 1, 0) ///< Set when -mno-red-zone is enabled.
-CODEGENOPT(EnableDebugEntryValues, 1, 0) ///< Emit call site parameter dbg info
 CODEGENOPT(EmitCallSiteInfo, 1, 0) ///< Emit call site info only in the case of
///< '-g' + 'O>0' level.
 CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs

diff  --git a/clang/include/clang/Driver/CC1Options.td 
b/clang/include/clang/Driver/CC1Options.td
index b7a2826d8fcb..cc30893703df 100644
--- a/clang/include/clang/Driver/CC1Options.td
+++ b/clang/include/clang/Driver/CC1Options.td
@@ -388,8 +388,6 @@ def flto_visibility_public_std:
 def flto_unit: Flag<["-"], "flto-unit">,
 HelpText<"Emit IR to support LTO unit features (CFI, whole program vtable 
opt)">;
 def fno_lto_unit: Flag<["-"], "fno-lto-unit">;
-def femit_debug_entry_values : Flag<["-"], "femit-debug-entry-values">,
-HelpText<"Enables debug info about call site parameter's

[clang] 9f6ff07 - [DebugInfo] Enable the debug entry values feature by default

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-02-12T10:25:14+01:00
New Revision: 9f6ff07f8a396dfc736c4cb6f9fba9a203531329

URL: 
https://github.com/llvm/llvm-project/commit/9f6ff07f8a396dfc736c4cb6f9fba9a203531329
DIFF: 
https://github.com/llvm/llvm-project/commit/9f6ff07f8a396dfc736c4cb6f9fba9a203531329.diff

LOG: [DebugInfo] Enable the debug entry values feature by default

This patch enables the debug entry values feature.

  - Remove the (CC1) experimental -femit-debug-entry-values option
  - Enable it for x86, arm and aarch64 targets
  - Resolve the test failures
  - Leave the llc experimental option for targets that do not
support the CallSiteInfo yet

Differential Revision: https://reviews.llvm.org/D73534

Added: 
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll

Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/ARM/smml.ll
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86/loclists-dwp.ll
llvm/test/tools/llvm-dwarfdump/X86/locstats.ll
llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll
llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll
llvm/test/tools/llvm-locstats/locstats.ll

Removed: 




diff  --git a/clang/include/clang/Basic/CodeGenOptions.

[clang] 97ed706 - Revert "[DebugInfo] Enable the debug entry values feature by default"

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-02-12T11:59:04+01:00
New Revision: 97ed706a962af7c6835c7b6716207c4072011ac1

URL: 
https://github.com/llvm/llvm-project/commit/97ed706a962af7c6835c7b6716207c4072011ac1
DIFF: 
https://github.com/llvm/llvm-project/commit/97ed706a962af7c6835c7b6716207c4072011ac1.diff

LOG: Revert "[DebugInfo] Enable the debug entry values feature by default"

This reverts commit rG9f6ff07f8a39.

Found a test failure on clang-with-thin-lto-ubuntu buildbot.

Added: 


Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/ARM/smml.ll
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86/loclists-dwp.ll
llvm/test/tools/llvm-dwarfdump/X86/locstats.ll
llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll
llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll
llvm/test/tools/llvm-locstats/locstats.ll

Removed: 
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll



diff  --git a/clang/include/clang/Basic/CodeGenOptions.def 
b/clang/include/clang/Basic/CodeGenOptions.def
index fa450724ddd4..48c0df49e32d 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -63,6 +63,7 @@ CODEGENOPT(ExperimentalNewPa

[clang] a82d3e8 - Reland "[DebugInfo] Enable the debug entry values feature by default"

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-02-18T14:41:08+01:00
New Revision: a82d3e8a6e67473c94a5ce6345372748e9b61718

URL: 
https://github.com/llvm/llvm-project/commit/a82d3e8a6e67473c94a5ce6345372748e9b61718
DIFF: 
https://github.com/llvm/llvm-project/commit/a82d3e8a6e67473c94a5ce6345372748e9b61718.diff

LOG: Reland "[DebugInfo] Enable the debug entry values feature by default"

This patch enables the debug entry values feature.

  - Remove the (CC1) experimental -femit-debug-entry-values option
  - Enable it for x86, arm and aarch64 targets
  - Resolve the test failures
  - Leave the llc experimental option for targets that do not
support the CallSiteInfo yet

Differential Revision: https://reviews.llvm.org/D73534

Added: 
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll

Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/AArch64/arm64-anyregcc.ll
llvm/test/CodeGen/AArch64/arm64-patchpoint.ll
llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
llvm/test/CodeGen/ARM/smml.ll
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/CodeGen/X86/hoist-invariant-load.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/statepoint-allocas.ll
llvm/test/CodeGen/X86/tail-dup-repeat.ll
llvm/test/CodeGen/X86/xray-custom-log.ll
llvm/test/CodeGen/X86/xray-typed-event-log.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test

[clang] 2bf44d1 - Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2020-02-18T16:38:11+01:00
New Revision: 2bf44d11cb42a952bdeb778210d8b3e737f0b96e

URL: 
https://github.com/llvm/llvm-project/commit/2bf44d11cb42a952bdeb778210d8b3e737f0b96e
DIFF: 
https://github.com/llvm/llvm-project/commit/2bf44d11cb42a952bdeb778210d8b3e737f0b96e.diff

LOG: Revert "Reland "[DebugInfo] Enable the debug entry values feature by 
default""

This reverts commit rGa82d3e8a6e67.

Added: 


Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Driver/CC1Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/debug-info-extern-call.c
clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
lldb/packages/Python/lldbsuite/test/decorators.py

lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
llvm/include/llvm/CodeGen/CommandFlags.inc
llvm/include/llvm/Target/TargetMachine.h
llvm/include/llvm/Target/TargetOptions.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/TargetOptionsImpl.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/AArch64/arm64-anyregcc.ll
llvm/test/CodeGen/AArch64/arm64-patchpoint.ll
llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
llvm/test/CodeGen/ARM/smml.ll
llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
llvm/test/CodeGen/X86/call-site-info-output.ll
llvm/test/CodeGen/X86/hoist-invariant-load.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/statepoint-allocas.ll
llvm/test/CodeGen/X86/tail-dup-repeat.ll
llvm/test/CodeGen/X86/xray-custom-log.ll
llvm/test/CodeGen/X86/xray-typed-event-log.ll
llvm/test/DebugInfo/AArch64/call-site-info-output.ll
llvm/test/DebugInfo/ARM/call-site-info-output.ll
llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
llvm/test/DebugInfo/X86/dbg-value-range.ll
llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
llvm/test/DebugInfo/X86/loclists-dwp.ll
llvm/test/tools/llvm-dwarfdump/X86/locstats.ll
llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll
llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll
llvm/test

[clang] [clang] Catch missing format attributes (PR #70024)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/70024
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[clang] 8420a53 - [Debugify] Expose original debug info preservation check as CC1 option

[Djordje Todorovic via cfe-commits]

Author: Djordje Todorovic
Date: 2021-03-25T05:29:42-07:00
New Revision: 8420a5332486c682c1aaddbcb58a571869d19832

URL: 
https://github.com/llvm/llvm-project/commit/8420a5332486c682c1aaddbcb58a571869d19832
DIFF: 
https://github.com/llvm/llvm-project/commit/8420a5332486c682c1aaddbcb58a571869d19832.diff

LOG: [Debugify] Expose original debug info preservation check as CC1 option

In order to test the preservation of the original Debug Info metadata
in your projects, a front end option could be very useful, since users
usually report that a concrete entity (e.g. variable x, or function fn2())
is missing debug info. The [0] is an example of running the utility
on GDB Project.

This depends on: D82546 and D82545.

Differential Revision: https://reviews.llvm.org/D82547

Added: 
clang/test/Driver/verify-debug-info-preservation.c

Modified: 
clang/include/clang/Basic/CodeGenOptions.def
clang/include/clang/Basic/CodeGenOptions.h
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Driver/Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/lib/Frontend/CompilerInvocation.cpp
llvm/docs/HowToUpdateDebugInfo.rst

Removed: 




diff  --git a/clang/include/clang/Basic/CodeGenOptions.def 
b/clang/include/clang/Basic/CodeGenOptions.def
index bbda74044a1c..4c354734dff8 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -70,6 +70,10 @@ CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug 
information for the new
 CODEGENOPT(DisableRedZone, 1, 0) ///< Set when -mno-red-zone is enabled.
 CODEGENOPT(EmitCallSiteInfo, 1, 0) ///< Emit call site info only in the case of
///< '-g' + 'O>0' level.
+CODEGENOPT(EnableDIPreservationVerify, 1, 0) ///< Enable di preservation verify
+ ///< each (it means check
+ ///< the original debug info
+ ///< metadata preservation).
 CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs
  ///< is specified.
 CODEGENOPT(DisableTailCalls  , 1, 0) ///< Do not emit tail calls.

diff  --git a/clang/include/clang/Basic/CodeGenOptions.h 
b/clang/include/clang/Basic/CodeGenOptions.h
index b38df2da97de..778340b34272 100644
--- a/clang/include/clang/Basic/CodeGenOptions.h
+++ b/clang/include/clang/Basic/CodeGenOptions.h
@@ -190,6 +190,10 @@ class CodeGenOptions : public CodeGenOptionsBase {
   /// The ABI to use for passing floating point arguments.
   std::string FloatABI;
 
+  /// The file to use for dumping bug report by `Debugify` for original
+  /// debug info.
+  std::string DIBugsReportFilePath;
+
   /// The floating-point denormal mode to use.
   llvm::DenormalMode FPDenormalMode = llvm::DenormalMode::getIEEE();
 

diff  --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td 
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 6f50774d8f1c..5e580cc4fbb7 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -342,6 +342,10 @@ def warn_drv_disabling_vptr_no_rtti_default : Warning<
 def warn_drv_object_size_disabled_O0 : Warning<
   "the object size sanitizer has no effect at -O0, but is explicitly enabled: 
%0">,
   InGroup, DefaultWarnNoWerror;
+def warn_ignoring_verify_debuginfo_preserve_export : Warning<
+  "ignoring -fverify-debuginfo-preserve-export=%0 because "
+  "-fverify-debuginfo-preserve wasn't enabled">,
+  InGroup;
 def err_invalid_branch_protection: Error <
   "invalid branch protection option '%0' in '%1'">;
 def err_invalid_sls_hardening : Error<

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index a48b922e884a..f4af1a4b10f1 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4877,6 +4877,18 @@ def fexperimental_debug_variable_locations : Flag<["-"],
 "fexperimental-debug-variable-locations">,
 HelpText<"Use experimental new value-tracking variable locations">,
 MarshallingInfoFlag>;
+def fverify_debuginfo_preserve
+: Flag<["-"], "fverify-debuginfo-preserve">,
+  HelpText<"Enable Debug Info Metadata preservation testing in "
+   "optimizations.">,
+  MarshallingInfoFlag>;
+def fverify_debuginfo_preserve_export
+: Joined<["-"], "fverify-debuginfo-preserve-export=">,
+  MetaVarName<"">,
+  HelpText<"Export debug info (by testing original Debug Info) failures "
+   "into specified (JSON) file (should be abs path as we use "
+   "append mode to insert new JSON objects).">,
+  MarshallingInfoString>;
 // The driver option takes the key as a parameter to the -msign-return-address=
 // and -mbranch-protection= options, but CC1 has a se

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-remove-back-to-back-branches"
+
+STATISTIC(NumInsertedAligments, "Number of aligments set");
+
+namespace {
+
+// According to the MIPS specification, there shouldn't be two conditional
+// branches in the same 8-byte aligned region of code.

djtodoro wrote:

I will move this into a separate PR commit.
After reviewing what I wrote earlier, I now understand what 'work correctly' 
means in this context. Functionally, the core will operate correctly, but this 
change could impact performance. Specifically, if two branches share the same 
predictor index, this feature would come into play. However, this change 
primarily addresses an older RTL issue, so it is not strictly necessary and can 
be omitted or kept as off by default. Apologies for any confusion caused.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-remove-back-to-back-branches"
+
+STATISTIC(NumInsertedAligments, "Number of aligments set");
+
+namespace {
+
+// According to the MIPS specification, there shouldn't be two conditional
+// branches in the same 8-byte aligned region of code.

djtodoro wrote:

I will try to explain in detail why it was needed :)

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

> Extensions belong in their own PRs, ditto CPU/scheduler, driver and any 
> additional passes. Each PR is one commit and this is not one commit's worth 
> of changes.

@jrtc27 Yes! I agree. That is why I marked it as `Draft`. The next step is to 
divide it into multiple commits. Thanks.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro converted_to_draft 
https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro edited 
https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetMachine.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-remove-back-to-back-branches"
+
+STATISTIC(NumInsertedAligments, "Number of aligments set");
+
+namespace {
+
+// According to the MIPS specification, there shouldn't be two conditional
+// branches in the same 8-byte aligned region of code.

djtodoro wrote:

Sure, I’ll describe it in more detail. To clarify, this is not a general RISC-V 
specification but rather a MIPS-specific requirement necessary for our core to 
function correctly.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, 
Group,
 def mno_save_restore : Flag<["-"], "mno-save-restore">, 
Group,
   HelpText<"Disable using library calls for save and restore">;
 } // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">, 
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, 
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;

djtodoro wrote:

Well, you are right. We have used those for testing purposes, and I will remove 
it. Thank you for the point.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro created 
https://github.com/llvm/llvm-project/pull/121394

Adding two extensions for MIPS p8700 CPU:
  1. cmove (conditional move)
  2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700


>From a2e1fd5ffab4fe64a160571a9dffaacc3f22c32d Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions

Adding two extensions for MIPS p8700 CPU:
  1. cmove (conditional move)
  2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700
---
 clang/include/clang/Driver/Options.td |   4 +
 clang/lib/Driver/ToolChains/Clang.cpp |  15 +
 llvm/docs/RISCVUsage.rst  |   6 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  10 +
 llvm/lib/Target/RISCV/CMakeLists.txt  |   1 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCV.h |   2 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  13 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   4 +-
 llvm/lib/Target/RISCV/RISCVInstrFormats.td|  72 +++
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp  |  43 ++
 llvm/lib/Target/RISCV/RISCVInstrInfo.h|   6 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   | 145 +
 llvm/lib/Target/RISCV/RISCVInstrInfoC.td  | 125 -
 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td  |  82 +++
 .../Target/RISCV/RISCVLoadStoreOptimizer.cpp  | 370 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |   4 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp  |  18 +
 llvm/lib/Target/RISCV/RISCVSubtarget.h|   2 +
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp  |  15 +
 llvm/test/CodeGen/RISCV/O0-pipeline.ll|   1 +
 llvm/test/CodeGen/RISCV/O3-pipeline.ll|   2 +
 llvm/test/CodeGen/RISCV/load-store-pair.ll| 509 ++
 llvm/test/CodeGen/RISCV/select-and.ll |  25 +
 llvm/test/CodeGen/RISCV/select-bare.ll|  14 +
 llvm/test/CodeGen/RISCV/select-cc.ll  |  86 +++
 llvm/test/CodeGen/RISCV/select-or.ll  |  25 +
 27 files changed, 1473 insertions(+), 127 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
 create mode 100644 llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
 create mode 100644 llvm/test/CodeGen/RISCV/load-store-pair.ll

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, 
Group,
 def mno_save_restore : Flag<["-"], "mno-save-restore">, 
Group,
   HelpText<"Disable using library calls for save and restore">;
 } // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">, 
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, 
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
 let Flags = [TargetSpecific] in {
 def menable_experimental_extensions : Flag<["-"], 
"menable-experimental-extensions">, Group,
   HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..e91df8838032cd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
   CmdArgs.push_back(A->getValue());
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+   options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+  }
+
+  if (Arg *A = Args.getLastArg(options::OPT_mccmov,
+   options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("-riscv-ccmov=0");
+}
+  }
   // Handle -mrvv-vector-bits=
   if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
 StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
 ``experimental-Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``Xmipscmove``
+  LLVM implements conditional move for the `p8700 processor 
<

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+  static char ID;
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+  RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+  MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+  // Find and pair load/store instructions.
+  bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+  // Convert load/store pairs to single instructions.
+  bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+  // Scan the instructions looking for a load/store that can be combined
+  // with the current instruction into a load/store pair.
+  // Return the matching instruction if one is found, else MBB->end().
+  MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+   bool &MergeForward);
+
+  MachineBasicBlock::iterator
+  mergePairedInsns(MachineBasicBlock::iterator I,
+   MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+  AliasAnalysis *AA;
+  MachineRegisterInfo *MRI;
+  const RISCVInstrInfo *TII;
+  const RISCVRegisterInfo *TRI;
+  LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+  bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME, 
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(Fn.getFunction()))
+return false;
+  const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+  if (!Subtarget.useLoadStorePairs())
+return false;
+
+  bool MadeChange = false;
+  TII = Subtarget.getInstrInfo();
+  TRI = Subtarget.getRegisterInfo();
+  MRI = &Fn.getRegInfo();
+  AA = &getAnalysis().getAAResults();
+  ModifiedRegUnits.init(*TRI);
+  UsedRegUnits.init(*TRI);
+  UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+  for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+  if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+  tryToPairLdStInst(MBBI))
+MadeChange = true;
+  else
+++MBBI;
+}
+  }
+  return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock::iterator E = MI.getParent()->end();
+
+  if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+  // Look ahead for a pairable instruction.
+  bool MergeForward;
+  MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+  if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+  }
+  return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+  if (!UseLoadStorePair)
+return false;
+
+  unsigned PairOpc;
+  switch (First->getOpcode()) {
+  default:
+return false;
+  case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+  case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+  case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+  case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+  }
+
+  MachineFunction *MF = First->getMF();
+  const MachineMemOperand *MMO = *First->memoperands_begin();
+  Align MMOAlign = MMO->getAlign();
+  if (const PseudoSourceValue *Sour

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+  static char ID;
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+  RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+  MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+  // Find and pair load/store instructions.
+  bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+  // Convert load/store pairs to single instructions.
+  bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+  // Scan the instructions looking for a load/store that can be combined
+  // with the current instruction into a load/store pair.
+  // Return the matching instruction if one is found, else MBB->end().
+  MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+   bool &MergeForward);
+
+  MachineBasicBlock::iterator
+  mergePairedInsns(MachineBasicBlock::iterator I,
+   MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+  AliasAnalysis *AA;
+  MachineRegisterInfo *MRI;
+  const RISCVInstrInfo *TII;
+  const RISCVRegisterInfo *TRI;
+  LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+  bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME, 
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(Fn.getFunction()))
+return false;
+  const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+  if (!Subtarget.useLoadStorePairs())
+return false;
+
+  bool MadeChange = false;
+  TII = Subtarget.getInstrInfo();
+  TRI = Subtarget.getRegisterInfo();
+  MRI = &Fn.getRegInfo();
+  AA = &getAnalysis().getAAResults();
+  ModifiedRegUnits.init(*TRI);
+  UsedRegUnits.init(*TRI);
+  UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+  for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+  if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+  tryToPairLdStInst(MBBI))
+MadeChange = true;
+  else
+++MBBI;
+}
+  }
+  return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock::iterator E = MI.getParent()->end();
+
+  if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+  // Look ahead for a pairable instruction.
+  bool MergeForward;
+  MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+  if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+  }
+  return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+  if (!UseLoadStorePair)
+return false;
+
+  unsigned PairOpc;
+  switch (First->getOpcode()) {
+  default:
+return false;
+  case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+  case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+  case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+  case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+  }
+
+  MachineFunction *MF = First->getMF();
+  const MachineMemOperand *MMO = *First->memoperands_begin();
+  Align MMOAlign = MMO->getAlign();
+  if (const PseudoSourceValue *Sour

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+  static char ID;
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+  RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+  MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+  // Find and pair load/store instructions.
+  bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+  // Convert load/store pairs to single instructions.
+  bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+  // Scan the instructions looking for a load/store that can be combined
+  // with the current instruction into a load/store pair.
+  // Return the matching instruction if one is found, else MBB->end().
+  MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+   bool &MergeForward);
+
+  MachineBasicBlock::iterator
+  mergePairedInsns(MachineBasicBlock::iterator I,
+   MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+  AliasAnalysis *AA;
+  MachineRegisterInfo *MRI;
+  const RISCVInstrInfo *TII;
+  const RISCVRegisterInfo *TRI;
+  LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+  bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME, 
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(Fn.getFunction()))
+return false;
+  const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+  if (!Subtarget.useLoadStorePairs())
+return false;
+
+  bool MadeChange = false;
+  TII = Subtarget.getInstrInfo();
+  TRI = Subtarget.getRegisterInfo();
+  MRI = &Fn.getRegInfo();
+  AA = &getAnalysis().getAAResults();
+  ModifiedRegUnits.init(*TRI);
+  UsedRegUnits.init(*TRI);
+  UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+  for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+  if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+  tryToPairLdStInst(MBBI))
+MadeChange = true;
+  else
+++MBBI;
+}
+  }
+  return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock::iterator E = MI.getParent()->end();
+
+  if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+  // Look ahead for a pairable instruction.
+  bool MergeForward;
+  MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+  if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+  }
+  return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+  if (!UseLoadStorePair)
+return false;
+
+  unsigned PairOpc;
+  switch (First->getOpcode()) {
+  default:
+return false;
+  case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+  case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+  case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+  case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+  }
+
+  MachineFunction *MF = First->getMF();
+  const MachineMemOperand *MMO = *First->memoperands_begin();
+  Align MMOAlign = MMO->getAlign();
+  if (const PseudoSourceValue *Sour

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+  static char ID;
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+  RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+  MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+  // Find and pair load/store instructions.
+  bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+  // Convert load/store pairs to single instructions.
+  bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+  // Scan the instructions looking for a load/store that can be combined
+  // with the current instruction into a load/store pair.
+  // Return the matching instruction if one is found, else MBB->end().
+  MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+   bool &MergeForward);
+
+  MachineBasicBlock::iterator
+  mergePairedInsns(MachineBasicBlock::iterator I,
+   MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+  AliasAnalysis *AA;
+  MachineRegisterInfo *MRI;
+  const RISCVInstrInfo *TII;
+  const RISCVRegisterInfo *TRI;
+  LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+  bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME, 
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(Fn.getFunction()))
+return false;
+  const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+  if (!Subtarget.useLoadStorePairs())
+return false;
+
+  bool MadeChange = false;
+  TII = Subtarget.getInstrInfo();
+  TRI = Subtarget.getRegisterInfo();
+  MRI = &Fn.getRegInfo();
+  AA = &getAnalysis().getAAResults();
+  ModifiedRegUnits.init(*TRI);
+  UsedRegUnits.init(*TRI);
+  UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+  for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+  if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+  tryToPairLdStInst(MBBI))
+MadeChange = true;
+  else
+++MBBI;
+}
+  }
+  return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock::iterator E = MI.getParent()->end();
+
+  if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+  // Look ahead for a pairable instruction.
+  bool MergeForward;
+  MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+  if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+  }
+  return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+  if (!UseLoadStorePair)
+return false;
+
+  unsigned PairOpc;
+  switch (First->getOpcode()) {
+  default:
+return false;
+  case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+  case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+  case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+  case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+  }
+
+  MachineFunction *MF = First->getMF();
+  const MachineMemOperand *MMO = *First->memoperands_begin();
+  Align MMOAlign = MMO->getAlign();
+  if (const PseudoSourceValue *Sour

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
 
+  /// Return true if pairing the given load or store may be paired with 
another.
+  static bool isPairableLdStInstOpc(unsigned Opc);
+
+  static bool isLdStSafeToPair(const MachineInstr &LdSt,
+   const TargetRegisterInfo *TRI);
+
+  std::optional>
+  isRVVSpillForZvlsseg(unsigned Opcode) const;

djtodoro wrote:

Yes, thanks, addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -514,6 +514,78 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro updated 
https://github.com/llvm/llvm-project/pull/121394

>From f833498eb48595cc6b2bd5dd0c1b05d941313877 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions

Adding two extensions for MIPS p8700 CPU:
  1. cmove (conditional move)
  2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700
---
 clang/include/clang/Driver/Options.td |   4 +
 clang/lib/Driver/ToolChains/Clang.cpp |  15 +
 llvm/docs/RISCVUsage.rst  |   6 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  10 +
 llvm/lib/Target/RISCV/CMakeLists.txt  |   1 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCV.h |   2 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  13 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   4 +-
 llvm/lib/Target/RISCV/RISCVInstrFormats.td|  72 +++
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp  |  43 ++
 llvm/lib/Target/RISCV/RISCVInstrInfo.h|   6 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   | 145 +
 llvm/lib/Target/RISCV/RISCVInstrInfoC.td  | 125 -
 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td  |  82 +++
 .../Target/RISCV/RISCVLoadStoreOptimizer.cpp  | 370 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |   4 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp  |  17 +
 llvm/lib/Target/RISCV/RISCVSubtarget.h|   2 +
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp  |  15 +
 llvm/test/CodeGen/RISCV/O0-pipeline.ll|   1 +
 llvm/test/CodeGen/RISCV/O3-pipeline.ll|   2 +
 llvm/test/CodeGen/RISCV/load-store-pair.ll| 509 ++
 llvm/test/CodeGen/RISCV/select-and.ll |  25 +
 llvm/test/CodeGen/RISCV/select-bare.ll|  14 +
 llvm/test/CodeGen/RISCV/select-cc.ll  |  86 +++
 llvm/test/CodeGen/RISCV/select-or.ll  |  25 +
 27 files changed, 1472 insertions(+), 127 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
 create mode 100644 llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
 create mode 100644 llvm/test/CodeGen/RISCV/load-store-pair.ll

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, 
Group,
 def mno_save_restore : Flag<["-"], "mno-save-restore">, 
Group,
   HelpText<"Disable using library calls for save and restore">;
 } // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">, 
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, 
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
 let Flags = [TargetSpecific] in {
 def menable_experimental_extensions : Flag<["-"], 
"menable-experimental-extensions">, Group,
   HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..ef708c85718e4b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
   CmdArgs.push_back(A->getValue());
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+   options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+  }
+
+  if (Arg *A = Args.getLastArg(options::OPT_mccmov, options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("-riscv-ccmov=0");
+}
+  }
+
   // Handle -mrvv-vector-bits=
   if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
 StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
 ``experimental-Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``Xmipscmove``
+  LLVM implements conditional move for the `p8700 processor 
` by MIPS.
+
+``Xmipslsp``
+  LLVM implements load/store pair instructions for the `p8700 processor 
` by MIPS.
+
 Exper

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1, 
(AddiPair:$rs2)),
 }
 
 
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [UsesMIPSCMov] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),

djtodoro wrote:

I have tried, but have not achieved to make a pattern that matches all the 
combinations. An alternative can be to add new `riscv_mips_setcc` 
ComplexPattern I guess.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -62,6 +62,20 @@ static cl::opt RISCVMinimumJumpTableEntries(
 "riscv-min-jump-table-entries", cl::Hidden,
 cl::desc("Set minimum number of entries to use a jump table on RISCV"));
 
+static cl::opt

djtodoro wrote:

Well, I do not think so.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -367,6 +372,16 @@ class RISCVPassConfig : public TargetPassConfig {
   DAG->addMutation(createStoreClusterDAGMutation(
   DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
 }
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusions().empty()) {
+  DAG = DAG ? DAG : createGenericSchedLive(C);
+
+  if (ST.useLoadStorePairs()) {

djtodoro wrote:

Yes, thanks, addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -426,6 +426,12 @@ The current vendor extensions supported are:
 ``Xwchc``
   LLVM implements `the custom compressed opcodes present in some QingKe cores` 
by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes 
by the name "XW".
 
+``xmipscmove``

djtodoro wrote:

Thanks, addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1, 
(AddiPair:$rs2)),
 }
 
 
//===--===//
+

djtodoro wrote:

Addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -2710,6 +2713,45 @@ MachineInstr 
*RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
   .setMemRefs(MemI.memoperands())
   .setMIFlags(MemI.getFlags());
 }
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+  switch (Opc) {
+  default:
+return false;
+  case RISCV::SH:

djtodoro wrote:

That is true. I have added a TODO marker for it in 
https://github.com/llvm/llvm-project/pull/121394.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
 def HasConditionalMoveFusion : 
Predicate<"Subtarget->hasConditionalMoveFusion()">;
 def NoConditionalMoveFusion  : 
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
+def TuneMIPSP8700
+: SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",
+   "MIPS p8700 processor">;
+def FeatureMIPSCMov : SubtargetFeature<"xmipscmov", "HasMIPSCMov",

djtodoro wrote:

Addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1, 
(AddiPair:$rs2)),
 }
 
 
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [UsesMIPSCMov] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+  (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+  (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+  (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setule (XLenVT GPR:$y), (XLenVT GPR:$x))),

djtodoro wrote:

Addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
 def HasConditionalMoveFusion : 
Predicate<"Subtarget->hasConditionalMoveFusion()">;
 def NoConditionalMoveFusion  : 
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
+def TuneMIPSP8700
+: SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",
+   "MIPS p8700 processor">;
+def FeatureMIPSCMov : SubtargetFeature<"xmipscmov", "HasMIPSCMov",
+   "true", "Using CCMov",
+   [Feature64Bit]>;
+def UsesMIPSCMov

djtodoro wrote:

Addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 7 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8, ReleaseAtCycles = [5] in {
+def : WriteRes;

djtodoro wrote:

You are right, thanks!

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add MIPS P8700 processor (PR #119882)

[Djordje Todorovic via cfe-commits]

@@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion
 def HasConditionalMoveFusion : 
Predicate<"Subtarget->hasConditionalMoveFusion()">;
 def NoConditionalMoveFusion  : 
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
+def TuneMIPSP8700
+: SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",

djtodoro wrote:

I agree, thanks for suggestion: 
https://github.com/llvm/llvm-project/pull/120073.

https://github.com/llvm/llvm-project/pull/119882
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }

djtodoro wrote:

The datasheet figure might indeed be a bit misleading. While there's a separate 
load queue and store queue, it's essentially a single LSU composed of these 
integrated blocks, not distinct pipelines. We'll consider clarifying this in a 
future revision of the datasheet.

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add MIPS P8700 processor (PR #119882)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/119882
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[clang] [llvm] Add scheduling model for mips p8700 CPU (PR #119885)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro created 
https://github.com/llvm/llvm-project/pull/119885

Depends on https://github.com/llvm/llvm-project/pull/119882.

>From 6e17be47f6a36f417547d9bff2f31b8c421ee03b Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Mon, 9 Dec 2024 13:01:11 +0100
Subject: [PATCH 1/2] [RISCV] Add MIPS P8700 processor

The P8700 is a high-performance processor from MIPS designed to
meet the demands of modern workloads, offering exceptional
scalability and efficiency. It builds on MIPS's established
architectural strengths while introducing enhancements that set
it apart. For more details, you can check out the official
product page here: https://mips.com/products/hardware/p8700/.

Scheduling model will be added in a separate commit/PR.
---
 clang/test/Driver/riscv-cpus.c  | 17 +
 clang/test/Misc/target-invalid-cpu-note/riscv.c |  2 ++
 llvm/docs/ReleaseNotes.md   |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  4 
 llvm/lib/Target/RISCV/RISCVProcessors.td| 15 +++
 5 files changed, 39 insertions(+)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 249216612f7ee7..1b09945620f8c3 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -98,6 +98,23 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck 
-check-prefix=MTUNE-ROCKET64 %s
 // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=mips-p8700 | FileCheck 
-check-prefix=MTUNE-MIPS-P8700 %s
+// MTUNE-MIPS-P8700: "-tune-cpu" "mips-p8700"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=mips-p8700 | FileCheck 
-check-prefix=MCPU-MIPS-P8700 %s
+// MCPU-MIPS-P8700: "-target-cpu" "mips-p8700"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+m"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+a"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+f"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+d"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+c"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zicsr"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zifencei"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zaamo"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
+
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s
 // MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 8c5df5884cd791..fc8536d99cb804 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -25,6 +25,7 @@
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are:
 // RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}}, mips-p8700
 // RISCV64-SAME: {{^}}, rocket-rv64
 // RISCV64-SAME: {{^}}, sifive-p450
 // RISCV64-SAME: {{^}}, sifive-p470
@@ -72,6 +73,7 @@
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV64-NEXT: note: valid target CPU values are:
 // TUNE-RISCV64-SAME: {{^}} generic-rv64
+// TUNE-RISCV64-SAME: {{^}}, mips-p8700
 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64
 // TUNE-RISCV64-SAME: {{^}}, sifive-p450
 // TUNE-RISCV64-SAME: {{^}}, sifive-p470
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index a5805e050bfdbe..391568b7a3ad3d 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -195,6 +195,7 @@ Changes to the RISC-V Backend
 * Added `Smctr`, `Ssctr` and `Svvptc` extensions.
 * `-mcpu=syntacore-scr7` was added.
 * `-mcpu=tt-ascalon-d8` was added.
+* `-mcpu=mips-p8700` was added.
 * The `Zacas` extension is no longer marked as experimental.
 * Added Smdbltrp, Ssdbltrp extensions to -march.
 * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 52268c3fa62ccb..3985d83ca075e4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion
 def HasConditionalMoveFusion : 
Predicate<"Subtarget->hasConditionalMoveFusion()">;
 def NoConditionalMoveFusion  : 
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
+def TuneMIPSP8700
+: SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",
+   "MIPS p8700 processor">;
+
 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors">;
 
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index c4e19c515b155b..7e4bcd07f2fa8a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.t

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -252,9 +252,17 @@ static const char *getLDMOption(const llvm::Triple &T, 
const ArgList &Args) {
   case llvm::Triple::ppc64le:
 return "elf64lppc";
   case llvm::Triple::riscv32:
-return "elf32lriscv";
-  case llvm::Triple::riscv64:
-return "elf64lriscv";
+  case llvm::Triple::riscv64: {
+bool IsBigEndian = false;
+if (Arg *A = Args.getLastArg(options::OPT_mlittle_endian,
+ options::OPT_mbig_endian))
+  IsBigEndian = A->getOption().matches(options::OPT_mbig_endian);
+
+if (T.getArch() == llvm::Triple::riscv32)
+  return IsBigEndian ? "elf32briscv" : "elf32lriscv";
+else
+  return IsBigEndian ? "elf64briscv" : "elf64lriscv";
+  }

djtodoro wrote:

I will drop this part for now, since it is dummy/unsed for now. I am planning 
to create/add support for `BE`, once we are done with these `p8700` patches.
This was a patch on Phabricator: https://reviews.llvm.org/D128612

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro edited 
https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// RISC-V processor by MIPS.
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96; // as per the specification
+  int LoadLatency = 4;
+  int MispredictPenalty = 8; // TODO: Estimated
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+
+// Handle ALQ Pipelines.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+def p8700IssueALU : ProcResource<1> { let Super = p8700ALQ; }

djtodoro wrote:

Not needed. Addressed in https://github.com/llvm/llvm-project/pull/119885.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on 
RV64I
 def WriteJmp: SchedWrite;// Jump
 def WriteJal: SchedWrite;// Jump and link
 def WriteJalr   : SchedWrite;// Jump and link register
+def WriteJmpReg : SchedWrite;// Jump register

djtodoro wrote:

Removed in https://github.com/llvm/llvm-project/pull/119885. `WriteJalr` should 
be used.

https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [RISCV] Add MIPS P8700 processor (PR #119882)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro created 
https://github.com/llvm/llvm-project/pull/119882

The P8700 is a high-performance processor from MIPS designed to meet the 
demands of modern workloads, offering exceptional scalability and efficiency. 
It builds on MIPS's established architectural strengths while introducing 
enhancements that set it apart. For more details, you can check out the 
official product page here: https://mips.com/products/hardware/p8700/.

Scheduling model will be added in a separate commit/PR.

>From 6e17be47f6a36f417547d9bff2f31b8c421ee03b Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Mon, 9 Dec 2024 13:01:11 +0100
Subject: [PATCH] [RISCV] Add MIPS P8700 processor

The P8700 is a high-performance processor from MIPS designed to
meet the demands of modern workloads, offering exceptional
scalability and efficiency. It builds on MIPS's established
architectural strengths while introducing enhancements that set
it apart. For more details, you can check out the official
product page here: https://mips.com/products/hardware/p8700/.

Scheduling model will be added in a separate commit/PR.
---
 clang/test/Driver/riscv-cpus.c  | 17 +
 clang/test/Misc/target-invalid-cpu-note/riscv.c |  2 ++
 llvm/docs/ReleaseNotes.md   |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  4 
 llvm/lib/Target/RISCV/RISCVProcessors.td| 15 +++
 5 files changed, 39 insertions(+)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 249216612f7ee7..1b09945620f8c3 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -98,6 +98,23 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck 
-check-prefix=MTUNE-ROCKET64 %s
 // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=mips-p8700 | FileCheck 
-check-prefix=MTUNE-MIPS-P8700 %s
+// MTUNE-MIPS-P8700: "-tune-cpu" "mips-p8700"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=mips-p8700 | FileCheck 
-check-prefix=MCPU-MIPS-P8700 %s
+// MCPU-MIPS-P8700: "-target-cpu" "mips-p8700"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+m"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+a"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+f"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+d"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+c"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zicsr"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zifencei"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zaamo"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zalrsc"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
+// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
+
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-base | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-BASE %s
 // MTUNE-SYNTACORE-SCR1-BASE: "-tune-cpu" "syntacore-scr1-base"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 8c5df5884cd791..fc8536d99cb804 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -25,6 +25,7 @@
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are:
 // RISCV64-SAME: {{^}} generic-rv64
+// RISCV64-SAME: {{^}}, mips-p8700
 // RISCV64-SAME: {{^}}, rocket-rv64
 // RISCV64-SAME: {{^}}, sifive-p450
 // RISCV64-SAME: {{^}}, sifive-p470
@@ -72,6 +73,7 @@
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV64-NEXT: note: valid target CPU values are:
 // TUNE-RISCV64-SAME: {{^}} generic-rv64
+// TUNE-RISCV64-SAME: {{^}}, mips-p8700
 // TUNE-RISCV64-SAME: {{^}}, rocket-rv64
 // TUNE-RISCV64-SAME: {{^}}, sifive-p450
 // TUNE-RISCV64-SAME: {{^}}, sifive-p470
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index a5805e050bfdbe..391568b7a3ad3d 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -195,6 +195,7 @@ Changes to the RISC-V Backend
 * Added `Smctr`, `Ssctr` and `Svvptc` extensions.
 * `-mcpu=syntacore-scr7` was added.
 * `-mcpu=tt-ascalon-d8` was added.
+* `-mcpu=mips-p8700` was added.
 * The `Zacas` extension is no longer marked as experimental.
 * Added Smdbltrp, Ssdbltrp extensions to -march.
 * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 52268c3fa62ccb..3985d83ca075e4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion
 def HasConditionalMoveFusion : 
Predicate<"Subtarget->hasConditionalMoveFusion()">;
 def NoConditionalMoveFusion  : 
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
+def TuneMIPSP8700
+: SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",
+   

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

@lenary thanks!

>You still have a whitespace change to this file?

No, the whitespaces are there on `main` branch. I applied `clang-format` 
initially, and that is why it was included in one of my previous patches.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0, 
mayStore = 0, DecoderNamespace = "Xmipscomve" in {

djtodoro wrote:

thanks!

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+  bits<7> imm7;
+  bits<5> rs1;
+  bits<5> rd1;
+  bits<5> rd2;
+
+  let Inst{31-27} = rd2;
+  let Inst{26-23} = imm7{6-3};
+  let Inst{22-20} = 0b000;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = rd1;
+  let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Load word pair format.
+class LWPFormat
+: RVInst {
+  bits<7> imm7;
+  bits<5> rs1;
+  bits<5> rd1;
+  bits<5> rd2;
+
+  let Inst{31-27} = rd2;
+  let Inst{26-22} = imm7{6-2};
+  let Inst{21-20} = 0b01;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b100;
+  let Inst{11-7} = rd1;
+  let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Store double pair format.
+class SDPFormat
+: RVInst {
+  bits<7> imm7;
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = imm7{6-5};
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b101;
+  let Inst{11-10} = imm7{4-3};
+  let Inst{9-0} = 0b001011;
+}
+
+// Store word pair format.
+class SWPFormat
+: RVInst {
+  bits<7> imm7;
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = imm7{6-5};
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b101;
+  let Inst{11-9} = imm7{4-2};
+  let Inst{8-0} = 0b010001011;

djtodoro wrote:

@topperc you meant `let Inst{6-0} = OPC_CUSTOM_0.Value;` I think :)

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

djolertrk wrote:

@topperc looks ok now?

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

@topperc Is it ok now? :)

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

https://github.com/djolertrk deleted 
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
 : Predicate<"Subtarget->hasVendorXCVbi()">,
   AssemblerPredicate<(all_of FeatureVendorXCVbi),
  "'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+  AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store 
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,

djtodoro wrote:

Aha ok. I understand.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
 : Predicate<"Subtarget->hasVendorXCVbi()">,
   AssemblerPredicate<(all_of FeatureVendorXCVbi),
  "'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+  AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store 
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,

djtodoro wrote:

IIUC, I think you proposed we use `hasVendorXMIPSCMove` for both.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
 : Predicate<"Subtarget->hasVendorXCVbi()">,
   AssemblerPredicate<(all_of FeatureVendorXCVbi),
  "'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+  AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store 
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,

djtodoro wrote:

https://github.com/llvm/llvm-project/pull/121394#discussion_r1918794675

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
 "riscv-min-jump-table-entries", cl::Hidden,
 cl::desc("Set minimum number of entries to use a jump table on RISCV"));
 
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",

djtodoro wrote:

Hmm, you are right. I will add `mips-` to remove confusion. Thanks @jrtc27!

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
 "riscv-min-jump-table-entries", cl::Hidden,
 cl::desc("Set minimum number of entries to use a jump table on RISCV"));
 
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",

djtodoro wrote:

Well, we have not seen benefits on some important applications/benchmarks for 
us when using this extension with `p8700` CPU, so that is why we keep it `OFF` 
by default for now.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

@topperc Thanks for the comments!

> This still isn't broken down enough. We usually like to see assembler support 
> in separate patches from code generation.

I have removed `RISCVLoadStoreOptimizer` Pass, and will add it in a separate 
PR/commit.

> Missing tests in test/MC/RISCV for the assembler and disassembler

Added.



https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,370 @@
+//===- RISCVLoadStoreOptimizer.cpp 
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+  static char ID;
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+  RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+  MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+  // Find and pair load/store instructions.
+  bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+  // Convert load/store pairs to single instructions.
+  bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+  // Scan the instructions looking for a load/store that can be combined
+  // with the current instruction into a load/store pair.
+  // Return the matching instruction if one is found, else MBB->end().
+  MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+   bool &MergeForward);
+
+  MachineBasicBlock::iterator
+  mergePairedInsns(MachineBasicBlock::iterator I,
+   MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+  AliasAnalysis *AA;
+  MachineRegisterInfo *MRI;
+  const RISCVInstrInfo *TII;
+  const RISCVRegisterInfo *TRI;
+  LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+  bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME, 
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(Fn.getFunction()))
+return false;
+  const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+  if (!Subtarget.useLoadStorePairs())
+return false;
+
+  bool MadeChange = false;
+  TII = Subtarget.getInstrInfo();
+  TRI = Subtarget.getRegisterInfo();
+  MRI = &Fn.getRegInfo();
+  AA = &getAnalysis().getAAResults();
+  ModifiedRegUnits.init(*TRI);
+  UsedRegUnits.init(*TRI);
+  UseLoadStorePair = Subtarget.useLoadStorePairs();

djtodoro wrote:

No need any more, thanks

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -389,6 +390,13 @@ class RISCVPassConfig : public TargetPassConfig {
   DAG->addMutation(createStoreClusterDAGMutation(
   DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
 }
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusions().empty() && ST.useLoadStorePairs()) {

djtodoro wrote:

Hm, I agree

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> {
   }];
 }
 
+// A 7-bit unsigned immediate where the least significant two bits are zero.

djtodoro wrote:

No need any more, thanks

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0, 
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"ccmov", "$rd, $rs2, $rs1, $rs3">,

djtodoro wrote:

Yep, I have added it. The PR for `mips.` prefix is here 
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/69.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals : 
SubtargetFeature<"tagged-globals",
 "AllowTaggedGlobals",
 "true", "Use an instruction sequence for taking the address of a global "
 "that allows a memory tag in the upper address bits">;
+
+def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", 
"HasVendorMIPSCMove",
+   "true", "Using CCMov",
+   [Feature64Bit]>;

djtodoro wrote:

>It would be better if this and def FeatureVendorMIPSLoadStorePairs both used 
>RISCVExtension. I think this means some changes to the functions on 
>riscvsubtarget too, it should be clear to follow from the other vendor 
>extensions. This will also have a knock-on effect on some other tests, 
>especially relating to RISCVISAInfo (and also some in clang iirc), but this is 
>for the better - it means the compiler can show it supports your extensions 😄

Good point. Yes, I have added it, and resolved test failures (there is one unit 
test as well). Thanks :)

>Please may you also put these definitions beside the other vendor extensions, 
>rather than at the end with these codegen options? The section starts 
>somewhere around line 1020, and you'll see each vendor's extensions are with 
>each other.

Sure.

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0, 
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+   Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+  (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+  (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+  (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+  (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),

djtodoro wrote:

I see, it makes sense! :D

Initially, I created it against an older LLVM, so I have missed this...Thanks!

https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro updated 
https://github.com/llvm/llvm-project/pull/121394

>From 29d22560f2987e81ea66e4c7dea42f594bda709f Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions

Adding two extensions for MIPS p8700 CPU:
  1. cmove (conditional move)
  2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700
---
 clang/include/clang/Driver/Options.td |   4 +
 clang/lib/Driver/ToolChains/Clang.cpp |  15 +
 llvm/docs/RISCVUsage.rst  |   6 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  10 +
 llvm/lib/Target/RISCV/CMakeLists.txt  |   1 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCV.h |   2 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  13 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   4 +-
 llvm/lib/Target/RISCV/RISCVInstrFormats.td|  72 +++
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp  |  43 ++
 llvm/lib/Target/RISCV/RISCVInstrInfo.h|   6 +
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   | 145 +
 llvm/lib/Target/RISCV/RISCVInstrInfoC.td  | 125 -
 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td  |  82 +++
 .../Target/RISCV/RISCVLoadStoreOptimizer.cpp  | 370 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |   4 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp  |  17 +
 llvm/lib/Target/RISCV/RISCVSubtarget.h|   2 +
 llvm/lib/Target/RISCV/RISCVTargetMachine.cpp  |  15 +
 llvm/test/CodeGen/RISCV/O0-pipeline.ll|   1 +
 llvm/test/CodeGen/RISCV/O3-pipeline.ll|   2 +
 llvm/test/CodeGen/RISCV/load-store-pair.ll| 509 ++
 llvm/test/CodeGen/RISCV/select-and.ll |  25 +
 llvm/test/CodeGen/RISCV/select-bare.ll|  14 +
 llvm/test/CodeGen/RISCV/select-cc.ll  |  86 +++
 llvm/test/CodeGen/RISCV/select-or.ll  |  25 +
 27 files changed, 1472 insertions(+), 127 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
 create mode 100644 llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
 create mode 100644 llvm/test/CodeGen/RISCV/load-store-pair.ll

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, 
Group,
 def mno_save_restore : Flag<["-"], "mno-save-restore">, 
Group,
   HelpText<"Disable using library calls for save and restore">;
 } // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">, 
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, 
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
 let Flags = [TargetSpecific] in {
 def menable_experimental_extensions : Flag<["-"], 
"menable-experimental-extensions">, Group,
   HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..ef708c85718e4b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
   CmdArgs.push_back(A->getValue());
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+   options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+  }
+
+  if (Arg *A = Args.getLastArg(options::OPT_mccmov, options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("-riscv-ccmov=0");
+}
+  }
+
   // Handle -mrvv-vector-bits=
   if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
 StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
 ``experimental-Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``Xmipscmove``
+  LLVM implements conditional move for the `p8700 processor 
` by MIPS.
+
+``Xmipslsp``
+  LLVM implements load/store pair instructions for the `p8700 processor 
` by MIPS.
+
 Exper

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

Lets wait another day or two, since someone may have additional comments. 
Thanks @mgoudar!

https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro approved this pull request.


https://github.com/llvm/llvm-project/pull/130587
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[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/117865
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[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

[Djordje Todorovic via cfe-commits]

@@ -0,0 +1,6 @@
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
+

djtodoro wrote:

nit: no need for 2 newlines here

https://github.com/llvm/llvm-project/pull/132907
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[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/132907
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[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro approved this pull request.


https://github.com/llvm/llvm-project/pull/132907
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[clang] [llvm] Revert "[MIPS] Define SubTargetFeature for i6500 cpu" (PR #133215)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro created 
https://github.com/llvm/llvm-project/pull/133215

Reverts llvm/llvm-project#132907 due to some test failures.

>From 9c22bc410d3e157686ae5fd76f8c000e65949a9e Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Thu, 27 Mar 2025 09:04:45 +0100
Subject: [PATCH] Revert "[MIPS] Define SubTargetFeature for i6500 cpu
 (#132907)"

This reverts commit 6294325a535d8042a667ccfb4400a9f63e1bee63.
---
 clang/test/CodeGen/Mips/subtarget-feature-test.c | 5 -
 llvm/lib/Target/Mips/Mips.td | 8 ++--
 llvm/lib/Target/Mips/MipsSubtarget.h | 2 +-
 3 files changed, 3 insertions(+), 12 deletions(-)
 delete mode 100644 clang/test/CodeGen/Mips/subtarget-feature-test.c

diff --git a/clang/test/CodeGen/Mips/subtarget-feature-test.c 
b/clang/test/CodeGen/Mips/subtarget-feature-test.c
deleted file mode 100644
index 7f0b8e7e77135..0
--- a/clang/test/CodeGen/Mips/subtarget-feature-test.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
-// CHECK-NOT: {{.*}} is not a recognized feature for this target
-
-// RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 | 
FileCheck --allow-empty %s
-// CHECK-NOT: {{.*}} is not a recognized feature for this target
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..9159d11fd486f 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,7 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
 : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-   "MIPS I6400 Processor", [FeatureMips64r6]>;
-
-def ImplI6500
-: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
-   "MIPS I6500 Processor", [FeatureMips64r6]>;
+   "MIPS I6400/I6500 Processors", [FeatureMips64r6]>;
 
 class Proc Features>
  : ProcessorModel;
@@ -272,7 +268,7 @@ def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h 
b/llvm/lib/Target/Mips/MipsSubtarget.h
index 15127b11d5cdd..0c75597d3decf 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
-  enum class CPU { P5600, I6400, I6500 };
+  enum class CPU { P5600, I6400 };
 
   // Used to avoid printing dsp warnings multiple times.
   static bool DspWarningPrinted;

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[clang] [llvm] Revert "[MIPS] Define SubTargetFeature for i6500 cpu" (PR #133215)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/133215
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[clang] [llvm] Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907) (PR #133366)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro approved this pull request.


https://github.com/llvm/llvm-project/pull/133366
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[clang] [llvm] Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907) (PR #133366)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/133366
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[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

> There's a lot going on here that has absolutely no explanation (no comments 
> in the code, and the commit message is a single sentence that tells me 
> nothing of use), and it's doing multiple different things. There's changing 
> default arch strings, which makes some sense (well, it makes sense for you to 
> want, I just don't love that changing the vendor changes -march, it's already 
> confusing enough that baremetal and Unix-y triples have different defaults, 
> but that ship has sailed). There's a whole bunch of -EL/-EB flag handling 
> which doesn't make sense, I don't understand why MIPS triples need it when 
> all the other vendors don't. Then there's extra sysroot stuff where again I 
> don't understand why there are cases where only MIPS wants --sysroot= to 
> work. Plus unexplained multilib changes.
> 
> I really don't want to see a proliferation of undocumented vendor-specific 
> quirks. If there are things the generic RISC-V code currently omits then 
> those should be added via standalone, well-documented (including in the 
> commit message) commits. If there are things that need to be vendor-specific 
> then they need explaining why they are there.

@jrtc27 Well, I do agree with the comment. We have some kind of an initial 
support for BE, and I left those lines there, which are NOOPs at the moment, 
but that can serve as a placeholder where we need to add BE related code in the 
future, but, I agree, it should have been added either with a decent comment, 
or not at all. Now that I think again, it introduces confusion only, so I will 
remove that part, and plan to post a new patch (or patch series) that will 
handle BE in a non-vendor specific way. Thanks!

https://github.com/llvm/llvm-project/pull/134065
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[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

@@ -1874,15 +1894,26 @@ static void findRISCVMultilibs(const Driver &D,
   MultilibBuilder("lib64/lp64f").flag("-m64").flag("-mabi=lp64f");
   MultilibBuilder Lp64d =
   MultilibBuilder("lib64/lp64d").flag("-m64").flag("-mabi=lp64d");
+
+  SmallVector Endian;
+  if (TargetTriple.getVendor() == llvm::Triple::MipsTechnologies) {
+Endian.push_back(
+MultilibBuilder("/riscv").flag("-EL").flag("-EB", /*Disallow=*/true));
+Endian.push_back(
+MultilibBuilder("/riscveb").flag("-EB").flag("-EL", 
/*Disallow=*/true));

djtodoro wrote:

yes, makes sense

https://github.com/llvm/llvm-project/pull/134065
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[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro updated 
https://github.com/llvm/llvm-project/pull/134065

>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/4] [clang][RISCV] Set default CPU for  vendor

---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp |  4 
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp   | 13 +++--
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 1c5b5ff5e5b40..d3cc889178d2c 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -365,5 +365,9 @@ std::string riscv::getRISCVTargetCPU(const 
llvm::opt::ArgList &Args,
   if (!CPU.empty())
 return CPU;
 
+  if (Triple.getVendor() == llvm::Triple::MipsTechnologies &&
+  Triple.isRISCV64())
+return "p8700";
+
   return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp 
b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3c996c82fcec4..30aa8c267b484 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -79,8 +79,17 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple 
&TT, StringRef CPU,
 StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
-  if (CPU.empty() || CPU == "generic")
-CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
+  if (CPU.empty() || CPU == "generic") {
+if (Is64Bit) {
+  if (TT.getVendor() == llvm::Triple::MipsTechnologies) {
+CPU = "p8700";
+  } else {
+CPU = "generic-rv64";
+  }
+} else {
+  CPU = "generic-rv32";
+}
+  }
 
   if (TuneCPU.empty())
 TuneCPU = CPU;

>From 8c1ca6afe3b57619ec65640dd6f0f7364bea15cc Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Wed, 26 Mar 2025 09:26:57 +0100
Subject: [PATCH 2/4] [clang] Add driver support for riscv64-mti toolchains

---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp|  6 ++-
 clang/lib/Driver/ToolChains/Gnu.cpp   | 40 +--
 clang/lib/Driver/ToolChains/Linux.cpp | 25 ++--
 .../lib/Driver/ToolChains/RISCVToolchain.cpp  |  4 ++
 4 files changed, 67 insertions(+), 8 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index d3cc889178d2c..679387240aa3b 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -337,12 +337,14 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList 
&Args,
   // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
   // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
   if (Triple.isRISCV32()) {
-if (Triple.getOS() == llvm::Triple::UnknownOS)
+if (Triple.getOS() == llvm::Triple::UnknownOS &&
+Triple.getVendor() != llvm::Triple::MipsTechnologies)
   return "rv32imac";
 return "rv32imafdc";
   }
 
-  if (Triple.getOS() == llvm::Triple::UnknownOS)
+  if (Triple.getOS() == llvm::Triple::UnknownOS &&
+  Triple.getVendor() != llvm::Triple::MipsTechnologies)
 return "rv64imac";
   if (Triple.isAndroid())
 return "rv64imafdcv_zba_zbb_zbs";
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index a0fa3c66d7dec..5a9e66e975fdc 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -402,6 +402,11 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, 
const JobAction &JA,
 CmdArgs.push_back(Arch == llvm::Triple::aarch64_be ? "-EB" : "-EL");
   }
 
+  if (Triple.isRISCV() &&
+  Triple.getVendor() == llvm::Triple::MipsTechnologies) {
+CmdArgs.push_back("-EL");
+  }
+
   // Most Android ARM64 targets should enable the linker fix for erratum
   // 843419. Only non-Cortex-A53 devices are allowed to skip this flag.
   if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily)) {
@@ -765,7 +770,8 @@ void tools::gnutools::Assembler::ConstructJob(Compilation 
&C,
   }
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64: {
-StringRef ABIName = riscv::getRISCVABI(Args, getToolChain().getTriple());
+const llvm::Triple &Triple = getToolChain().getTriple();
+StringRef ABIName = riscv::getRISCVABI(Args, Triple);
 CmdArgs.push_back("-mabi");
 CmdArgs.push_back(ABIName.data());
 std::string MArchName =
@@ -774,6 +780,10 @@ void tools::gnutools::Assembler::ConstructJob(Compilation 
&C,
 CmdArgs.push_back(Args.MakeArgString(MArchName));
 if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
   Args.addOptOutFlag(CmdArgs, options::OPT_mrelax, options::OPT_mno_relax);
+
+if (Triple.getVendor() == llvm::Triple::MipsTechnologies)
+  CmdArgs.push_back("-EL"

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro updated 
https://github.com/llvm/llvm-project/pull/134065

>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/5] [clang][RISCV] Set default CPU for  vendor

---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp |  4 
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp   | 13 +++--
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 1c5b5ff5e5b40..d3cc889178d2c 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -365,5 +365,9 @@ std::string riscv::getRISCVTargetCPU(const 
llvm::opt::ArgList &Args,
   if (!CPU.empty())
 return CPU;
 
+  if (Triple.getVendor() == llvm::Triple::MipsTechnologies &&
+  Triple.isRISCV64())
+return "p8700";
+
   return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp 
b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3c996c82fcec4..30aa8c267b484 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -79,8 +79,17 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple 
&TT, StringRef CPU,
 StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
-  if (CPU.empty() || CPU == "generic")
-CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
+  if (CPU.empty() || CPU == "generic") {
+if (Is64Bit) {
+  if (TT.getVendor() == llvm::Triple::MipsTechnologies) {
+CPU = "p8700";
+  } else {
+CPU = "generic-rv64";
+  }
+} else {
+  CPU = "generic-rv32";
+}
+  }
 
   if (TuneCPU.empty())
 TuneCPU = CPU;

>From 8c1ca6afe3b57619ec65640dd6f0f7364bea15cc Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Wed, 26 Mar 2025 09:26:57 +0100
Subject: [PATCH 2/5] [clang] Add driver support for riscv64-mti toolchains

---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp|  6 ++-
 clang/lib/Driver/ToolChains/Gnu.cpp   | 40 +--
 clang/lib/Driver/ToolChains/Linux.cpp | 25 ++--
 .../lib/Driver/ToolChains/RISCVToolchain.cpp  |  4 ++
 4 files changed, 67 insertions(+), 8 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index d3cc889178d2c..679387240aa3b 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -337,12 +337,14 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList 
&Args,
   // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
   // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
   if (Triple.isRISCV32()) {
-if (Triple.getOS() == llvm::Triple::UnknownOS)
+if (Triple.getOS() == llvm::Triple::UnknownOS &&
+Triple.getVendor() != llvm::Triple::MipsTechnologies)
   return "rv32imac";
 return "rv32imafdc";
   }
 
-  if (Triple.getOS() == llvm::Triple::UnknownOS)
+  if (Triple.getOS() == llvm::Triple::UnknownOS &&
+  Triple.getVendor() != llvm::Triple::MipsTechnologies)
 return "rv64imac";
   if (Triple.isAndroid())
 return "rv64imafdcv_zba_zbb_zbs";
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index a0fa3c66d7dec..5a9e66e975fdc 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -402,6 +402,11 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, 
const JobAction &JA,
 CmdArgs.push_back(Arch == llvm::Triple::aarch64_be ? "-EB" : "-EL");
   }
 
+  if (Triple.isRISCV() &&
+  Triple.getVendor() == llvm::Triple::MipsTechnologies) {
+CmdArgs.push_back("-EL");
+  }
+
   // Most Android ARM64 targets should enable the linker fix for erratum
   // 843419. Only non-Cortex-A53 devices are allowed to skip this flag.
   if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily)) {
@@ -765,7 +770,8 @@ void tools::gnutools::Assembler::ConstructJob(Compilation 
&C,
   }
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64: {
-StringRef ABIName = riscv::getRISCVABI(Args, getToolChain().getTriple());
+const llvm::Triple &Triple = getToolChain().getTriple();
+StringRef ABIName = riscv::getRISCVABI(Args, Triple);
 CmdArgs.push_back("-mabi");
 CmdArgs.push_back(ABIName.data());
 std::string MArchName =
@@ -774,6 +780,10 @@ void tools::gnutools::Assembler::ConstructJob(Compilation 
&C,
 CmdArgs.push_back(Args.MakeArgString(MArchName));
 if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
   Args.addOptOutFlag(CmdArgs, options::OPT_mrelax, options::OPT_mno_relax);
+
+if (Triple.getVendor() == llvm::Triple::MipsTechnologies)
+  CmdArgs.push_back("-EL"

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

@@ -115,6 +115,20 @@
 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
 // MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
 
+// RUN: %clang --target=riscv64-mti-linux-gnu -### -c %s 2>&1| FileCheck 
-check-prefix=MCPU-MTI-P8700 %s

djtodoro wrote:

Sure.

https://github.com/llvm/llvm-project/pull/134065
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[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro closed 
https://github.com/llvm/llvm-project/pull/134065
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[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

djtodoro wrote:

I will postpone this PR until I prepare big endian support, thank you all for 
the comments!

https://github.com/llvm/llvm-project/pull/134065
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[clang] [llvm] [NFC] Fix xmipscmov extension name (PR #135647)

[Djordje Todorovic via cfe-commits]

https://github.com/djtodoro created 
https://github.com/llvm/llvm-project/pull/135647

The right name was used in riscv-toolchain-conventions docs.

>From 86eef6e45b92a8601d2873d89b1b7b153a587bb3 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic 
Date: Mon, 14 Apr 2025 11:22:28 +0200
Subject: [PATCH] [NFC] Fix xmipscmov extension name

The right name was used in riscv-toolchain-conventions docs.
---
 clang/test/Driver/print-supported-extensions-riscv.c |  2 +-
 llvm/docs/RISCVUsage.rst |  2 +-
 .../Target/RISCV/Disassembler/RISCVDisassembler.cpp  |  4 ++--
 llvm/lib/Target/RISCV/RISCVFeatures.td   | 12 ++--
 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td |  4 ++--
 llvm/lib/Target/RISCV/RISCVProcessors.td |  2 +-
 llvm/lib/Target/RISCV/RISCVSubtarget.cpp |  2 +-
 llvm/test/CodeGen/RISCV/features-info.ll |  2 +-
 llvm/test/CodeGen/RISCV/select-and.ll|  2 +-
 llvm/test/CodeGen/RISCV/select-bare.ll   |  2 +-
 llvm/test/CodeGen/RISCV/select-cc.ll |  2 +-
 llvm/test/CodeGen/RISCV/select-or.ll |  2 +-
 llvm/test/MC/RISCV/xmips-invalid.s   |  4 ++--
 llvm/test/MC/RISCV/xmips-valid.s |  6 +++---
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp |  2 +-
 15 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index d06cedac5b1eb..39002d7b4780a 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -161,7 +161,7 @@
 // CHECK-NEXT: xcvmac   1.0   'XCVmac' (CORE-V 
Multiply-Accumulate)
 // CHECK-NEXT: xcvmem   1.0   'XCVmem' (CORE-V 
Post-incrementing Load & Store)
 // CHECK-NEXT: xcvsimd  1.0   'XCVsimd' (CORE-V SIMD ALU)
-// CHECK-NEXT: xmipscmove   1.0   'XMIPSCMove' (MIPS 
conditional move instruction(s) (ccmov))
+// CHECK-NEXT: xmipscmov1.0   'XMIPSCMov' (MIPS 
conditional move instruction (mips.ccmov))
 // CHECK-NEXT: xmipslsp 1.0   'XMIPSLSP' (MIPS 
optimization for hardware load-store bonding)
 // CHECK-NEXT: xsfcease 1.0   'XSfcease' (SiFive sf.cease 
Instruction)
 // CHECK-NEXT: xsfvcp   1.0   'XSfvcp' (SiFive Custom 
Vector Coprocessor Interface Instructions)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index cda7e5fec8488..137b537f00ea0 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -491,7 +491,7 @@ The current vendor extensions supported are:
 ``experimental-Xqcisync``
   LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
-``Xmipscmove``
+``Xmipscmov``
   LLVM implements conditional move for the `p8700 processor 
` by MIPS.
 
 ``Xmipslsp``
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 366291b53bebb..27809d96b647c 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -737,8 +737,8 @@ static constexpr DecoderListEntry DecoderList32[]{
 {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
 {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive 
sf.cease"},
 {DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
-{DecoderTableXmipscmove32,
- {RISCV::FeatureVendorXMIPSCMove},
+{DecoderTableXmipscmov32,
+ {RISCV::FeatureVendorXMIPSCMov},
  "MIPS mips.ccmov"},
 // Standard Extensions
 {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 21bcf343139c2..f51fcf82077f4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1300,12 +1300,12 @@ def HasVendorXCVbi
  "'XCVbi' (CORE-V Immediate Branching)">;
 // MIPS Extensions
 
-def FeatureVendorXMIPSCMove
-: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
-def HasVendorXMIPSCMove
-: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
-  AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
- "'Xmipscmove' ('mips.ccmov' instruction)">;
+def FeatureVendorXMIPSCMov
+: RISCVExtension<1, 0, "MIPS conditional move instruction (mips.ccmov)">;
+def HasVendorXMIPSCMov
+: Predicate<"Subtarget->hasVendorXMIPSCMov()">,
+  AssemblerPredicate

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

[Djordje Todorovic via cfe-commits]

@@ -337,13 +337,17 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList 
&Args,
   // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
   // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
   if (Triple.isRISCV32()) {
-if (Triple.getOS() == llvm::Triple::UnknownOS)
+if (Triple.getOS() == llvm::Triple::UnknownOS &&
+Triple.getVendor() != llvm::Triple::MipsTechnologies)
   return "rv32imac";
 return "rv32imafdc";
   }
 
-  if (Triple.getOS() == llvm::Triple::UnknownOS)
+  if (Triple.getOS() == llvm::Triple::UnknownOS &&
+  Triple.getVendor() != llvm::Triple::MipsTechnologies)
 return "rv64imac";
+  if (Triple.getVendor() == llvm::Triple::MipsTechnologies)
+return "rv64imafdc_zba_zbb_zicsr_zifencei";

djtodoro wrote:

Well, by just moving the `if (Triple.getVendor() == 
llvm::Triple::MipsTechnologies)` above, we make it cleaner.

https://github.com/llvm/llvm-project/pull/134065
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