[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

================
@@ -367,6 +372,16 @@ class RISCVPassConfig : public TargetPassConfig {
       DAG->addMutation(createStoreClusterDAGMutation(
           DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
     }
+
+    const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
+    if (!ST.getMacroFusions().empty()) {
+      DAG = DAG ? DAG : createGenericSchedLive(C);
+
+      if (ST.useLoadStorePairs()) {
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djtodoro wrote:

Yes, thanks, addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
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