[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

================
@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
 
+  /// Return true if pairing the given load or store may be paired with 
another.
+  static bool isPairableLdStInstOpc(unsigned Opc);
+
+  static bool isLdStSafeToPair(const MachineInstr &LdSt,
+                               const TargetRegisterInfo *TRI);
+
+  std::optional<std::pair<unsigned, unsigned>>
+  isRVVSpillForZvlsseg(unsigned Opcode) const;
----------------
djtodoro wrote:

Yes, thanks, addressed in https://github.com/llvm/llvm-project/pull/121394

https://github.com/llvm/llvm-project/pull/117865
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits