On 1/25/22 09:18, Cédric Le Goater wrote:
On 1/19/22 07:09, David Gibson wrote:
On Tue, Jan 18, 2022 at 03:44:42PM -0300, Fabiano Rosas wrote:
There's no sc 1.
No... but what exactly should and will happen if you attempt to
execute an "sc 1" on 40x. Will it be treated as an "sc 0", or will it
cause a 0x700? If it's a 0x700, better double check that that is
generated at translation time, if you're removing the check on level
here.
A Program Interrupt with the illegal instruction error code should be
generated at translation time but it is not the case today. It never
was correctly implemented AFAICT :
/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
We would need a simple 'sc' instruction for the PPC405 and other
processors. Let's add that to the TODO list.
The ref405ep machine now boots a mainline Linux with a buildroot user space.
Let's get this series merged first.
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
