On Tue, Jan 18, 2022 at 03:44:40PM -0300, Fabiano Rosas wrote:
> powerpc_excp_40x applies only to the 405, so remove HV code and
> references to BookE.
>
> Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 26 ++------------------------
> 1 file changed, 2 insertions(+), 24 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index bddea702be..e98d783ecd 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -457,34 +457,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> cs->halted = 1;
> cpu_interrupt_exittb(cs);
> }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - }
>
> /* machine check exceptions don't have ME set */
> new_msr &= ~((target_ulong)1 << MSR_ME);
>
> - /* XXX: should also have something loaded in DAR / DSISR */
DAR and DSISR don't apply for 40x, but I wonder if we should be
loading something into DEAR or ESR for machine checks.
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_MCSRR0;
> - srr1 = SPR_BOOKE_MCSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> - break;
> - default:
> - break;
> - }
> + srr0 = SPR_40x_SRR2;
> + srr1 = SPR_40x_SRR3;
> break;
> case POWERPC_EXCP_DSI: /* Data storage exception
> */
> trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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