On Tue, Jan 18, 2022 at 03:44:38PM -0300, Fabiano Rosas wrote: > Differences from the generic powerpc_excp code: > > - Not BookE, so some MSR bits are cleared at interrupt dispatch; > - No MSR_HV or MSR_LE; > - No power saving states; > - No Hypervisor Emulation Assistance; > - Not 64 bits; > - No System call vectored; > - No Interrupts Little Endian; > - No Alternate Interrupt Location. > > Exceptions used: > > POWERPC_EXCP_ALIGN > POWERPC_EXCP_CRITICAL > POWERPC_EXCP_DEBUG > POWERPC_EXCP_DSI > POWERPC_EXCP_DTLB > POWERPC_EXCP_EXTERNAL > POWERPC_EXCP_FIT > POWERPC_EXCP_ISI > POWERPC_EXCP_ITLB > POWERPC_EXCP_MCHECK > POWERPC_EXCP_PIT > POWERPC_EXCP_PROGRAM > POWERPC_EXCP_SYSCALL > POWERPC_EXCP_WDT > > Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: David Gibson <da...@gibson.dropbear.id.au>
> ---
> target/ppc/excp_helper.c | 205 ++-------------------------------------
> 1 file changed, 10 insertions(+), 195 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 12ab5e1b34..b5975dff3e 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -409,54 +409,26 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> excp, env->error_code);
>
> /* new srr1 value excluding must-be-zero bits */
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - msr = env->msr;
> - } else {
> - msr = env->msr & ~0x783f0000ULL;
> - }
> + msr = env->msr & ~0x783f0000ULL;
>
> /*
> - * new interrupt handler msr preserves existing HV and ME unless
> - * explicitly overriden
> + * new interrupt handler msr preserves existing ME unless
> + * explicitly overriden.
> */
> - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> + new_msr = env->msr & (((target_ulong)1 << MSR_ME));
>
> /* target registers */
> srr0 = SPR_SRR0;
> srr1 = SPR_SRR1;
>
> - /*
> - * check for special resume at 0x100 from doze/nap/sleep/winkle on
> - * P7/P8/P9
> - */
> - if (env->resume_as_sreset) {
> - excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> - }
> -
> /*
> * Hypervisor emulation assistance interrupt only exists on server
> - * arch 2.05 server or later. We also don't want to generate it if
> - * we don't have HVB in msr_mask (PAPR mode).
> + * arch 2.05 server or later.
> */
> - if (excp == POWERPC_EXCP_HV_EMU
> -#if defined(TARGET_PPC64)
> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> -#endif /* defined(TARGET_PPC64) */
> -
> - ) {
> + if (excp == POWERPC_EXCP_HV_EMU) {
> excp = POWERPC_EXCP_PROGRAM;
> }
>
> -#ifdef TARGET_PPC64
> - /*
> - * SPEU and VPU share the same IVOR but they exist in different
> - * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> - */
> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> - excp = POWERPC_EXCP_SPEU;
> - }
> -#endif
> -
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> cpu_abort(cs, "Raised an exception without defined vector %d\n",
> @@ -645,24 +617,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> new_msr |= (target_ulong)MSR_HVB;
> }
> break;
> - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception
> */
> - lev = env->error_code;
> - dump_syscall(env);
> - env->nip += 4;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -
> - vector += lev * 0x20;
> -
> - env->lr = env->nip;
> - env->ctr = msr;
> - break;
> - case POWERPC_EXCP_FPU: /* Floating-point unavailable exception
> */
> - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable
> */
> - case POWERPC_EXCP_DECR: /* Decrementer exception
> */
> - break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt
> */
> - /* FIT on 4xx */
> trace_ppc_excp_print("FIT");
> break;
> case POWERPC_EXCP_WDT: /* Watchdog timer interrupt
> */
> @@ -693,119 +648,9 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> cpu_abort(cs, "Debug exception triggered on unsupported
> model\n");
> }
> break;
> - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU
> */
> - env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> - break;
> - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt
> */
> - break;
> - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt
> */
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_RESET: /* System reset exception
> */
> - /* A power-saving exception sets ME, otherwise it is unchanged */
> - if (msr_pow) {
> - /* indicate that we resumed from power save mode */
> - msr |= 0x10000;
> - new_msr |= ((target_ulong)1 << MSR_ME);
> - }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - } else {
> - if (msr_pow) {
> - cpu_abort(cs, "Trying to deliver power-saving system reset "
> - "exception %d with no HV support\n", excp);
> - }
> - }
> - break;
> - case POWERPC_EXCP_DSEG: /* Data segment exception
> */
> - case POWERPC_EXCP_ISEG: /* Instruction segment exception
> */
> - case POWERPC_EXCP_TRACE: /* Trace exception
> */
> - break;
> - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception
> */
> - msr |= env->error_code;
> - /* fall through */
> - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception
> */
> - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception
> */
> - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception
> */
> - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception
> */
> - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt
> */
> - case POWERPC_EXCP_HV_EMU:
> - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization
> */
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - break;
> - case POWERPC_EXCP_VPU: /* Vector unavailable exception
> */
> - case POWERPC_EXCP_VSXU: /* VSX unavailable exception
> */
> - case POWERPC_EXCP_FU: /* Facility unavailable exception
> */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> -#endif
> - break;
> - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable
> Exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code <<
> FSCR_IC_POS);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -#endif
> - break;
> case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt
> */
> trace_ppc_excp_print("PIT");
> break;
> - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error
> */
> - case POWERPC_EXCP_DLTLB: /* Data load TLB miss
> */
> - case POWERPC_EXCP_DSTLB: /* Data store TLB miss
> */
> - switch (excp_model) {
> - case POWERPC_EXCP_602:
> - case POWERPC_EXCP_603:
> - case POWERPC_EXCP_G2:
> - /* Swap temporary saved registers with GPRs */
> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> - new_msr |= (target_ulong)1 << MSR_TGPR;
> - hreg_swap_gpr_tgpr(env);
> - }
> - /* fall through */
> - case POWERPC_EXCP_7x5:
> - ppc_excp_debug_sw_tlb(env, excp);
> -
> - msr |= env->crf[0] << 28;
> - msr |= env->error_code; /* key, D/I, S/L bits */
> - /* Set way using a LRU mechanism */
> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> - break;
> - default:
> - cpu_abort(cs, "Invalid TLB miss exception\n");
> - break;
> - }
> - break;
> - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt
> */
> - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt
> */
> - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt
> */
> - case POWERPC_EXCP_IO: /* IO error exception
> */
> - case POWERPC_EXCP_RUNM: /* Run mode exception
> */
> - case POWERPC_EXCP_EMUL: /* Emulation trap exception
> */
> - case POWERPC_EXCP_FPA: /* Floating-point assist exception
> */
> - case POWERPC_EXCP_DABR: /* Data address breakpoint
> */
> - case POWERPC_EXCP_IABR: /* Instruction address breakpoint
> */
> - case POWERPC_EXCP_SMI: /* System management interrupt
> */
> - case POWERPC_EXCP_THERM: /* Thermal interrupt
> */
> - case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt
> */
> - case POWERPC_EXCP_VPUA: /* Vector assist exception
> */
> - case POWERPC_EXCP_SOFTP: /* Soft patch exception
> */
> - case POWERPC_EXCP_MAINT: /* Maintenance exception
> */
> - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint
> */
> - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint
> */
> - cpu_abort(cs, "%s exception not implemented\n",
> - powerpc_excp_name(excp));
> - break;
> default:
> excp_invalid:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> @@ -824,41 +669,11 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> }
> }
>
> - /*
> - * Sort out endianness of interrupt, this differs depending on the
> - * CPU, the HV mode, etc...
> - */
> - if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> - new_msr |= (target_ulong)1 << MSR_LE;
> - }
> + /* Save PC */
> + env->spr[srr0] = env->nip;
>
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> - new_msr |= (target_ulong)1 << MSR_CM;
> - } else {
> - vector = (uint32_t)vector;
> - }
> - } else {
> - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> - vector = (uint32_t)vector;
> - } else {
> - new_msr |= (target_ulong)1 << MSR_SF;
> - }
> - }
> -#endif
> -
> - if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> - /* Save PC */
> - env->spr[srr0] = env->nip;
> -
> - /* Save MSR */
> - env->spr[srr1] = msr;
> - }
> -
> - /* This can update new_msr and vector if AIL applies */
> - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> + /* Save MSR */
> + env->spr[srr1] = msr;
>
> powerpc_set_excp_state(cpu, vector, new_msr);
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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