On 9/1/20 3:39 AM, Bin Meng wrote: > From: Bin Meng <bin.m...@windriver.com> > > Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems > enough to create unimplemented devices to cover their register > spaces at this point. > > With this commit, QEMU can boot to U-Boot (2nd stage bootloader) > all the way to the Linux shell login prompt, with a modified HSS > (1st stage bootloader). > > For detailed instructions on how to create images for the Icicle > Kit board, please check QEMU RISC-V WiKi page at: > https://wiki.qemu.org/Documentation/Platforms/RISCV > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> > --- > > (no changes since v1) > > include/hw/riscv/microchip_pfsoc.h | 3 +++ > hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++ > 2 files changed, 17 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
