On 9/1/20 3:38 AM, Bin Meng wrote: > From: Bin Meng <bin.m...@windriver.com> > > RISC-V machines do not instantiate RISC-V CPUs directly, instead > they do that via the hart array. Add a new property for the reset > vector address to allow the value to be passed to the CPU, before > CPU is realized. > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> > --- > > (no changes since v1) > > include/hw/riscv/riscv_hart.h | 1 + > hw/riscv/riscv_hart.c | 3 +++ > 2 files changed, 4 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
